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Pe 4306 Ds
Pe 4306 Ds
PE4306
50Ω RF Digital Attenuator
Product Description 5-bit, 31 dB, 1 – 4000 MHz
fe
The PE4306 is manufactured on Peregrine’s UltraCMOS® 50Ω impedance
process, a patented variation of silicon-on-insulator (SOI) Pin compatible with PE430x series
technology on a sapphire substrate, offering the performance Packaged in a 20 Lead 4x4 mm QFN
of GaAs with the economy and integration of conventional
CMOS.
Parallel Control 5
En
Power-Up Control 2
DOC-02145
Document No. DOC-30007-2 │ www.psemi.com ©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4306
Product Specification
0 35
31 dB
30
-1
25
-2
20
16 dB
15
-3
insertion loss @ 25 C
insertion loss @ -40 C 10 8 dB
insertion loss @ 85 C
fe
-4
5 4 dB
2 dB
-5 0 1 dB
0 500 1000 1500 2000
Frequency (MHz)
2500 3000 3500 4000
Frequency (MHz)
3000 3500 4000
of
Figure 5. Input Return Loss at Major Figure 6. Output Return Loss at Major
Attenuation Steps Attenuation Steps
d
0 0
En
-10 -10
-20 -20
S22 (dB)
s11 (dB)
-30
16 dB -30
31 dB 31 dB 16 dB
-40 -40
-50 -50
0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
©2003-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30007-2 │ UltraCMOS® RFIC Solutions
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4306
Product Specification
Figure 7. Attenuation Error vs. Frequency Figure 8. Attenuation Error vs. Attenuation
Setting at 10 MHz and 510 MHz
2 1.5
0 1
-2 0.5
31 dB
Error (dB)
Error (dB)
-4 0
-6 -0.5
10 MHz @ 25 C
510 MHz @ 25 C
fe
10 MHz @ -40 C
-8 -1 510 MHz @ -40 C
10 MHz @ 85 C
510 MHz @ 85 C
-10 -1.5
0 500 1000 1500 2000
Frequency (MHz)
2500 3000 3500 4000
Li 0 5 10 15 20
1.5 1.5
En
1 1
0.5 0.5
Error (dB)
Error (dB)
0 0
-0.5 -0.5
1210 MHZ @ 25 C 1510 MHz @ 25 C
1210 MHz @ -40 C 2010 MHz @ 25 C
1210 MHz @ 85 C 1510 MHz @ -40 C
-1 -1 2010 MHz @ -40 C
1010 MHz @ 25 C
1010 MHz @ -40 C 1510 MHz @ 85 C
1010 MHz @ 85 C 2010 MHz @ 85 C
-1.5 -1.5
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
Note: Positive attenuation error indicates higher attenuation than target value
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4306
Product Specification
Figure 11. Attenuation Error vs. Attenuation Figure 12. 1 dB Compression vs. Frequency
Setting at 2010 MHz and 2510 MHz
1.5 40
35
1 dB Compression (dBm)
0.5
Error (dB)
0 30
0 dB
-0.5 1 dB
2210 MHz @ 25 C
2 dB
2510 MHz @ 25 C 25
fe
31 dB
2210 MHz @ -40 C
-1 2510 MHz @ -40 C
2210 MHz @ 85 C
2510 MHz @ 85 C
-1.5 20
0 5 10 15 20
Frequency (MHz)
2500 3000
of
Figure 13. Input IP3 vs. Frequency
d
60
55
En
50
45
IP3 (dBm)
40
35
0 dB 8 dB
30 1 dB 16 dB
2 dB 31 dB
25 4 dB
20
1000 1500 2000 2500 3000
Frequency (MHz)
Note: Positive attenuation error indicates higher attenuation than target value
©2003-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30007-2 │ UltraCMOS® RFIC Solutions
Page 4 of 11
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4306
Product Specification
Figure 14. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings
GND
N/C
Symbol Parameter/Conditions Min Max Units
C1
C2
C4
VDD Power supply voltage -0.3 4.0 V
20
19
18
17
16
VDD+
VI Voltage on any DC input -0.3 V
C16 1 15 C8 0.3
VDD
GND
PUP1
PUP2
fe
Table 4. Operating Ranges
Pin Parameter Min Typ Max Units
Pin No. Description
Name
VDD Power Supply
1 C16 Attenuation control bit, 16 dB (Note 4) 2.7 3.0 3.3 V
2
3
4
5
RF1
Data
Clock
LE
RF port (Note 1)
Serial interface data input (Note 4)
Serial interface clock input
Latch Enable input (Note 2)
Li Voltage
IDD Power Supply
Current
Digital Input High 0.7xVDD
100 μA
V
of
Digital Input Low 0.3xVDD V
6 VDD Power supply pin
Digital Input Leakage 1 μA
7 PUP1 Power-up selection bit
8 PUP2 Power-up selection bit Input Power +24 dBm
Negative supply voltage or GND connection must be grounded for proper device operation.
12 Vss/GND
(Note 3)
13 P/S Parallel/Serial mode select Electrostatic Discharge (ESD) Precautions
14 RF2 RF port (Note 1) When handling this UltraCMOS® device, observe the
15 C8 Attenuation control bit, 8 dB same precautions that you would use with other ESD-
16 C4 Attenuation control bit, 4 dB sensitive devices. Although this device contains
17 C2 Attenuation control bit, 2 dB circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
18 GND Ground connection
rate specified in Table 3.
19 C1 Attenuation control bit, 1 dB
20 N/C No connect. Can be connected to any bias Latch-Up Avoidance
Paddle GND Ground for proper operation Unlike conventional CMOS devices, UltraCMOS®
Notes: 1. Both RF ports must be held at 0 VDC or DC blocked with an external
devices are immune to latch-up.
series capacitor
2. Latch Enable (LE) has an internal 100 kΩ resistor to VDD Switching Frequency
3. Connect pin 12 to GND to enable internal negative voltage generator. The PE4306 has a maximum 25 kHz switching rate.
Connect pin 12 to VSS (-VDD) to bypass and disable internal negative
voltage generator
4. Place a 10 kΩ resistor in series, as close to pin as possible to avoid Resistor on Pin 1 & 3
frequency resonance. See “Resistor on Pin 1 & 3” paragraph A 10 kΩ resistor on the inputs to Pin 1 & 3 (see
Figure 16) will eliminate package resonance between
Moisture Sensitivity Level the RF input pin and the two digital inputs. Specified
The Moisture Sensitivity Level rating for the 5x5 mm QFN attenuation error versus frequency performance is
package is MSL1. dependent upon this condition.
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4306
Product Specification
fe
Characteristics), and switching speed (Table 1).
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
For parallel programming the Latch Enable (LE)
and allows a known attenuation state to be
should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 18) to latch new attenuation state into
device.
Li established before an initial serial or parallel control
word is provided.
P/S C16 C8 C4 C2 C1 Attenuation State set to one of four possible values. These four values
are selected by the two power-up control bits, PUP1
0 0 0 0 0 0 Reference Loss
and PUP2, as shown in Table 6 (Power-Up Truth
0 0 0 0 0 1 1 dB Table, Parallel Mode).
0 0 0 0 1 0 2 dB
0 0 0 1 0 0 4 dB Table 6. Power-Up Truth Table, Parallel
Interface Mode
0 0 1 0 0 0 8 dB
0 1 0 0 0 0 16 dB P/S LE PUP2 PUP1 Attenuation State
0 1 1 1 1 1 31 dB 0 0 0 0 Reference Loss
Note: Not all 32 possible combinations of C1-C16 are shown 0 0 1 0 8 dB
0 0 0 1 16 dB
Serial Interface 0 0 1 1 31 dB
parallel-out shift register buffered by a transparent Note: Power up with LE = 1 provides normal parallel operation with C1-C16,
and PUP1 and PUP2 are not active.
latch. The latch is controlled by three CMOS-
compatible signals: Data, Clock, and Latch Enable
(LE). The Data and Clock inputs allow data to be
serially entered into the shift register, a process that
is independent of the state of the LE input.
©2003-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30007-2 │ UltraCMOS® RFIC Solutions
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PE4306
Product Specification
fe
software, enable or disable each attenuation
setting to the desired combined attenuation. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
To evaluate the power up options, first disconnect
the control cable from the evaluation board. The
control cable must be removed to prevent the PC
Li
of
port from biasing the control pins.
Document No. DOC-30007-2 │ www.psemi.com ©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4306
Product Specification
C0.5
1 1
C1
C2
C4
2
2
20
19
18
17
16
C5
C1
C2
C4
GND
J4 C16 R3 10K 1 15 C8 J5
SMASM Z=50 Ohm C16 C8 Z=50 Ohm SMASM
1 R6 0 OHM 2 14 R7 0 OHM 1
RFin U1 RFout
DATA R8 10K 3 MLPQ4X4 13 PS J9
2
2
DATA PS SUPPLY
CLK 4 12
CLK VNEG VDD 4
VDD_D
LE 5 11 -VDD 3
PUP1
PUP2
GND
LE GND
VDD
2
-3V 1
10
C17 C18
100pF 0.1μF
PUP1
PUP2
DOC-02201
R5 0 OHM
VDD
fe
C13 C16
100pF 0.1μF
Note: Resistors on pins 1 and 3 are required and should be placed as close to the part as
possible to avoid package resonance and meet error specifications over frequency
Li
of
d
En
©2003-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30007-2 │ UltraCMOS® RFIC Solutions
Page 8 of 11
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4306
Product Specification
Figure 17. Serial Interface Timing Diagram Table 7. 5-Bit Attenuator Serial Programming
Register Map
LE
B5 B4 B3 B2 B1 B0
C16 C8 C4 C2 C1 0
Clock
MSB (first in) LSB (last in)
fe
LE
Parallel Data
C16:C1
Li
of
tLEPW
tPDSUP tPDHLD
d
En
Symbol Parameter Min Max Unit Symbol Parameter Min Max Unit
Serial data clock tLEPW LE minimum pulse width 10 ns
fClk 10 MHz
frequency (Note 1)
Data set-up time before
tClkH Serial clock HIGH time 30 ns tPDSUP 10 ns
rising edge of LE
Data hold time after
tClkL Serial clock LOW time 30 ns tPDHLD 10 ns
falling edge of LE
LE set-up time after last
tLESUP 10 ns
clock falling edge
tLEPW LE minimum pulse width 30 ns
Serial data set-up time
tSDSUP 10 ns
before clock rising edge
Serial data hold time
tSDHLD 10 ns
after clock falling edge
Note 1: fClk is verified during the functional pattern test. Serial programming
sections of the functional pattern are clocked at 10 MHz to verify fclk
specification
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PE4306
Product Specification
0.10 C
A 4.00 (2X) 2.15±0.05 0.28
0.55±0.05 0.50
B (x20)
(x20)
11 15
0.75
0.50 (x20)
10 16
6 20
0.23±0.05
0.10 C (x20)
(2X) 5 1
0.18 2.20
2.00
Pin #1 Corner 4.40
0.18 0.435 SQ
REF
TOP VIEW BOTTOM VIEW RECOMMENDED LAND PATTERN
fe
DOC-01880
0.10 C
0.10 C A B
0.90 MAX 0.05 C
0.05 C
SEATING PLANE
0.203
SIDE VIEW
0.05 C
Li
ALL FEATURES
of
Figure 20. Marking Specifications
d
En
4306
YYWW
ZZZZZ
17-0007
©2003-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-30007-2 │ UltraCMOS® RFIC Solutions
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4306
Product Specification
fe
Li
of
Table 10. Ordering Information
d
4306-52 4306 PE4306G-20MLP 4x4mm-3000C Green 20-lead 4x4mm QFN 3000 units / T&R
Document No. DOC-30007-2 │ www.psemi.com ©2003-2013 Peregrine Semiconductor Corp. All rights reserved.
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