23BBS0050

Kriti Arora
Lab-Activity 4: Combinational Multiplier
Combinational Multiplier
Aim: To Design Combinational Multiplier.

Description:
Assume a 4 bit multiplier(a0,a1,a2,a3) and multiplicand(b0,b1,b2,b3). Perform a
multiplication process which may result in a sub-product that may result in an
logical manipulation and an Adder for the logical manipulation, the
representation was carried out with an AND logic and the addition operation
was implemented using an Adder circuit.
The Adder circuit involved gets a carry-out from the previous adder and serves
as a carry-in for the current adder.
Diagrammatically represented as :

b0b1b2b3* a0a1a2a3

b3a0 b2a0 b1a0 a0b0

b3a1 b2a1 b1a1 b0a1
b3a2 b2a2 b1a2 b0a2
b3a3 b2a3 b1a3 b0a3

Circuit:
Result:

Thus, we have successfully designed the combinational multiplier.