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Efficient Mapping on FPGA of a Viterbi Decoder
for Wireless LANs
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ARAT UNIVERSITY
Declared under sec.3 of UGC Act, 1956,
Chennai-7

CcLober 2011

ARAT UNIVERSITY
Declared under sec.3 of UGC Act, 1956,
Chennai-7


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CerLlfled LhaL Lhls pro[ecL reporL Efficient Mapping on FPGA of a
Viterbi Decoder for Wireless LANs ~ is the bonafire work of
~UDIDA 1YOTI(P10VD002) ' done in the acadmic year oI 2011-
2012 . This project is certiIied to be done under my supervision.






Mr. . Karthik Mr. R. Varatharajn
Head oI The Department Internal Gudie
Electronics and Communication Electronics and Communication
Bharath University Bharath University
Chennai-600073 Chennai-600073

Signature oI the Internal Examiner Signature oI the External Examiner



ACKNOWLEDGEMENT


We take tremendous pleasure in acknowledging the assistance oI many
erudite personnel whom we wish to recognize wit whose help and encouragement
we were able to do this project.

To being with we would like to dedicate this prject to our Parents , who
have guide and supported us morally and emotionally all
Though the way and who have constantly elated us with spirit and conIidence.

We are greatly indebted to our beloved SECRETARY Mr .1.LAKSMI
NARAYANAN , VICE CANCELLOR Dr.K.P. TOOYAMANI and Ior
their constant support and encouragement.

We thank our EAD OF DEPARTMENT Mr..KARTIK For being
a source oI encouragement during the course oI our study. He gave us guidance an
experience man whenever we are in a Iix. He shared all his wealth oI knowledge
and vision oI excellence with us and gave us the conIidence to complete the project
without any loopholes.

We extend our sincere thank to our PROJECT CORDINATOR
R.VARATARA1AN Ior his constant encouragement . His repeated suggestions
and correction helped us in rectiIying our mistakes and present it in the best
possible way with the time he devoted durig the process is appreciative and we
thank you Ior this support.

Finally we wish to thank our department staII members , Iriends and all those who
have helped me by sparing their time Ior this project work.

Thank you all,









ASTRACT


Wireless Local Area Networks (WLANs) provide wideband wireless connectivity
between electronic devices. The two standards, Hiperlan/2 (HL/2) deIined by ETSI
BRAN |1| and the IEEE 802.11a |2| support multiple transmission modes`, providing
data rates up to 54 Mbps in the 5 GHz band, depending on channel characteristics. Both
oI them are based on Orthogonal Frequency Division Multiplexing (OFDM).

An eIIicient mapping oI an optimized hardware implementation on FPGA oI a
Viterbi decoder is presented Ior WLAN. A Iixed-point analysis is made and its
perIormance is compared with a soIt decision decoding Iloating point model
with CSI weight.

Only 6 bits are needed to perIorm the soIt quantiIication and bits to the CSI, in order to
maintain the perIormance oI the Iloating point model. A normalization method is
proposed to increase the throughput oI the decoder,
being possible to decode 172 Mbps when it is implemented in a Virtex 2 device. Power
consumption results oI the decoder implementation are presented Ior Hiperlan/2
maximum rate.

Moreover, it has been shown that it is possible to reduce the power consumption
disabling the unnecessary hardware
depending on the WLAN modes.
















TABLE OF CONTENTS

CHAPTER NO TITLE PAGE NO.
1.INTRODUCTION...............................................................................1
1.1 Wlreless CommunlcaLlons
12 MulLluser lnLerference problem assumpLlons and condlLlons
13 revlous Work
14 roposed work
2. ullL8LnCnC MuL1S1ACL uL1LC1C8 6
21 MulLluser CommunlcaLlon Model
22 MaLched lllLers and CrossCorrelaLlon MaLrlx
23 MulLlsLage ueLecLlon
24 uerlvaLlon of Lhe ulfferenclng MulLlsLage ueLecLor
23 roLoLyplng Lhe ulfferenclng MulLlsLage ueLecLlon AlgorlLhm
231 8lock descrlpLlon 232 Cascade Mode
3 8LAL 1ML MLLMLn1A1Cn16
31 SynLhesls and mplemenLaLlon 8esulLS
4 SMuLA1Cn 8LSuL1S21
3CCnCLuSCnS28
6L1L8A1u8L Su8vL? 29
78LlL8LnCLS 31