MIPI CSI2 Document Ver2.0

MIPI CSI-2
Micro Architecture Document

Rev 0.2
MosChip Technologies Ltd. Proprietary and Confidential Copyright © 2014-2024, All Rights Reserved
Revision list
Version Date Author Changes
0.1 9/1/2024 Design team Initial draft
0.2 17/2/2024 Design team Added low power mode operation, lanes are
configurable and supported with different resolutions.
Contents
1 Introduction..............................................................................................................................................8
1.1 Features.............................................................................................................................................8
1.2 Limitations.........................................................................................................................................8
1.3 Clocks and reset.................................................................................................................................9
1.4 References.........................................................................................................................................9
2 Block Diagram.........................................................................................................................................10
3 CSI2 top pin diagram..............................................................................................................................12
4 Functional Description............................................................................................................................23
4.1 Lane merger block...........................................................................................................................23
4.1.2 Pin description..........................................................................................................................24
4.1.3 Functional description..............................................................................................................34
4.2 Packet analyzer................................................................................................................................41
4.2.1 Block diagram...........................................................................................................................41
4.2.2 Pin diagram...............................................................................................................................41
4.2.3 Pin description..........................................................................................................................42
4.3 Functional description.....................................................................................................................43
4.3.1 ECC (Error Correction Code)......................................................................................................46
4.3.2 CRC -16 (Cycle redundancy check)............................................................................................53
4.4 Image data interface block..............................................................................................................60
4.4.1 pin diagram...............................................................................................................................60
4.4.2 pin description..........................................................................................................................60
4.4.3 Functional description..............................................................................................................63
4.5 AXI Top............................................................................................................................................69
4.5.1 Pin diagram...............................................................................................................................69
4.5.2 Pin description..........................................................................................................................70
4.6 Interrupt Block.................................................................................................................................77
4.6.1 Pin diagram...............................................................................................................................77
4.6.2 Pin description..........................................................................................................................77
4.7 APB4 Slave controller......................................................................................................................79
4.7.1 Pin diagram...............................................................................................................................79
4.7.2 Pin description..........................................................................................................................79
4.8 Register bank...................................................................................................................................83
4.8.1 Pin diagram........................................................................................................................83
4.8.2 Pin description..........................................................................................................................84
4.8.3 Register descriptions................................................................................................................85
4.9 System control block.......................................................................................................................93
4.9.1 Pin diagram...............................................................................................................................93
4.9.2 Pin description..........................................................................................................................93
5 Error cases..........................................................................................................................................94
6 Programming sequence......................................................................................................................95
7 Thumb Rules:..........................................................................................................................................96
List Of Figures
Figure 1. Host controller overview diagram................................................................................................9
Figure 2. CSI2 Host controller block diagram.............................................................................................11
Figure 3. CSI2 Host controller pin diagram................................................................................................13
Figure 4. Lane merger pin diagram............................................................................................................24
Figure 5. Lane merging data diagram........................................................................................................35
Figure 6. Lane 0 &1 high speed mode data transmission..........................................................................36
Figure 7. Low power mode data transmission...........................................................................................37
Figure 8. HS and LPS data transmission.....................................................................................................38
Figure 9. HS and ULPS modes....................................................................................................................39
Figure 10. Single-bit error in SoT...............................................................................................................40
Figure 11. Multi-bit error in SoT................................................................................................................40
Figure 12. Error in low power data............................................................................................................40
Figure 13. Packet analyzer block diagram..................................................................................................42
Figure 14. Packet analyzer pin diagram.....................................................................................................42
Figure 15. Long packet...............................................................................................................................44
Figure 16. Data identifier...........................................................................................................................46
Figure 17. Short packet..............................................................................................................................46
Figure 18. ECC pin diagram........................................................................................................................47
Figure 19. 24-bit ECC on Rx side Including Error Correction diagram........................................................50
Figure 20. Error Correction Code diagram.................................................................................................53
Figure 21. CRC-16 pin diagram..................................................................................................................54
Figure 22. CRC-16 wave form....................................................................................................................57
Figure 23. Packet analyzer FSM.................................................................................................................57
Figure 24. Controller block waveform.......................................................................................................59
Figure 25. Format of image transferred....................................................................................................59
Figure 26. IDI pin diagram..........................................................................................................................61
Figure 27. IDI state machine......................................................................................................................64
Figure 28. Transferring for short packets waveform.................................................................................67
Figure 29. Transferring for long packet waveform....................................................................................68
Figure 30. Transferring of frame waveform...............................................................................................69
Figure 31. AXI Top pin diagram..................................................................................................................70
Figure 32. Interrupt pin diagram...............................................................................................................78
Figure 33. Generation of interrupt 1 waveform........................................................................................79
Figure 34. Generation of interrupt 2 waveform........................................................................................79
Figure 35. APB4 SLAVE pin diagram...........................................................................................................80
Figure 36. APB4 slave FSM.........................................................................................................................81
Figure 37. APB4 slave Write timing diagram..............................................................................................82
Figure 38 .APB4 slave read timing diagram...............................................................................................83
Figure 39. Register bank pin diagram........................................................................................................84
Figure 40. System control block pin diagram.............................................................................................94
List Of Tables
Table 1. Abbreviations.................................................................................................................................7
Table 2. CSI2 HOST CONTROLLER clock signals............................................................................................9
Table 3. CSI2 HOST CONTROLLER reset signals............................................................................................9
Table 4. CSI2 Host controller IO pin list.....................................................................................................13
Table 5. Lane merger pin description........................................................................................................24
Table 6. Timing parameters description....................................................................................................40
Table 7. Packet analyzer I/O pin list...........................................................................................................42
Table 8. Long packet data types................................................................................................................44
Table 9. Short packet data types...............................................................................................................46
Table 10. ECC pin description....................................................................................................................47
Table 11. ECC syndrome table...................................................................................................................48
Table 12. CRC pin description....................................................................................................................53
Table 13. IDI pin description......................................................................................................................60
Table 14. AXI Top pin description..............................................................................................................70
Table 15. Interrupt block...........................................................................................................................77
Table 16. APB4 SLAVE controller IO pin list...............................................................................................79
Table 17. Register bank IO pin list.............................................................................................................84
Table 18. Register block.............................................................................................................................85
Table 19. System control pin list................................................................................................................93
Table 20. Error cases.................................................................................................................................94
Table 1. Abbreviations
CSI Camera Serial Interface

DSI Display Serial Interface
DI Data Identifier
DT Data Type
ECC Error Correction Code
PF Packet Footer
PH Packet Header
RGB Red, Green, Blue (Color Format)
SoT Start of Transmission
EoT End of Transmission
WC Word Count
LP Low Power
APB Advanced Peripheral Bus
MIPI Mobile Industry Processor Interface
IDI Image Data Interface
UI Unit interval
Freq Frequency
DT Data type
VC Virtual channel
FIFO First In First Out
1 Introduction
This document describes the design architecture of MIPI CSI (Camera Serial Interface) Host
controller IP. MIPI (Mobile Industry Processor Interface) is a set of rules and standards that helps
different parts inside smartphones to talk to each other more efficiently. It allows connections between
different sensors and processors in mobile devices. CSI-2 is one of the MIPI standardized interfaces
which stands for Camera serial interface. CSI-2 is an interface between camera device and host
processor. CSI-2 efficiently transmits high quality image data or video between camera device and
processor.
Figure 1. Host controller overview diagram
1.1 Features
 MIPI CSI features
 Multi lane merging (Data lanes are configurable).
 Long and short packet decoding.
 All RGB formats supported - 16 to 24 bits per pixel. (444,555,565,666,888)
 Resolution supported - (640 x 480) pixels, (1280 x 720) pixels, (1920 x 1080) pixels.
 Single error detection and correction (SEDC)
 Supports Cyclic redundancy Check.
 Supports 32-bit IDI interface for payload.
 ECC Multibit error detection.
 Error cases are supported.
 AXI features
 Supports fixed burst only.
 Supports aligned address only.
 Supports write address, write data and write response channels.
1.2 Limitations
 Outstanding, Data interleaving is not supported in AXI.
 Increment, Wrapping, narrow transfers are not supported in AXI.
 Time out condition is not supported in AXI.
 Unaligned addresses are not supported in AXI.
1.3 Clocks and reset
Table 2. CSI2 HOST CONTROLLER clock signals
S.no Signal name Direction Freq(MHz) Description

1. sys_clk_i Input 375 Input clock for system. Global clock
2. pclk_i Input 125 Input clock for APB4 slave controller
3. rxclkesc_n_i Input 20 Input clock for low power mode
4. rxbyteclkhs_i Input 125 Input clock for high-speed

transmission.
5. lane_byte_clk_o Output 125/93.75/62.5/ Output clock is generated based on
number of lanes selected:
31.25 Lane 0 : 31.25 MHz
Lane 0,1,2 : 62.5 MHz
Lane 0,1,2 : 93.75 MHz
Lane 0,1,2,3: 125 MHz
6. aclk_i Input 250 Input clock for AXI block
7. clk_data_o Output lane_byte_clk_o Output clock generated by IDI
Table 3. CSI2 HOST CONTROLLER reset signals
S.no Reset name Direction Freq (MHz) Description

1. presetn_i Input Async Active-low reset for APB4
2. arst_n Input Async Active-low reset for AXI block
3. sys_rst_n Input Async Active-low reset
1.4 References
1. https://caxapa.ru/thumbs/799244/MIPI_Alliance_Specification_for_Camera_S.pdf
2. https://docs.xilinx.com/r/en-US/pg202-mipi-dphy/Example-10-Low-Power-Data-Receive-with-
Synchronization-Error-at-D-PHY-RX-Slave-Side
3. https://docs.xilinx.com/r/en-US/pg232-mipi-csi2-rx
4. Design ware Cores MIPI CSI-2 Host Controller Databook,1.04a
5. https://www.arasan.com/wp-content/uploads/2019/08/Total-MIPI-Camera-IP-Solution_CSI-2-
v1.3_Aug-2019.pdf
6. https://sci-hub.3800808.com/10.1109/ISCE.2013.6570183
2 Block Diagram
The CSI-2 Host controller IP consists of sub modules
 System control
 Lane merger
 Packet analyzer
 Image Data Interface block
 Image Data Interface Controller
 APB4 slave controller
 Register bank
 Interrupt block
The Block level interface diagram is shown in figure-2, which includes System control, Lane
merger, Packet analyzer, Image data interface, Image data interface controller, AXI master, APB4 slave
controller, Register bank and Interrupt block. Each sub module functionality is explained in respective
section
Figure 2. CSI2 Host controller block diagram
 System control Block:
1. This block generates the required frequencies by dividing sys_clk_i(375 MHz) based on
N_LANES register.
2. N_LANES register is updated when the clock lane is not in the stop state.
 Lane merger:
1. It merges the data on lanes based on round robin process.
2. When the data lanes are in high-speed mode then only the data is merged, if the data lanes
are in any one of the escape modes, data is not merged.
3. Along with the merged data, valid is generated.
4. Some fields of ERR1 and ERR2 registers has been updated.
 Packet analyzer:
1. Packet analyzer receives the 32-bit merged data from lane merger when the valid is high.
2. If the received data is frame start, line start, frame end, line end or packet header of long
packet then data is sent to the ECC block. ECC block calculates the ECC, detects and correct
single-bit error and detects multi-bit errors.
3. If the received data from lane merger is payload, it is sent to the CRC block. CRC block
calculates the CRC for the payload and compares the CRC with the received CRC.
4. Based on the results of ECC and CRC, ERR1 and ERR2 registers has been updated. Based on
results from ECC, packet analyzer decides whether the packet have to be sent to the IDI or it
has to be dropped.
 Image data Interface block:
1. It receives the data from packet analyzer when the valid is high.
2. IDI generates the signals by decoding the packet information.
 AXI Master Interface:
1. It receives the signals from IDI block. IDI_to_FIFO_Controller generates the required signals
for Asynchronous FIFO. FIFO stores the data in the memory.
2. AXI master gets the rdata by reading from asynchronous FIFO and it drives the data onto AXI
interface.
 APB4 Slave controller:
1. All the required signals for storing data into the registers and reading from the registers are
generated by APB4 Slave controller.
2. APB4 slave receives the register data during read operation.
 Register Bank:
1. The configuration of registers (CSI host and AXI master) is done through APB4 slave
interface. It has both R/W and RO registers.
2. The registers such as MSK1, MSK2, PHY_SHUTDOWNZ, DPHY_RSTZ, WRITE_REG,
CONTROL_REG, MODE_REG, CSI_RESETN and NUM_BYTES_REG values are stored based on
configuration. Based on the control signals from APB4 Slave Controller, register bank either
stores the value into the register or gives the register value to APB4 Slave Controller.
3. The registers N_LANES, ERR1, ERR2 and PHY_STATE fields will be updated by the lane
merger and packet analyzer.
 Interrupt Block:
1. Generates interrupt signals based on the value updated in the ERR1 and ERR2 registers
independent of MSK1 and MSK2 registers.
3 CSI2 top pin diagram

The below figure shows the pin diagram of MIPI_CSI-2 HOST CONTROLLER TOP.
Figure 3. CSI2 Host controller pin diagram
The table below describes the IO signals in detail.
Table 4. CSI2 Host controller IO pin list
S.no Signal name Directions Width Freq (MHz) Description

1 sys_clk_i Input 1 375 A global clock runs with frequency 375MHz.
2 sys_rst_n Input 1 Async Global active-low reset
CLOCK LANE
High speed receives byte clock. This clock is not
2 rxbyteclkhs_i Input 1 125 continuous and only available for sampling when Rx
clock lane is in high-speed mode.
Lane is in Stop state. This Active-High signal indicates
3 stopstate_i Input 1 Async
that the Lane module is currently in the Stop state.
ULP State (not) Active. This Active-Low signal is asserted
4 ulpsactivenot_i Input 1 20 to indicate that the Lane is in the ULP state. This signal
indicates that the Lane is in the Ultra Low Power state.
Clock lane in ULP (ultra-low power) state. This signal
5 rxulpsclknot_i Input 1 20 indicates that the clock lane has entered Ultra-low
power state.
DATA LANE-0
High-Speed Receive Data. 8-bit high-speed data received
6 rxdatahs_0_i Input 8 125 by the lane module. Data is transferred on rising edge of
rxbyteclkhs from lane-0.
High-Speed Receive Data Valid. This active high signal
7 rxvalidhs_0_i Input 1 125 indicates that the lane module is driving valid data to the
protocol on the Rxdatahs.
High-Speed Reception Active. This active high signal
8 rxactivehs_0_i Input 1 125 indicates that the lane module is actively receiving a
high-speed transmission from the lane-0.
Receiver Synchronization Observed. This active high
signal indicates that the lane module has seen an
appropriate synchronization event. In a typical high-
9 rxsynchs_0_i Input 1 125
speed transmission, Rxsynchs is high for one cycle of
rxbyteclkhs at the beginning of a high-speed transmission
when rxactivehs is first asserted for lane-0.
Escape Mode Receive Clock for lane-0. In low power
10 rxclkesc_0_i Input 1 20 mode data will be taken at rising edge of rxclkesc clock
signal.
Escape Low-Power Data Receive Mode. This active-High
11 rxlpdtesc_0_i Input 1 20 signal is asserted to indicate that the lane module is in
low-power data receive mode on lane-0.
Escape Mode Receive Data. Data is transferred on rising
12 rxdataesc_0_i Input 8 20
edges of rxclkesc for lane-0.
13 rxvalidesc_0_i Input 1 20 Escape Mode Receive Data Valid. This active-High signal
indicates that the lane module is driving valid data to the
protocol on the rxdataesc[7:0] for lane-0.
Escape Ultra-Low Power (Receive) Mode. This active-
14 rxulpmesc_0_i Input 1 Async High signal is asserted to indicate that the lane module
has entered the ultra-low power state.
Lane is in Stop state. This Active-High signal indicates
15 stopstate_0_i Input 1 Async
that the Lane module is currently in the Stop state.
ULP State (not) Active. This active-Low signal is asserted
16 ulpsactivenot_0_i Input 1 20 to indicate that the Lane is in the ULP state. This signal
Start-of-Transmission (SoT) Error. If the high-speed SoT
sequence is corrupted, but in such a way that proper
synchronization can still be achieved, this active-High
17 errsoths_0_i Input 1 125
signal is asserted for one cycle of rxbyteclkhs. This
indicates a single-bit of error in SoT but further data can
be considered for lane-0.
Start-of-Transmission Synchronization Error. If the high-
speed SoT sequence is corrupted in a way that proper
18 errsotsynchs_0_i Input 1 125
synchronization cannot be expected, this active-High
signal is asserted for one cycle of rxbyteclkhs for lane-0.
Escape Entry Error. If an unrecognized escape entry
command is received, this active-High signal is asserted
19 erresc_0_i Input 1 Async
and remains asserted until the next change in line state
for lane-0.
Low-Power Data Transmission Synchronization Error. If
the number of bits received during a low-power data
transmission is not a multiple of eight when the
20 errsyncesc_0_i Input 1 Async
transmission ends, this active-High signal is asserted and
remains asserted until the next change in line state for
lane-0.
DATA LANE-1
High-Speed Receive Data. Eight-bit high-speed data
21 rxdatahs_1_i Input 8 125 received by the lane module. Data is transferred on
rising edges of rxbyteclkhs from lane-1.
protocol on the Rxdatahs from lane-1.
high-speed transmission from lane-1.
24 rxsynchs_1_i Input 1 125 Receiver Synchronization Observed. This active high
speed transmission, rxsynchs is high for one cycle of
signal.
low-power data receive mode.
Escape Mode Receive Data. Data is transferred on rising
edges of rxclkesc for lane-1.
Escape Mode Receive Data Valid. This active-High signal
29 rxvalidesc_1_i Input 1 20 indicates that the lane module is driving valid data to the
Lane is in Stop state. This active-High signal indicates that
the Lane module is currently in the Stop state.
ULP State (not) Active. This Active-Low signal is asserted
for lane-1.
lane-1.
DATA LANE-2
High-Speed Receive Data. Eight-bit high-speed data
36 rxdatahs_2_i Input 8 125
received by the lane module. Data is transferred on
protocol on the rxdatahs from lane-2.
high-speed transmission from the lane-2.
signal.
Escape Low-Power Data Receive Mode.This Active-High
Escape Mode Receive Data. This is the 8-bit escape mode
low-power data received by the lane module. The signal
connected to rxdataesc[0] is received first. Data is
transferred on rising edges of rxclkesc for lane-2.
be considered for lane-2
for lane-2.
lane-2.
DATA LANE-3
High-Speed Receive Data. 8-bit high-speed data received
51 rxdatahs_3_i Input 8 125 by the lane module. Data is transferred on rising edges of
52 rxvalidhs_3_i Input 1 125 indicates that the lane module is driving valid data to
the protocol on the rxdatahs from lane-3.
high-speed transmission from lane-3.
55 rxclkesc_3_i Input 1 20 mode data will be taken at the rising edge of rxclkesc
clock signal.
Escape Mode Receive Data. This is the 8-bit escape mode
low-power data received by the lane module. The signal
connected to rxdataesc[0] is received first. Data is
transferred on rising edges of rxclkesc for lane-3.
protocol on the rxdataesc[7:0] output for lane-3.
to indicate that the Lane is in the ULP state. This signal
61 ulpsactivenot_3_i Input 1 20
indicates that the Lane is in the Ultra Low Power (ULP)
state.
for lane-3.
lane-3.
AXI4 INTERFACE SIGNALS
1 AXI clock. Write & Read address, write & Read data
66 aclk_i Input 250
channels, asserted with synchronous with aclk_i.
67 arst_n Input 1 Async Active-low axi reset signal.
WRITE ADDRESS CHANNEL SIGNALS
Write address ready. This signal indicates that the slave
is ready to accept an address and associated control
68 awready_i Input 1 250 signals:
1 = slave ready
0 = slave not ready.
Write address ID. This signal is the identification tag for
69 awid_o Output 4 250
the write address group of signals.
Write address valid. This signal indicates that valid write
address and control information are available:
1 = address and control information available
70 awvalid_o Output 1 250
0 = address and control information not available.
The address and control information remain stable until
the address acknowledges the signal,
Write address. The write address bus gives the address
of the first transfer in a write burst transaction. The
71 awaddr_o Output 32 250
associated control signals are used to determine the
addresses of the remaining transfers in the burst.
Burst length. The burst length gives the exact number of
72 awlen_o Output 8 250 transfers in a burst. This information determines the
number of data transfers associated with the address.
Burst size. This signal indicates the size of each transfer
73 awsize_o Output 3 250 in the burst. Byte lane strobes indicate exactly which
byte lanes to update.
Burst type. The signal indicates the type of burst:
00: Fixed burst
74 awburst_o Output 2 250
01: Incrementing burst
10: Wrapping burst
READ ADDRESS CHANNEL SIGNALS
Read address ready. This signal indicates that the slave is
ready to accept an address and associated control
75 arready_i Input 1 250
signals:
1 = slave ready, 0 = slave not ready.
Read address ID. This signal is the identification tag for
76 arid_o Output 4 250
the read address group of signals.
Read address valid. This signal indicates, when HIGH,
that the read address and control information is valid
and will remain stable until the address acknowledge
77 arvalid_o Output 1 250
signal, arready, is high.1 = address and control
information valid 0 = address and control information
not valid.
Read address. The read address bus gives the initial
address of a read burst transaction. Only the start
address of the burst is provided and the control signals
78 araddr_o Output 32 250
that are issued alongside the address detail how the
address is calculated for the remaining transfers in the
burst.
Burst length. The burst length gives the exact number of
79 arlen_o Output 8 250 transfers in a burst. This information determines the
number of data transfers associated with the address.
Burst size. This signal indicates the size of each transfer
80 arsize_o Output 3 250
in the burst.
Burst type. The burst type, coupled with the size
81 arburst_o Output 2 250 information, details how the address for each transfer
within the burst is calculated.
WRITE DATA CHANNEL SIGNALS
Write ready. This signal indicates that the slave can
82 wready_i Input 1 250 accept the write data:
1 = slave ready , 0 = slave not ready.
Write valid. This signal indicates that valid write data and
strobes are available:
83 wvalid_o Output 1 250
1 = write data and strobes available
0 = write data and strobes not available.
84 wdata_o Output 32 250 Write data. The write data bus
Write strobes. This signal indicates which byte lanes to
update in memory. There is one write strobe for each 8-
85 wstrb_o Output 4 250
bits of the write data bus. Therefore, wstrb[n]
corresponds to wdata [(8 × n) + 7:(8 × n)].
Write last. This signal indicates the last transfer in a write
86 wlast_o Output 1 250
burst.
WRITE RESPONSE CHANNEL SIGNALS
Response ID. The identification tag of the write response.
87 bid_i Input 4 250 The BID value must match the AWID value of the write
transaction to which the slave is responding.
Write response valid. This signal indicates that a valid
write response is available:
88 bvalid_i Input 1 250
1 = write response available
0 = write response not available.
Write response. This signal indicates the status of the
89 bresp_i Input 1 250 write transaction. The allowable responses are OKAY,
EXOKAY, SLVERR, and DECERR.
Response ready. This signal indicates that the master can
90 bready_o Output 1 250 accept the response information.
1 = master ready, 0 = master not ready.
READ DATA CHANNEL SIGNALS
Read ID tag. This signal is the ID tag of the read data
group of signals. The RID value is generated by the slave
91 rid_i Input 4 250
and must match the ARID value of the read transaction
to which it is responding.
Read valid. This signal indicates that the required read
data is available and the read transfer can complete:
92 rvalid_i Input 1 250
1 = read data available
0 = read data not available.
93 rdata_i Input 32 250 Read data. The read data bus
Read response. This signal indicates the status of the
94 rresp_i Input 2 250 read transfer. The allowable responses are OKAY,
EXOKAY, SLVERR, and DECERR.
Read last. This signal indicates the last transfer in a read
95 rlast_i Input 1 250
burst.
Read ready. This signal indicates that the master can
96 rready_o Output 1 250 accept the read data and response information:
1 = master ready, 0 = master not ready.
APB4 SIGNALS
97 pclk_i Input 1 125 Clock with a frequency of 125MHZ
98 preset_n Input 1 Async preset_n is active low reset signal
99 psel_i Input 1 125 Slave Select Input
Enable Input Indicates the beginning of a valid transfer
100 penable_i Input 1 125
cycle.
Write enable which indicate
101 pwrite_i Input 1 125
pwrite_i = 0, read transfer , pwrite_i = 1, write transfer
It is a 32-bit address signal to write/read from register
102 paddr_i Input 32 125
address.
103 pstrb_i Input 4 125 It is a 4bit strobe signal to indicate valid bytes
It is a 32-bit data signal used to write the data into the
104 pwdata_i Input 32 125
registers.
It is a 32-bit data signal used to read the data from
105 prdata_o Output 32 125
register
Peripheral ready Output. This signal indicates the
106 pready_o Output 1 125
completion of transfer.
Slave error signal, which indicates the error in the
107 pslverr_o Output 1 125
transfer.
D-PHY SIGNALS
D-PHY data lane enabled. phy_enable[0]: Enable for
lane-0 , if exists
phy_enable[1]: Enable for lane-1 ,if exists
108 phy_enable_o Output 4 125
phy_enable[3]: Enable for lane-3 ,if exists.
When phy_shutdownz_o is low, phy_enable is 4’d0.
When phy_shutdownz_o is high, phy-enable is 4’b1111,
indicating all the lanes are existing.
109 phy_shutdownz_o Output 1 125 Active-low D-PHY shutdown
D-PHY clock lane enable. phy_enable_clk_o is high when
110 phy_enable_clk_o Output 1 125 phy_shutdownz_o is high, phy_enable_clk_o is low when
phy_shutdownz_o is low
111 phy_rstz_o Output 1 125 Active-low D-PHY reset
INTERRUPT SIGNALS
Interrupt signal is asserted if one of the fields of MSK1 is
112 intr1_o Output 1 125 low and ERR1 of that field is high. intr1_o is low when
the ERR1 register is read
Interrupt signal is asserted if one of the fields of MSK2 is
113 intr2_o Output 1 125 low and ERR2 of that field is high. intr2_o is low when
the ERR1 register is read
4 Functional Description
The functional description contains all the internal blocks information: Lane merger, Packet
analyzer, Image data interface, Interrupt, Register bank and APB4 slave controller blocks. Each internal
block provides the detailed information of pin diagram, pin description, FSM (if required) and
waveforms.
4.1 Lane merger block

Lane merger functional description contains pin diagram, pin description and operating FSM which is
mentioned below.
4.1.1 Pin diagram

The below figure shows the pin diagram of LANE MERGER TOP.
Figure 4. Lane merger pin diagram
4.1.2 Pin description
The below table describes the IO signals in detail.

Table 5. Lane merger pin description

1 sys_clk_i Input 1 375 A global clock with frequency 375MHz.
2 csi_reset_n Input 1 Async Active-low reset for CSI2 host controller.
CLOCK LANE
High speed receives byte clock. This clock
is not continuous and only available for
3 rxbyteclkhs_i Input 1 125
sampling when Rx clock lane is in high-
speed mode.
Lane is in Stop state. This Active-High
4 stopstate_i Input 1 Async signal indicates that the Lane module is
currently in the Stop state.
ULP State (not) Active. This Active-Low
signal is asserted to indicate that the
5 ulpsactivenot_i Input 1 20 Lane is in the ULP state. This signal
indicates that the Lane is in the Ultra
Low Power (ULP) state.
Clock lane in ULP (ultra-low power) state.
6 rxulpsclknot_i Input 1 20 This signal indicates that the clock lane
has entered Ultra-low power state.
DATA LANE-0
High-Speed Receive Data. 8-bit high-
speed data received by the lane module.
Data is transferred on rising edges of
High-Speed Receive Data Valid. This
active high signal indicates that the lane
8 rxvalidhs_0_i Input 1 125
module is driving valid data to the
High-Speed Reception Active. This active
high signal indicates that the lane
9 rxactivehs_0_i Input 1 125
module is actively receiving a high-speed
transmission from the lane-0.
Receiver Synchronization Observed. This
module has seen an appropriate
synchronization event. In a typical high-
speed transmission, rxsynchs is high for
one cycle of rxbyteclkhs at the beginning
of a high-speed transmission when
rxactivehs is first asserted for lane-0.
Escape Mode Receive Clock for lane-0. In
11 rxclkesc_0_i Input 1 20 low power mode data will be taken at
rising edge of rxclkesc clock signal.
Escape Low-Power Data Receive Mode.
This Active-High signal is asserted to
12 rxlpdtesc_0_i Input 1 20
indicate that the lane module is in low-
power data receive mode for lane-0.
Escape Ultra-Low Power (Receive) Mode.
This active-High signal is asserted to
13 rxulpmesc_0_i Input 1 Async
indicate that the lane module has
entered the ultra-low power state.
Escape Mode Receive Data.
This is the 8-bit escape mode low-power
data received by the lane module. The
signal connected to rxdataesc[0] is
received first. Data is transferred on
rising edges of rxclkesc for lane-0.
Escape Mode Receive Data Valid. This
active-High signal indicates that the lane
15 rxvalidesc_0_i Input 1 20 module is driving valid data to the
protocol on the rxdataesc[7:0] output for
lane-0.
16 stopstate_0_i Input 1 Async signal indicates that the Lane module is
17 ulpsactivenot_0_i Input 1 20 Lane is in the ULP state. This signal
Start-of-Transmission (SoT) Error. If the
high-speed SoT sequence is corrupted,
but in such a way that proper
synchronization can still be achieved, this
active-High signal is asserted for one
cycle of rxbyteclkhs. This indicates a
single-bit of error in SoT but further data
can be considered for lane-0.
Start-of-Transmission Synchronization
Error. If the high-speed SoT sequence is
corrupted in a way that proper
synchronization cannot be expected, this
cycle of rxbyteclkhs for lane-0.
Escape Entry Error. If an unrecognized
escape entry command is received, this
20 erresc_0_i Input 1 Async active-High signal is asserted and
remains asserted until the next change in
line state for lane-0.
Low-Power Data Transmission
Synchronization Error. If the number of
bits received during a low-power data
transmission is not a multiple of eight
when the transmission ends, this active-
High signal is asserted and remains
asserted until the next change in line
state for lane-0.
DATA LANE-1
High-Speed Receive Data. Eight-bit high-
speed data received by the
lane module. Data is transferred on
active high signal indicates that the
23 rxvalidhs_1_i Input 1 125
lane module is driving valid data to the
high signal indicates that the
lane module is actively receiving a high-
speed transmission from the lane-1.
active high signal indicates that
the lane module has seen an appropriate
power data receive mode.
Escape Mode Receive Data Valid.
This active-High signal indicates that the
30 rxvalidesc_1_i Input 1 20 lane module is driving valid data to the
lane-1.
Lane is in Stop state.
This Active-High signal indicates that the
Lane module is currently in the Stop
state.
ULP State (not) Active.
This Active-Low signal is asserted to
32 ulpsactivenot_1_i Input 1 20 indicate that the Lane is in the ULP state.
This signal indicates that the Lane is in
the Ultra Low Power (ULP) state.
33 errsoths_1_i Input 1 125 high-speed SoT sequence is corrupted,
Error.If the high-speed SoT sequence is
Escape Entry Error.If an unrecognized
Synchronization Error.If the number of
state for lane-1.
DATA LANE-2
speed data received by thelane module.
37 rxdatahs_2_i Input 8 125 The signal connected to RxDataHS[0]
was received first. Data is transferred on
38 rxvalidhs_2_i Input 1 125 module is driving valid data to the
protocol on the rxdatahs output from
lane-2.
high signal indicates that the
lane module is actively receiving a high-
speed transmission from the lane-2.
40 rxsynchs_2_i Input 1 125 active high signal indicates that the lane
power data receive mode.
Escape Mode Receive Data Valid. This
active-High signal indicates that the lane
45 rxvalidesc_2_i Input 1 20 module is driving valid data to the
lane-1.
signal indicates that the Lane module is
currently in the Stop state. Also, the
protocol can use this signal to indirectly
determine if the PHY line levels are in the
LP-11 state.
Error.If the high-speed SoT sequence is
state for lane-2.
DATA LANE-3
speed data received by the lane module.
Data is transferred on rising edges of
53 rxvalidhs_3_i Input 1 125 module is driving valid data to the
protocol on the rxdatahs output from
lane-3.
high signal indicates that the lane
module is actively receiving a high-speed
transmission from the lane-3.
power data receive mode on lane-3
Escape Mode Receive Data. This is the 8-
bit escape mode low-power data
received by the lane module. The signal
connected to rxdataesc[0] is received
first. Data is transferred on rising edges
of rxclkesc for lane-3.
Escape Mode Receive Data Valid.
This active-High signal indicates that the
60 rxvalidesc_3_i Input 1 20
lane module is driving valid data to the
61 stopstate_3_i Input 1 Async signal indicates that the Lane module is
63 errsoths_3_i Input 1 125 but in such a way that proper
Error. If the high-speed SoT sequence is
state for lane-3.
Input clock from system control, which is
generated based on N_LANES register.
125/93.75/ Lane 0 : 31.25 MHz
67 lane_clock_i Input 1
62.5/31.25 Lane 0,1,2 : 62.5 MHz
Lane 0,1,2 : 93.75 MHz
Lane 0,1,2,3: 125 MHz
DPHY-SIGNALS
D-PHY data lane enabled.
phy_enable[0]: Enable for lane-0 , if
exists
68 phy_enable_o Output 4 125 phy_enable[3]: Enable for lane-3 ,if exists
When phy_shutdownz_o is low,
phy_enable_o is 4’d0. When
phy_shutdownz_o is high, phy_enable_o
is 4’b1111, indicating all the lanes are
existing.
69 Phy_enable_clk_o Output 1 125 D-PHY clock lane enable.
Phy_enable_clk_o is high when
phy_shutdownz_o is high,
phy_enable_clk_o is low when
phy_shutdownz_o is low
phy_shutdownz_
70 Output 1 125 Active-low D-PHY shutdown.
o
71 phy_rstz_o Output 1 125 Active-low D-PHY reset.
PACKET ANALYZER
This signal indicates merging of 32-bit
lane2packet_anyl lane_byte_ data and it is synchronous to
72 Output 32
z_o clk_o lane_byte_clk_o it will be either 125/
93.75/62.5/31.25 MHz.
Indicates valid merged data is sending to
lane_byte_ packet analyzer and it is synchronous to
73 valid_2packet_o Output 1
clk_o lane_byte_clk_o it will be either 125/
93.75/62.5/31.25 MHz.
REGISTER BANK
error_1_i signal of 4 bits indicates
74 lerror_1_o Output 4 125
errorsyncsoths for four datalanes.
error_2_i signal of 8-bits indicates
75 lerror_2_o Output 8 125
errorsoths for four datalanes.
4.1.3 Functional description
 Lane merger functionality is to manage the PPI interface signals. It detects whether the PPI
signals of data lanes are in Active mode (high-speed mode) or in escape mode.
 In high-speed mode image data is received and sent for merging operation. In escape mode no
data is given for merging operation.
 Whenever 32-bit merged data is sent through lane2packet_anlyz_o pin, valid_2packet_o signal
is asserted.
 A lane can be sending active high-speed data, or it can be in escape mode. In escape mode the
lane can be in ultra-low power mode or low power mode.
 In low power mode blanking data is received which is not given for merging operation. In ultra-
low power mode, no data is received, and no data is sent for merging operation.
Figure 5. Lane merging data diagram
Wave forms
Figure 6. Lane 0 &1 high speed mode data transmission
Figure 6 shows the data transmission in high-speed mode on data lane-0 & 1. The same functionality will be repeated on each data lane based
on the number of active lanes. Before receiving the first byte in High-speed mode the data lanes should maintain the minimum time interval [1].
When rxactivehs_n is high at the same pulse rxsynchs_n has to be high to establish the synchronization. From the next active edge, the high-
speed data must receive along with rxvalidhs_n to indicate that is the valid data which need to be considered. After last byte of high-speed data
is being transmitted the rxactivehs_n should be low. While high speed data is being received the escape mode signals will not be considered.
[1] : TA = TLPX+ THS_PREPARE
Figure 7. Low power mode data transmission
Figure 7 shows the data transmission in low power mode on data lane-0 & data lane-1. The same functionality will be repeated on each data
lane based on the number of active lanes. When rxlpdtesc_n is high it indicates the data lane has entered to low power mode. In this mode the
low power data will be transmitted on the rxdataesc_n pin along rxvalidesc_n indicating the valid data is being transmitted.
[2]: TC = THS_TRIAL + TCLK_POST

[3]: TD = TCLK_TRIAL
[4]: TE = THS_EXIT + TLPX + TCLK_PREPARE
[5]: TF = TCLK_ZERO
Figure 8. HS and LPS data transmission
Figure 8 shows the timing parameters required for data transmission in high speed and low power mode on data lane-0. The same functionality
will be repeated on each data lane based on the number of active lanes. In between every Active mode (high speed mode) and escape mode
(ultra-low power or low power mode) on data lanes there is a stopstate_n_i asserting for unspecified time period. The above figure also shows
the behavior of the rxbyteclkhs of the clock lane along with stop state. The occurrence of first stop state on the clock and data lanes which is
followed by assertion of csi_enable bit to high is known as Initialization state. Therefore, the time for which the lanes must go through the
initialization state is for T (time) > 100 us.
[6]: Tca = TLPx + TCLK_PREPARE [10]: Tdb = THS_TRIAL + TCLK_POST

[7]: Tcb = TCLK_ZERO [11]: Tcz = TCLK_ZERO
[8]: Tcc = TCLK_PRE [12] : TG = THS_EXIT
[9]: Tda = TLPx + THS_PREPARE + THS_ZERO
Figure 9. HS and ULPS modes
Figure 9 shows the timing parameters when clock lanes switch to ULPS mode after the last data lane enters in LPS and the behavior of data lane-
0 switching from HS mode to ULPS. The same functionality will be repeated on each data lane based on the number of active lanes. The Rx data
lane ULPS entry is indicated by assertion of rxulpmesc_n_i along with the assertion of ulpsactivenot_n_i (active-low). ULPS exit is marked by
reception of MARK-1 on the line and ulpsactivenot_n_i de-assertion. After receiving MARK-1 for time Twakeup(1ms minimum) rxulpmesc_n_i is
de-asserted. Similarly on the clock lane ULPS entry is indicated by assertion of rxulpsclknot_i (active low) along with the assertion of
ulpsactivenot_i (active-low).
Figure 10. Single-bit error in SoT
Figure 10 shows the single-bit error in SoT in high-speed data transmission. This is indicated by asserting
rxsynchs_n_i along with errsoths_n_i for one pulse on high-speed clock. It also tells the data which is
transmitted on the next rising edge can be considered and sent further.
Figure 11. Multi-bit error in SoT
Figure 11 shows the multi-bit error in SoT in high-speed data transmission. This is indicated by asserting
errsotsynchs_n_i for one pulse on high-speed clock. Proper synchronization is not expected as it
indicates SoT sequence is corrupted. Further data is not sent for merging operation. If there is
errsotsynchs in any of the lanes, the whole packet is dropped at the lane merger.
Figure 12. Error in low power data
Figure 12 shows the data transmission error in low power mode on data lane-0. The same functionality will be repeated
on each lane based on the number of active lanes. Low power data transmission synchronization error (errsyncesc_n_i).
Indicates if the number of bits received during a low-power data transmission is not a multiple of eight when the
transmission ends, this active-High signal is asserted and remains asserted until the next change in line state.
Table 6. Timing parameters description
S.no Parameter Description min max unit
1 TLPX Transmitted length of any Low-Power state 50 - ns

period
2 THS_PREPARE + THS-PREPARE + time that the transmitter 145 ns + 10*UI 85 ns + 6*UI ns

THS_ZER0 drives the HS-0 state prior to transmitting
the Sync sequence.
3 THS_TRIAL Time that the transmitter drives the flipped Max (n*8*UI, 60 ns - ns
differential state after last payload data bit +n*4*UI)
of a HS transmission burst
4 THS_SKIP Time interval during which the HS-Rx should 40 55 ns + 4*UI ns

ignore any transitions on the Data Lane,
following a HS burst. The end point of the
interval is defined as the beginning of the
LP-11 state following the HS burst.
5 TCLK_POST Time that the transmitter continues to send 60 ns + 52*UI - ns

HS clock after the last associated Data Lane
has transitioned to LP Mode. Interval is
defined as the period from the end of THS-
TRAIL to the beginning of TCLK-TRAIL.
6 TCLK_TRIAL Time that the transmitter drives the HS-0 60 - ns

state after the last payload clock bit of a HS
transmission burst.
7 THS_EXIT Time that the transmitter drives LP-11 100 - ns

following a HS burst.
8 TCLK-PREPARE + TCLK-PREPARE + time that the transmitter 300 - ns

TCLK-ZERO drives the HS-0 state prior to starting the
Clock.
9 TCLK_PRE Time that transmitter drives HS clock before 8 - ns

any data lanes begin the transition from LS
to HS mode
4.2 Packet analyzer
Packet analyzer contains Controller block, ECC and CRC. Each block provides detailed information of
pin diagram, pin description, FSM (if required) and waveforms.
4.2.1 Block diagram
Figure 13. Packet analyzer block diagram
4.2.2 Pin diagram
The below figure shows the pin diagram of packet analyzer.
Figure 14. Packet analyzer pin diagram

Table 7. Packet analyzer I/O pin list
Packet analyzer runs with a

125/93.75/62.5
1 lane_byte_clk_i Input 1 frequency of 125/93.75/
/31.25
/62.5/31.25 MHz.
Active-low reset for packet
2 csi_reset_n Input 1 Async
Analyzer.
Lane merger to packet analyzer block
Packet analyzer input of 32-
3 lane2packet_anylz_i Input 32 lane_byte_clk_o
bit from the lane merger.
4 Valid_2packet_i Input 1 lane_byte_clk_o Indicates valid merged data
nlanes_i signal updated
5 nlanes_i Input 2 lane_byte_clk_o
based on N_LANES register.
Register bank signals
perror_1_o signal is 25-bit
6 perror_1_o Output 25 125 error1 register data signal
from register block
perror_2_o signal is 16-bit
7 perror_2_o Output 16 125 error 2 register data signal
from register block.
Packet analyzer to IDI block
Packet analyzer output 32
8 packet_anylz_2_idi_o Output 32 125
bit.
Indicates that valid data is
9 Valid_2IDI_o Output 1 125 begin transmitted to Image
data interface.
4.3 Functional description
Packet analyzer receives 32-bit data when valid_2packet_i at rising edge of lane_byte_clk_i and calculates ECC for short packets, long packet
(packet header) and CRC for payload data. If there is a single-bit error in ECC, it is detected, corrected and sent to IDI block. If there is a multi-bit
error the data is not sent to IDI block.
Long packet
Figure 15. Long packet
Packet header
 A Long Packet is identified when Data Types in between 0x10 to 0x37.

 The Packet Header is further composed of three elements: 8-bit Data Identifier, 16-bit Word
Count field, 8-bit ECC.
 The Data Identifier defines the Virtual Channel for the data and the data Type for the application
specific payload data.
 The Word Count defines the number of 8-bit data words in the data payload between the end of
the Packet Header and the start of the Packet Footer. Neither the Packet Header nor the Packet
Footer is included in the Word Count.
 The Error Correction Code (ECC) byte allows single-bit errors to be corrected. This includes both
the data identifier value and the word count value.
Table 8. Long packet data types
S.no Data types Description

1 0x10 to 0x17 Generic long packet data types
2 0x18 to 0x1F YUV data
3 0x20 to 0x27 RGB data
4 0x28 to 0x2F RAW data
5 0x30 to 0x37 User defined byte-based data
Data identifier
 The Data Identifier byte contains the Virtual Channel Identifier (VC) value and the Data Type (DT)
value.
 The Virtual Channel Identifier is contained in the two MS bits of the Data Identifier Byte.
 The Data Type value is contained in the six LS bits of the Data Identifier Byte.
Figure 16. Data identifier
Packet footer
 The Packet footer has one element, a 16-bit checksum.

 To detect possible errors in transmission of data bytes between packet header and packet
footer, a checksum is calculated over each data packet.
 The generator polynomial is x16+x12+x5 +x0.
 The 16-bit checksum sequence is transmitted as part of the Packet Footer.
Short packet
 A Short Packet is identified by Data Types 0x00 to 0x0F.

 A Short Packet shall contain Packet Header and Packet Footer is not present.
 The Word Count field in the Packet Header is replaced by a Short Packet Data Field.
Figure 17. Short packet
 For frame synchronization data types, the short packet data field is the frame number. For line
synchronization data types, the short packet data field is the line number.
 Short packet data types are transmitted using only the short packet format.
Table 9. Short packet data types
Sno Data types Description

1 0x00 to 0x07 Synchronization short packet data types
2 0x08 to 0x0F Generic short packet data types
4.3.1 ECC (Error Correction Code)
This block gives detailed explanation regarding ECC calculations for both fair case and error case
scenarios using a syndrome table.
4.3.1.1 Pin diagram
The below figure shows the block diagram of ECC block
Figure 18. ECC pin diagram
4.3.1.2 Pin description
The Below table describes the pin list of ECC block detailed.
Table 10. ECC pin description

125/93.75/62.5/ ECC block runs with a frequency of
1 lane_byte_clk_i Input 1
31.25 125/93.75/62.5/31.25 MHz.
2 csi_reset_n Input 1 Async Active-low reset for ECC block.
Packet analyzer controller to ECC
3 enable_i Input 1 lane_byte_clk_o Enable signal for calculating ECC
Packet header data from controller
4 pkthdr_i Input 24 lane_byte_clk_o
block.
5 ecc_i input 6 lane_byte_clk_o ECC from the controller block
ECC to Packet analyzer controller
6 header_valid_o Output 1 lane_byte_clk_o Valid signal for valid output
single_error_o indicates single
7 single_error_o Output 1 lane_byte_clk_o error corrected and detected flag
to controller block.
multiple_error_o indicates multi-
8 multiple_error_o Output 1 lane_byte_clk_o
bit error flag to controller block.
9 pktcorrected_o Output 30 lane_byte_clk_o Header data after calculating ECC
Word count value from header
10 wc_o Output 16 lane_byte_clk_o
data
ECC Calculations
 The Packet Header Error Correction Code byte allows single-bit errors in the data identifier and
the word count to be corrected and multibit errors to be detected.
 By using the syndrome table parity p0 to p7 bits will get generated, the 1’s in table indicate
these are data bits positions involved for generating parity bits.
 For 24 bits parity calculations p6 and p7 bits are zero.
Table 11. ECC syndrome table
S.no Bit p7 p6 p5 p4 p3 p2 p1 p0 Hex

1 0 0 0 0 0 0 1 1 1 0x07
2 1 0 0 0 0 1 0 1 1 0x0B
3 2 0 0 0 0 1 1 0 1 0x0D
4 3 0 0 0 0 1 1 1 0 0x0E
5 4 0 0 0 1 0 0 1 1 0x13
6 5 0 0 0 1 0 1 0 1 0x15
7 6 0 0 0 1 0 1 1 0 0x16
8 7 0 0 0 1 1 0 0 1 0x19
9 8 0 0 1 1 1 0 1 0 0x1A
10 9 0 0 1 1 1 1 0 0 0x1C
11 10 0 0 1 0 0 0 1 1 0x23
12 11 0 0 1 0 0 1 0 1 0x25
13 12 0 0 1 0 0 1 1 0 0x26
14 13 0 0 1 0 1 0 0 1 0x29
15 14 0 0 1 0 1 0 1 0 0x2A
16 15 0 0 1 0 1 1 0 0 0x2C
17 16 0 0 1 1 0 0 0 1 0x31
18 17 0 0 1 1 0 0 1 0 0x32
19 18 0 0 1 1 0 1 0 0 0x34
20 19 0 0 1 1 1 0 0 0 0x38
21 20 0 0 0 1 1 1 1 1 0x1F
22 21 0 0 1 0 1 1 1 1 0x2F
23 22 0 0 1 1 0 1 1 1 0x37
24 23 0 0 1 1 1 0 1 1 0x3B
 Applying ECC on Rx side involves generating a new ECC for the received packet, computing the
syndrome using the new ECC and the received ECC, decoding the syndrome to find if a single-bit
error has occurred and if so, correct it.
Figure 19. 24-bit ECC on Rx side Including Error Correction diagram
Decoding the syndrome has three aspects:
 Finding if the packet has any errors (if syndrome is 0, no errors are present)
 Checking if a single-bit error has occurred by searching ECC syndrome table, if the syndrome is
one of the entries in the table, then a single-bit error has occurred and the corresponding bit is
affected, thus this position in the data stream needs to be complemented. Also, if the syndrome
is one of the rows of the identity matrix I, then one of the parity bits is in error.
 If the syndrome cannot be identified, then a higher order error occurs, and the error flag is
asserted (the stream is corrupted and cannot be restored).
Example 1: Fair case scenario
The above figure is showing the information of packet header excluding ECC. Packet header contains 32-
bit in which first 24-bits is the information and last 6-bits are ECC bits. First parity bits have to be
calculated as per the below equations. In the below equations P represents parity bit and D represents
data bit.
Step1 : The equations are the reference from the MIPI alliance specification.
P7 = 0
P6 = 0
P5 = D10^D11^D12^D13^D14^D15^D16^D17^D18^D19^D21^D22^D23
P4 = D4^D5^D6^D7^D8^D9^D16^D17^D18^D19^D20^D22^D23
P3 = D1^D2^D3^D7^D8^D9^D13^D14^D15^D19^D20^D21^D23
P2 = D0^D2^D3^D5^D6^D9^D11^D12^D15^D18^D20^D21^D22
P1 = D0^D1^D3^D4^D6^D8^D10^D12^D14^D17^D20^D21^D22^D23
Step2: Applying the equation and calculating parity bits.
P5 = 0 ^ 0 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 = 1
P4 = 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 = 1
P3 = 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 1 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 = 1
P2 = 1 ^ 1 ^ 0 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 = 1
P1 = 1 ^ 1 ^ 0 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 = 1
P0 = 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1^ 1 ^ 0 ^ 0 ^ 0 ^ 0 = 1, calculated ECC is “00111111”
Step 3: Perform Ex-or operation on calculated ECC and received ECC.
Transmitted ECC = 0 0 1 1 1 1 1 1
Calculated ECC = 0 0 1 1 1 1 1 1
Result exor = 0 0 0 0 0 0 0 0
Step 4: If the syndrome is 0, there is no error in the ECC. If the syndrome is other than 0 value check the
syndrome value in the table and find the corresponding bit number. The bit number indicates that error
is in the error bit.
Example 2: Single-bit error scenario
The above figure is showing the information of packet header excluding ECC. Packet header contains 32
bits in which first 24 bits is the information and last six bits are ECC bits. The red color indicates that the
bit is corrupted. First parity bits have to be calculated as per the below equations. In the below
equations P represents parity bit and D represents data bit.
Step1 : The equations are the reference from the MIPI alliance specification.
P7 = 0
P6 = 0
P5 = D10^D11^D12^D13^D14^D15^D16^D17^D18^D19^D21^D22^D23
P4 = D4^D5^D6^D7^D8^D9^D16^D17^D18^D19^D20^D22^D23
P3 = D1^D2^D3^D7^D8^D9^D13^D14^D15^D19^D20^D21^D23
P2 = D0^D2^D3^D5^D6^D9^D11^D12^D15^D18^D20^D21^D22
Step2: Applying the equation and calculating parity bits.
P7 = 0
P6 = 0
P5 = 0 ^ 0 ^ 1 ^ 1 ^ 1 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 = 1
P4 = 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 = 0
P3 = 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 1 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 = 1
P2 = 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 = 0
P1 = 1 ^ 1 ^ 0 ^ 1 ^ 0 ^ 0 ^ 0 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 0 = 1
P0 = 1 ^ 1 ^ 1 ^ 1 ^ 0 ^ 0 ^ 0 ^ 0 ^ 1^ 1 ^ 0 ^ 0 ^ 0 ^ 0 = 0, calculated ECC = “101010”
Step 3: Perform Ex-or operation on calculated ECC and received ECC.
Transmitted ECC = 0 0 1 1 1 1 1 1
Calculated ECC = 0 0 1 0 1 0 1 0
Result exor = 0 0 0 1 0 1 0 1
Step 4: If the syndrome is 0, there is no error in the ECC. If the syndrome is other than 0 value check the
syndrome value in the table ECC syndrome and find the corresponding bit number. The bit number
indicates that error is in the error bit. The syndrome calculated above is matched with one of entries in
the syndrome table i.e., 5th data bit position so corresponding bit is affected, thus this position in the
data stream needs to be complemented.
Step 5: Complement the 5th bit in the packet header and continue the next process
Waveforms
Figure 20. Error Correction Code diagram
4.3.2 CRC -16 (Cycle redundancy check)
4.3.2.1 Pin diagram
The figure below shows the block diagram of CRC-16 block
Figure 21. CRC-16 pin diagram
4.3.2.2 Pin description
The below table describes the pin list of CRC-16 block detailed.
Table 12. CRC pin description
S.no Signal name Directions Width Freq (MHZ) Description

CRC block runs with a frequency
125/93.75/62.5/
1 lane_byte_clk_i Input 1 of either 125/93.75/62.5/31.25
31.25
MHz.
2 csi_reset_n Input 1 lane_byte_clk_o Active-low reset for CRC block
Packet analyzer controller to CRC
Valid signal for CRC-16 block to
3 calc_i Input 1 lane_byte_clk_o collect 32-bit payload data from
controller block.
32-bit data for which CRC-16
4 pld_i Input 32 lane_byte_clk_o
must be calculated
Enable signal for calculating CRC-
5 en32crc_i Input 1 lane_byte_clk_o
16
CRC to packet analyzer controller
16-bit CRC-16 output for all the
6 crc_o Output 16 lane_byte_clk_o
payload bytes
CRC-16 calculations
Procedure for calculating CRC-16:
 Initially 16-bit register is loaded with FFFF hex (all 1's), when the Word Count is zero.
 When both least significant bits of CRC-16 & 8-bit data byte are different then, the first shift
LSB bit of CRC-16 register & 8-bit data byte to right and Ex-or the CRC-16 register with the
polynomial function.
 If both least significant bits of CRC-16 & 8-bit data byte are same then, need to shift the LSB
bit of CRC-16 register & 8-bit data byte to right.
 Repeat the process until 8 shifts have been performed.
 When this is done, a complete 8-bit byte is processed.
 Repeat the same process for the next 8-bit byte of the message.
 Continue doing this until all bytes have been processed based on word count length.
 The final contents of the CRC -16register are the CRC-16 value.
Example:
Step 1: Associate bits for coefficient polynomial x16+x12+x5 +x0.
Step 2: CRC-16 polynomial = 0001 0000 0010 0001 = 0x1021
Step 3: 8408 is the reflected (reversal) polynomial form of 1021.
Step 4: Calculate CRC-16 by following procedure:
 By following the procedure of CRC-16, the result is = 86E7.
Waveforms
Figure 22. CRC-16 wave form
When calc_i and crc32req_i are both high the payload data at the instance 32-bit data transmitted to
CRC block to calculate CRC-16, en32crc_i indicates which bytes of payload data need to consider as valid
bytes. For every payload data of 32-bits the CRC-16 calculated at the next cycle. Likewise for all 32-bits
of payload the CRC16 has been calculated, and the final calculated CRC16 is compared with the given
CRC-16.
Operating states for packet analyzer
Figure 23. Packet analyzer FSM
The state machine operates through the following states:
 IDLE state:
i. On csi_reset_n, FSM moves to IDLE state.
ii. If valid and pos_det signals both are 1’s then FSM moves to ECC state.
 ECC state:
i. In ECC state when valid and pos_det is high at that time it will collect the packet header
information of short packets and long packets.
ii. To evaluate if the packet header contains any error bits, when valid is 0, FSM moves to
IDLE state. So, when valid and pos_det signals both are at low it indicates no information
is coming from lane merger at that time state changes IDLE because of after completion
of short packet another long packet data is transmitted in that to extract the packet
header. So, for long packet header purpose it moves to idle state when valid and
pos_det are low.
iii. In ECC state corresponding valid and 32-bit data signals are generated to ECC block. The
purpose of Valid signal is to activate the ECC block by giving valid signal as high and
packet header 32-bit data is passed at the same instance.
iv. After performing operations of error correction code in ECC block from that block it
generates output signals multibit error, single-bit error and header valid signal.
v. When the header valid signal is high it indicates no error or single-bit error detected and
corrected from that point payload data receives. Word count is an output signal from
ECC block to indicate the payload bytes.
vi. If valid is one and pos_det is zero FSM moves to PAYLOAD state.
 PAYLOAD state:
i. In this state, for CRC-16 block to perform the operation of 16-bit CRC calculations inputs
has been generated.
ii. In payload state after generating valid and data signals to CRC-16 block parallelly it will
forward the packets of data to IDI block process continues until internal counter reaches
to word count value when there is no multibit error.
iii. When valid is 0, FSM moves to IDLE state. In this state payload is collected and required
signals for CRC-16 block are generated.
Figure 24. Controller block waveform
Figure 25. Format of image transferred
MIPI CSI 2 host controller gets the packets as shown in the above figure.
 Frame start, line start, Line end and frame end are short packets, actual payload is long packets.
 Short packets and long packets are to be transferred as discussed in above sections.
 The above figure shows only the example. One line starts, long packet and line end represents one line of the image. For example, If the
resolution of the image is (640(width) x 480(height)) then 480 lines have to be transmitted.
 MIPI CSI controller should receive the packets in the above packet format for a successful transmission of image data from IDI block.
4.4 Image data interface block
Image data interface provides the detailed information of pin diagram, pin description, FSM and
waveforms.
4.4.1 Pin diagram

The below figure shows the pin diagram of Image data interface block.
Figure 26. Image data interface pin diagram

Table 13. IDI pin description

IDI block runs with a frequency
125/93.75/62.5/
1 lane_byte_clk_i Input 1 of either 125/93.75/62.5/31.25
31.25
MHz.
Active-low reset for Image data
interface.
Packet analyzer to IDI
32-bit output data from packet

3 packet_anyl2_idi Input 32 lane_byte_clk_o
analyzer to Image data interface.
Indicates the valid data is coming
4 Valid_2IDI_i Input 32 lane_byte_clk_o
from packet analyzer.
IDI outputs
Image data interface clock signal
4 clk_data_o Output 1 lane_byte_clk_o
runs with lane_byte_clk_i signal.
This signal indicates that the
header data at the output signals
of IDI block virtual_channel_o,
data_type_o, word_count_o,
5 header_en_o Output 1 lane_byte_clk_o
and ecc_o is valid for the packet
being transferred. This signal
stays high during the complete
packet transfer.
Virtual channel identifier, it is a
part of data identifier byte which
contains 4 virtual channels.
6 virtual_channel_o Output 2 lane_byte_clk_o 00: Virtual channel 0
01: Virtual channel 1
Data type identifier it is also part
of a data identifier byte, which
7 data_type_o Output 6 lane_byte_clk_o
indicates type of data it belongs
to in packet transfer.
word_count_o signal indicates
8 word_count_o Output 16 lane_byte_clk_o number of bytes in a packet for
packet header
ecc_o signal indicates the error
9 ecc_o output 8 lane_byte_clk_o correction code for the packet
header.
data_en_o indicates that new
10 data_en_o Output 1 lane_byte_clk_o payload data is present at the
output (csi_data_o & byte_en_o)
csi_data_o signal 32 bit indicates
11 csi_data_o Output 32 lane_byte_clk_o
the payload data
byte_en_o is a 2-bit signal used
12 byte_en_o Output 2 lane_byte_clk_o for valid data bytes in csi data
output.
Vertical Blanking Packet
13 vvalid_o Output 4 lane_byte_clk_o
Indicator This signal is asserted
when Frame Start is detected,
and de-asserted when Frame
End is detected. There is one
valid signal per virtual channel.
vvalid[0]: for virtual channel 0
dvalid_o signal indicates when
data being transferred excluding
header information. It is
asserted when payload data is
transferring and deasserted at
14 dvalid_o output 4 lane_byte_clk_o
the end of payload. There is
dvalid[0]: for virtualchannel0
dvalid[1]: for virtual channel1
Horizontal Blanking Packet
when Line Start is detected, and
de-asserted when Line End is
detected. There is one valid
15 hvalid_o output 4 lane_byte_clk_o
signal per virtual channel
hvalid[0]: for virtual channel 0
IDI is Image data interface which receives 32-bit data from packet analyzer along with a valid
signal at rising edge of lane_byte_clk_i. This block separates CSI-2 short packet, long packet header
information which is received from packet-analyzer through packet_anyl2IDI signal and generates the
respective output signals.
Operating states of IDI
Figure 27. IDI state machine
In the above FSM the DT = {packet_anyl2IDI[26] , packet_anyl2IDI[27], packet_anyl2IDI[28],

packet_anyl2IDI[29], packet_anyl2IDI[30], packet_anyl2IDI[31]} .
 IDLE state:
i. On csi_reset_n, FSM moves to IDLE state.
ii. If valid and datatype is equal to 6’h00, FSM moves to FRAME_START state.
 FRAME_START state:
i. In frame start which is a short packet, the input 32 bit of packet_anyl2IDI data is splitted
according to its fields and sent as outputs.
ii. Those are: [25:24] bits of packet_anyl2IDI represents vvalid_o, DT represents Data Type,
[23:8] bits represent Word Count, [7:0] bits represent ECC field.
iii. Every packet is followed by Blanking data which is represented as valid low.
iv. After Blanking data if valid_2IDI is high and Data Type is 6’h02 FSM moves to
LINE_START state.
v. If valid_2IDI and Data Type is 6’h24 FSM moves to PAYLOAD state skips LINE_START
state.
vi. Otherwise till valid_2IDI becomes high FSM remains in FRAME_START state.
 LINE_START state:
i. In LINE_START state, which is a short packet, the input 32-bit of packet_anyl2IDI, the
data will separate accordingly to generate the respective output signals.
ii. Those are: [25:24] bits of packet_anyl2IDI represents hvalid_o, DT represents Data Type,
iii. Every packet is followed by Blanking data which is represented by a valid_2IDI as low.
iv. After Blanking data if valid_2IDI is high and Data Type is 6’h24 FSM moves to PAYLOAD
state.
v. Otherwise till valid_2IDI becomes asserts high FSM remains in LINE_START state.
 PAYLOAD state:
i. In PAYLOAD state, which is a long packet, the first 32-bit input is considered as packet
header which contains the information about packet’s Virtual channel, Data Type, Word
Count, ECC at bit positions which are fed as outputs respectively.
ii. Every packet is followed by Blanking data which is represented as valid_2IDI low.
iii. After Blanking data if valid_2IDI and Data Type is 6’h01 FSM moves to FRAME_END
state, or of valid_2IDI and Data Type is 6’h03 FSM moves to LINE_END state, or if
valid_2IDI and Data Type is 6’h02 FSM moves to LINE_START state or if valid_2IDI and
Data Type is 6’h00 FSM moves to FRAME_START state.
iv. Otherwise till valid_2IDI asserts high FSM remains in PAYLOAD state.
 LINE_END state:
i. In LINE END state where short packet is received by the input 32 bit of packet_anyl2IDI,
the data will separate accordingly to generate the respective output signals.
ii.
Those are: [25:24] bits of packet_anyl2IDI represents hvalid_o, DT represents Data Type,
iii. Every packet is followed by Blanking data which is represented by a valid_2IDI low.
iv. After Blanking data if valid_2IDI is high and Data Type is 6’h02 FSM moves to
LINE_START state or if valid_2IDI is high and Data Type is 6’h01 FSM moves to
FRAME_END state, or if valid_2IDI and Data Type is 6’h00 the FSM moves to
FRAME_START.
v. Otherwise till valid_2IDI asserts high FSM remains in LINE_END state.
 FRAME_END state:
i. In FRAME END state where short packet is received by the input 32 bit of
packet_anyl2IDI, the data will separate accordingly to generate the respective output
signals.
ii. Those are: [25:24] bits of packet_anyl2IDI represents vvalid_o, DT represents Data Type,
iii. Every packet is followed by Blanking data which is represented as valid_2IDI low.
iv. After Blanking data if valid_2IDI asserted is high and Data Type is 6’h02 FSM moves to
LINE_START state or if valid_2IDI is high and Data Type is 6’h01 FSM moves to
FRAME_END state, or if valid_2IDI is high and Data Type is 6’h00 the FSM moves to
FRAME_START.
v. Otherwise till valid_2IDI asserts high FSM remains in LINE_END state.
Waveforms of IDI block
Figure 28. Transferring for short packets waveform
 The above figure shows the Image Data Interface with two short packets.
 The header_en_o signal is used to indicate that new data is being transferred at the Image data interface.it asserts high when a new packet
becomes available at the interface and falls as soon as packet finishes. Between two consecutive packets, there is always toggling the
header_en_o, because the CSI-2 transmitter must enter any of the escape state.
 The dvalid_o, hvalid_o, vvalid_o signals are used to provide information about frame start, line start, line end, frame end packets. These
signals are used for synchronization purpose. As no payload is transferring here dvalid_o remains zero.
 vvalid_o is asserted on detection of frame start packets and de-assert by Frame End packet. As these packets are mandatory, vvalid_o is
always reliable for video applications to synchronize frame updating. In case a new frame start packet is received without frame end
indicating the end of previous frame, a pulse is generated in vvalid_o to signal that a new frame start packet was received.
 hvalid_o signal is asserted on detection of line start packets and de-assert by line end. As line start and line end packets are optional when
they are not available, hvalid_o remains at zero.
Figure 29. Transferring for long packet waveform
 The above figure shows timing Interface for a Long Packet, Receiving Data from Four Lanes. If less than four lanes are used,32-bit word
take more than one cycle to be received.
 Data_en_o signal is asserted only when a new word has been fully received and becomes available at the interface. Both header_en_o
and data_en_o returns to ‘0’ as soon as all the data has been transferred.
 Bytes_en signal is always kept at 2’b11 while the payload data is being transferred, indicating that four bytes in csi_data are valid bytes
from packet’s payload. When last word becomes available the bytes_en may change according to the number of remaining valid bytes.
for all data types, the LS bytes contain the remaining bytes.
 The dvalid_o signal is used to indicate when the data is being transferred, excluding header information. Data sent through Blanking
data or null Packets does not activate dvalid_o.
Figure 30. Transferring of frame waveform
 The above figure shows timing interface of a frame with one-line receiving on four data lanes.
 VC(FS) indicates that is a short packet which tells about the frame start information (FE) indicates another short packet which tells about
the frame end information. Similar VC(LS) and VC(LE) indicates short packets containing information about line start and line end. Short
packet is 32-bit wide.VC (long packet) indicates the Virtual channel data in the long packet header.
 DT(FS) and DT(FE) indicates the data types value in short packets which tells about frame start, frame end. Similar DT(LS) and DT(LE)
indicates the data types in short packets which tells about line start and line end. DT (long packet) indicates the data type which is in
long packet.
 WC(FS), WC(FE), WC(LS), WC(LE) indicates the word count which tells about frame number, line number in short packets. WC (long
packet) indicates the Word count which tells about number of payload bytes in long packet.
 ECC(FS), ECC(FE), ECC(LS), ECC(LE) indicates about the error correction code in short packets of frame start, frame end, line start, line
end respectively.
 vvalid_o, hvalid_o, dvalid_o as 4’b0010 indicates the vertical blanking packet indication, horizontal blanking packet indication, data
availability indication of virtual channel 1.
4.5 Image Data Interface Controller
Image data interface controller provides the detailed information of pin diagram, pin description and
waveforms.
4.5.1 Pin diagram

The below figure shows the pin diagram of Image data interface controller.
Figure 31. Image data interface controller pin diagram

Table 14. Image data interface controller pin description
Freq
S.no Signal name Directions Width Description
(MHz)
31.25/62.5/93.75/ Clock generated from Image data

1 clk_data_i Input 1
125 interface block.
Active-low reset for Image data

interface.
3 header_en_i Input 1 lane_byte_clk_o This signal indicates that the

header data at the output signals
of IDI block virtual_channel_o,
data_type_o, word_count_o, and
ecc_o is valid for the packet being
transferred. This signal stays high
during the complete packet
transfer.
Virtual channel identifier, it is a

part of data identifier byte which
contains 4 virtual channels.
4 virtual_channel_i Input 2 lane_byte_clk_o 00: Virtual channel 0
Data type identifier it is also part

of a data identifier byte, which
5 data_type_i Input 6 lane_byte_clk_o
indicates type of data it belongs
to in packet transfer.
word_count_o signal indicates

6 word_count_i Input 16 lane_byte_clk_o number of bytes in a packet for
packet header
ecc_o signal indicates the error

7 ecc_i Input 8 lane_byte_clk_o correction code for the packet
header.
data_en_o indicates that new

8 data_en_i Input 1 lane_byte_clk_o payload data is present at the
output (csi_data_o & byte_en_o)
csi_data_o signal 32 bit indicates

9 csi_data_i Input 32 lane_byte_clk_o
the payload data
byte_en_o is a 2-bit signal used

10 byte_en_i Input 2 lane_byte_clk_o for valid data bytes in csi data
output.
Vertical Blanking Packet Indicator

This signal is asserted when
Frame Start is detected, and de-
asserted when Frame End is
detected. There is one valid signal
11 vvalid_i Input 4 lane_byte_clk_o
per virtual channel.
dvalid_o signal indicates when
data being transferred excluding
header information. It is asserted
when payload data is transferring
and deasserted at the end of
12 dvalid_i Input 4 lane_byte_clk_o
payload. There is
dvalid[0]: for virtualchannel0

detected. There is one valid signal
13 hvalid_i Input 4 lane_byte_clk_o
per virtual channel
Write enable is generated to

14 wen_o Output 1 lane_byte_clk_o indicate that the data on wdata_o
have to be written in the FIFO.
Concatenated data generated

15 wdata_o Output 32 lane_byte_clk_o based on input signals is sent on
wdata_o.

 Image data interface controller receives control signals generated by image data interface block.
 Based on the control signals such as header_en_i and bytes_en_i short or long packets are
concatenated as 32 bit.
 concatenated 32-bit data is sent on wdata_o along with wen_o.
Waveforms of IDI controller block
Figure 32. Short packet generation from IDI controller
The above figure describes about the concatenation of short-packet with the outputs generated from IDI
block.
Figure 33. Long packet generation from IDI controller
The above figure describes about transmitting wdata_o and wen_o based on the inputs from IDI block
4.6 AXI Top
The below figure shows the pin diagram of AXI TOP.
4.6.1 Pin diagram
Figure 34. AXI Top pin diagram
Table 15. AXI Top pin description

ECC block runs with a frequency
125/93.75/62.5/3
1 lane_byte_clk_i Input 1 of either 125/93.75/62.5/
1.25
31.25MHz.
Active-low reset signal for AXI
TOP block
aclk_i is input signal of AXI block
3 aclk_i Input 1 250
with a frequency of 250 MHz.
arst_n is an active low reset
4 arst_n Input 1 Async
signal.
IDI to AXI
5 csi_data_i Input 32 lane_byte_clk_o Payload of frame 32-bit data.
6 virtual_channel_i Input 2 lane_byte_clk_o Virtual channel identifier 2-bits.
Data type identifier 6-bits
7 data_type_i Input 6 lane_byte_clk_o indicates type of data it belongs
to in each packet transfer.
word count indicates number of
8 word_count_i Input 16 lane_byte_clk_o bytes in a packet for packet
header.
ecc_i signal indicates the error
9 ecc_i Input 6 lane_byte_clk_o correction code for the packet
header.
data_en_i indicates that new
10 data_en_i Input 1 lane_byte_clk_o payload data is present at the
input (csi_data_i & byte_en_i)
byte_en_i is a 2-bit signal used
11 bytes_en_i Input 2 lane_byte_clk_o for valid data bytes in csi data
output.
12 vvalid_i Input 4 lane_byte_clk_o Vertical Blanking Packet
when Frame Start is detected,
and de-asserted when Frame
End is detected. There is one
valid signal per virtual channel.
vvalid[0]:vvalid
forvirtualchannel0
vvalid[1]:vvalid forvirtual
channel 1 vvalid[2]: vvalid for
virtual channel2
vvalid[3]: vvalid for
virtualchannel3
detected. There is one valid
signal per virtual channel.
13 hvalid_i Input 4 lane_byte_clk_o hvalid[0]:
vvalidforvirtualchannel0
hvalid[1]:vvalidfor virtual
channel1
hvalid[2]: vvalid
forvirtualchannel2 hvalid[3]:
vvalid for virtualchannel3
Write address register to store
14 waddr_value Input 32 125 the address for write address
channel.
This 32-bit Field Specifies how
many bytes to be transferred
15 num_bytes_reg Input 32 125 and lets the AXI master how
many transactions it should be
performed.
The control information for the
address channel is splitted into
Register fields and stored in the
16 cntrl_value Input 32 125
register and utilized for the
ADDRESS channel transmission
purpose.
The mode register is used for the
enabling of the channels and the
17 mode_value Input 32 125
enabling is controlled by the
mode_reg
This signal indicates that the

header data of
virtual_channel_i, data_type_i,
18 header_en_i Input 1 lane_byte_clk_o word_count_i, and ecc_i is valid
for the packet being transferred.
This signal stays high during the
complete packet transfer.
AXI signals
Write address channel signals
Write address ready. This signal
indicates that the slave is ready
to accept an address and
19 awready_i Input 1 250
associated control signals:
1 = slave ready
Write address ID. This signal is
20 awid_o Output 4 250 the identification tag for the
write address group of signals.
Write address valid. This signal
indicates that valid write address
and control information are
available:
1 = address and control
information available
21 awvalid_o Output 1 250
information not available.
The address and control
information remain stable until
the address acknowledges the
signal,
Write address. The write address
bus gives the address of the first
transfer in a write burst
22 awaddr_o Output 32 250 transaction. The associated
control signals are used to
determine the addresses of the
remaining transfers in the burst.
Burst length. The burst length
gives the exact number of
transfers in a burst. This
23 awlen_o Output 8 250
information determines the
number of data transfers
associated with the address.
Burst size. This signal indicates
the size of each transfer in the
24 awsize_o Output 3 250 burst. Byte lane strobes indicate
exactly which byte lanes to
update.
Burst type. The signal indicates
the type of burst:
25 awburst_o Output 2 250 00: Fixed burst
01: Incrementing burst
10: Wrapping burst
Read address channel signals
Read address ready. This signal
indicates that the slave is ready
to accept an address and
26 arready_i Input 1 250
associated control signals:
1 = slave ready
Read address ID. This signal is
27 arid_o Output 4 250 the identification tag for the
read address group of signals.
Read address valid. This signal
indicates, when HIGH, that the
read address and control
information is valid and will
remain stable until the address
28 arvalid_o Output 1 250 acknowledge signal, arready, is
high.
information valid
information not valid.
Read address. The read address

bus gives the initial address of a
read burst transaction. Only the
start address of the burst is
29 araddr_o Output 32 250 provided and the control signals
that are issued alongside the
address detail how the address is
calculated for the remaining
transfers in the burst.
Burst length. The burst length
gives the exact number of
transfers in a burst. This
30 arlen_o Output 8 250
information determines the
number of data transfers
associated with the address.
Burst size. This signal indicates

31 arsize_o Output 3 250 the size of each transfer in the
burst.
Burst type. The burst type,

coupled with the size
32 arburst_o Output 2 250 information, details how the
address for each transfer within
the burst is calculated.
Write data channel signals
Write ready. This signal indicates

that the slave can accept the
34 wready_i Input 1 250 write data:
1 = slave ready
Write valid. This signal indicates

that valid write data and strobes
are available:
35 wvalid_o Output 1 250 1 = write data and strobes
available
0 = write data and strobes not
available.
36 wdata_o Output 32 250 Write data. The write data bus
Write strobes. This signal
indicates which byte lanes to
update in memory. There is one
37 wstrb_o Output 4 250 write strobe for each 8 bits of
the write data bus. Therefore,
wstrb[n] corresponds
to wdata[(8 × n) + 7:(8 × n)].
Write last. This signal indicates

38 wlast_o Output 1 250
the last transfer in a write burst.
Write response channel signals

Response ID. The identification
tag of the write response. The
BID value must match the
39 bid_i Input 4 250
AWID value of the write
transaction to which the slave is
responding.
Write response valid. This signal
indicates that a valid write
40 bvalid_i Input 1 250 response is available:
1 = write response available
0 = write response not available.
Write response. This signal
indicates the status of the write
41 bresp_i Input 2 250 transaction. The allowable
responses are OKAY, EXOKAY,
SLVERR, and DECERR.
Response ready. This signal
indicates that the master can
accept the response information.
42 bready_o Output 1 250
1 = master ready
0 = master not ready.
Read data channel signals
Read ID tag. This signal is the ID
tag of the read data group of
43 rid_i Input 4 250 signals. The RID value is
generated by the slave and must
match the ARID value of the read
transaction to which it is
responding.
Read valid. This signal indicates
that the required read data is
available and the read transfer
44 rvalid_i Input 1 250
can complete:
1 = read data available
0 = read data not available.
45 rdata_i Input 32 250 Read data. The read data bus
Read response. This signal
indicates the status of the read
46 rresp_i Input 2 250 transfer. The allowable
responses are OKAY, EXOKAY,
SLVERR, and DECERR.
Read last. This signal indicates
47 rlast_i Input 1 250
the last transfer in a read burst.
Read ready. This signal indicates
that the master can accept the
read data and response
48 rready_o Output 1 250
information:
1= master ready
0 = master not ready.
4.7 Interrupt Block
 ERR1 and ERR2 registers contain the information independent of MSK1 and MKS2 register.
 MSK1 and MSK2 used to select which bits of ERR1 and ERR2 are used to generate the interrupts
by asserting intr1_o and intr2_o respectively.
 ERR1 and ERR2 self-clear after APB4 read access.
 Intr1_o and intr2_o signal deasserts after reading of ERR1 and ERR2 register.
4.7.1 Pin diagram

The below figure shows the pin diagram of Interrupt block.
Figure 35. Interrupt pin diagram

Table 16. Interrupt block

1 pclk_i Input 1 125 Clock with a frequency of 125MHz
2 preset_n Input 1 - preset_n is active low reset signal
3 err1_i Input 32 125 Refer to the table of err1 which is
output from register block.
4 err2_i Input 32 125 Refer to the table of err2 which is
5 msk1_i Input 32 125 Refer to the table of msk1 which is
6 msk2_i Input 32 125 Refer to the table of msk2 which is
7 intr1_o output 1 125 Interrupt signal is asserted if one of
the fields of MSK1 register is low
and ERR1 register of the respective
field is high.
8 intr2_o output 1 125 Interrupt signal is asserted if one of
the fields of MSK2 register is low
and ERR2 register of the respective
field is high.
Waveforms of Interrupt block
Figure 36. Generation of interrupt 1 waveform
Interrupt signal is asserted if one of the fields of MSK1 register is low and ERR1 register of the respective
field is high. Interrupt is deasserted when the ERR1 register is read.
Figure 37. Generation of interrupt 2 waveform
Interrupt signal is asserted if one of the fields of MSK2 register is low and ERR2 register of the respective
field is high. Interrupt is deasserted when the ERR2 register is read.
4.8 APB4 Slave controller
The below figure shows the pin diagram of APB4 slave controller.
4.8.1 Pin diagram
Figure 38.APB4 Slave pin diagram

The below table describes the IO signals In detail.
Table 17. APB4 SLAVE controller IO pin list
S.no Signal name Directions Width Freq(MHz Description

)
1 pclk_i Input 1 125 Clock with a frequency of 125MHz
2 preset_n Input 1 - preset_n is active low reset signal
3 psel_i Input 1 125 Slave Select Input
4 penable_i Input 1 125 Enable Input Indicates the beginning of a
valid transfer cycle.
5 pwrite_i Input 1 125 Write enable which indicate
pwrite_i = 0, read transfer
pwrite_i = 1, write transfer
6 paddr_i Input 32 125 It is a 32-bit address signal to write/read
from register address.
7 pstrb_i Input 4 125 It is a 4-bit strobe indicates valid byte.
8 pwdata_i Input 32 125 It is a 32-bit data signal used to write the
data into the registers.
9 prdata_o Output 32 125 It is a 32-bit data signal used to read the
data from register
10 pready_o Output 1 125 Peripheral ready Output. This signal
indicates the completion of transfer.
11 pslverr_o Output 1 125 Slave error signal, which indicates the
error in the transfer.
Operating states for APB4 SLAVE
Figure 39. APB4 slave FSM
 IDLE state:
The idle state is typically used as the initial state of FSM. When the system starts up or
resets, it enters the idle state and remains there until it receives an input that causes a
state transition.
 SETUP state:
The SETUP state is followed by the ADDRESS phase, during which the slave decodes the
address information and determines if it is the intended target of the transaction. If the
slave matches the address, it proceeds to the subsequent phases (such as the DATA,
WRITE, or READ phases) based on the control signals received from the master.
 ACCESS state:
The ACCESS phase is a critical part of the APB4 protocol as it involves the actual transfer
of data or access to registers between the master and slave components.
Waveforms of APB4 Slave controller
The diagrams below show APB4 slave write configuration.
Figure 40. APB4 slave Write timing diagram
The diagram below shows the register read using APB4 slave controller.
Figure 41 .APB4 slave read timing diagram
4.9 Register bank
 Register bank is used for reading and writing into the registers. It contains both read-write
registers and read only registers.
 Based on control signals generated by APB4 slave controller register bank either writes the data
into the registers or sends the data to the APB4 slave controller.
4.9.1 Pin diagram

The below figure shows the pin diagram of Register bank.
Figure 42. Register bank pin diagram
Table 18. Register bank IO pin list

1 pclk_i Input 1 125 Clock with a frequency of 125MHZ
2 preset_n Input 1 125 preset_n is active low reset signal
apb_read_o signal indicates read operation when
3 apb_read_i Input 1 125 it is asserted
apb_write_o signal indicates write operation
4 apb_write_i Input 1 125 when it is asserted
apb_addr_o signal 32- bit indicates address of
5 apb_addr_i Input 32 125 register for register block
apb_wdata_o signal 32-bit indicates data of
6 apb_wdata_i Input 32 125 register for register block
apb_strb_o signal indicates valid byte lanes in 32
7 apb_strb_i Input 4 125 bits for register block.
8 lerror_1_i Input 4 125 lerror_1_i signal from lane merger
9 lerror_2_i Input 8 125 lerror_2_i signal from lane merger
10 perror_1_i Input 25 125 perror_1_i signal from packet analyzer
11 perror_2_i Input 16 125 perror_2_i signal from packet analyzer
12 err1_o output 32 125 ERR1 register of 32bits from register bank
13 err2_o ouput 32 125 ERR2 register of 32bits from register bank.
14 msk1_o
ouput 32 125 MSK1 register of 32bits from register bank
15 msk2_o
ouput 32 125 MSK21 register of 32bits from register bank
16 nlanes_o output 2 125 Nlanes register of 2 bits from register bank.
apb_rdata_o 32-bit signal gives data of register
17 apb_rdata_o output 32 125 for the address mentioned
18 waddr_value_o output 32 125 WADDR register of 32 bits from register bank.
19 ctrl_value_o output 32 125 CTRL register of 32 bits from register bank
20 num_bytes_o output 32 125 NUM_BYTES register of 32 bits from register bank
21 dphy_shutdownz_o output 1 125 DPHY_SHUTDOWNZ register of 1 bit from
register bank.
22 dphy_rstz_o output 1 125 DPHY_RSTZ register of 1 bit from register bank
4.9.3 Register descriptions
The description for the register block is detailed below.

Table 19. Register block
Default
S.no Address Register Width Name R/W Description
values
N LANES
Number of active data
lanes
00:1 datalane(lane-0)
01: 2 data lanes (lanes
CSI_NUMBER_OF_LANES
0 and 1)
10: 3 data lanes (lanes
0, 1, and 2)
1-0 nlanes R/W
1 0x04 N_LANES 11:4 data lanes (All)
Can only be updated
when the D-PHY lanes
are in Stop state. Not
updated when clock
lane is in stop state.
31-16 Reserved - - -
PHY SHUTDOWN
Active-low D-PHY
PHY_SHUTDOWN 0 phy_shutdownz R/W 1'b1
shutdown control
2 0x08
Z
31-1 Reserved - 31'b0 -
DPHY RST
Active-low D-PHY
0 dphy_rstz R/W 1'b1
3 0x0c DPHY_RSTZ reset control.
31-1 Reserved R/W 31'b0 -
PHY_STATE
4 0x10 PHY_STATE Lane-0 has entered
0 phy_rxulpesc_0 RO 1'b0 the Ultra Low Power
mode
Lane-1 has entered
mode
Lane-2 has entered
mode
3 phy_rxulpesc_3 RO 1'b0 Lane-3 has entered
the Ultra Low Power
mode
Data lane-0 in stop
4 phy_stopstatedata_0 RO 1'b0
state.
Data lane-1 in stop
state.
Data lane 2in stop
state.
Data lane-3 in stop
state.
8 Reserved - 1'b0 -
This signal indicates
that the clock lane
9 phy_rxulpsclknot RO 1'b0 module has entered
the Ultra Low Power
state. Active-low
Clock lane in Stop
10 phy_stopstateclk RO 1'b0
state
31-11 Reserved - 20'b0 -
CSI2_ RESETN
CSI2 host controller
0 csi2_resetn R/W 1'b1
5 0x14 CSI2_RESETN reset active low
31-1 Reserved - 30'b0 -
ERROR1
Start of transmission
error on data lane-0
0 phy_errsotsynchs_0 RO 1'b0 (no synchronization
achieved). Multi-bit
error in SoT
achieved) Multi-bit
error in SoT
6 0x18 ERR1
achieved) Multi-bit
error in SoT
error on data lane-
3 phy_errsotsynchs_3 RO 1'b0 3(no synchronization
achieved) Multi-bit
error in SoT
Error matching frame
4 err_f_bndry_match_vc0 RO 1'b0
start with frame end
for virtual channel 0
5 err_f_bndry_match_vc1 RO 1'b0 start with frame end
for VC- 1
for VC- 2
for VC- 3
Incorrect frame
sequence detected in
8 err_f_seq_vc0 RO 1'b0
VC- 0(expected
sequence is 1,2,3,4....)
Incorrect frame
VC- 1 (expected
Incorrect frame
VC- 2 (expected
Incorrect frame
VC- 3 (expected
Last received frame, in
12 err_frame_data_vc0 RO 1'b0 VC- 0, had at least one
CRC error
CRC error
CRC error
CRC error
16 err_l_bndry_match_di0 RO 1'b0 Error matching line
start with line end for
VC0
VC1
VC2
VC3
20 err_i_seq_di0 RO 1'b0 Error in sequence of
lines for VC0
lines for VC1
lines for VC2
lines for VC3
Checksum error
24 vc0_err_crc RO 1'b0
detected on VC- 0
Checksum error
detected on VC- 1
Checksum error
detected on VC- 2
Checksum error
detected on VC- 3
Header ECC contains 2
28 err_ecc_double RO 1'b0
errors, unrecoverable
ERROR2
Escape Entry Error
0 phy_erresc_0 RO 1'b0
(ULPM)on datalane0
Escape Entry Error
(ULPM)on datalane1
Escape Entry Error
(ULPM)on datalane2
Escape Entry Error
(ULPM)on datalane3
7 0x1c ERR2 SoT error on data
lane-0(synchronization
4 phy_errsoths_0 RO 1'b0
can still be achieved).
single-bit error in SoT
SoT error on data
5 phy_errsoths_1 RO 1'b0
can still be achieved)
6 phy_errsoths_2 RO 1'b0 SoT error on data
SoT error on data
7 phy_errsoths_3 RO 1'b0 lane-3(synchronization
Header error detected
8 vc0_err_ecc_corrected RO 1'b0 and corrected on VC-
0
9 vc1_err_ecc_corrected RO 1'b0
corrected on VC-1
corrected on VC- 2
corrected on VC- 3
Unrecognized or
12 err_id_vc0 RO 1'b0 unimplemented data
type detected in VC- 0
Unrecognized or
Unrecognized or
Unrecognized or
MASK 1
Mask for
0 mask_phy_errsotsynchs_0 R/W 1'b0
phy_errsotsynchs_0
Mask for
phy_errsotsynchs_1
Mask for
phy_errsotsynchs_2
Mask for
8 0x20 MSK1 3 mask_phy_errsotsynchs_3 R/W 1'b0
phy_errsotsynchs_3
mask_err_f_bndry_match_ Mask for
4 R/W 1'b0
vc0 err_f_bndry_match_0
5 R/W 1'b0
6 R/W 1'b0
7 R/W 1'b0
8 mask_err_f_seq_vc0 R/W 1'b0 Mask err_f_seq_vc0
Mask for
12 mask_err_frame_data_vc0 R/W 1'b0
err_frame_data_vc0
Mask for
err_frame_data_vc1
Mask for
err_frame_data_vc2
Mask for
err_frame_data_vc3
16 mask_err_l_bndry_match_ R/W 1'b0 Mask for
di0 err_l_bndry_match_0
20 mask_err_i_seq_di0 R/W 1'b0 Mask for err_i_seq_di0
24 mask_vc0_err_crc R/W 1'b0 Mask forvc0_err_crc
Mask for
28 mask_err_ecc_double R/W 1'b0
err_ecc_double
MASK2
0 mask_phy_erresc_0 R/W 1'b0 Maskforphy_erresc0
9 0x24 MSK2
Mask for
4 mask_phy_errsoths_0 R/W 1'b0
phy_errsoths_0
Mask for
phy_errsoths_1
Mask for
phy_errsoths_2
Mask for
phy_errsoths_3
mask_vc0_err_ecc_correct Mask for
8 R/W 1'b0
ed vc0_err_ecc_correct
9 R/W 1'b0
10 R/W 1'b0
11 R/W 1'b0
12 mask_err_id_vc0 R/W 1'b0 Mask for err_id_vc0
31-0 Reserved - - -
WADDR
Write address register
to store the address
10 0x28 WADDR 31-0 waddr_reg R/W 0
for write address
channel.
CONTROL
11 0x2c ctrl_reg The WID is responsible
for storing the unique
ID value in the write
3:0 WID R/W 4'b0
channels; this is the 4-
bit register field from
LSB.
7:4 Reserved - - -
The AWSIZE is the 3-
bit field. This signal
10:8 AWSIZE R/W 3'b0 indicates the size of
each transfer in the
burst.
13:11 Reserved - - -
15:14 BURST R/W 2'b0 The BURST is the 2-bit
field Burst type. The
burst type, coupled
with the size
information, details
how the address for
each transfer within
the burst is calculated.
31:16 Reserved - - -
MODE
Enable a single-bit
field that indicates the
enabling of the Write
and Read channels 1-
indicates channel is
0 EN R/W 1'b0 enabled,0-indicates
12 0x30 mode_reg the channels are
disabled this enabling
and disabling helps in
parallel operations of
the channel.
31:1 Reserved - 31'b0 -
NUMBER BYTES
This 32-bit Field
Specifies how many
bytes to be
13 0x34 NUM_BYTES 31-0 no_of_bytes R/W 32'b0 transferred and lets
the AXI master how
many transactions it
should be performed.
4.10 System control block
 This block is responsible for generating clocks required for blocks inside MIPI-CSI2 Host
Controller. The blocks include: Lane merger, Packet analyzer, AXI controller.
 lane_byte_clk_o is generated by dividing sys_clk_i based on N_LANES input, which comes from
the register bank.
4.10.1 Pin diagram
The below figure shows the pin diagram of system control block.
Figure 43. System control block pin diagram

The below table describes the IO signals in detail
Table 20. System control pin list
S.no Signal name Direction Width Freq (MHz) Description
Input clock with frequency: 375

1 sys_clk_i Input 1 375
MHz.
2 sys_reset_n Input 1 Async Active-low reset
Output clock to all blocks (packet
3 freq_by_3_clk_o Output 1 125
analyzer, IDI, AXI): Freq: 125 MHz
4 freq_by_4_clk_o Output 1 93.75
analyzer, IDI, AXI): Freq: 93.75 MHz
Waveforms
Figure 44. Generation of 125 MHz clock
The above figure represents generation of output clock with frequency of 125 MHz, when 4 lanes are
active
Figure 45. Generation of 93.75 MHz clock
The above figure represents generation of output clock with frequency of 93.75 MHz, when 3 lanes are
active.
The above figure represents generation of output clock with frequency of 62.5 MHz, when 2 lanes are
active.
The below figure represents generation of output clock with frequency of 31.25 MHz, when only 1 lane
is active.
5 Error cases
Table 21. Error cases
S.no Error name Description Action taken
1 vc*_err_crc Checksum error detected on virtual channel Error is acknowledged in the register
and interrupt is asserted.
2 Vc*_err_ecc_corrected Header information has one error corrected Error is acknowledged in the register
and detected on virtual channel and interrupt is asserted.
3 Err_ecc_double Header ECC contains 2 errors, and they can’t packet is not sent to IDI. The error is
be corrected. acknowledged and interrupt pin is
asserted.
4 Err_id_vc* Unrecognized data type on virtual channel. Error is acknowledged in the register
Data types are for FS,LS,FE,LE and RGB all and interrupt is asserted.
formats. Except these data types all the
remaining data types are unrecognized.
4 Err_f_bndry_match_di If frame number of end packet is not same Error is acknowledged in the register
for last received frame start packet and interrupt is asserted.
5 Err_f_seq_di If the Frame Number in a Frame Start packet Error is acknowledged in the
is not incremented by 1 relatively to the respective register and interrupt is
previous one, for some virtual channel, asserted.
err_f_seq_di error is asserted. The exception
is that if the Frame Number
is 0, frame numbering is inactive; if it is 1, the
frame numbers restart. Therefore, the error
is not asserted in these exceptions.
6 phy_errsotsynchs_* Start of transmission error on Packets with this error are not
data lane* with no synchronization achieved delivered in IDIInterface. Error is
acknowledged and interrupt is
asserted.
7 phy_errsoths_* Start of transmission error on Error is acknowledged in the register
data lane* but synchronization and interrupt is asserted.
can still be achieved
8 Phy_erresc_* Escape Entry (ULPM) on data lane. Informative error. Error is
acknowledged in the register and
interrupt is asserted.
9 Err_l_bndry_match_di* Error matching line start number with line Informative error. Error is
end number acknowledged in the register and
10 Err_l_seq_di* Error in sequence of line number Informative error. Error is

acknowledged in the register and
6 Programming sequence
 After power up/reset (preset_n) configure the registers as required.
 The registers which need to be configured are PHY_SHUTDOWNZ (0x08), DPHY_RSTZ (0x0c),
CSI2_RESETN(0x14), MSK1(0x20), MSK2(0x24), WADDR (0x28), NUM_BYTES_REG (0x34), CTRL
(0x2c), MODE (0x30). Configure the registers in the order mentioned.
 First configure PHY_SHUTDOWNZ as low then configure as high. After this configure DPHY_RSTZ
as low then configure as high. Configure CSI2_RESETN as low then configure as high. After
configuring MSK1, MSK2, WADDR, NUM_BYTES_REG, CTRL and MODE register.
 Along with the registers a parameter named CSI_NUMBER_OF_LANES must assert which tells
the number of active lanes from which the data is transmitted. Example if ‘1’ is asserted in the
parameter the number of active lanes is 0 & 1.
 The CSI_HOST_CONTROLLER will activate by setting the csi_enable bit which must configure
through the registers.
 Based on the registers PHY_SHUTDOWNZ (active-low), DPHY_RSTZ (active-low) the
phy_shutdownz (active high), dphy_rstz (active-high) DPHY control output signals are updated. If
phy_shutdownz or dphy_rstz are asserted then PPI lanes of CSI_HOST_CONTROLLER is in default
state.
 After exit from the shutdown mode, phy_enable[3:0] & phy_enable_clk_o signals are asserted
to high.
 After csi_reset_n, the initial stopstate in both clock and data lanes must be held for initialization
period ( >100 us).
 When data lanes are in stop state and no stop state in clock lane N_LANES register is updated.
 N_LANES register has to be updated when there is no stopstate in clock lane. According to the
stopstate signals on the data lanes this N_LANES register is updated after every packet end. The
whole CSI HOST CONTROLLER works on the updated value of N_LANES register.
 Initialization is followed by active mode or escape mode, according to the timing parameters
mentioned.
 SoT and EoT is discarded in D-PHY itself.
 In HS mode rxactivehs_n must be asserted high along with rxsynchs_n for one pulse to indicate
the synchronization. Along with the rxsynchs_n, if errsoths_n is asserted high for one pulse then
the data from the next cycle is considered. Along with the rxactivehs_n, if errsotsynch_n is
asserted high for a pulse without rxsynchs_n then the packet is not sent from the IDI block.
 The valid data is merged as mentioned in the Lane merger block if errsotsynchs_n is not asserted
for a pulse, where Lane Merger Block is synchronous to rxbyteclkhs_i clock.
 Based on the errsoths_n and errsotsynchs_n the ERR1 & ERR2 register fields are updated in HS
mode, and interrupts are asserted.
 The Blanking data which is sent in low power mode is not considered.
 In between every active mode and escape mode the lanes must enter stop state as mentioned
in the figures.
 Interrupt gives the information regarding the error occurrence as mentioned in the error case
scenarios.
 IDI interface receives the 32-bit data along with the valid signal from packet analyzer and
generates the respective output IDI signals.
 IDI outputs and payload data had been passed through AXI master with the help of write
address, write data and write response channels.
7 Thumb Rules:
 While driving wready signal in write data channel for AXI, once data is available it should be
high. It should not toggle in between transactions.
 Frame number increments from 1 to 30 (FPS) for each virtual channel, once the count reaches
the maximum count, it retuns to initial value.
 The functionality of erresc_i and errsyncesc_n_i input signals are not considered.

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MIPI CSI-2

Micro Architecture Document

CSI Camera Serial Interface

FIFO First In First Out

Figure 1. Host controller overview diagram

S.no Signal name Direction Freq(MHz) Description

4. rxbyteclkhs_i Input 125 Input clock for high-speed

Table 3. CSI2 HOST CONTROLLER reset signals

S.no Reset name Direction Freq (MHz) Description

Figure 2. CSI2 Host controller block diagram

 System control Block:

3 CSI2 top pin diagram

S.no Signal name Directions Width Freq (MHz) Description

4.1 Lane merger block

4.1.1 Pin diagram

Figure 4. Lane merger pin diagram

The below table describes the IO signals in detail.

S.no Signal name Directions Width Freq (MHz) Description

Figure 5. Lane merging data diagram

Figure 6. Lane 0 &1 high speed mode data transmission

[1] : TA = TLPX+ THS_PREPARE

[2]: TC = THS_TRIAL + TCLK_POST

[6]: Tca = TLPx + TCLK_PREPARE [10]: Tdb = THS_TRIAL + TCLK_POST

Figure 11. Multi-bit error in SoT

Figure 12. Error in low power data

Table 6. Timing parameters description

S.no Parameter Description min max unit

1 TLPX Transmitted length of any Low-Power state 50 - ns

2 THS_PREPARE + THS-PREPARE + time that the transmitter 145 ns + 10*UI 85 ns + 6*UI ns

4 THS_SKIP Time interval during which the HS-Rx should 40 55 ns + 4*UI ns

5 TCLK_POST Time that the transmitter continues to send 60 ns + 52*UI - ns

6 TCLK_TRIAL Time that the transmitter drives the HS-0 60 - ns

7 THS_EXIT Time that the transmitter drives LP-11 100 - ns

8 TCLK-PREPARE + TCLK-PREPARE + time that the transmitter 300 - ns

9 TCLK_PRE Time that transmitter drives HS clock before 8 - ns

4.2.1 Block diagram

Figure 13. Packet analyzer block diagram

4.2.2 Pin diagram

The below figure shows the pin diagram of packet analyzer.

Figure 14. Packet analyzer pin diagram

The below table describes the IO signals in detail.

S.no Signal name Directions Width Freq (MHz) Description

Packet analyzer runs with a

Figure 15. Long packet

 A Long Packet is identified when Data Types in between 0x10 to 0x37.

Table 8. Long packet data types

S.no Data types Description

Figure 16. Data identifier

 The Packet footer has one element, a 16-bit checksum.

 A Short Packet is identified by Data Types 0x00 to 0x0F.

Figure 17. Short packet

Table 9. Short packet data types

Sno Data types Description

2 0x08 to 0x0F Generic short packet data types

4.3.1.1 Pin diagram

The below figure shows the block diagram of ECC block

Figure 18. ECC pin diagram

4.3.1.2 Pin description

S.no Signal name Directions Width Freq (MHz) Description

Table 11. ECC syndrome table

S.no Bit p7 p6 p5 p4 p3 p2 p1 p0 Hex

Decoding the syndrome has three aspects:

Figure 20. Error Correction Code diagram

2 THS_PREPARE + THS-PREPARE + time that the transmitter 145 ns + 10UI 85 ns + 6UI ns