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Language - Verilog
Sequential Circuits
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU
Outline
Review
Module Instantiation
Ports Connection
Number Representation
Assignments
Operators
Sequential Circuit
Introduction
Counter
Sequential Verilog Syntax
Procedural Assignment
Non-blocking
Example
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REVIEW
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Module Instantiation
Adder
instance
example
A d d e r _0 A d d e r _1
A d d e r_ tre e
instance name IO interface
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Ports Declaration
Two port types Two net types
Input port wire
input a; wire c;
Output port reg
output b; reg d;
a ab
b
b bc
co
c
c ac
a
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Ports Connection
in1
adder out
in2
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Number Representation
Format: <size>’<base_format><number>
<size> - decimal specification of number of bits
<base format> - ' followed by arithmetic base of number
<number> - value given in base of <base_format>
Examples:
6’b010_111 gives 010111
8’b0110 gives 00000110
4’bx01 gives xx01
16’H3AB gives 0000_0011_1010_1011
24 gives 0…0011000
5’O36 gives 11_100
16’Hx gives xxxxxxxxxxxxxxxx
8’hz gives zzzzzzzz
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Values Assignment
Assignment: Drive value onto nets and registers
There are two basic forms of assignment
continuous assignment, which assigns values to wire type
procedural assignment, which assigns values to reg type
Basic form
Assignments Left Hand Side Example
Continuous wire a;
wire
Assignment assign a = 1’b1;
Procedural reg a;
reg
Assignment always@(*) a = 1’b1;
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Operators
Operator Sign Example
Equality == , !=
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SEQUENTIAL CIRCUIT
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Introduction
Combinational Circuits (without memory)
A
B F(A,B,C)
F(A,B,C)
C
A
B F F(t+1) = F(A,B,C, D(t))
C
D(t) D(t+1)
MEM
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Edge-triggered D Flip-Flop
Positive (Rising edge) trigger
Negative (Falling edge) trigger
to align with clock edges
DQ Q+ Q+ = D
0 0 0
0 1 0
1 0 1
1 1 1
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K-map
Circuit Implement
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SEQUENTIAL
VERILOG SYNTAX
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Procedural Assignment
Procedure blocks
always block
Only reg type can be LHS in procedure blocks
It’s syntax. Not relevant to whether it’s a flip-flop or a metal wire!
RHS is not restricted.
Variable is updated by procedural assignment
For combinational circuit
Pure logic circuit
Use blocking assignment (=)
Use always @ (*)
For sequential circuit
D-FF circuit
Use non-blocking assignment (<=)
Edge trigger of clock or reset signal
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Blocking or Non-Blocking?
Blocking assignment (=) Combinational!!!!
Evaluation and assignment are immediate
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AND
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0
nxt_cnt cnt
MUX DFF
4 4
4 + 1
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Header/Comment
Module instantiation
Input/output declaration
Combinational
Parameter
Continuous
Sensitivity list Assignment
Number Representation
Reg/WIre
Operator
FSM Procedure Block
Procedure Assignment
If statement
Sequential
case statement
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