Branch Predic on Technique and it’s performance: A Holis c Review

The evolu on of the microprocessor and its high performance depends upon mul ple factors. Branch
Predic on is one of the architectural technique and methods to improve the performance of the
hardware by providing set of instruc ons based on condi onal branches. Simultaneous execu on of
more than one instruc on takes place in a pipelined processor. Run me branch predictors helps in
execu ng mul opera on. It also helps to prefetch the next set of instruc ons to be executed.

Branch predic on schemes are of two types:

 sta c branch schemes - A sta c branch scheme (so ware techniques) is very simple and easy.
This scheme assembles the majority of the data/informa on prior to the execu on of the
program or during the compile me and it doesn’t require any hardware
 dynamic branch schemes. This is hardware techniques based on the hardware and it assembles
the informa on during the run- me of the program

The idea behind this review to summarize various scheme of branch predic on, perform comparison
between the schemes.

Reference

1. R. Thomas, M. Franklin, C. Wilkerson, and J. Stark, “Improving branch predic on by dynamic

dataflow-based iden fica on of correlated branches from a large global history,” Proc. 30th
Annu. Int. Symp. Comput. Archit., vol. 31, no. 2, pp. 314–323, 2003.
2. T.-Y. Y. T.-Y. Yeh and Y. N. Pa , “A Comparison Of Dynamic Branch Interna onal Journal of Pure
and Applied Mathema cs Special Issue 2849 Predictors That Use Two Levels Of Branch History,”
Proc. 20th Annu. Int. Symp. Comput. Archit., vol. 21, no. 2, pp. 257–266, 1993.