slvs212

TPS7415, TPS7418, TPS7425, TPS7430, TPS7433
FAST-TRANSIENT-RESPONSE USING SMALL OUTPUT CAPACITOR

200-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS212 – DECEMBER 1999
D Fast Transient Response Using Small D PACKAGE

(TOP VIEW)
Output Capacitor (10 µF)
D 200-mA Low-Dropout Voltage Regulator EN 1 8 SENSE
D Available in 1.5-V, 1.8-V, 2.5-V, 3-V and 3.3-V NC 2 7 OUT
D Dropout Voltage Down to 170 mV at 200 mA NC 3 6 GND
(TPS7433) IN 4 5 IN
D 3% Tolerance Over Specified Conditions NC – No internal connection
D 8-Pin SOIC Package
D Thermal Shutdown Protection
description
This device is designed to have a fast transient response and be stable with 1-µF capacitors. This combination
provides high performance at a reasonable cost.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV
at an output current of 200-mA for the TPS7433). This LDO family also features a sleep mode; applying a TTL
high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at
TJ = 25°C.
The TPS74xx is offered in 1.5-V, 1.8-V, 2.5-V, 3-V, and 3.3-V. Output voltage tolerance is specified as a
maximum of 3% over line, load, and temperature ranges. The TPS74xx family is available in 8 pin SOIC
package.
TPS7433
DROPOUT VOLTAGE
vs TPS7418
JUNCTION TEMPERATURE LOAD TRANSIENT RESPONSE
300 100
VI = 3.2 V CO = 10 µF
Output Voltage – mV
di/dt = 200 mA
∆ VO – Change in
50 25 µs
250
VDO – Dropout Voltage – mV
IO = 200 mA 0
200
–50
150
I O – Output Current – mA
100
IO = 75 mA
200
IO = 50 mA
50
0
IO = 1 mA
0
–50 –25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800 900 1000
TJ – Junction Temperature – °C t – Time – µs
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

AVAILABLE OPTIONS
OUTPUT VOLTAGE
PACKAGED DEVICES
(V)
TJ
SOIC
TYP
(D)
3.3 TPS7433D
3 TPS7430D
– 40°C to 125°C 2.5 TPS7425D
1.8 TPS7418D
1.5 TPS7415D
The D package is available taped and reeled. Add an R suffix to the device type (e.g.,
TPS7433DR).
TPS74xx
4 8
VI IN SENSE SENSE
5 IN
7
OUT VO
1 µF 1
EN CO†
+
1 µF
GND
6 ESR
† See application information section for capacitor selection details.
Figure 1. Typical Application Configuration
functional block diagram
IN
EN
+
OUT
SENSE
R1
Vref
R2
GND
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
EN 1 I Enable input
GND 6 Regulator ground
IN 4, 5 I Input voltage
NC 2, 3 Not connected
OUT 7 O Regulated output voltage
SENSE 8 I Sense
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Ĕ
Input voltage range‡, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 8 V

Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VI + 0.3 V
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURES

AIR FLOW TA < 25°C DERATING FACTOR TA = 70°C TA = 85°C
PACKAGE
(CFM) POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
0 568 mW 5.68 mW/°C 312 mW 227 mW
D
250 904 mW 9.04 mW/°C 497 mW 361 mW
recommended operating conditions

MIN MAX UNIT
Input voltage, VI§ 2.5 7 V
Output current, IO (see Note 1) 0 200 mA
Operating virtual junction temperature, TJ (see Note 1) – 40 125 °C
§ To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the
device operate under conditions beyond those specified in this table for extended periods of time.

electrical characteristics over recommended operating free-air temperature range,

Vi = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 1 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS TEST CONDITIONS MIN TYP MAX UNIT
TJ = 25°C 1.5
TPS7415 2 5 V < VI < 7 V
2.5
TJ = –40°C to 125°C 1.455 1.545
TJ = 25°C 1.8
TPS7418 2 8 V < VI < 7 V
2.8
TJ = –40°C to 125°C 1.746 1.854
g ((10 µA
Output voltage µ to 200 mA load)) TJ = 25°C 2.5
TPS7425 3 5 V < VI < 7 V
3.5 V
(see Note 2) TJ = –40°C to 125°C 2.425 2.575
TJ = 25°C 3.0
TPS7430 4 0 V < VI < 7 V
4.0
TJ = –40°C to 125°C 2.910 3.090
TJ = 25°C 3.3
TPS7433 4 3 V < VI < 7 V
4.3
TJ = –40°C to 125°C 3.201 3.399
TJ = 25°C 80
IO = 1 mA
mA, EN = 0 V µA
TJ = –40°C to 125°C 115
TJ = 25°C 550
Quiescent current (GND current) (See Note 2) IO = 100 mA,
mA EN = 0 V µA
TJ = –40°C to 125°C 850
TJ = 25°C 1300
IO = 200 mA
mA, EN = 0 V µA
TJ = –40°C to 125°C 1500
Output voltage line regulation (∆VO/VO)
VO + 1 V < VI ≤ 7 V, TJ = 25°C 0.06 %/V
(see Notes 2 and 3)
Load regulation 5 mV
BW = 300 Hz to 50 kHz, CO = 1 µF,
Output noise voltage 190 µVrms
TJ = 25°C
Output current Limit VO = 0 V 500 750 mA
Thermal shutdown junction temperature 150 °C
2.5 V < VI < 7 V, EN = VI,
1 µA
TJ = 25°C
Standby current
2.5 V < VI < 7 V, EN = VI,
3 µA
TJ = –40°C to 125°C
High level enable input voltage 2 V
Low level enable input voltage 0.7 V
EN = 0 V –1 1
Input current (EN) µA
EN = VI –1 1
f = 100 Hz, CO = 1 µF,
Power supply ripple rejection (see Note 2) 55 dB
TJ = 25°C
IO = 200 mA, TJ = 25°C 180
TPS7430
IO = 200 mA, TJ = –40°C to 125°C 350
Dropout voltage (see Note 4) mV
IO = 200 mA, TJ = 25°C 170
TPS7433
IO = 200 mA, TJ = –40°C to 125°C 315
NOTES: 2. Minimum IN operating voltage is 2.5 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 7 V.
3. If VO = 1.5 V then Vimax = 7 V, Vimin = 2.5 V:
4. IN voltage equals VO(Typ) – 100 mV; TPS7430 and TPS7433 dropout limited by input voltage range limitations (i.e., TPS7430 input
voltage needs to drop to 2.9 V for purpose of this test).
Line Reg. (mV) + ǒ%ńVǓ

V
O
ǒ
V
imax
* 2.5 V Ǔ 1000
100
If VO ≥ 2.5 V then Vimax = 7 V, Vimin = VO + 1 V:
Line Reg. (mV) + ǒ%ńVǓ

V
O
ǒ V
imax
* ǒ
V
O
)1 V ǓǓ 1000
100

Table of Graphs
FIGURE
vs Output current 2, 3, 4
VO Output voltage
vs Junction temperature 5, 6
Ground current vs Junction temperature 7, 8
Power supply ripple rejection vs Frequency 12
Output noise vs Frequency 9
Zo Output impedance vs Frequency 10
VDO Dropout voltage vs Junction temperature 11
Line transient response 13, 15
Load transient response 14, 16
Output voltage vs Time 17
(Stability) Equivalent series resistance (ESR) vs Output current 19
TYPICAL CHARACTERISTICS
TPS7418 TPS7433
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT OUTPUT CURRENT
1.810 3.310
VI = 2.8 V VI = 4.3 V
TA = 25°C TA = 25°C
VO – Output Voltage – V
1.805
3.305
1.800
1.795 3.300
0 50 100 150 200 250 0 50 100 150 200 250
IO – Output Current – mA IO – Output Current – mA
Figure 2 Figure 3

TPS7425 TPS7418
OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs
OUTPUT CURRENT JUNCTION TEMPERATURE
2.5 1.820
VI = 3.5 V VI = 4.0 V
TA = 25°C 1.818
2.498
1.816
1.814
2.496 IO = 1 mA
1.812
IO = 50 mA
2.494 1.810
1.808 IO = 100 mA
2.492 1.806
IO = 200 mA
1.804
2.49
1.802
0 50 100 150 200 250 –50 –25 0 25 50 75 100 125 150
IO – Output Current – mA TJ – Junction Temperature – °C
Figure 4 Figure 5
TPS7433 TPS7418
OUTPUT VOLTAGE GROUND CURRENT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
3.330 10000
VI = 4.3 V VI = 2.8 V
3.325
IO = 200 mA
3.320 1000
Ground Current – µ A
3.315 IO = 1 mA
IO = 100 mA
3.310 IO = 50 mA
100
3.305 IO = 1 mA
IO = 100 mA
3.300
10
3.295
3.290 IO = 200 mA
3.285 1
–50 –25 0 25 50 75 100 125 150 –50 0 50 100 150
TJ – Junction Temperature – °C TJ – Junction Temperature – °C
Figure 6 Figure 7

TPS7433
GROUND CURRENT OUTPUT SPECTRAL NOISE DENSITY
vs vs
JUNCTION TEMPERATURE FREQUENCY
10000 20 µV ǸHz
VI =4.3 V VI = 4.3 V
CL = 1 µF
IO = 200 mA IO = 1 mA TA = 25°C
Output Spectral Noise Density

1000 2 µV ǸHz
Ground Current – µ A
IO = 100 mA
IO = 200 mA
100 200 nV ǸHz

IO = 1 mA
10 20 nV ǸHz
1 2 nV ǸHz
–50 0 50 100 150 250 1k 10k 100k
TJ – Junction Temperature – °C f – Frequency – Hz
Figure 8 Figure 9
TPS7430
OUTPUT IMPEDANCE DROPOUT VOLTAGE
vs vs
FREQUENCY JUNCTION TEMPERATURE
100 250
VI = 4.3 V VI = 2.9 V
CL = 1 µF:
CL = 1 µF
IO = 1 mA
TA = 25°C
200
200 mA
VDO – Dropout Voltage – mV
Zo – Output Impedance – Ω
10
150
1 100 mA
100
0.1 CL = 1 µF
IO = 200 mA 50
10 mA
0.01 0
0.01 0.1 1 10 100 1000 –40 10 60 110
f – Frequency – kHz TJ – Junction Temperature – °C
Figure 10 Figure 11

RIPPLE REJECTION
vs
FREQUENCY
80
70
CL = 1 µF
60 IO = 100 mA CL = 1 µF
Ripple Rejection – dB
IO = 1 mA
50
40
CL = 1 µF
IO = 200 mA
30
20
10
0
10 100 1k 10k 100k 1M 10M
f – Frequency – Hz
Figure 12
TPS7418 TPS7418
LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
100
CO = 10 µF
di/dt = 200 mA
50 25 µs
200
0 0
–200 –50
–300
3.8
VI – Input Voltage – V
2.8 200
0
CO = 1 µF
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t – Time – ms t – Time – ms
Figure 13 Figure 14

TPS7433 TPS7433
LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE
100
CO = 10 µF
di/dt = 200 mA
200 50 25 µs
0 0
–200 –50
–50
VI – Input Voltage – V
5.3
4.3 200
0
CO = 1 µF
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t – Time – ms t – Time – ms
Figure 15 Figure 16
TPS7433
OUTPUT VOLTAGE
vs
TIME (AT STARTUP)
VO– Output Voltage – V
VI = 7 V
4
5
Enable Pulse – V
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

t – Time – ms
Figure 17

IN To Load
VI
OUT
+
CO
EN RL
GND
ESR
Figure 18. Test Circuit for Typical Regions of Stability (Figure 19)
TYPICAL REGIONS OF STABILITY

EQUIVALENT SERIES RESISTANCE (ESR)†
vs
OUTPUT CURRENT
100
ESR – Equivalent Series Resistance – Ω
10
0.1
Region of Instability
0.01
0 50 100 150 200
IO – Output Current – mA
Figure 19
† ESR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.

APPLICATION INFORMATION
The TPS74xx family includes five voltage regulators (1.5 V, 1.8 V, 2.5 V, 3 V, and 3.3 V).
minimum load requirements

The TPS74xx family is stable even at zero load; no minimum load is required for operation.
SENSE terminal connection

The SENSE terminal must be connected to the regulator output for proper functioning of the regulator. Normally,
this connection should be as short as possible; however, the connection can be made near a critical circuit
(remote sense) to improve performance at that point. Internally, SENSE connects to a high-impedance
wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through to the regulator
output. Routing the SENSE connection to minimize/avoid noise pickup is essential. Adding an RC network
between SENSE and OUT to filter noise is not recommended because it can cause the regulator to oscillate.
external capacitor requirements

An input capacitor is not usually required; however, a ceramic bypass capacitor (1 µF or larger) improves load
transient response and noise rejection if the TPS74xx is located more than a few inches from the power supply.
A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients
with fast rise times are anticipated.
Like all low dropout regulators, the TPS74xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance value is 1 µF and the ESR
(equivalent series resistance) must be at least 300 mΩ. Solid tantalum electrolytic and aluminum electrolytic
are all suitable, provided they meet the requirements described previously.
TPS74xx
4 8
VI IN SENSE SENSE
5 IN
7
OUT VO
1 µF 1
EN CO
+
1 µF
GND
6 ESR
Figure 20. Typical Application Circuit
regulator protection
The TPS74xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.

APPLICATION INFORMATION
regulator protection (continued)

The TPS74xx also features internal current limiting and thermal protection. During normal operation, the
TPS74xx limits output current to approximately 500 mA. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross
device failure, care should be taken not to exceed the power dissipation ratings of the package. If the
temperature of the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has
cooled below 130°C (typ), regulator operation resumes.
power dissipation and junction temperature

Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than
or equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
P + TJmax * TA
D(max) R
qJA
Where
TJmax is the maximum allowable junction temperature.
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 172°C/W for the 8-terminal
SOIC.
TA is the ambient temperature.
ǒ Ǔ
The regulator dissipation is calculated using:
P
D
+ VI * VO I
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.

PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS7415D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 7415
TPS7418DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 7418
TPS7433DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 7433
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 13-Aug-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Dec-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7433DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS7433DR SOIC D 8 2500 350.0 350.0 43.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS7415D D SOIC 8 75 505.46 6.76 3810 4
TPS7418D D SOIC 8 75 505.46 6.76 3810 4
TPS7418DG4 D SOIC 8 75 505.46 6.76 3810 4
TPS7425D D SOIC 8 75 505.46 6.76 3810 4
TPS7430D D SOIC 8 75 505.46 6.76 3810 4
TPS7433D D SOIC 8 75 505.46 6.76 3810 4
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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IMPORTANT NOTICE AND DISCLAIMER
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TPS7415, TPS7418, TPS7425, TPS7430, TPS7433

FAST-TRANSIENT-RESPONSE USING SMALL OUTPUT CAPACITOR

D Fast Transient Response Using Small D PACKAGE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

† See application information section for capacitor selection details.

Figure 1. Typical Application Configuration

functional block diagram

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Input voltage range‡, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 8 V

DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURES

recommended operating conditions

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

electrical characteristics over recommended operating free-air temperature range,

Line Reg. (mV) + ǒ%ńVǓ

If VO ≥ 2.5 V then Vimax = 7 V, Vimin = VO + 1 V:

Line Reg. (mV) + ǒ%ńVǓ

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Output Spectral Noise Density

100 200 nV ǸHz

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TYPICAL REGIONS OF STABILITY

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

minimum load requirements

SENSE terminal connection

external capacitor requirements

Figure 20. Typical Application Circuit

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

regulator protection (continued)

power dissipation and junction temperature

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

Reel Width (W1)

Q3 Q4 Q3 Q4 User Direction of Feed

*All dimensions are nominal

TAPE AND REEL BOX DIMENSIONS

*All dimensions are nominal

B - Alignment groove width

*All dimensions are nominal

LAND PATTERN EXAMPLE

SOLDER MASK SOLDER MASK

NON SOLDER MASK SOLDER MASK

SOLDER MASK DETAILS

6. Publication IPC-7351 may have alternate designs.

SOLDER PASTE EXAMPLE

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