4 Channel Programmable

Delay Generation ASIC

Thomas H. Toifl
EP/MIC

Delay Chip Thomas Toifl CERN / EP / MIC

Delaychip Overview
4Delays Digital signals
4Delay can be programmed in 1ns steps
44+1 independent delay channels
4Needs 40Mhz clock as timing reference
4Programmed via I2C interface
44 bit I2C address space

Delay Chip Thomas Toifl CERN / EP / MIC

 Delaychip Block diagram

In0 Out0
delay/MUX
Out1
In1
delay/MUX
4 digital inputs In2 Out2 4 digital outputs
delay/MUX
Out3
In3
delay/MUX
Vcntr 4 5
Clk OutClk
40 Mhz clock DLL/MUX Skewed clock out
w_en delay
I2C
Interface
SCL
SDA } I2C Bus
5 Addr
Interface

Delay Chip Thomas Toifl CERN / EP / MIC

Delay Locked Loop (DLL)

in
Phase detector
Loop filter
Charge pump Vctrl

Multiplexer
out

Delay Chip Thomas Toifl CERN / EP / MIC

 Timing diagram
T0

fIN
t

fOUT ...
t
0123 … 24ns

Delay Chip Thomas Toifl CERN / EP / MIC

 2
IC Command word format
Data Format:
7 6 5 4 3 2 1 0

Bit 7-5 : device select Bit 4-0: delay select

000 signal 1 0-24 : delay (0-24ns)
001 “ 2 25 : 0 (disable output)
010 “ 3 27 : 1
011 “ 4
100 “ CLK

Delay Chip Thomas Toifl CERN / EP / MIC

 Specifications
Supply voltage: 3.3±0.2 V
Input Clock frequency 40 MHz
SCL
NC
NC
A2
A3
A4
A5

11 10 9 8 7 6 5
GND
PHI2
GND
12
13
4
3
2
VDD
SDA
GND
Signaling Low V CMOS
14
JLCC28
2.6x2.3 mm2
DO1 15 1 DO2
VDD
DO0
16
17
28
27
VDD
DO3
Chip size:
GND 18 26 GND
19 20 21 22 23 24 25
Package: 28 pin J-leaded
DI0
DI1
VDD
PHI1
GND
DI2
DI3

ceramic
Current consumption
DLL only: 3mA
1 Delay channel: 3mA+75µA/Mhz

Delay Chip Thomas Toifl CERN / EP / MIC

 Delaychip Layout

I2C and
initialisation
logic
Delay-locked
Loop

Matched delay lines

Delay Chip Thomas Toifl CERN / EP / MIC

Measured Delay vs. programmed delay

25

20

Delay [ns]
15

10

0
0 5 10 15 20 25

Delay tap #

Delay Chip Thomas Toifl CERN / EP / MIC

Jitter as a function of delay tap

60

rms Jitter [ps]

55

50

45

40

35

30

25
0 5 10 15 20 25

Delay tap #

Delay Chip Thomas Toifl CERN / EP / MIC

Differential Nonlinearity
∆ T Distribution
35

30

25
Hits

20

15 σ = 26 ps
10

0
0.92 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 1.1

∆T [ns]

Delay Chip Thomas Toifl CERN / EP / MIC

Integral Nonlinearity
0.5
0.4
Deviation [ns]
0.3
0.2 Channel 1
0.1
Channel 2
0 CLK
-0.1 Channel 3
-0.2
Channel 4
-0.3
-0.4
-0.5
0 5 10 15 20 25

Delay tap #

Delay Chip Thomas Toifl CERN / EP / MIC

Current consumption / channel

Current consumption [mA]

6
500 Ω load
5

4 No external load

2
Output switched off

0
0 5 10 15 20 25 30 35 40

Frequency [MHz]

Delay Chip Thomas Toifl CERN / EP / MIC