North South University

Department of Computer Science & Engineering

Quiz 2: Fall, 2021, ETE412/EEE411/CSE435- Section 2: VLSI Design Date: Nov 12, 2021

1. a) Show the design path of VLSI design starting from idea to chip as shown in the class.
Indicate how your courses coves the different stages in that path.
b) In brief (any five): (i) Design Team (ii) Design Hierarchy: Top down and Bottom Up (iii)
Logical Design and Physical Design (iv) ASIC and System on Chip (v) Moor’s Law. (vi)
List of Integrated Ckt based on size and years

2. a) Describe: (any 4)
i. Create own ckt using 3 push and 2 pull switches and show the function by Boolean
equation.
ii. Create your own Boolean equation where you have 2 active high and three active
low controls and implement that function using push pull switches.
iii. Complementary Pair
iv. Threshold Voltage: Strong One, Weak One, Strong Zero, Weak Zero
v. Pass Characteristics.

b) Using truth table method design the CMOS circuit that implements following function

g = ab

3. a) What is Transmission Gate? Design XOR or 4-to-1 MUX using TGs.

b) Design a CMOS logic circuit using bubble pushing technique.

g= ab+cd
(Hint: Implement the nFET network and then apply bubble pushing to find the pFET
network).