Microprocessor Course

LECTURE(02)

The microprocessor and Its

Architecture

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Chapter Contents

 Computer Structure

 Internal Microprocessor Architecture

 Real Mode Memory Addressing

 Introduction to Protected Mode Memory Addressing

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Computer Structure

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Computer Structure

Peripherals Computer

Central Main
Processing Memory
Unit

Computer Systems
Interconnection

Input
Output
Communication
lines

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The Main Memory
 It is a set of numbered cells.
 The number is called address, which can be
used to locate the cell.
 Each cell contains data, a number, which is
the thing to be processed by the computer .
 The memory also contains the program, coded
as numbers, which describe how to process
data.

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The Main Memory
 Therefore, inside the machine, there is nothing to distinguish data from
programs, nor data from addresses, except in how they are used.
 All commercial computers are based on stored program concept, with
programs and data sharing the same main memory.
 Such computers are called Von Neumann machines.

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The Interconnection Systems (Busses)
 It provides a mean for the connection/communication among CPU, main
memory, and input/output (I/O) devices.
 During the execution of a program, there are three sorts of data flowing
along the bus: addresses, instructions and actual data, and control
signals.

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The Interconnection Systems (Busses)
 A normal bus includes three parts:
 Address bus: for passing the addresses of instructions and data in memory .
 Data bus: for transferring the instructions and data themselves.
 Control bus: for issuing control signals such as reading or writing.
 The size of each bus affects the performance of the system, determines
the type of microprocessor and limits the maximum size of memory that
can be addressed.

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Input and Output Devices
 I/O operation moves data between the computer and its external
environment.
 Input devices include keyboard, disk drives, CD and DVD drives,
magnetic tape drives, mouse devices, scanners, modems, microphones,
stylus, bluetooth, etc.
 Output devices include disk drives, printers, screens, CD and DVD
drives, magnetic tape drives, modems, speakers, etc.
 Communications with these devices can be done in a manner similar to
memory reading/writing.

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The Execution Cycle
 To execute a program (a sequence of instructions) stored in main
memory, the CPU controller performs a fetch-execute cycle:
1) Fetch an instruction from the memory.
2) Decode the instruction.
3) Execute the instruction by sending control signals to the ALU and other
parts of the computer .
4) Send the result back to memory, or to an input/output device.

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Main Concepts of Bus Interface
 The Industry Standard Architecture (ISA) bus interface is found in
all machines since the very start of the IBM personal computer
system till modern Pentium 4- based computers. It is either 8 or 16-
bits, and supports either memory or I/O transfers at rates of 8 MHz.
 The Extended Industry Standard Architecture (EISA) supports 8, 16,
and 32-bit transfers between the personal computer and memory or
I/O at rates of 8 MHz.

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Internal Microprocessor
architecture

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Internal Microprocessor Architecture
 8086/8088 Microprocessors
 Intel 80x86 Programming Model
 General-Purpose Registers
 Special-purpose Registers
 Segment Registers

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16 Bit Microprocessor: 8086-8088
 8086 MP
 Inside: 16 bit (ALU)
 Outside: 16 bit (Data Bus D0-D15)
 Address Lines: 20 Lines (A0-A19)
 8088 MP
 Inside: 16 bit (ALU)
 Outside: 8 bit (Data Bus D0-D7)
 Address Lines: 20 Lines (A0-A19)
 8086/8088
 Have the same architecture.
 Have the same instruction set.

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Features of 8086/8088

 8086 is a 16-bit processor.

 Its ALU, internal registers work with 16-bit binary words

 8086 has a 16-bit data bus.

 It can read or write data to a memory/port either 16bits or 8 bit at a time

 8086 has a 20-bit address bus which means,

 it can address up to 220 = 1MB memory locations

 Frequency range of 8086 is 4-10 MHz

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8086/8088 Internal Architecture
 8086/8088 more efficient
 Bus Interface Unit (BIU)
• Fetch instructions from the memory and put them in a queue
 Execution Unit (EU)
• Take the instruction from the queue and execute it.

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8086/8088 Internal Architecture
 Pipeline
Process in sequence

Process in pipeline

BIU:

EU:

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8086/8088 Registers

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8086/8088 Registers
 Bus Interface Unit (BIU)
 IP (Instruction Pointer)
• contains address of next instruction to be executed
 CS (Code Segment Register)
• defines the memory location where the code/instructions are stored
 DS (Data Segment Register)
• defined where the data from the program will be stored
 ES (Extra Segment Register)
• defined where the strings and arrays from the program will be stored
 SS (Stack Segment Register)
• defined where the MP stores the important addresses and data required to return
from subroutine.

 All addresses are defined with respect to the segment registers

 8086 has a segmented memory architecture
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8086/8088 Registers
 Execution Unit (EU)
 4 general purpose registers
• AX Accumulator Register: AX (16 bit register) or AL,AH (two 8 bit registers)
 all I/O operations & some arithmetic
• BX Base Register: BX -> BH,BL
 can be used as an address register
• CX Counter Register: CX -> CH,CL
 Used with LOOP instruction
• DX Data Register: DX -> DH,DL
 some I/O and when multiplying & dividing
 SP Stack Pointer: point to the top of the stack
 BP Base Pointer: point to any location in the stack
 SI Source Index Register: extended addressing commands
 DI Destination Index Register: used in some addressing modes
 F Flag Register: determines the current state of the processor
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Memory Segmentation
 8086 has a 20-bit address space (1MB)
 But can only directly address 64kB (16-bit address space)
 I.e. it addresses the 1MB in chunks or segments
 A segmented memory address location is identified with a segment and
an offset address (this is the logical address)
Segment : Offset 16 bits : 16 bits
 The actual physical address is calculated by shifting the segment
address 4 bits to the left and adding the offset!
 What’s the actual physical address in the following example?

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Memory Segmentation

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Memory Segmentation – Segment Registers
 CS: points at the segment containing the current program.
 DS: generally points at segment where variables are defined.
 ES: extra segment register, it's up to a coder to define its usage.
 SS: points at the segment containing the stack.
 The address formed with 2 registers is called an effective address, by default
 BX, SI and DI registers work with DS segment register;
 BP and SP work with SS segment register.
 SI and DI registers work with ES segment register;

Physical Address = Segment Reg. x 10)H + Logic Address

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Intel 80x86 Programming Model

- Program-visible Registers

- 8-bit registers (like AL), 16-bit registers (like AX), 32-bit registers (like EAX)
too keep upward compatibility

- 8086, 8088, 80286: 16-bit registers

- 80386-Pentium 4: 32-bit (Shaded Registers) 24

Intel 80x86 Programming Model(cont’d)
 These are the program-visible registers
 8-bit registers (like AL), 16-bit register (like AX), and 32-bit register
(like EAX)
 8086, 8088, 80286: 16-bit registers
 80386-Pentium 4: 32-bit (shaded registers)
 Upward compatibility is kept (The recent products can perform as old
versions).

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Basic Program Execution Registers
1) General-purpose registers: These eight registers are available for
storing operands and pointers.
2) Segment registers: These registers hold up to six segment
selectors.
3) EFLAGS (program status and control) register: The EFLAGS register
report on the status of the program being executed and allows
limited (application-program level) control of the processor.
4) EIP (instruction pointer) register: The EIP register contains a 32-bit
pointer to the next instruction to be executed.

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General-Purpose Registers
 The 32-bit general-purpose registers EAX, EBX, ECX, EDX, ESI, EDI,
EBP, and ESP are provided for holding the following items:
1) Operands for logical and arithmetic operations
2) Operands for address calculations
3) Memory pointers
 Although general in nature, usually used for special purpose:
 EAX – accumulator (as general as they come)
 EBX – base index often used to address memory data
 ECX – count used in shifts and loops
 EDX – data used in multiply and divide
 EBP – base point used to address stack data
 ESI – source index addresses memory data
 EDI – destination index addresses memory data
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Special-purpose registers
 Have special tasks
 ESP – address stack data
 The Stack pointer (ESP) register contains the offset of the top of the
stack segment.
 EIP
 The instruction pointer (EIP) register contains the offset in the current
code segment for the next instruction to be executed.
 The EIP register cannot be accessed directly by software; it is controlled
implicitly by control-transfer instructions
 EFLAGS
 Indicates conditions of the microprocessor
 Not changed by data transfer and program flow instructions
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Special-purpose registers (cont’d)
 EFLAGS
 Each flag is a single binary bit
 C, P, A, Z, S, and O change by arithmetic and logic instructions

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Special-purpose registers (cont’d)
 EFLAGS
 C: Carry (addition), borrow (subtraction)
 P: Parity (0=odd parity, 1=even parity)
 A: Auxiliary carry (between bits 3 and 4 to adjust BCDs)
 Z: Zero (1=result is zero, 0=result is not zero)
 S: Sign (1=negative, 0=positive)
 T: Trap (debug mode)
 I: Interrupt (1=enable interrupt, 0=disable interrupt)
 D: Direction (1=auto increment, 0=auto decrement of SI and DI for string
operations)
 O: Overflow (result exceeds capacity)

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Segment registers
 Generate memory addresses (combined with other registers, like IP)
 CS: Code Segment
 Beginning of program in memory
 In real mode: start of 64kB code segment
 In protected mode: selects a descriptor that holds the starting address and
the length of the code segment
 DS: Data Segment
 Beginning of data segment

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Segment registers (cont’d)
 ES: Extra Segment
 Extra data segment (specially for string operations)
 SS: Stack Segment
 Beginning of the stack segment
 FS, GS
 60386 – Pentium4
 Extra segment if needed
 Windows uses them for internal operations

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Modes of Operation

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Modes of Operation
1) Real address Mode
2) Protected Mode
3) System Management Mode

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Real Mode Memory Addressing
 Default mode after reset
 1MB RAM maximum addressable
 Single tasking
 Supported by MS-DOS operating system
 8086 and 8088: only in real mode
 80286 – Pentium4: real or protected mode

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Real Mode Memory Addressing (cont’d)
 Beginning of a segment = segment register
 End of a Segment= Segment Register * (10)H + FFFFH
 Calculating linear (absolute) address
 Multiply segment register by 16 (add a hexadecimal zero),
 Add the 5-digit segment to the offset
 Example: convert 08F1:0100 to a linear address

Adjusted Segment value: 0 8 F 1 0

Add the offset: 0 1 0 0
Linear address: 0 9 0 1 0

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Real Mode Memory Addressing (cont’d)
 Defaults
 Next instruction: CS with IP/EIP

Ex. CS= 028Fh, IP=0030h  next instruction=028F0 + 0030 = 02920h

 Stack: SS with SP or BP
Ex. SS= F280h, SP=0200h  Top of the stack = F2800 + 0200 = F2A00h

 Segment and offset addressing allow relocation

 Move the program to the new segment
 Update the segment register

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Introduction to Protected Mode Addressing
 Windows operating system
 80286 – Pentium4
 Address is still selected by segment and offset registers
 Offset points to the location within the segment
 Segment register is a selector that selects a descriptor (entry in a global or
local descriptor tables)
 Descriptor has the segment starting address, limit, and access rights
 Protected mode operation is done through program-invisible registers
(GDTR, LDTR…etc)


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