Physical Address Segmentation

8086 Microprocessor
 A 40pin, +5V supply, VLSI Chip launched by Intel in 1978

 Other family members of 8086:
8088, 80186, 80286, 80386, 80486, Pentium
 A 16-bit microprocessor with
• 16-bit Data Bus
• 20-bit Address Bus
 Generates 20-bit address by multiplexing Address-Data
(AD0-AD15) and Address-Status (A15-A16/S3-S6) buses
 Can access up to 220 =1 MB memory (00000H - FFFFFH)
 Clock input frequency: 5MHz-10MHz
 Can operate in two modes- Minimum and Maximum
 can support up to 64K I/O ports
8086 Chip
8086 Internal Architecture
 8086 architecture has two blocks or units:
-Bus Interface Unit (BIU): handles read/write operations from/to Memory/IO
-Execution Unit (EU): Decoding/Execution and Control
 It employs asynchronous parallel processing (or pipelining)
in which both units operate at the same time & thus in
contrast to 8085 it performs instruction fetching & execution
simultaneously to speed up the process
8086 MPU
Fetching Bus Interface

Unit (BIU)
Decoding
Execution Unit
& (EU)
Execution
BIU/EU
 The 8086 CPU logic has been partitioned into two functional units
namely BIU & EU
 The major reason for this separation is to increase the processing
speed of the processor
 BIU contains Instruction queue, Segment registers, Instruction
pointer, Address adder
 BIU performs all external transactions (bus operations) such as
instruction fetching, reading/writing operands from/to memory and
I/O devices. It also calculates 20-bit physical addresses
 BIU pre-fetches instruction bytes (upto 6) in a FIFO register called
instruction queue
 EU contains Control circuitry, Instruction decoder, ALU, Pointer &
Index register and Flag register
 EU decodes & executes instructions from instruction queue. Control
unit in EU generates various control signals
 While EU is executing instructions, BIU keeps on fetching instruction
(but upto a max. of 6) in the queue. This parallel processing of both
units is called pipelining which speeds up the overall process
Memory
∑ Interface
EXTRA SEGMENT (ES) FIFO BIU

CODE SEGMENT (CS) 6 5 4 3 2 1
STACK SEGMENT (SS)
DATA SEGMENT (DS) Instruction Queue
INSTRUCTION POINTER (IP)
Instruction
Decoder
AH AL AX
BH BL BX
ARITHMETIC
CH CL CX LOGIC UNIT
DH DL DX
CONTROL
SYSTEM
STACK POINTER (SP)
BASE POINTER (BP) OPERANDS
SOURCE INDEX (SI)
DESTINATION INDEX (DI)
FLAGS
EU
8086 REGISTER ORGANIZATION
Type Register Name of the
ES Extra Segment size Register
CS Code Segment
SS Stack Segment General 16 bit AX, BX, CX, DX
DS Data Segment purpose
registers
IP Instruction Pointer 8 bit AL, AH, BL, BH,
CL, CH, DL, DH
AX AH AL Accumulator
BL Pointer 16 bit SP, BP
BX BH Base Register
registers
CX CH CL Count Register
DX DH DL Data Register Indexed 16 bit SI, DI
Stack Pointer registers
SP
BP Base Pointer
Instruction 16 bit IP
SI Source Index
Pointer
DI Destination Index
FLAGS Segment 16 bit CS, DS, SS, ES
registers
Flags 16 bit Flag register

General Purpose Registers
8086 has 8 general purpose registers which:
 Can be individually used for storing 8-bit data
 Two registers can be combined to store 16-bit data
 Valid register pairs are: AX, BX, CX, DX
 AX is also called Accumulator having some special features
 BX, also called Base Register is the only general purpose
register which can also be used in based-addressing mode
 CX is also used as a default Counter Register in some
instructions (SHIFT, ROTATE & LOOP)
 DX or Data Register is also Acc. AH AL AX
used by default to store upper
16-bit data in division and Base BH BL BX
multiplication operations
Counter CH CL CX
Data DH DL DX
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations
BX Base register Used to hold base value in base addressing mode to access
memory data
CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions
DX Data Register Used to hold data for multiplication and division operations
SP Stack Pointer Used to hold the offset address of top stack memory location
BP Base Pointer Used to hold the offset or base value in based addressing
mode to access data from stack memory
SI Source Index Used to hold index value of source operand (data) for string
instructions
DI Data Index Used to hold the index value of destination operand (data) for
string operations
Flag Register
Flag register is a 16-bit register with 9 active flags
U U U U OF DF IF TF SF ZF U AF U PF U CF
1. CF CARRY FLAG
2. PF PARITY FLAG
Conditional Flags
3. AF AUXILIARY CARRY (Compatible with 8085, except OF):
4. ZF ZERO FLAG Set/Reset by ALU on the basis
5. SF SIGN FLAG of results of arithmetic
6. OF OVERFLOW FLAG
operations
7. TF TRAP FLAG Control Flags:

8086 Flag
Register Auxiliary Carry Flag Carry Flag
This is set, if there is a carry from the lowest This flag is set, when there is a
nibble, i.e, bit three during addition, or carry out of MSB in case of
borrow for the lowest nibble, i.e, bit three, addition or a borrow in case of
during subtraction. subtraction.
Sign Flag Zero Flag Parity Flag
This flag is set, when the result This flag is set, if the result of the This flag is set to 1, if the lower byte of
of any computation is negative computation or comparison the result contains even number of
performed by an instruction is zero 1’s ; for odd number of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed operation enters the single step execution
is large enough to accommodate in a destination register. The result is of mode by generating internal
more than 7-bits in size in case of 8-bit signed operation and more than 15- interrupts after the execution of
bits in size in case of 16-bit sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit is ‘0’, the
string is processed beginning from the lowest address to the highest Causes the 8086 to recognize external
address, i.e., auto incrementing mode. Otherwise, the string is mask interrupts; clearing IF disables these
processed from the highest address towards the lowest address, i.e., interrupts. 10
auto incrementing mode.
Memory Segmentation in 8086
 8086 has a 20-bit address bus & thus can address a maximum of
1MB of memory
 But 8086 has 16-bit registers which can hold only 16-bit addresses
 Solution is to divide 1MB memory in 64KB segments (total sixteen)
as they can be accessed by using 16-bit addresses. However, only 4
segments are accessible by 8086 at a time. These 4 segments are:
• Code segment: Used for storing the codes or instructions
• Stack segment: Used as a stack
• Data segment: Used for storing data
• Extra segment: Used for storing in-excess data
 Address of a segment is of 20-bits, however, within a segment a
memory location can be specified or accessed using a 16-bit
address called effective address or offset
Advantages of Memory Segmentation:
 Allows the memory capacity to be 1MB although actual addresses to
be handled are of 16-bit size
 Allows the placing of code, data and stack portions of the same
program in different parts (segments) of the memory, for data and
code protection.
Memory
64KB Memory 1
00000H
Segment 2
3
4
4
5
Only 4 such segments can be 6
addressed (active) at a time 7
8
1MB
9 Address
10 Range
11
12
13
14
15
16
FFFFFH
Memory
Code Segment 1
00000H
2
4
Data & Extra 5
Segments 6
8
1MB
9 Address
• Segments may or may not be Range
10
consecutive 11
• Segments can also be contiguous 12
13
(adjacent), disjointed or overlapping
14
15
Stack Segment 16 FFFFFH

SEGMENT REGISTERS
Segment registers
(CSR, DSR, SSR & 1 00000H
ESR) hold upper
16-bits of 20-bits CSR 1000 0H Code Segment
starting address 3
of segments
4
DSR 4000 0H Data Segment

Extra Segment
ESR 5000 0H
7
Starting Addresses
8
1MB
9
We can take any value Address
Range
of Segments
of starting address of a 10
segments but it must be 11
divisible by 16 and
12
lowest 4 bits (lowest
hex digit) must be 0 13
14
15
SSR F000 0H Stack Segment

FFFFFH
Memory
Instruction Pointer
 Instruction Pointer (IP) is a 16-bit register that identifies the
location of the next instruction to be fetched from the code
segment
 It contains the offset or effective address of the next instruction
instead of its physical address
 IP and CS are both 16-bit registers, but a 20-bit address is
needed to access memory
 The offset in IP is combined with the starting address of CS
(contained by CSR) to generate 20-bit physical address of the
next instruction
 The offset or effective address (EA) is a 16-bit address which
points to a memory location within a segment
 Every time an instruction is fetched from memory, 8086 updates
IP by incrementing it by two (instead of one as in 8085)
because it reads two bytes at a time
Intel Physical Address Generation in 8086
 The 20-bit physical address is generated by adding 16-bit contents of a
segment register with an 16-bit offset value (also called Effective Address)
which is stored in a corresponding default register (either in IP, BX, SI, DI,
BP or SP. Different segments have different default register for offset, for
example IP is default offset register for Code Segment)
 BIU always appends 4 zeros automatically to the 16-bit address of a segment
register (to make it 20-bit) because it knows the starting address of a
segment always ends with 4 zeros
Points to a memory Offset Value (16 bits)

location within a
segment
CS DS ES SS Segment Register (16 bits) 0000
IP BX DI BP Upper 16bit of starting

address of a segment 20-bits 16-bits
DI SP
Actual address for
SI memory Adder
Default Registers Assigned to store

offset values for different segments Physical Address (20 Bits)
Physical Address Calculation
 Offset is derived from the combination of

pointer registers, index registers the
Instruction Pointer, and immediate values Segment address 0000
(called displacement)
+ Offset
Memory address
 Examples
CS 3 4 8 A 0 SS 5 0 0 0 0
IP + 4 2 1 4 SP + F F E 0
Instruction 3 8 A B 4 Stac 5 F F E 0
(code) k
address 1 2 3 4 0 addr
DS
ess
DI + 0 0 2 2
Data 1 2 3 6 2
addr
ess
Example of Physical Address Generation for Code Segment
Memory
Start of Code Segment
1 00000H
(348A0H) Data
Segment
IP = 4214H 3
4
Code Byte at 38AB4H
Code
Segment
Extra
Segment
7 1MB
8 Address
9
Range
CS 348A0 H 10
11
IP + 4214 H 12
Physical Address 38AB4 H 13
14
15
Stack
Segment FFFFFH
Example of Physical Address Generation for Data Segment
0H
05C00H
DS: 05C0
05C50H
SI 0050 DS:EA
Memory
05C0 0
Segment Register
Offset + 0050
Physical Address 05C50H 0FFFFFH
Data is fetched with respect to the DS register which contains starting

or base address
The effective address (EA) or offset is in SI (default register for DS)
The EA depends on the addressing mode

Example of Physical Address Generation for Stack Segment
0H
0A00 0A000H
SS:
0A100H
SP 0100 SS:SP
Memory
0A00 0
Segment Register
Offset + 0100
Physical Address 0A100H 0FFFFFH
The offset is given by the SP register.

The stack is always referenced with respect to the stack segment register.
The stack grows toward decreasing memory locations.
The SP points to the last or top item on the stack.
Pin Diagram of Intel 8086
This set of
pins works in
two modes
For Minimum Mode
For Maximum Mode

AD0 – AD15 (Bi-directional)
These lines are multiplexed

bi-directional address/data
bus.
During T1, they carry lower
order 16-bit address.
In the remaining clock
cycles, they carry 16-bit
data.
AD0-AD7 carry lower order
byte of data.
AD8-AD15 carry higher order
byte of data.
A19/S6, A18/S5, A17/S4, A16/S3
(Unidirectional)
 These lines are multiplexed

unidirectional address and
status bus.
 During T1, they carry higher
order 4-bit address.
 In the remaining clock cycles,
they carry status signals.
BHE / S7 (Output)
BHE stands for Bus High

Enable.
BHE signal is used to
indicate the transfer of data
over higher order data bus
(D8 – D15).
It is multiplexed with status
pin S7.
RD (Read) (Output)
 It is a read signal used

for read operation.
 It is an output signal.
 It is an active low
signal.
READY (Input)
This is an acknowledgement
signal from slower I/O
devices or memory.
It is an active high signal.
When high, it indicates that
the device is ready to transfer
data.
When low, then
microprocessor is in wait
state.
RESET(Input)
It is a system reset.

It is an active high signal.
When high, microprocessor
enters into reset state and
terminates the current
activity.
It must be active for at least
four clock cycles to reset
the microprocessor.
INTR (Input)
 It is an interrupt request
signal.
 It is active high.
 It is level triggered.
NMI (Input)
 It is a non-maskable
interrupt signal.
 It is an active high.
 It is an edge triggered
interrupt.
TEST (Input)
 It can be used to test the

status of math co-processor
(8087)
 The BUSY pin of 8087 is
connected to this pin of
8086.
 If low, execution continues
else microprocessor is in
wait state.
CLK (Input)
 This clock input provides

the basic timing for
processor operation.
 The range of frequency of
different versions is 5 MHz,
8 MHz and 10 MHz.
VCC and VSS (Input)
 VCC is power supply signal.

 +5V DC is supplied
through this pin.
VSS is ground signal.
MN / MX (Input)
 8086 works in two modes:

• Minimum Mode
• Maximum Mode
 If MN/MX is high, it works
in minimum mode.
 If MN/MX is low, it works in
maximum mode.
 Pins 24 to 31 issue two
different sets of signals.
 One set of signals is
issued when CPU
operates in minimum
mode.
 Other set of signals is
issued when CPU
operates in maximum
mode.
Pin Description for Minimum
Mode
INTA (Output)
 This is an interrupt
acknowledge signal.
 When microprocessor
receives INTR signal, it
acknowledges the interrupt
by generating this signal.
 It is an active low signal.
ALE (Output)
 This is an Address Latch

Enable signal.
 It indicates that valid
address is available on bus
AD0 – AD15.
 It is an active high signal
and remains high during T1
state.
 It is connected to enable pin
of latch 8282.
DEN (Output)
 This is a Data Enable signal.

 This signal is used to enable
the transceiver 8286.
 Transceiver is used to
separate the data from the
address/data bus.
DT / R (Output)
 This is a Data
Transmit/Receive signal.
 It decides the direction of
data flow through the
transceiver.
 When it is high, data is
transmitted out.
 When it is low, data is
received in.
M / IO (Output)
 This signal is issued by the

microprocessor to
distinguish memory
access from I/O access.
 When it is high, memory is
accessed.
 When it is low, I/O devices
are accessed.
WR (Output)
 It is a Write signal.
 It is used to write data in
memory or output device
depending on the status of
M/IO signal.
HOLD (Input)
 When DMA controller

needs to use address/data
bus, it sends a request to
the CPU through this pin.
 It is an active high signal.
 When microprocessor
receives HOLD signal, it
issues HLDA signal to the
DMA controller.
HLDA (Output)
 It is a Hold Acknowledge
signal.
 It is issued after receiving
the HOLD signal.
 It is an active high signal.
Pin Description for Maximum
Mode
QS1 and QS0 (Output)
These pins provide the

status of instruction queue.
QS1 QS0 Status
0 0 No operation
0 1 1st byte of opcode from queue
1 0 Empty queue
1 1 Subsequent byte from queue

S0, S1, S2 (Output)
 These status signals

indicate the operation being
done by the microprocessor.
 This information is required
by the Bus Controller 8288.
 Bus controller 8288
generates all memory and
I/O control signals.
S0, S1, S2 (Output)
S2 S1 S0 Status
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive
LOCK (Output)
 This signal indicates that other

processors should not ask CPU
to relinquish the system bus.
 When it goes low, all interrupts
are masked and HOLD request
is not granted.
 This pin is activated by using
LOCK prefix on any instruction.
RQ/GT1 and RQ/GT0 (Bi-directional)
 These are Request/Grant pins.

 Other processors request the
CPU through these lines to
release the system bus.
 After receiving the request,
CPU sends acknowledge signal
on the same lines.
 RQ/GT0 has higher priority than

RQ/GT1.
8086 Minimum Mode
 In the minimum mode of 8086, MN/MX pin is connected
to logic 1 (+5V )
 There is a single processor (8086) in this mode
 All the control signals are given out by the
microprocessor chip itself.
 Other supporting components in the system are latches,
transreceiver, clock generator, memory and I/O devices.
 Requires less (or minimum) hardware (than maximum
mode) & thus less costly but can not be used in large
multiprocessor systems
No extra
processor
except 8086
is used
Octal
transceiver
51
8086 Maximum Mode
 In the maximum mode, the 8086 is operated by connecting MN/MX
pin to ground (logic 0).
 In the maximum mode, there may be more than one processor in
the system (e.g. math co-processor 8087)
 A bus controller (8288) is also used in this mode which is connected
to 8086 by using status signals S2,S1,S0. Some of the control
signals in this mode are generated by 8288 instead of 8086
 8288 derives (regenerates) various control signals like ALE, DEN,
DT/R, Memory read/write (MRDC, MWTC), I/O read/write (IORC,
IOWC), AMWC & AIOWC by using information at status signals
S2,S1,S0 supplied by 8086
 Other supporting components in the system are same as in
minimum mode (latches, transreceiver, clock generator, memory
and I/O devices)
 This mode is costly due to greater hardware but is useful in large
multiprocessor systems
8288 Input & output
Derived
control
signals
Octal
transceiver54
T1 T2 T3 TW T4 READ BUS
CYCLE IN 8086
CLK
M/IO
ALE
ADDR/ MEMORY ACCESS TIME

DATA A15-
RESERVED VALID
FOR DATA D15-
A0
D0
ADDR/
STATUS A19-
A16
RD
DT/R
DEN
T1 T2 T3 TW T4 WRITE BUS
CYCLE IN 8086
CLK
M/IO
ALE
ADDR/
DATA A15- DATA OUT (D15-D0)
A0
ADDR/
STATUS A19-
A16
WR
DT/R
DEN
8086 MEMORY ORGANIZATION
 8086 supports 220 = 1,048,576 bytes (1Mbytes) of memory over the
address range 0000016 to FFFFF16 (00000H to FFFFFH)
 Two consecutive bytes can be accessed as one word (16-bits)
 The lower-addressed byte is the least significant byte of the word, and
the higher-addressed byte is its most significant byte
 Address of lower byte of word is called address of the full word
 Memory space of 1MB is divided into two chips (called banks) of
512KB each having even & odd addresses
 This is done because most memories are ‘byte-oriented’ (1 byte
read/write at a time), but as 8086 is capable to read/write 16-bit (2
bytes) at a time, we need to use two chips for 16-bit word operations
 Two banks have alternate addresses because 16-bit words are stored
in consecutive locations & at the same time 8086 must access both
banks simultaneously for 16-bit operations
 If we had used only 1 chip of 1MB, 8086 could read only 1 byte at a
time & thus would need two operations (bus cycles) for every 16-bit
word operation. Thus process would have been slower.
8086 MEMORY ORGANIZATION
(Also called BLE)

BYTE/WORD TRANFER IN 8086
A, B = any assumed
memory location address in
even, odd banks. Brackets
indicate contents of
location & not address
BYTE/WORD TRANFER IN 8086
Aligned
word
Misaligned
word
A word stored at an even-address boundary (00000H, 00002H, 00004H etc) is said to be

an aligned word while a word stored at an odd address boundary (00001H, 00003H,
00005H etc) is called misaligned word. A misaligned word requires two read
operations (or bus cycles) & thus double time
8086 INTERRUPTS
Sources of Interrupts in
8086:
Three types of interrupts sources are there in 8086:
1. An external signal applied to NMI or INTR input pin
(Hardware interrupt)
2. Execution of INTn (n=00H-FFH) instruction
(Software interrupt)
3.Interrupt caused by some error condition produced
in 8086 instruction execution process.
(Divide by zero, overflow errors etc)
8086
8086 Interrupts
Interrupts
Hardware
Hardware Software
SoftwareInterrupts
Interrupts
Interrupts
Interrupts INT
INT nn
Maskable
Maskable Nonmaskable
Nonmaskable 256
256Types
Typesof of
Interrupt
Interrupt Interrupt
Interrupt software
softwareInterrupts
Interrupts
(INTR)
(INTR) (NMI)
(NMI) INT
INT 00
00 to
to INT
INT FF
FF
The
Theprogrammer
programmer The
The programmer
programmer cannot
cannot
can
can choose
choose to
to mask
mask control
control when
when aa non non
specific
specific interrupts
interrupts maskable
maskableinterrupt
interruptisisserved
served
and
and re-enable
re-enable them
them
later
later The
Theprocessor
processorhas
hastotostop
stop
the
the main
main program
program to
to execute
execute
the
theNMI
NMIService
ServiceRoutine.
Routine.
8086 Interrupt Processing Steps
If an interrupt has been requested, the 8086 Microprocessor processes it by
performing the following series of steps:
1. Pushes the content of the flag register onto the stack to preserve the status of
IF and TF flags, by decrementing the stack pointer (SP) by 2
2. Disables the INTR interrupt by clearing IF in the flag register
3. Resets TF in the flag register, to disable the single step or trap interrupt
4. Pushes the content of the code segment (CS) register onto the stack by
decrementing SP by 2
5. Pushes the content of the instruction pointer (IP) onto the stack by
decrementing SP by 2
6. Performs an indirect far jump to the start of the interrupt service routine
(ISR) corresponding to the received interrupt.
Steps involved in processing an interrupt instruction by
the processor
Executes the Interrupt instruction
Jumps to the Interrupt Vector Table
Takes the CS and IP in the Vector Table
Pushes the existing CS and IP on the Stack
Loads the new CS and IP
Jumps to the ISR
Executes ISR
Comes back and continues the Main Program

Processing of an Interrupt by the 8086
Main Program Push flags register Interrupt Service

Clear IF and TF Routine (ISR)
Push CS and IP
Load CS and IP
Interrupt program
Interrupt :
:
:
Pop IP and CS :
Pop flags register :
:
IRET
RESET as a
Non-
Maskable
Interrupt
NMI pin connected to Ground : No interrupt

RESET
BUTTON
Non-Maskable Interrupt activated

by RESET button in 8086
(due to high on NMI pin)
003FFH Type FFH Interrupt (Available)
003FCH
Available Interrupts
(224)
Interrupt Vector Table (IVT)
Type 21H Interrupt (Available)

00084H
Type 20H Interrupt (Available)
00080H
Type 1FH Interrupt (Reserved)
0007CH
Reserved Interrupts
(27)
Type 05H Interrupt (Reserved)
00014H
Type 04H Interrupt (Over Flow)
00010H
Type 03H Interrupt (Break Point)
0000CH
Type 02H Interrupt (NMI)
00008H
Type 01H Interrupt Dedicated Interrupts
0004FH (Trap or Single step)
(05)
0003FH
CS CSInterrupt
Type 00H
00002H
(Divide by Zero)
IP 00001H IP
00000H
Interrupt Vector Table
2 bytes 00002H
CS LSB CS 00003H
CS MSB Type 0 or
INT 00 Interrupt
2 bytes 00000H
IP LSB IP00001H
IP MSB
CS LSB MSB
Given a vector, where is the ISR address stored in memory ?
Offset = Type number X 4

Example:- INT 02H
Offset = 02 x 4 = 08
= 00008H
256 Interrupts of 8086 are Divided into
3 Groups
1. Type 00 to Type 04 interrupts -
These are used for fixed operations and hence are called
dedicated interrupts
2. Type 05 to Type 31 interrupts

Not used by 8086,reserved for higher processors like 80286
80386 etc.
3. Type 32 to Type 255 interrupts

Available for user, called user defined interrupts. These can be
either H/W interrupts and activated through INTR line or can
be S/W interrupts.
Type – 0 :- Divide by Zero Error Interrupt
Quotient is large, cant be fit in AL/AX or divide by zero
Type –1:- Single step or Trap Interrupt
Used for executing the program in single step mode by setting
trap flag.
Type – 2:- Non-Maskable Interrupt
This interrupt is used for executing ISR of NMI pin (positive
edge signal), NMI can’t be masked by S/W.
Type – 3:- One-byte INT instruction interrupt
Used for providing break points in the program
Type – 4 Over flow Interrupt
Used to handle any overflow error after signed arithmetic.
An example of an interrupt generated
due to overflow error in an 8086 system
8086 Addressing Modes
1. Register Addressing
The instruction will specify the name of the register which
2. Immediate Addressing holds the data to be operated by the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to another 8-bit
6. Indexed Addressing register CL
7. Based Index Addressing (CL) ← (DH)
8. String Addressing
9. Direct I/O port Addressing
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing

In immediate addressing mode, an 8-bit or 16-bit data is
2. Immediate Addressing specified as part of the instruction
3. Direct Addressing
Example:
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is moved to DL
6. Indexed Addressing
(DL) ← 08H
7. Based Index Addressing
MOV AX, 0A9FH
10. Indirect I/O port Addressing The 16-bit data (0A9FH) given in the instruction is moved to
AX register
(AX) ← 0A9FH
2. Immediate Addressing
Here, the effective address of the memory location at
4. Register Indirect Addressing which the data operand is stored is given in the
instruction.
5. Based Addressing
The effective address is just a 16-bit number written
6. Indexed Addressing directly in the instruction.
7. Based Index Addressing Example:
8. String Addressing MOV BX, [1354H]

MOV BL, [0400H]
The square brackets around the 1354 H denotes the
contents of the memory location. When executed, this
11. Relative Addressing instruction will copy the contents of the memory location
into BX register.
This addressing mode is called direct because the
displacement of the operand from the segment base is
specified directly in the instruction.
1. Register Addressing In Register indirect addressing, name of the register which
holds the effective address (EA) will be specified in the
2. Immediate Addressing instruction.
3. Direct Addressing Registers used to hold EA are any of the following

registers:
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base address
calculation.
Example:
8. String Addressing Note : Register/ memory
MOV CX, [BX] enclosed in brackets refer to
9. Direct I/O port Addressing content of register/ memory

2. Immediate Addressing In Based Addressing, BX or BP is used to hold the base

value for effective address and a signed 8-bit or unsigned
3. Direct Addressing 16-bit displacement will be specified in the instruction.
5. Based Addressing When BX holds the base value of EA, 20-bit physical
address is calculated from BX and DS.
When BP holds the base value of EA, BP and SS is used.
Example:

MOV AX, [BX + 08H]

SI or DI register is used to hold an index value for memory
2. Immediate Addressing data and a signed 8-bit or unsigned 16-bit displacement will
be specified in the instruction.
Displacement is added to the index value in SI or DI
4. Register Indirect Addressing register to obtain the EA.
5. Based Addressing In case of 8-bit displacement, it is sign extended to 16-bit

before adding to the base value.

Example:
MOV CX, [SI + 0A2H]

In Based Index Addressing, the effective address is
2. Immediate Addressing computed from the sum of a base register (BX or BP), an
index register (SI or DI) and a displacement.
Example:
MOV DX, [BX + SI + 0AH]
5. Based Addressing

Employed in string operations to operate on string data.
The effective address (EA) of source data is stored in SI
4. Register Indirect Addressing register and the EA of destination is stored in DI register.
5. Based Addressing
Segment register for calculating base address of
source data is DS and that of the destination data is ES

Example: MOVS BYTE
Operations:
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA
11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
Note : Effective address of the

Extra segment register
(MAE) ← (MA)
If DF = 1, then (SI) ← (SI) – 1 and (DI) = (DI) - 1

If DF = 0, then (SI) ← (SI) +1 and (DI) = (DI) + 1
1. Register Addressing These addressing modes are used to access data from
standard I/O mapped devices or ports.
In direct port addressing mode, an 8-bit port address is
3. Direct Addressing directly specified in the instruction.
4. Register Indirect Addressing Example: IN AL, [09H]
5. Based Addressing Operations: PORTaddr = 09H

(AL) ← (PORT)

Content of port with address 09H is
moved to AL register
In indirect port addressing mode, the instruction will
9. Direct I/O port Addressing specify the name of the register which holds the port
address. In 8086, the 16-bit port address is stored in the
10. Indirect I/O port Addressing DX register.
11. Relative Addressing Example: OUT [DX], AX

Operations: PORTaddr = (DX)
(PORT) ← (AX)
Content of AX is moved to port

whose address is specified by DX
register.
In this addressing mode, the effective address of a
4. Register Indirect Addressing program instruction is specified relative to Instruction
Pointer (IP) by an 8-bit signed displacement.
5. Based Addressing
Example: JZ 0AH
Operations:
000AH ← 0AH (sign extend)
If ZF = 1, then
10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing MA = BA + EA
12. Implied Addressing If ZF = 1, then the program control jumps to new

address calculated above.
If ZF = 0, then next instruction of the program is

executed.
5. Based Addressing
6. Indexed Addressing Instructions using this mode have no operands. The

instruction itself will specify the data to be operated by
the instruction.
Example: CLC
This clears the carry flag to zero.

Interfacing I/O and peripheral devices
I/O devices
⇒ For communication between microprocessor and

outside world
⇒ Keyboards, CRT displays, Printers, Compact Discs

etc.
⇒ Ports
Ports/ /Buffer
BufferIC’s
IC’s
Microprocessor
Microprocessor I/I/OOdevices
devices
(interface
(interfacecircuitry)
circuitry)
⇒ Data transfer types

Memory mapped
Programmed I/ O
Data transfer is accomplished I/O mapped
through an I/O port
controlled by software
Interrupt driven I/ O
I/O device interrupts the
processor and initiate data
transfer
Direct memory access
Data transfer is achieved by
bypassing the microprocessor
Memory mapped I/O vs I/O mapped I/O
Memory mapping I/O mapping
20 bit address are provided for I/O devices 8-bit or 16-bit addresses are provided for
I/O devices
The I/O ports or peripherals can be treated Only IN and OUT instructions can be used
like memory locations and so all for data transfer between I/O device and
instructions related to memory can be processor
used for data transmission between I/O
device and processor
Data can be moved from any register to Data transfer takes place only between
ports and vice versa accumulator and ports
When memory mapping is used for I/O Full memory space can be used for
devices, full memory address space addressing memory.
cannot be used for addressing memory.
⇒ Suitable for systems which require large
⇒ Useful only for small systems where memory capacity
memory requirement is less

Physical Address Segmentation

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Physical Address Segmentation

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8086 Microprocessor

 A 40pin, +5V supply, VLSI Chip launched by Intel in 1978

Fetching Bus Interface

EXTRA SEGMENT (ES) FIFO BIU

Flags 16 bit Flag register

7. TF TRAP FLAG Control Flags:

Sign Flag Zero Flag Parity Flag

Direction Flag Interrupt Flag

• Segments can also be contiguous 12

Stack Segment 16 FFFFFH

DSR 4000 0H Data Segment

SSR F000 0H Stack Segment

Points to a memory Offset Value (16 bits)

CS DS ES SS Segment Register (16 bits) 0000

IP BX DI BP Upper 16bit of starting

Default Registers Assigned to store

 Offset is derived from the combination of

Physical Address 05C50H 0FFFFFH

Data is fetched with respect to the DS register which contains starting

The effective address (EA) or offset is in SI (default register for DS)

The EA depends on the addressing mode

Physical Address 0A100H 0FFFFFH

The offset is given by the SP register.

For Minimum Mode

For Maximum Mode

These lines are multiplexed

 These lines are multiplexed

BHE stands for Bus High

 It is a read signal used

It is a system reset.

 It can be used to test the

 This clock input provides

 VCC is power supply signal.

 8086 works in two modes:

 This is an Address Latch

 This is a Data Enable signal.

 This signal is issued by the

 When DMA controller

These pins provide the

QS1 QS0 Status

0 1 1st byte of opcode from queue

1 1 Subsequent byte from queue

 These status signals

 This signal indicates that other

 These are Request/Grant pins.

 RQ/GT0 has higher priority than

ADDR/ MEMORY ACCESS TIME

(Also called BLE)

A word stored at an even-address boundary (00000H, 00002H, 00004H etc) is said to be

Jumps to the Interrupt Vector Table

Takes the CS and IP in the Vector Table

Pushes the existing CS and IP on the Stack

Loads the new CS and IP

Jumps to the ISR

Comes back and continues the Main Program

Main Program Push flags register Interrupt Service

NMI pin connected to Ground : No interrupt

Non-Maskable Interrupt activated

Type 21H Interrupt (Available)

Given a vector, where is the ISR address stored in memory ?

Offset = Type number X 4

2. Type 05 to Type 31 interrupts

3. Type 32 to Type 255 interrupts

7. Based Index Addressing (CL) ← (DH)