VLSI Design

Assignment
Module 2
(1) Draw the stick diagram and layout diagram for the following and also estimate the area
(i) Y=𝐴𝐵𝐶
(ii) Y=(𝐴 + 𝐵 + 𝐶)𝐷
(iii) 𝑌 = 𝐴𝐵𝐶 + 𝐷
(iv) 𝑌 = 𝐴(𝐵 + 𝐶) + 𝐷𝐸
(2) What is scaling? Mention the types. Compute Current, Power, Current density, Power density,
Cox and doping densities for both the types of scaling.
(3) With neat diagrams, explain the lumped representation of parasitic MOSFET Capacitances.
(4) Mention different types of Oxide Capacitances in various regions of MOSFET Operation.
(5) Explain MOSFET Junction Capacitances in brief

Assignment
Module 3

1. Define the following terms (i) Propagation delay (ii) Contamination delay (iii)Rise time (iv) Fall
time (v) Edge rate with the help of waveforms
2. Explain various stages of Timing Optimization in VLSI
3. Write note on Timing Analyzer OR Make use of timing analyzer to compute slack of a given
circuit
4. Evaluate the transient response of a inverter for falling transition
Ideal step input
Practical(ramp) input
5. Explain the RC delay model and obtain equivalent RC circuit for MOSFETs and inverter.
6. Compute the delay of unit inverter and 3-input NAND Gate using RC delay model
7. Explain Elmore delay and compute the rising and falling propagation delay and rising and falling
contamination delay for a 3 input NAND gate
8. Estimate tpd for a unit inverter driving m identical unit inverters using Elmore delay model
9. Repeat 8, if the driver is W times the unit sized inverter
10. Explain linear model and find the logical effort of inverter, 2 and 3 input NAND gate, 2 and 3
input NOR gate
11. Define Path logical effort, Path Electrical Effort, Branching Effort and Path Stage Effort in a
multistage Logic Network
12. Estimate the minimum delay of the path from A to B in fig shown below and choose transistor
sizes to achieve this delay. The initial NAND2 gate may present a load of 8λ of transistor width
on the input and output load is equivalent to 45 λ of transistor widths