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Assignment 2
Assignment 2
MCQ:
1.WecanoptimisethedatapathofanFSMDby
A. Sharingasinglefunctionalunit,incasethesameoperationoccursindifferentstates.
B. ImplementingasharedALUsystemamongoperationsoccurringindifferentstates.
C. BothAandB
D. Noneoftheabove.
Solution:OptionC.BothAandB
Explanation:Onsharingthesamefunctionalunit,theonetoonemappingfromoperationtounit
willnotberequired.Also,sharinganALUwillreducethecomplexityofthedatapath
implemented.
2.FPGAscanbeusedforimplementing
A. HardwareSecurityModules(HSM)
B. HighFrequencyTrading(HFT)systems
C. BothAandB
D. Noneoftheabove
Solution:OptionC.BothAandB
Explanation:FPGAscanbeusedforimplementinganHSMsincetheycanbeusedfor
encryptionanddecryptionofdigitalsignaturesataverylowlatency.Thehighoperationspeed
ofFPGAsalsoallowtheaccelerationofdifferentcomponentsofanHFTsystemlikenetwork
stack,financialprotocolparsing.
3.TheinterconnectivityamongthecircuitalelementsofanFPGAinestablishedusing
A. Fuse
B. Antifuse
C. SRAM
D. BothBandC
Solution:OptionD.BothBandC
Explanation:AntifuseisusedinFPGAinsegmentedchannelroutingarchitecturesincethey
haveasmallareaandlowparasiticresistanceandcapacitance.SRAMcellsarepresentin
SRAM-basedFPGAsintheformarraysandtheyprogramtheinterconnectsintheFPGA.
4.SupposeIwanttouseasingleFPGAboardtoperformtwosetsofmathematicaloperations
oneaftertheother.Whatkindofinterconnectivitywillbesuitable?
A. AntifuseFPGA
B. SRAM-basedFPGA
C. BothAandB
D. Noneoftheabove
Solution:OptionB.SRAM-basedFPGA
Explanation:AntifuseFPGAsuseantifuses(lowresistancedeviceshavingasmallareaanda
limitedfieldofoperation).Hence,theyareprogrammableonlyonceandthereforecanperform
onlyonemathematicaloperationwhichdoesnotsatisfytherequirements.SRAM-basedFPGA
boardshavearraysofSRAMcellswhichprogramtheinterconnectivityandhencecanbe
programmedtoperformtwomathematicaloperationsoneaftertheother.
5.TheinputsofanyProgrammableLogicDeviceisfedthrough
A. ORgates
B. NORgates
C. ANDgates
D. NANDgates
Solution:OptionC.ANDgates
Explanation:TheinputisfedthroughtheANDgatefollowedbyinvertingand/ornoninverting
buffers.
6.TheConfigurableLogicBlocksonanFPGAcomprise
A. XORgate,transistor,Decoder
B. Johnsoncounter,transistor,HalfAdder
C. Flipflop,LUT,Multiplexer
D. Noneoftheabove
Solution:OptionC.Flipflop,LUT,Multiplexer
Explanation:Flipfloptostoreonebitofdata,LUTtocontainthepredefinedoutputofcertain
logicaloperations,andmultiplexertoselectbetweeninputs,arethecomponentsofaCLB.
7.WhichofthefollowingisalibraryinVHDL?
A. IEEE
B. std_logic_1164
C. numeric_std
D. Noneoftheabove
Solution:OptionA.IEEE
Explanation:IEEEisastandardlibraryinVHDL.std_logic_1164(usedtodefineinterconnection
datatypes)andnumeric_std(usedtodefinenumerictypesandstandardarithmeticfunctions)
arepackagesintheIEEElibrary.
8.WhattypeofFPGAispreferredfordesigningaerospacedevices?
A. AntifuseFPGAs
B. SRAM-basedFPGAs
C. BothAandB
D. Noneoftheabove
Solution:OptionA.AntifuseFPGAs
Explanation:AntifuseFPGAshaveafasterbootthanSRAM-basedFPGAs.Also,antifuse
FPGAsarenotaffectedbyradiation.
9.ReducingthesizeofCLBswillleadto
A. IncreaseinareaofFPGA
B. DecreaseinthepropagationdelayofFPGA
C. BothAandB
D. Noneoftheabove
Solution:OptionC.BothAandB
Explanation:ReducingthesizeofanCLBleadstoanincreaseintheirnumberintheFPGA.
AlsothepropagationdelayincreasesduetotheincreaseinthenumberofCLBs.
10.InVHDL,portdescriptionisgivenby
A. Identifier
B. Mode
C. Datatype
D. Alloftheabove
Solution:OptionD.Alloftheabove
Explanation:Portdescriptionhasanidentifier(notareservedword),mode(in,out,buffer),and
datatype(predefined).
Short-Answertype(Alphanumericanswersonly):
11.Whatisthedefaultsize(inbits)ofintegersinVHDL?
Solution:32
Explanation:VHDLwasmadeinthetimewhenthedominantprocessorsinthemarketwereof
32bits.EvennowforFPGAsthedefaultsizeiskeptto32bits.
12.AnalysethefollowingpieceofcodetodesignablinkingLED.
signalpulse:std.logic:=‘0’;
signalcount:integerrange0to4999:=0;
begin
counter:process(CLK)
begin
if‘CLK’eventandCLK=‘1’then
ifcount=4999then
count=0
pulse=notpulse
else
count+=1
endif
endif
endprocess
LED=pulse
end
HowmanytimesdoestheLEDblinkiftheabovecodeisprogrammedinanantifuseFPGAwith
theinterconnectionscodedtorunonce?
Solution:5000
Explanation:SincetheFPGAisantifuse,thecoderunsonlyforonce.Onanalyzingthecode,
weseethatthelooprunsfor5000timesandeachtimethecountertochecktheblinkofthe
LEDisincrementedtillitreaches4999.HencetheLEDblinks5000times.