CoA Lab Manual

Computer
Organization
and Architecture
Lab Manual
Semester IV
Department of CSE (AIML/CSBS)

Institute of Engineering & Management, SaltLake
Compiled by: Snehal Ghosh, Abhiroop Sarkar,

Debayan Ghosh (students of 2022-2026 batch)
under guidance of Prof. Tanima Bhowmick, Prof.
Mousumi Laha & Prof. Ankita Ray Chowdhury
Institute of Engineering
& Management, SaltLake
DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

Contents
SR. MARKS/
EXPERIMENT DATE
NO. GRADE
1 Basic Gates
2 Full/Half Adder
3 Full/Half Subtractor
4 4 X 1 Multiplexer
4 X 2 Encoder
5
2 X 4 Decoder
Carry LookAhead
6
Adder
7 Ripple Carry Adder
8 SR, JK & D FlipFlops
Course Outcomes (CO):
1. To develop ability to design the mechanism by
which the performance of the system can be
enhanced.
2. To understand memory storage & connec ons.
3. To understand the communica on among
processing elements inside the computer
architecture.
4. To understand how to simulate the electronic
circuits and measure their func onali es.
Program Specific Outcomes (PO)
PO
SUMMARY DESCRIPTION
NUMBER
Apply the knowledge of mathematics, science, engineering
Engineering
PO1 fundamentals, and an engineering specialization to the
knowledge
solution of the complex engineering problems.
Identify, formulate, research literature, and analyze complex
engineering problems reaching substantial conclusion using
PO2 Problem analysis
first principal of mathematics, natural science and
engineering sciences.
Design solutions for complex engineering problems and
Design/ design system components or processes that meet the
PO3 development of specified needs with appropriate consideration for the public
solutions health and safety, and the cultural, societal, and
environmental considerations.
Conduct Use research-based knowledge and research methods
investigations including designs of experiments analysis and interpretation
PO4
of complex of data and synthesis of information to provide valid
problems conclusions.
Create, select, and apply appropriate techniques, resources
Modern tool and modern engineering and IT tools including prediction
PO5
usage and modeling to complex engineering values activities with
an understanding of the limitation.
Apply reasoning informed by the contextual knowledge to
The engineer and assess societal, health, safety, legal and cultural issues and
PO6
society the consequent responsibilities relevant to the professional
engineering practice.
Understand the impact of professional engineering solutions
Environment and
PO7 in societal and environmental contexts, and demonstrate the
sustainability
knowledge of, and need for sustainable development.
Apply ethical principles and commit to professional ethics
PO8 Ethics
and responsibilities and norms of the engineering practice
Individual and Function effectively as an individual, and as a member or

PO9
team work leader in diverse teams, and in multidisciplinary settings
Communicate effectively on complex engineering
activities with the engineering community and with
P010 Communication society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
Project Demonstrate knowledge and understanding of the
P011 management and engineering and management principles and apply these to
finance one’s own work, as a member and leader in a team,
Recognize the need for, and have the preparation and ability
P012 Life-long learning to engage in independent and life-long learning in the
broadest context of technological change.

Program Outcomes (PSO)
PSO
Description
Number
Ability to understand the principles and development
methodologies of computer systems. Students can assess the
PSO 1
hardware of computer systems and possess professional skills and
knowledge of software design process.
Ability to apply mathematical methodologies to solve computation
PSO 2 task, model real world problem using appropriate data structure
and suitable algorithm.
Ability to use knowledge in various domains to identify research
PSO 3
gaps and hence to provide solution to new ideas and innovations.
Program Educational Objectives (PEO)

PEO 01: High Quality Engineering Design and Development Work:
Graduates of the program will engage in the effective practice of computer
science and engineering to identify and solve important problems in a diverse
range of application areas.
PEO 02: Real Life Problem Solving:

To educate students with proficiency in core areas of Computer science &
Engineering and related engineering so as to comprehend engineering trade-
offs, analyze, design, and synthesize data and technical concepts to create
novel products and solutions for the real life problems.
PEO 03: Leadership:

Graduates of the program will engage in successful careers in industry,
academia and attain positions of importance where they have impact on their
business, profession and community.
PEO 04: Lifelong Learning:

Graduates of the program will adapt to contemporary technologies, tools and
methodologies to remain at the frontier of computer science and engineering
practice with the ability to respond to the need of a challenging environment.
Reference Resources
https://github.com/Abhiroop2004/Computer-Organization-and-Architecture-Lab

Computer Organization and Architecture Lab Manual
EXPERIMENT 1: BASIC & UNIVERSAL GATES
DEPARTMENT OF CSE (AIML/CSBS)
NAME OF THE STUDENT
ROLL NO.
DATE OF EXPERIMENT
DATE OF SUBMISSION
GRADE/MARKS
TEACHER’S SIGNATURE

IMPLEMENTATION OF AND, OR, NOT,

NAND, NOR & XOR USING VHDL
Theory:
The basic logic gates are the building blocks of more complex logic circuits.
These logic gates perform the basic Boolean func ons, such as AND, OR,
NAND, NOR, Inversion, Exclusive-OR, Exclusive-NOR. It is seen that each gate
has one or two binary inputs, A and B, and one binary output, C. The small
circle on the output of the circuit symbols designates the logic complement.
The AND, OR, NAND, and NOR gates can be extended to have more than two
inputs. A gate can be extended to have mul ple inputs if the binary opera on
it represents is commuta ve and associa ve. These basic logic gates are
implemented as small-scale integrated circuits (SSICs) or as part of more
complex medium scale (MSI) or very large-scale (VLSI) integrated circuits.
The OR, AND, and NOT are the three basic logic gates as they together can
construct the logic circuit for any given Boolean expression. NOR and NAND
gates have the property that they individually can be used to hardware-
implement any logic circuit. For this reason, the NAND and NOR gates are
called universal gates.
Observations
INPUT OUTPUT
A B AND NAND OR NOR XOR NOT GATE
INPUT
0 0 OUTPUT
0 1 0
1 0 1
1 1

And Gate Testbench
library IEEE; wait for 1 ns;
use IEEE.std_logic_1164.all; assert(q_out='0') report "Fail 1/0"
severity error;
en ty testbench is
-- empty a_in <= '1';
end testbench; b_in <= '1';
wait for 1 ns;
architecture tb of testbench is assert(q_out='1') report "Fail 1/1"
severity error;
-- DUT component
component and_gate is -- Clear inputs
port( a_in <= '0';
a, b : in std_logic; b_in <= '0';
q : out std_logic);
end component; assert false report "Test done."
severity note;
signal a_in, b_in, q_out: std_logic; wait;
end process;
begin end tb;
-- Connect DUT
DUT: and_gate port map (a_in, b_in,
q_out); design.vhd
library IEEE;
process use IEEE.std_logic_1164.all;
begin en ty and_gate is
a_in <= '0'; port(
b_in <= '0'; a, b: in std_logic;
wait for 1 ns; q: out std_logic);
assert(q_out='0') report "Fail 0/0" end and_gate;
severity error;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
assert(q_out='0') report "Fail 0/1"
severity error;
a_in <= '1';

b_in <= '0';

Or Gate Testbench
severity error;
en ty testbench is
-- empty a_in <= '1';
wait for 1 ns;
severity error;
-- DUT component
component or_gate is -- Clear inputs
port( a_in <= '0';
q : out std_logic);
severity note;
end process;
begin end tb;
-- Connect DUT
DUT: or_gate port map (a_in, b_in,
q_out); design.vhd
library IEEE;
begin en ty or_gate is
a_in <= '0'; port(
assert(q_out='0') report "Fail 0/0" end or_gate;
severity error;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
severity error;
a_in <= '1';

b_in <= '0';

Nand Gate Testbench
severity error;
en ty testbench is
-- empty a_in <= '1';
wait for 1 ns;
severity error;
-- DUT component
component nand_gate is -- Clear inputs
port( a_in <= '0';
q : out std_logic);
severity note;
end process;
begin end tb;
-- Connect DUT
DUT: nand_gate port map (a_in, b_in,
q_out); design.vhd
library IEEE;
begin en ty nand_gate is
a_in <= '0'; port(
assert(q_out='1') report "Fail 0/0" end nand_gate;
severity error;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
severity error;
a_in <= '1';

b_in <= '0';

Nor Gate Testbench
severity error;
en ty testbench is
-- empty a_in <= '1';
wait for 1 ns;
severity error;
-- DUT component
component nor_gate is -- Clear inputs
port( a_in <= '0';
q : out std_logic);
severity note;
end process;
begin end tb;
-- Connect DUT
DUT: nor_gate port map (a_in, b_in,
q_out); design.vhd
library IEEE;
begin en ty nor_gate is
a_in <= '0'; port(
assert(q_out='1') report "Fail 0/0" end nor_gate;
severity error;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
severity error;
a_in <= '1';

b_in <= '0';

Xor Gate Testbench
severity error;
en ty testbench is
-- empty a_in <= '1';
wait for 1 ns;
severity error;
-- DUT component
component xor_gate is -- Clear inputs
port( a_in <= '0';
q : out std_logic);
severity note;
end process;
begin end tb;
-- Connect DUT
DUT: xor_gate port map (a_in, b_in, design.vhd
q_out); library IEEE;
use IEEE.std_logic_1164.all;
process en ty xor_gate is
begin port(
a_in <= '0'; a, b: in std_logic;
b_in <= '0'; q: out std_logic);
wait for 1 ns; end xor_gate;
severity error;
a_in <= '0';

b_in <= '1';
wait for 1 ns;
severity error;
a_in <= '1';

b_in <= '0';

Not Gate Testbench
library IEEE; -- Clear inputs
use IEEE.std_logic_1164.all; a_in <= '0';
en ty testbench is assert false report "Test done."

-- empty severity note;
end testbench; wait;
end process;
architecture tb of testbench is end tb;
-- DUT component
component not_gate is
port(
a : in std_logic;
q : out std_logic);
end component;
signal a_in, q_out: std_logic; design.vhd

library IEEE;
begin
en ty not_gate is
-- Connect DUT
port(
DUT: not_gate port map (a_in, q_out);
a: in std_logic;
q: out std_logic);
process
end not_gate;
begin
a_in <= '0';
wait for 1 ns;
assert(q_out='1') report "Fail 0"
severity error;
a_in <= '1';

wait for 1 ns;
assert(q_out='0') report "Fail 1"
severity error;
Please provide the waveforms generated by your code and specify whether they verify truth tables

EXPERIMENT 2 : HALF/FULL ADDER
NAME OF THE STUDENT
ROLL NO.
DATE OF EXPERIMENT
DATE OF SUBMISSION
GRADE/MARKS

DESIGN & IMPLEMENTATION OF HALF/

FULL ADDER USING VHDL
Theory:
Half-Adder
A half-adder is a combina onal logic circuit that performs the addi on of two
bits, A and B. The output of the half-adder is two bits: the sum bit, S, and the
carry bit, C. The Boolean func ons describing the half-adder are as follows:
Sum bit: S = A ⊕ B Carry bit: C = A ⋅ B
Half-Adder using X-OR and basic gates Half-Adder using NAND gate only
Full-Adder
A full-adder is a combina onal
logic circuit that performs the
addi on of two bits, A and B, and
a carry-in bit, Cin. The output of
the full-adder is two bits: the
sum bit, S, and the carry bit, Cout.
Sum bit: S = (A ⊕ B) ⊕ Cin
Carry bit: Cout = A ⋅ B + Cin ⋅ (A ⊕ B) Full-Adder using X-OR and basic gates
Full-Adder using
NAND gate only

Truth Table
Half Adder
INPUT OUTPUT
A B Sum Carry
0 0
0 1
1 0
1 1
K-map: Sum Carry

A B B’ (0) B (1) A B B’ (0) B (1)
A’ (0) A’ (0)
A (1) A (1)
Sum: Carry:
Full Adder
INPUT OUTPUT
A B Cin Sum Cout
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
K-map: Sum Carry

BCin B’Cin’ B’Cin BCin BCin’ BCin B’Cin’ B’Cin BCin BCin’
A (00) (01) (11) (10) X (00) (01) (11) (10)
A’ (0) A’ (0)
A (1) A (1)
Sum: Carry:

Half Adder Testbench a_in <= '1';
library IEEE; b_in <= '0';
use IEEE.std_logic_1164.all; wait for 1 ns;
assert(sum_out='1');
en ty testbench is assert(carry_out='0')
-- empty report "Fail 1/X" severity error;
end testbench;
a_in <= '1';
architecture tb of testbench is b_in <= '1';
wait for 1 ns;
-- DUT component assert(sum_out='0');
component half_adder is assert(carry_out='1')
port( report "Fail 1/1" severity error;
a, b: in std_logic;
sum, carry: out std_logic); -- Clear inputs
end component; a_in <= '0';
b_in <= '0';
signal a_in, b_in, sum_out,
carry_out: std_logic; assert false report "Test done."
severity note;
begin wait;
end process;
-- Connect DUT end tb;
DUT: half_adder port map( Dataflow Model
a_in, b_in, sum_out, carry_out); library ieee;
use ieee.std_logic_1164.all;
process
en ty half_adder is
begin
port (a, b: in std_logic;
a_in <= '0';
sum, carry: out std_logic);
b_in <= '0';
end half_adder;
wait for 1 ns;
assert(sum_out='0'); architecture dataflow of half_adder is
assert(carry_out='0') begin
sum <= a xor b;
report "Fail 0/0" severity error; carry <= a and b;
end dataflow;
a_in <= '0';
b_in <= '1';
wait for 1 ns;
assert(carry_out='0')
report "Fail 0/0" severity error;

Behavioral Model
library ieee;
en ty half_adder is
end half_adder;
architecture behavior of half_adder is
begin
ha: process (a, b)
begin
if a = ‘1’ then
sum <= not b;
carry <= b;
else
sum <= b;
carry <= ‘0’;
end if;
end process ha;
end behavior;
Structural Model
library ieee;
en ty half_adder is
sum, carry: out std_logic); architecture structure of half_adder is
component xor_gate
end half_adder; port (i1, i2: in std_logic;
o1: out std_logic);
end component;
component and_gate
port (i1, i2: in std_logic;
o1: out std_logic);
end component;
begin
u1: xor_gate port map (i1 => a, i2 => b, o1 => sum);
u2: and_gate port map (i1 => a, i2 => b, o1 => carry_out);
end structure;

Full Adder Testbench assert(sum_out='1');
library IEEE; assert(carry_out='0');
use IEEE.std_logic_1164.all; report "Fail 0/0/1" severity error;
en ty testbench is a_in <= '0';

-- empty b_in <= '1';
end testbench; c_in <= '0';
wait for 1 ns;
architecture tb of testbench is assert(sum_out='1');
assert(carry_out='0');
-- DUT component report "Fail 0/1/0" severity error;
component full_adder is
port( a_in <= '0';
a,b,c: in std_logic; b_in <= '1';
sum,carry: out std_logic); c_in <= '1';
end component; wait for 1 ns;
signal a_in, b_in, c_in, sum_out, assert(carry_out='1');
carry_out: std_logic; report "Fail 0/1/1" severity error;
begin a_in <= '1';

b_in <= '0';
-- Connect DUT c_in <= '0';
DUT: full_adder port map wait for 1 ns;
(a_in, b_in, c_in, sum_out, carry_out); assert(sum_out='1');
process report "Fail 1/0/0" severity error;
begin
a_in <= '0'; a_in <= '1';
b_in <= '0'; b_in <= '0';
c_in <= '0'; c_in <= '1';
wait for 1 ns; wait for 1 ns;
assert(sum_out='0'); assert(sum_out='0');
assert(carry_out='0'); assert(carry_out='1');
report "Fail 0/0/0" severity error; report "Fail 1/0/1" severity error;
a_in <= '0'; a_in <= '1';

b_in <= '0'; b_in <= '1';
c_in <= '1'; c_in <= '0';

report "Fail 1/1/0" severity error;
a_in <= '1';

b_in <= '1';
c_in <= '1';
wait for 1 ns;
assert(sum_out='1'); Behavioral Model
assert(carry_out='1'); library ieee;
report "Fail 1/1/1" severity error; use ieee.std_logic_1164.all;
en ty full_adder is
-- Clear inputs port (a, b, c: in std_logic;
a_in <= '0'; sum, carry: out std_logic);
b_in <= '0'; end full_adder;
c_in <= '0'; architecture Behavioral of full_adder is
begin
assert false report "Test done." process(a,b,c)
severity note; begin
wait; if(a='0' and b='0' and c='0')then
sum<='0'; carry<='0';
end process; elsif( a='0' and b='0' and c='1')then
end tb; sum<='1'; carry<='0';
elsif( a='0' and b='1' and c='0')then
sum<='1'; carry<='0';
elsif( a='0' and b='1' and c='1')then
sum<='0'; carry<='1';
Dataflow Model elsif( a='1' and b='0' and c='0')then
library ieee; sum<='1'; carry<='0';
use ieee.std_logic_1164.all; elsif( a='1' and b='0' and c='1')then
sum<='0'; carry<='1';
en ty full_adder is elsif( a='1' and b='1' and c='0')then
port (a, b, c: in std_logic; sum<='0'; carry<='1';
sum, carry: out std_logic); else
end full_adder; sum<='1'; carry<='1';
end if;
architecture dataflow of full_adder is end process;
begin end Behavioral;
sum <= a XOR b XOR c ;
carry <= (a AND b) OR (c AND a) OR (c AND b) ;
end dataflow;

Structural Model
library ieee;
en ty full_adder is
port (a, b, c: in std_logic;
end full_adder;
architecture structural of full_adder is
signal a1, a2, a3: std_logic;
begin
a1 <= a xor b;
a2 <= a and b;
a3 <= a and c;
carry <= a2 or a3;
sum <= a1 xor c;
end structural;

EXPERIMENT 3 : HALF/FULL SUBTRACTOR
NAME OF THE STUDENT
ROLL NO.
DATE OF EXPERIMENT
DATE OF SUBMISSION
GRADE/MARKS

DESIGN & IMPLEMENTATION OF HALF/

FULL SUBTRACTOR USING VHDL
Theory:
Half Subtractor
Subtrac ng a single-bit binary value B
from another A (i.e. A -B) produces a
difference bit D and a borrow out bit B-
out. This opera on is called half
subtrac on and the circuit to realize it is
called a half subtractor. Half Subtractor using basic gates
A half subtractor is a
digital circuit that
computes the difference
(D) and the borrow-out
(Br) when subtrac ng a
single-bit binary value (B)
from another single-bit
value (A), i.e., A - B. Half Subtractor using NAND gates
Boolean Func ons: D =X ⊕ Y B = XY
Full Subtractor: A full subtractor is a more comprehensive circuit that calculates
the difference (D) and the borrow-out (Br) when subtrac ng two single-bit
binary values (B and Cin) from a single-bit value (A).
Boolean func ons: D = (X ⊕ Y) ⊕ Bin B = XY + X (Bin) + Y (Bin)
Full Subtractor using basic gates

Truth Table
Half Subtractor
INPUT Using XOR and basic gates Using NAND gate only
X Y D B D B
0 0
0 1
1 0
1 1
K-map: Difference Borrow

X Y Y’ (0) Y (1) X Y Y’ (0) Y (1)
X’ (0) 0
X (1) 1
Difference: Borrow:
Full Subtractor
INPUT Using XOR and basic gates Using NAND gate only
X Y Bin D B D B
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
K-map: Difference Borrow

YBin Y’Bin’ Y’Bin YBin YBin’ YBin Y’Bin’ Y’Bin YBin YBin’
X (00) (01) (11) (10) X (00) (01) (11) (10)
X’ (0) X’ (0)
X (1) X (1)
Difference: Borrow:

Half Subtractor Testbench a_in <= '1';
use IEEE.std_logic_1164.all; wait for 1 ns;
assert(q_out='0');
en ty testbench is assert(d_out='1')
-- empty report "Fail 1/X" severity error;
end testbench;
a_in <= '1';
architecture tb of testbench is b_in <= '1';
wait for 1 ns;
-- DUT component assert(q_out='0');
component half_substractor is assert(d_out='0')
port( report "Fail 1/1" severity error;
a, b: in std_logic;
q, d: out std_logic); -- Clear inputs
b_in <= '0';
signal a_in, b_in, q_out, d_out:
std_logic; assert false report "Test done."
severity note;
begin wait;
end process;
-- Connect DUT
end tb;
DUT: half_substractor port
map(a_in, b_in, q_out, d_out);
Dataflow Model
library IEEE;
begin en ty half_substractor is
a_in <= '0'; port( a, b: in std_logic;
b_in <= '0'; q,d : out STD_LOGIC);
wait for 1 ns; end half_substractor;
assert(q_out='0'); architecture dataflow of
assert(d_out='0') half_subtractor is
begin
report "Fail 0/0" severity error; q <= a xor b;
d<= (not a) and b;
a_in <= '1'; end dataflow;
b_in <= '1';
wait for 1 ns;
assert(q_out='1');
assert(d_out='1')
report "Fail 0/1" severity error;

Behavioral Model
library IEEE; architecture behavioural of
use IEEE.std_logic_1164.all; notgate is
begin
en ty half_substractor is b <= not a;
Port ( a,b : in STD_LOGIC; end behavioural;
q,d : out STD_LOGIC); entity andgate is
Port ( a,b : in std_logic;
end half_substractor; c : out std_logic);
architecture Behavioral of end andgate;
half_subtractor is architecture behavioural of
begin andgate is
process (a,b) begin
begin c <= a and b;
if (a='0')then end behavioural;
q <= b; entity xorgate is
d <= b; Port ( a,b : in std_logic;
else c : out std_logic);
q <= '0'; end xorgate;
d <= not b; architecture behavioral of
end if; xorgate is
end process; begin
end Behavioral; c <= a xor b;
end behavioural;
architecture Structural of
half_subtractor is
component notgate
port ( a : in std_logic;
b : out std_logic);
end component;
Structural Model component andgate
port ( a,b : in std_logic;
library IEEE; c : out std_logic);
use IEEE.std_logic_1164.all; end component;
component xorgate
en ty half_substractor is port ( a,b : in std_logic;
Port ( a,b : in STD_LOGIC; c : out std_logic);
q,d : out STD_LOGIC); end component;
end half_substractor; signal s : STD_LOGIC := '0';
begin
library IEEE; G1: notgate port map(x,s);
use IEEE.std_logic_1164.all; G2: andgate port map(s,y,b);
G3: xorgate port map(x,y,d);
use IEEE.STD_LOGIC_ARITH.ALL; end Structural;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity notgate is
Port ( a : in std_logic;
b : out std_logic);
end notgate;

Full Subtractor Testbench a_in <= '0';
use IEEE.std_logic_1164.all; borrowin_in<='1';
wait for 1 ns;
en ty testbench is assert(borrowout_out='1');
-- empty assert(difference_out='1')
end testbench; report "Fail 0/0/1" severity error;
a_in <= '0';

architecture tb of testbench is
b_in <= '1';
borrowin_in<='0';
-- DUT component
wait for 1 ns;
component Fullsubtractor is
assert(borrowout_out='1');
port(
assert(difference_out='1')
a, b, borrowin: in std_logic;
difference, borrowout: out std_logic);
b_in <= '1';
signal a_in, b_in, borrowin_in, borrowin_in<='1';
difference_out, borrowout_out: wait for 1 ns;
std_logic; assert(borrowout_out='1');
assert(difference_out='0')
begin report "Fail 0/1/1" severity error;
-- Connect DUT a_in <= '1';

DUT: Fullsubtractor port map(a_in, b_in <= '0';
b_in, borrowin_in, difference_out, borrowin_in<='0';
borrowout_out); wait for 1 ns;
assert(borrowout_out='0');
process assert(difference_out='1')
begin report "Fail 1/0/0" severity error;
a_in <= '0';
b_in <= '0'; a_in <= '1';
borrowin_in<='0'; b_in <= '0';
wait for 1 ns; borrowin_in<='1';
assert(borrowout_out='0'); wait for 1 ns;
assert(difference_out='0') assert(borrowout_out='0');
report "Fail 0/0/0" severity error; assert(difference_out='0')

a_in <= '1';
b_in <= '1'; architecture dataflow of
Fullsubtractor is
borrowin_in<='0'; begin
wait for 1 ns; difference<= a xor b xor borrowin;
assert(borrowout_out='0'); borrowout<= ((not a) and (b or borrowin))
assert(difference_out='0') or (b and borrowin);
end dataflow;
a_in <= '1';

b_in <= '1';
borrowin_in<='1';
wait for 1 ns; Behavioral Model
assert(borrowout_out='1'); library ieee;
assert(difference_out='0') use ieee.std_logic_1164.all;
report "Fail 1/1/1" severity error; en ty Fullsubtractor is
port (a, b, borrowin: in std_logic;
-- Clear inputs difference, borrowout: out std_logic);
a_in <= '0'; end Fullsubtractor;
b_in <= '0'; architecture Behavioral of
borrowin_in <= '0'; Fullsubtractor is
begin
difference <= a xor b xor borrowin;
assert false report "Test done." borrowout <= (((not a) and b) or
severity note; (b and borrowin) or (borrowin and (not a)));
wait; end Behavioral;
end process;
end tb;
Dataflow Model
library ieee;
en ty Fullsubtractor is
end Fullsubtractor;

Structural Model
library ieee;
en ty Fullsubtractor is
end Fullsubtractor;
architecture structural of Fullsubtractor is
signal c1, c2, c3, s1: in std_logic;
component xor_2 is
port (k,d,e: in std_logic; f: out std_logic);
end component;
component and_1 is
Port ( x,y : in STD_LOGIC; z : out STD_LOGIC);
end component;
component or_1 is
Port ( g,h,i : in STD_LOGIC; z : out STD_LOGIC);
end component;
component not_1 is
port (u: in std_logic; v: out std_logic);
end component;
begin
X0: xor_2 port map (a,b,c, diff);
X2: and_1 port map (s1,b,c1);
X3: and_1 port map (c,b,c2);
X4: and_1 port map (s1,c,c3);
x5: or_1 port map (c1, c2, c3, borrow);
end structural;

EXPERIMENT 4: MULTIPLEXER
NAME OF THE STUDENT
ROLL NO.
DATE OF EXPERIMENT
DATE OF SUBMISSION
GRADE/MARKS

DESIGN & IMPLEMENTATION OF 4 X 1

MULTIPLEXER USING VHDL
Theory:
Mul plexing is the generic term used to describe the opera on of sending one
or more analogue or digital signals over a common transmission line at
different mes or speeds and the device used to do that is called Mul plexer.
The mul plexer, shortened to “MUX” or “MPX”, is a combina onal logic circuit
designed to switch one of several input lines through to a single common
output line by the applica on of a control signal. Mul plexers operate like very
fast ac ng mul ple posi on rotary switches connec ng or controlling mul ple
input lines called “channels” one at a me to the output. Mul plexers, or
MUX’s, can be either digital circuits made from high-speed logic gates used to
switch digital or binary data or they can be analogue types using transistors,
MOSFET’s or relays to switch one of the voltage or current inputs through to a
single output.
Basic
Mul plexing
Switch
The rotary switch, also called a wafer switch as each layer of the switch is
known as a wafer, is a mechanical device whose input is selected by rota ng a
sha . In other words, the rotary switch is a manual switch that you can use to
select individual data or signal lines simply by turning its inputs “ON” or “OFF”.
So how can we select each data input automa cally using a digital device.
In digital electronics, mul plexers are also known as data selectors because
they can “select” each input line, are constructed from individual Analogue
Switches encased in a single IC package as opposed to the “mechanical” type
selectors such as normal conven onal switches and relays.
They are used as one method of
reducing the number of logic
gates required in a circuit
design or when a single data
line or data bus is required to
carry two or more different
digital signals. For example, a
single 8-channel mul plexer.

Generally, the selec on of each input line in a mul plexer is controlled by an
addi onal set of inputs called control lines and according to the binary
condi on of these control inputs, either “HIGH” or “LOW” the appropriate
data input is connected directly to the output. Normally, a mul plexer has an
even number of 2 n data input lines and a number of “control” inputs that
correspond with the number of data inputs.
Block Diagram Observations
SELECT LINES
OUTPUT
S1 S0
0 0
0 1
1 0
1 1
Multiplexer Testbench DUT: mul plexer port map (i0_in, i1_in

library IEEE; i2_in, i3_in, s0_in, s1_in, output_out);
process
en ty testbench is begin
-- empty i0_in <= '0';
end testbench; i1_in <= 'X';
i2_in <= 'X';
architecture tb of testbench is i3_in <= 'X';
s0_in <= '0';
-- DUT component s1_in <= '0';
component mul plexer is wait for 1 ns;
port( assert(output_out='0') report "Fail
i0, i1, i2, i3, s0, s1 : in std_logic; 0/X/X/X/0/0" severity error;
output: out std_logic); i0_in <= '1';
end component; i1_in <= 'X';
i2_in <= 'X';
signal i0_in, i1_in, i2_in, i3_in, s0_in, i3_in <= 'X';
s1_in, output_out: std_logic; s0_in <= '0';
s1_in <= '0';
begin wait for 1 ns;
assert(output_out='1') report "Fail
-- Connect DUT 1/X/X/X/0/0" severity error;

i0_in <= 'X'; i0_in <= 'X';

i1_in <= '0'; i1_in <= 'X';
i2_in <= 'X'; i2_in <= 'X';
i3_in <= 'X'; i3_in <= '0';
s0_in <= '1'; s0_in <= '1';
s1_in <= '0'; s1_in <= '1';
assert(output_out='0') report "Fail assert(output_out='0') report "Fail
X/0/X/X/1/0" severity error; X/X/X/0/1/1" severity error;
i0_in <= 'X'; i0_in <= 'X';

i1_in <= '1'; i1_in <= 'X';
i2_in <= 'X'; i2_in <= 'X';
i3_in <= 'X'; i3_in <= '1';
s0_in <= '1'; s0_in <= '1';
s1_in <= '0'; s1_in <= '1';
assert(output_out='1') report "Fail assert(output_out='1') report "Fail
X/1/X/X/1/0" severity error; X/X/X/0/1/1" severity error;
i0_in <= 'X';

i1_in <= 'X'; -- Clear inputs
i2_in <= '0'; i0_in <= '0';
i3_in <= 'X'; i1_in <= '0';
s0_in <= '0'; i2_in <= '0';
s1_in <= '1'; i3_in <= '0';
wait for 1 ns; s0_in <= '0';
assert(output_out='0') report "Fail s1_in <= '0';
X/X/0/X/0/1" severity error;
assert false report "Test done."
i0_in <= 'X'; severity note;
i1_in <= 'X'; wait;
i2_in <= '1'; end process;
i3_in <= 'X'; end tb;
s0_in <= '0';
s1_in <= '1';
wait for 1 ns;
assert(output_out='1') report "Fail
X/X/1/X/0/1" severity error;

Dataflow Model Behavioral Model
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
en ty mul plexer is en ty mul plexer is
port( port(
i0, i1, i2, i3, s0, s1 : IN std_logic; i0, i1, i2, i3, s0, s1 : IN std_logic;
output : OUT std_logic); output : OUT std_logic);
end mul plexer; end mul plexer;
architecture dataflow of multiplexer is architecture behavior of multiplexer is
signal s0,s1,i0,i1,i2,i3: std_logic; begin
begin process (s0, s1, i0, i1, i2, i3)
s0<=not s0; begin
s1<=not s1; if (s = "00") then
i0<=A and s0 and s1; output<= i0;
i1<=B and s0 and sr1; elsif (s= "01") then
i2<=C and s0 and s1; output<= i1;
i3<=D and s0 and s1; elsif (s = "10") then
output<=i0 or i1 or i2 or i3; output<= i2;
end dataflow; else
output<= i3;
end if;
end process;
end behavior;

Structural Model
library IEEE;
en ty mul plexer is
port(
i0, i1, i2, i3, s0, s1 : IN std_logic;
output : OUT std_logic);
end mul plexer;
architecture structural of multiplexer is
component inv
port (pin : in std_logic;
pout :out std_logic);
end component;
component and3
port (a0,a1,a2: in std_logic;
aout:out std_logic);
end component;
component or4
port (r0,r1,r2,r3:in std_logic;
rout:out std_logic);
end component;
signal s0,s1,i0,i1,i2,i3: std_logic;
begin
INV0: inv port map (s0, s1);
INV1: inv port map (s0, s1);
A1: and3 port map (A, s0, s1, i0);
A2: and3 port map (B, s0, s1, i1);
A3: and3 port map (C, s0, s1, i1);
A4: and3 port map (D, s0, s1, i3);
O1: or4 port map (i0, i1, i2, i3, output);
end structural;

EXPERIMENT 5: ENCODER - DECODER
NAME OF THE STUDENT
ROLL NO.
DATE OF EXPERIMENT
DATE OF SUBMISSION
GRADE/MARKS

DESIGN & IMPLEMENTATION OF 4:2

ENCODER& 2:4DECODER USING VHDL
Encoder:
An encoder is a digital circuit that converts a set of binary inputs into a unique
binary code. The binary code represents the posi on of the input and is used
to iden fy the specific input that is ac ve. Encoders are commonly used in
digital systems to convert a parallel set of inputs into a serial code.
The basic principle of an encoder is to assign a unique binary code to each
possible input. For example, a 2-to-4 line encoder has 2 input lines and 4
output lines and assigns a unique 4-bit binary code to each of the 22 = 4
possible input combina ons.
There are different types of encoders, including priority encoders, which
assign a priority to each input, and binary-weighted encoders, which use a
binary weigh ng system to assign binary codes to inputs. Encoders are widely
used in digital systems to convert parallel inputs into serial codes.
An Encoder has a maximum of 2n input lines and ‘n’ output lines, hence it
encodes the informa on from 2n inputs into an n-bit code. It will produce a
binary code equivalent to the input, which is ac ve High. Therefore, the
encoder encodes 2n input lines with ‘n’ bits.
Truth Table
INPUT OUTPUT
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
Logical expressions:
A 1=
A 0=

Encoder Testbench i <= (3=>'1', others=>'0');
use IEEE.std_logic_1164.all; assert(o1='1' and o0='1') report "Fail
1/0/0/0" severity error;
en ty testbench is
-- empty assert false report "Test done."
end testbench; severity note;
architecture tb of testbench is wait;
end process;
-- DUT component end tb;
component encoder is
port( Structural Model
i : in std_logic_vector(3 downto 0); library IEEE;
o1, o0 : out std_logic); use IEEE.STD_LOGIC_1164.all;
end component; en ty encoder is
port(
signal i : std_logic_vector(3 downto 0); i : in std_logic_vector(3 downto 0);
signal o1, o0 : std_logic; o1, o0 : out std_logic );
end encoder;
begin
architecture structural of encoder is
-- Connect DUT component and2 is
port (
DUT: encoder port map(i, o1, o0); a : in std_logic;
b : in std_logic;
process c : out std_logic
begin );
i <= (0=>'1', others=>'0'); end component and2;
signal temp : std_logic_vector(1 downto 0);
wait for 1 ns; begin
assert(o1='0' and o0='0') report "Fail u1 : and2 port map (input(3),
0/0/0/1" severity error; input(2), temp(0));
u2 : and2 port map (input(1),
input(0), temp(1));
i <= (1=>'1', others=>'0'); o <= temp;
wait for 1 ns; end architecture structural;
assert(o1='0' and o0='1') report "Fail
i <= (2=>'1', others=>'0');

wait for 1 ns;
assert(o1='1' and o0='0') report "Fail

Dataflow Model Behavioral Model
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.STD_LOGIC_1164.all;
en ty encoder is en ty encoder is
port( port(
i : in std_logic_vector(3 downto 0); i : in std_logic_vector(3 downto 0);
o1, o0 : out std_logic ); o1, o0 : out std_logic );
end encoder; end encoder;
architecture dataflow of encoder is architecture behavioral of encoder is
begin process(i)
o<= i(3) & i(2); begin
end dataflow; if i(3) = '1' then
o <= "00";
elsif i(2) = '1' then
o <= "01";
elsif i(1) = '1' then
o <= "10";
else
o <= "11";
end if;
end process;
end architecture behavioral;
Decoder
A binary decoder is a digital circuit that converts a binary code into a set of
outputs. The binary code represents the posi on of the desired output and is
used to select the specific output that is ac ve. Binary decoders are commonly
used in digital systems to convert a serial code into a parallel set of outputs.
The basic principle of a binary decoder is to assign a unique output to each
possible binary code. For example, a binary decoder with 2 inputs and 22 = 4
outputs can assign a unique output to each of the 4 possible 2-bit binary codes
In Digital Electronics, discrete quan es of informa on are represented by
binary codes. A binary code of n bits is capable of represen ng up to 2n dis nct
coded informa on. A decoder is a combina onal circuit that converts binary
informa on from n input lines to a maximum of 2n unique output lines.
If a binary decoder receives n inputs it ac vates only one of its 2n outputs
based on that input with all other outputs deac vated. If the n-bit coded
informa on has unused combina ons, the decoder may have fewer than 2n
outputs. Binary decoders generate the 2n (or fewer) minterms of n input
variables with each input combina on asser ng a unique output.

INPUT OUTPUT
EN S1 S0 O3 O2 O1 O0
0 X X
1 0 0
1 0 1
1 1 0
1 1 1
Decoder Testbench e <= '1';
library IEEE; s1 <= '0';
use IEEE.std_logic_1164.all; s0 <= '0';
wait for 1 ns;
en ty testbench is assert(o="0001") report "Fail 1/0/0"
-- empty severity error;
end testbench;
e <= '1';
architecture tb of testbench is s1 <= '0';
s0 <= '1';
-- DUT component wait for 1 ns;
component decoder is assert(o="0010") report "Fail 1/0/1"
port( severity error;
e, s1, s0 : in std_logic;
e <= '1';
o : out std_logic_vector(3 downto 0) );
s1 <= '1';
end component;
s0 <= '0';
wait for 1 ns;
signal e, s1, s0 : std_logic;
assert(o="0100") report "Fail 1/1/0"
signal o : std_logic_vector(3 downto 0);
severity error;
begin e <= '1';
-- Connect DUT s1 <= '1';
DUT: decoder port map(e, s1, s0, o); s0 <= '1';
wait for 1 ns;
process assert(o="1000") report "Fail 1/1/1"
begin severity error;
e <= '0';
s1 <= 'X'; assert false report "Test done."
s0 <= 'X'; severity note;
wait for 1 ns; wait;
assert(o="0000") report "Fail 0/X/X" end process;
severity error; end tb;

Dataflow Model Structural Model
library IEEE; library ieee;
use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_1164.all;
en ty decoder is en ty decoder is
port( e, s0, s1: in std_logic; port( e, s1, s0 : in std_logic;
o : out std_logic_vector(3 downto 0) ); o : out std_logic_vector(3 downto 0) );
end decoder; end decoder;
architecture dataflow of decoder is architecture structural of decoder is
begin component and2 is
o(0) <= ((not s0)and(not s1)); port (
o(1)<= ((not s0) and s1); s1, s0 : in std_logic;
o(2) <= (s0 and (not s1)); o : out std_logic
o(3) <= (s0 and s1); );
end dataflow; end component and2;
signal not_s1, not_s0 : std_logic;
begin
not_s0 <= not s0;
not_s1 <= not s1;
u1: and2 port map (s0, not_s1, o(0));
u2: and2 port map (not_s0, s1, o(1));
u3: and2 port map (s0, s1, o(2));
Behavioral Model u4: and2 port map (not_s0, not_s1, o(3));
end architecture structural;
library ieee;
en ty decoder is
port( e, s0, s1: in std_logic;
o : out std_logic_vector(3 downto 0) );
end decoder;
architecture bhv of decoder is
begin
o(0) <= not s0 and not s1;
o(1) <= not s0 and s1;
o(2) <= s0 and not s1;
o(3) <= s0 and s1;
end bhv;

EXPERIMENT 6: RIPPLE CARRY ADDER
NAME OF THE STUDENT
ROLL NO.
DATE OF EXPERIMENT
DATE OF SUBMISSION
GRADE/MARKS

DESIGN & IMPLEMENTATION OF

4-BIT RIPPLE CARRY ADDER
Theory:
Ripple Carry Adders offer a straigh orward approach to binary addi on using
cascaded full adders to gives the results of the addi on of two n bit binary
sequence. This adder includes cascaded full adders in its structure so, the carry
will be generated at every full adder stage in a ripple-carry adder circuit. These
carry output at each full adder stage is forwarded to its next full adder and
there applied as a carry input to it. This process con nues up to its last full
adder stage. So, each carry output bit is rippled to the next stage of a full adder.
By this reason, it is named as “Ripple Carry Adder”.
Ripple Carry Adders serve as essen al components in digital computers for
performing binary addi on. By employing basic logic gates like AND, OR, and
XOR, these adders enable the addi on of mul -bit binary numbers.
In a Ripple Carry Adder, each full adder waits for the carry bit from the previous
full adder, thus propaga ng the carry bit through the chain. While they
facilitate rapid design due to their simple layout, their performance is limited
by carry propaga on delays, resul ng in rela vely slower opera on compared
to alterna ve adder designs.
The expressions for sum and carry for each stage is same as that of a full adder:
Sumi = Ai ⊕ Bi ⊕ Ci-1 Carryi = AiBi + ACi-1 + BCi-1
Truth Table (Full Adder)
INPUT OUTPUT
Ai Bi Ci-1 Sumi Carryi
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

Testbench
library ieee;
en ty testbench is
-- empty
end testbench;
component Ripple_Adder
port(A, B : in std_logic_vector(3 downto 0);
Cin : in std_logic;
S : out std_logic_vector(3 downto 0);
Cout : out std_logic);
end component;
signal A, B, S : std_logic_vector(3 downto 0);

signal Cin, Cout : std_logic;
begin
dut: Ripple_Adder port map ( A, B, Cin, S, Cout);
process
begin
A <= "1000"; B <= "0001"; Cin <= '0'; wait for 10 ns;
assert (S="1001" and Cout='0') report "Fail 1000/0001/0" severity error;
A <= "0100"; B <= "0010"; Cin <= '1'; wait for 10 ns;
A <= "0010"; B <= "0100"; Cin <= '0'; wait for 10 ns;
A <= "0001"; B <= "1000"; Cin <= '1'; wait for 10 ns;
A <= "0000"; B <= "0000"; Cin <= '0'; wait for 10 ns;
A <= "1111"; B <= "1111"; Cin <= '1'; wait for 10 ns;
A <= "0110"; B <= "0110"; Cin <= '0'; wait for 10 ns;
assert false report "Test done." severity note;

wait;
end process;
end;

Structural Model
library ieee;
en ty Ripple_Adder is
port ( A, B : in std_logic_vector (3 downto 0);
Cin : in std_logic;
S : out std_logic_vector (3 downto 0);
end Ripple_Adder;
architecture structural of Ripple_Adder is
component full_adder is
port (
a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic
);
end component;
signal carry : std_logic_vector (3 downto 0);
begin
u0 : full_adder port map (a(0), b(0), '0', sum(0), carry(0));
u1 : full_adder port map (a(1), b(1), carry(0), sum(1), carry(1));
u2 : full_adder port map (a(2), b(2), carry(1), sum(2), carry(2));
u3 : full_adder port map (a(3), b(3), carry(2), sum(3), carry_out);
end architecture structural;
Please provide the waveforms generated by your code

EXPERIMENT 7: CARRY LOOKAHEAD ADDER
NAME OF THE STUDENT
ROLL NO.
DATE OF EXPERIMENT
DATE OF SUBMISSION
GRADE/MARKS


4-BIT CARRY LOOKAHEAD ADDER
Theory:
In ripple carry adders, each adder block waits for the carry to arrive from its
previous block. The ith block waits for the i-1th block to produce its carry. This
causes carry propaga on delay, which increases as the number of bits increase
Consider a 4-bit ripple carry adder. Even a er inputs A3 and B3 are given, the
4th full adder cannot produce steady state outputs un l C3 is available at its
final steady-state value. Similarly C3 depends on C2 and C2 on C1. Therefore,
though the carry must propagate to all the stages in order that outputs S3 and
C4 se le at their final steady-state value.
The propaga on me is equal to the propaga on delay of each adder block,
mul plied by the number of adder blocks in the circuit. For example, if each
full adder stage has a propaga on delay of 20 nanoseconds, then S3 will reach
its final correct value a er 60 (20 × 3) nanoseconds. The situa on gets worse,
if we extend the number of stages for adding more number of bits.
Carry Lookahead Adders func on by compu ng the carry signals in constant

me. In this approach, two signals, known as Carry Propagator (P) and Carry
Generator (G), are calculated for each stage of the adder.
The Carry Propagator signal indicates whether a carry will be propagated to
the next stage from if the previous stage passed a carry signal. The Carry
Generator signal indicates whether a carry will be generated at the current
stage, regardless of input carry.
Pi = Ai ⊕ Bi Gi = A i · Bi
Using the expressions for P and G, the sum & carry outputs for each stage are
Sumi = Pi ⊕ Ci Carryi+1 = Gi + (Pi·Ci)
By subs tu ng the previous carry value (Ci) into the expression for Ci+1, we get:
C1 = G0 + P0·C0
C2 = G1 + P1·C1 = G1 + P1·G0 + P1·P0·C0
C3 = G2 + P2·C2 = G2 + P2·G1 + P2·P1·G0 + P2·P1·P0·C0
C4 = G3 + P3·C3 = G3 + P3·G2·P2·G1 + P3·P2·P1·G0 + P3·P2·P1·P0·C0

INPUT OUTPUT
Ai Bi Ci Gi Pi Ci+1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Carry generator and

Carry propagator generation
Carry calculation
Sum calculation
CLA can generate the en re output in 4 gate delays. 1 gate delay for genera ng
the carry propagators and carry generators; 2 gate delays for the compu ng
the carry bit and 1 addi onal gate delay for compu ng the sum bit

Testbench
library ieee;
en ty testbench is
-- empty
end testbench;
component CLA
port(A, B : in std_logic_vector(3 downto 0);
Cin : in std_logic;
end component;
signal A, B, S : std_logic_vector(3 downto 0);

signal Cin, Cout : std_logic;
begin
DUT: CLA port map ( A, B, Cin, S, Cout);
process
begin
A <= "1000"; B <= "0001"; Cin <= '0'; wait for 10 ns;
A <= "0100"; B <= "0010"; Cin <= '1'; wait for 10 ns;
A <= "0010"; B <= "0100"; Cin <= '0'; wait for 10 ns;
A <= "0001"; B <= "1000"; Cin <= '1'; wait for 10 ns;
A <= "0000"; B <= "0000"; Cin <= '0'; wait for 10 ns;
A <= "1111"; B <= "1111"; Cin <= '1'; wait for 10 ns;
A <= "0110"; B <= "0110"; Cin <= '0'; wait for 10 ns;

wait;
end process;
end;

DataFlow Model
library ieee;
en ty CLA is
port (A, B : in std_logic_vector(3 downto 0);
Cin : in std_logic;
end CLA;
architecture dataflow of CLA is
signal p,g,c : STD_LOGIC_VECTOR(3 downto 0);
begin
p <= a xor b;
g <= a and b;
c(0) <= cin;
c(1) <= g(0) or (p(0) and cin);
c(2) <= g(1) or(p(1) and g(0)) or (p(1) and p(0) and cin);
c(3) <= g(2) or (p(2) and g(1)) or (p(2) and p(1) and
g(0)) or (p(2) and p(1) and p(0) andcin);
cout <= g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1))
or (p(3) and p(2) and p(1) and g(0)) or
(p(3) and p(2) and p(1) and p(0) and cin);
sum <= p xor c;
end dataflow;

Structural Model
library ieee;
en ty CLA is
port ( A, B : in std_logic_vector (3 downto 0);
Cin : in std_logic;
S : out std_logic_vector (3 downto 0);
end CLA;
architecture Behavioral of Carry_Look_Ahead is
component Partial_Full_Adder
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
P : out STD_LOGIC;
G : out STD_LOGIC);
end component;
signal c1,c2,c3: STD_LOGIC;
signal P,G: STD_LOGIC_VECTOR(3 downto 0);
begin
PFA1: Partial_Full_Adder port map( A(0), B(0), Cin, S(0), P(0), G(0));
PFA2: Partial_Full_Adder port map( A(1), B(1), c1, S(1), P(1), G(1));
c1 <= G(0) OR (P(0) AND Cin);
c2 <= G(1) OR (P(1) AND G(0)) OR (P(1) AND P(0) AND Cin);
c3 <= G(2) OR (P(2) AND G(1)) OR (P(2) AND P(1)
AND G(0)) OR (P(2) AND P(1) AND P(0) AND Cin);
Cout <= G(3) OR (P(3) AND G(2)) OR
(P(3) AND P(2) AND G(1)) OR (P(3) AND P(2) AND P(1) AND G(0))
OR (P(3) AND P(2) AND P(1) AND P(0) AND Cin);
end Behavioral;
Please provide the waveforms generated by your code

EXPERIMENT 8: SR, JK & D FLIPFLOPS
NAME OF THE STUDENT
ROLL NO.
DATE OF EXPERIMENT
DATE OF SUBMISSION
GRADE/MARKS


SR, JK & D FLIPFLOPS USING VHDL
Sequen al circuits are digital circuits that store and use the previous state
informa on to determine their next state. Unlike combina onal circuits, which
only depend on the current input values to produce outputs, sequen al
circuits depend on both the current inputs and the previous state stored in
memory elements.
SR flip-flop : The SR flip-flop is one of the fundamental parts of the
sequen al circuit logic. SR flip-flop is a memory device and binary data of 1 bit
can be stored in it. SR flip-flop has two stable states in which it can store data
in the form of either binary zero or binary one. Like all flip-flops, an SR flip-flop
is also an edge sensi ve device. SR
flip–flop is one of the most vital
components in digital logic and it is
also the most basic sequen al
circuit that is possible. The S (SET)
input, sets the output to 1 and the
R(RESET) input resets it to 0.
JK flip-flop : JK flip-flop is a
refinement of SR flip-flop where the
indeterminate state of SR type is
defined. Input J and K are respec vely
the set and reset inputs of the flip-flop.
When both the inputs are high then
the output of the flip-flop switches to
its complemented state.
D flip-flop : To ensure that both
S and R inputs don’t become the
same, we can use the Delay/Data
flipflop. Here there is a single
‘Data’ input which is connected to
the Set pin, while its complement
goes to the Reset pin.

Present Next Present Next
Set Reset J K
State State State State
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1
SR Flip Flop Testbench INPUT (D) 0 1

library ieee; OUTPUT (Q)
en ty testbench is
-- empty
end testbench;
component SRFF
port(S, R : in std_logic;
Q, Qnot : out std_logic);
end component;
signal S, R, Q, Qnot : std_logic;
begin
DUT: SRFF port map (S, R, Q, Qnot);
process
begin
S <= '1'; R <='0'; wait for 10 ns;
assert (Q='1' and Qnot='0') report "Fail 1/0" severity error;
S <= '0'; R <='1'; wait for 10 ns;
S <= '0'; R <='0'; wait for 10 ns;
wait;
end process;
end;

SR FlipFlop DataFlow Model SR FlipFlop Structural Model
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
en ty SRFF is en ty SRFF is
port(S, R : in std_logic; port(S, R : in std_logic;
Q, Qnot : out std_logic); Q, Qnot : out std_logic);
end SRFF; end SRFF;
architecture srff of SRFF is
signal S,R:STD_LOGIC; architecture srff of SRFF is
begin component nand21
S<= s nand clk; port(a,b: in STD_LOGIC;
R <= r nand clk; y:out STD_LOGIC);
Q <= S nand Qnot; end component;
Qnot <= R nand Q; signal s1,r1:STD_LOGIC;
end srff; begin
0 n1: nand21 port map(S,clk,s1);
n2: nand21 port map(R,clk,r1);
n3: nand21 port map(s1,Qnot,Q);
n4: nand21 port map(r1,Q,Qnot);
end srff;
SR FlipFlop Behavioural Model
library ieee;
en ty SRFF is
port(S, R : in std_logic;
end SRFF;
architecture Behavioral of SRFF is
process (S,R,RST,CLK)
begin
if (RST = '1') then
Q <= '0';
elsif (RISING_EDGE(CLK))then
if (S /= R) then
Q <= S; Qnot <= R;
elsif (S = '1' AND R = '1') then
Q <= 'Z'; Qnot <= 'Z';
end if;
end if;
end process;
end Behavioral;

JK FlipFlop TestBench JK FlipFlop Behavioural Model
library ieee;
library ieee;
use ieee.std_logic_1164.all; en ty JKFF is
port(J, K : in std_logic;
en ty testbench is Q, Qnot : out std_logic);
-- empty end JKFF;
end testbench; architecture behavioral of JKFF is
begin
process(clock)
architecture tb of testbench is variable TMP: std_logic;
begin
if(clock='1' and clock'event) then
component JKFF if(J='0' and K='0')then
TMP:=TMP;
port(J, K : in std_logic; elsif(J='1' and K='1')then
Q, Qnot : out std_logic); TMP:= not TMP;
elsif(J='0' and K='1')then
end component; TMP:='0';
else
TMP:='1';
signal J, K, Q, Qnot : std_logic; end if;
end if;
Q<=TMP;
begin Q <=not TMP;
DUT: JKFF port map (J, K, Q, Qnot); end process;
end behavioral;
process
begin
J <= '1'; K <='0'; wait for 10 ns;

J <= '0'; K <='1'; wait for 10 ns;
J <= '1'; K <='1'; wait for 10 ns;
J <= '0'; K <='0'; wait for 10 ns;

wait;
end process;
end;

D FlipFlop TestBench D FlipFlop Dataflow Model
library ieee; library IEEE;
use ieee.std_logic_1164.all; use IEEE.std_logic_1164.all;
en ty testbench is en ty DFF is
-- empty port(D : in std_logic;
end testbench; Q, Qnot : out std_logic);
end DFF;
architecture tb of testbench is architecture dataflow of DFF is
begin
component DFF Q <= D when clk'event and clk = '1';
port(D : in std_logic; end dataflow;
end component;
signal D, Q, Qnot : std_logic;
begin
DUT: DFF port map (D, Q, Qnot);
process
begin
D <= '0'; wait for 10 ns;
assert (Q='0' and Qnot='1')
report "Fail 0" severity error;
D <= '1'; wait for 10 ns;
assert (Q='1' and Qnot='0')
report "Fail 1" severity error;
assert false report "Test done."

severity note;
wait;
end process;
end;

D FlipFlop Behavioural Model D FlipFlop Structural Model
library ieee; library IEEE;
use ieee.std_logic_1164.all; use IEEE.std_logic_1164.all;
en ty DFF is en ty DFF is
port(D : in std_logic; port(D : in std_logic;
Q, Qnot : out std_logic); Q, Qnot : out std_logic);
end DFF; end DFF;
architecture behavioral of DFF is architecture structural of DFF is
begin component D_latch is
process(CLOCK) port (
begin clk : in std_logic;
if(CLOCK='1' and CLOCK'EVENT) then d : in std_logic;
Q <= D; q : out std_logic
end if; );
end process; end component;
end behavioral; signal d_latch_q : std_logic;
begin
d_latch_inst : D_latch port map (
clk => clk,
d => d,
q => d_latch_q
);
q <= d_latch_q;
end structural;
Please provide the waveforms generated by your code and specify whether they verify truth table

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Computer

Department of CSE (AIML/CSBS)

Compiled by: Snehal Ghosh, Abhiroop Sarkar,

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

Individual and Function effectively as an individual, and as a member or

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

Program Educational Objectives (PEO)

PEO 02: Real Life Problem Solving:

PEO 03: Leadership:

PEO 04: Lifelong Learning:

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

DEPARTMENT OF CSE (AIML/CSBS)

NAME OF THE STUDENT

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

IMPLEMENTATION OF AND, OR, NOT,

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

a_in <= '0';

a_in <= '1';

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

a_in <= '0';

a_in <= '1';

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

a_in <= '0';

a_in <= '1';

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

a_in <= '0';

a_in <= '1';

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

a_in <= '0';

a_in <= '1';

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

en ty testbench is assert false report "Test done."

signal a_in, q_out: std_logic; design.vhd

a_in <= '1';

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

DEPARTMENT OF CSE (AIML/CSBS)

NAME OF THE STUDENT

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

DESIGN & IMPLEMENTATION OF HALF/

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

K-map: Sum Carry

K-map: Sum Carry

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

en ty testbench is a_in <= '0';

begin a_in <= '1';

a_in <= '0'; a_in <= '1';

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

a_in <= '1';

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

DEPARTMENT OF CSE (AIML/CSBS)

NAME OF THE STUDENT

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

DESIGN & IMPLEMENTATION OF HALF/

Full Subtractor using basic gates

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

K-map: Difference Borrow

K-map: Difference Borrow

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

DEPARTMENT OF CSE (AIML/CSBS), IEM SALTLAKE Semester IV

a_in <= '0';