MS-5 introduction

Jason Lee (8039)

Mail to: jasonlee@msi.com.tw
 Content
• Power delivery map
• MS-5 Block Diagram
• MS-5 Circuit
• System Power Sequence
• 5VDL/5VSB
• 3VSB&DDR2.5 Circuit
• DDR_VTT Circuit
• VCC_AGP Circuit
• VCC_VID Circuit
Intel 845 chipset platform power delivery map
ATX 12V POWER Supply

3.3V 5V 5VSB 12V

1A

VRM Processor Core

Processor Vtt
VID REG Processor VID

1.5V VREG MCH Core 1.5V

MCH Vtt
MCH AGP
MCH HUB Interface 1.5V
2.5V VREG MCH DDR Memory 2.5V

DDR System Memory 2.5V

1.25V VREG DDR Vtt 1.25V

ICH4 Core 1.5V

ICH4 Vtt
ICH4 Hub Interface 1.5V
ICH4 I/O 3.3V
1.5V SB ICH4 Resume 1.5V
3V_Dual ICH4 Resume I/O 3.3V
ICH4 RTC 3.3V
ICH4 5V
ICH4 5V Standby

FWH 3.3V

LPC Super I/O 3.3V

CK-408 3.3V
MS-5 Block Diagram
 MS-5 Circuit SEL0
H
5VUSB
2 MOSFET
**S5O# pin function(Hi level = 5V)
same as 5VUSB(Hi level = 12V)
Power S0 S3 S5 VCC5_SB VCC3
VCC3_SB Main Standby Standby VCC5_SB L 1 MOSFET 5VUSB USE 2 MOSFET
VCC5_STR Main Standby 0V
MEM_STR Main Standby 0V VCC5_SB

VCC3_SB R33
R34 R37 R36 R38 10K
SLP_S3# {10,11}
X_0 330 330 4.7K
R35 CT1 CB4

D
R1 1K 1000u-10V 475P/0805
4.7K G Q8
NDS351S
{10} SLP_S4#

S
C
C23
{6,10} PWR_GD VCC5_STR
R7 B Q2 R421 X_0 222P
{11,20} PS_ON# {10,20} RSMRST#
10K 2N3904S
{11}
PWR_OK1 5V DUAL Power
{22} VRM_GD

E
C13
{20} PWR_OK

+
X_104P
{20} PWR_LED
CT3
{20} SUS_LED
R278 X_0 470u_10V
{10,20} FP_RST#
Q7
45N02_T0252

Low RDS ON MOSFET

+
C30 CT9
X_102P 470u_10V

48
47
46
45
44
43
42
41
40
39
38
37
U1 VCC5

EXTRA_PWGD/GPIOC

S5O#/GPIOB/SEL0
CHIP_PWGD/GPIOC
CPU_PWGD/GPIOC
RSM_RST#/GPIOB
PWR_OK1/GPIOC
FP_RST#/GPIOB
**INPUT 2 AND 3 MUST BE HI LEVEL WHEN USE

SLP_S3#
SLP_S5#
PWR_OK
PLED1
PLED0
OUTPUT 1 AND 2 FOR GPIO FUNCTION
Near
R31 330 302D
VCC5
R21 180
R20 180
VCC3 VCC_AGP
1 36
2 DGND 5V_USB 35
{9,13} PCIRST# PCIRST#/GPIOA 5VSB_DRV
3 34
{3} HD_RST# HDD_RST#/GPIOA 5V_DRV
4 33
{17} PCIRST#2 SLOT_RST#/GPIOA TYPEDET#
5 32
{6} PCIRST#1 DEV_RST#/GPIOA VAGP_SEN
6 31
{3,11,14} SMBDATA_ISO I2C_DATA VAGP_DRV
7 30 Dual

1
{3,11,14} SMBCLK_ISO I2C_CLK AGND2 VREF1_25 +12V
8 29 D3 FootPrint
9 BT_DRV 1.25VREF 28 1N4148S 2
BT_SEN 9VSB 9VSB

VRAM_2.5_DEN
VRAM_2.5_DRV
10 27
DDR VTT Power R2 11 BT_SINK C2 26 C12 475P/0805
12 AGND0 C1 25 C11

VRAMDRV2

VRAMDRV1
VCC5_SB SEL1 VCC3 VCC3

VRAMSEN
VCC3

1.2V_DRV
105P/0805 Q24

1.2V_SEN
VRGOOD
10K NIKO-P3055LD-TO252

3
4
AGND1
C15 C5 CB123
D

5VSB
+

VCC
CT42 X_102P 104P 104P
VCC5_SB

SS
1000U/6.3V VCC2.5
D1
1.25V/2.1A G 1N5817S CB5

13
14
15
16
17
18
19
20
21
22
23
24
Q11 W83302E 104P
NIKO-P3055LD-TO252
D S

VTT_DDR VCC5 VCC3

VCC5_SB
+

C17 VCC_VID / VID_GOOD

G C7 C6 104P

D
104P 104P
Q14 G Q9
S

EC2 EC3 NIKO-P3055LD-TO252 2N7002AS

Place MOSFET near CPU
1000U/6.3V 1000U/6.3V C4

S
474P-X7R_0805
VCC_VID {5}
SEL1 VRAM VRAM_2.5 VCC3 CB6 1.2V/0.1A
X_104P C20
H 3.3VDUAL 2.5V 105P/0805
+

TRI-STATE 3.3VSB 2.5V CT4 Q1 R131 X_0

1000U/6.3V 45N02_T0252 VCC5
L 3.3VSTR 1.25V VID_GD {22}

THIS PIN IS OPEN DRAIN OUTPUT 1.0V

FOR 3VSB OR 3VSTR VCC3_SB
SETTING BY SEL1 VCC3_SB
Wide Trace
Q10 DDR 2.5V Power
3
4
NIKO-P3055LD-TO252 CB10
+

Dual 104P 2.5V/2.8A+5.92A

S

EC1 FootPrint
1000U/6.3V G 2
MEM_STR
Q3
D11 X_1N4001-S-SM-1
1

NIKO-P3055LD-TO252 VCC2.5
+
D

CT8
C28 CB107
+

1000U/6.3V 104P 104P

CT11
** SETTING 3VSTR THEN VRAM_2.5 470u_10V
BECOME TO 1.25 VREF VCC5_SB
SYSTEM Power Sequence(S1=L)
SYSTEM Power Sequence(S1=H or Tri-state)
5VDL/5VUSB Power Circuit
 5VDUAL Power Circuit
SEL0(Pin37) 5VUSB
**S5O# pin function(Hi level = 5V)
H 2 MOSFET same as 5VUSB(Hi level = 12V)
L 1 MOSFET 5VUSB USE 2 MOSFET
VCC5_SB

CT1 CB4

D
1000u-10V 475P/0805
5V_USB(Pin36) G Q8
NDS351S

S
C23
222P VCC5_STR

5V DUAL Power

+
CT3
470u_10V
Q7
45N02_T0252
5V_DRV(Pin34)
Low RDS ON MOSFET
+

C30 CT9
X_102P 470u_10V
VCC5
5VDUAL Power Sequence (STR)
5VDUAL Power Sequence (Dual)
5VDUAL Power Sequence (5Vcc)
 3VSB & DDR2.5V Circuit

VRAMDRV2(Pin14)

VRAMDRV1(Pin16)
SEL1 VRAM VRAM_2.5

VRAM_2.5_SEN(Pin19)

VRAM_2.5_DRV(Pin20)
VRAMSEN(Pin15)
H 3.3VDUAL 2.5V
TRI-STATE 3.3VSB 2.5V
L 3.3VSTR 1.25V

FOR 3VSB OR 3VSTR

SETTING BY SEL1
VCC3 CB6
X_104P
+

CT4 Q1
1000U/6.3V 45N02_T0252

VCC3_SB

VCC3_SB
Wide Trace
Q10 DDR 2.5V Power

3
4
NIKO-P3055LD-TO252 CB10
104P 2.5V/2.8A+5.92A
+

Dual
S

EC1 FootPrint2
1000U/6.3V G
MEM_STR
Q3
D11 X_1N4001-S-SM-1

1
NIKO-P3055LD-TO252 VCC2.5
CT8
+
D

** SETTING 3VSTR THEN VRAM_2.5 C28 CB107

+

BECOME TO 1.25 VREF 1000U/6.3V 104P 104P

CT11
470u_10V
VCC5_SB
3VSB Power sequence (S1=0, 3.3VSTR)
3VSB Power sequence (S1=1, 3.3VDUAL)
3VSB Power sequence (S1=Tri-state, 3.3VSB)
 DDR VTT Circuit

BT_DRV(Pin8)
BT_SEN(Pin9)
BT_SINK(Pin10)
DDR VTT Power
VCC3

C15

D
+
CT42 X_102P
1000U/6.3V

G
Q11
NIKO-P3055LD-TO252
D S
VTT_DDR
1.25V/2.1A
+

Q14
EC2 EC3 NIKO-P3055LD-TO252
S

1000U/6.3V 1000U/6.3V
VRAM_2.5 and DDR Termination VTT power sequence
VCC_AGP Circuit [TYPEDET#(Pin33)=0]

VCC_AGP

VAGP_SEN(Pin32)

Dual

1
FootPrint
VAGP_DRV(Pin31) 2

Q24
NIKO-P3055LD-TO252
3
4
CB123
104P
VCC2.5
VCC_AGP Power Sequence
 VCC_VID Circuit

VCC3

C17 VCC_VID / VID_GOOD

104P

D
1.2V_DRV(Pin24) G Q9
2N7002ASPlace MOSFET near CPU
1.2V_SEN(Pin23)
S

VCC_VID {5}
1.2V/0.1A
C20
105P/0805
VCC_VID Power Sequence
Q&A