Introduction to Computing

CENG380 Microprocessor and Microcontroller

Chapter 0

1
Outline
• Introduction
• Semiconductor Memory
• Bus Design
• CPU Architecture
• Microprocessor Architecture

2
Introduction

3
Microcontroller & Number Representation
•

4
Terminology

5
Terminology
1 binary digit
either 0 or 1

4 Bits

8 Bits

16 Bits or 2 Bytes

6
 Byte: B
Bit: b
Terminology
• 1 kilobyte (1KB) = 210 bytes = 210 B
• 1 megabyte (1MB) = 220 bytes = 220 B
• 1 gigabyte (1GB) = 230 bytes = 230 B
• 1 terabyte (1TB) = 240 bytes = 240 B

• Ex: 16 megabyte memory corresponds to 24 X 220 =224 bytes = 227

bits

7
Internal organization of computers
• Computers’ internal organization can be broken into 3 parts;
• Central Processing Unit (CPU): To execute and process information stored in
memory.
• Memory: Store information.(RAM, ROM …)
• Input/Output (I/O) devices: Provide means of communication with the CPU
(e.g. keyboard, monitor, mouse…).
• The CPU is connected to memory and I/O through strips of wire called
a bus.

8
Internal organization of computers

9
Semiconductor Memory

10
Memory types
• RAM: random access memory (read/write memory)
• Used for temporary data storage.
• Volatile memory, data is lost when the computer is turned off.
• ROM: Read Only Memory
• Contains programs(codes) and information essential to operation of the
computer.
• Information in ROM is permanent, it cannot be changed by the user
• Nonvolatile memory, data is not lost when power is turned off

11
 1 Pin = 1 bit
1 line = 1 bit
Memory organization
• A memory chip contains 2x locations, where x is
the number of address pins.
• Each location contains y bits, where y is the
number of data pins on chip.
• Each location can contain y = 1bit, 4 bits, 8 bits, or
16 bits.
• The entire chip will contain 2x x y bits.

12
Memory organization example (X=10, Y=4)

13
b

14
 Y=4b

X=12

b Y=8b=1B

X=16

64K =

15
Bus Designing and Address
Decoding

16
Bus designing

17
Bus designing
• The CPU needs to send/receive data to/from memory and I/O.
• The CPU is connected to memory and I/O through shared strips of
wire called the bus.
• There are 3 types of buses:
• Address bus
• Data bus
• Control bus

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Data bus
• Data buses are used to carry information in and out of a CPU, the
more data buses the better the CPU.
• Data buses are bidirectional because the CPU use them either to send
or receive data.
• Example: 8-bit bus can send out one byte at a time, but a 16-bit bus
can send out two bytes at time, which is twice as fast.(when data bus
size increase => computer speed increase)
• Data bus gives the naming of a computer, 64-bit PC vs 32-bit PC

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Address bus
•

20
Control bus
• CPU enables:
• MEMR to read from memory
• IOR to read from I/O
• MEMW to write on memory
• IOW to write on I/O
• Example: CPU wants to store 50 into address 15 of memory
• The CPU puts 15 on the address bus, and 50 on the data bus
• The CPU activates MEMW => Data on data bus is stored in the location
indicated by the address bus

21
Bus designing

15

50
MEMW

22
Control bus
• CPU enables:
• MEMR to read from memory
• IOR to read from I/O
• MEMW to write on memory
• IOW to write on I/O
• Example: CPU wants to store 50 into address 15 of memory
• The CPU puts 15 on the address bus, and 50 on the data bus
• The CPU activates MEMW => Data on data bus is stored in the location indicated by
the address bus
• Example: Get data from I/O device whose address is 40 ?
•
•

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Control bus
• CPU enables the following control bus signals:
• MEMR to read from memory
• IOR to read from I/O
• MEMW to write on memory
• IOW to write on I/O
• Example: CPU wants to store 50 into address 15 of memory
• The CPU puts 15 on the address bus, and 50 on the data bus.
• The CPU activates MEMW => Data on data bus is stored in the location indicated by
the address bus.
• Example: Get data from I/O device whose address is 40 ?
• The CPU puts 40 on the address bus.
• The CPU activates the IOR => I/O of address 40 puts data on data bus.

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Bus designing

40

IOR

25
CPU Architecture

26
Inside CPU

27
Inside CPU
• A program stored in memory provides instructions to the CPU to perform
an action
• The function of the CPU is to fetch instructions from memory and execute
them: Fetch and Execute
• CPU Resources:
• Registers of 8, 16, 32, or 64-bit to store information temporarily. The more
and bigger register the better, however the higher cost.
• Arithmetic/Logic Unit (ALU) is responsible for performing arithmetic
operation such as add, subtract, multiply, and divide, and logic functions
such as AND, OR, and NOT.

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Inside CPU (continue)
• CPU Resources:
• The program counter (PC) is incremented to point to the address of
the next instruction to be executed. The contents of the PC are
placed on the address bus to fetch the instruction. PC is also called
Instruction Pointer (IP) in IBM PC.
• Instruction decoder interprets the fetched instruction. It stores the
meaning of each instruction and the steps that should be taken by
the CPU upon receiving the instruction.

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Internal working of CPU
• Example: Assume that a CPU has 4
registers called A, B, C, and D. It has
8-bit data bus and 16-bit address
bus (it can access memory from
address 0000 to FFFFH)
• Assume that instruction opcode to
move a value to register A is B0H
and to add value to A is 04H.
• The following put the value 21H
into register A, and then add to
register A the values 42H and 12H.
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Internal working of CPU
• Example: Assume that a CPU has 4
registers called A, B, C, and D. It has
8-bit data bus and 16-bit address
bus (it can access memory from
address 0000 to FFFFH) Instruction Opcode Operand
Move value to A B0H X
• Assume that instruction to move a
Add value to A 04H X
value to register A is B0H and to
add value to A is 04H. Halt F4H -

• The following put the value 21H

into register A, and then add to
register A the values 42H and 12H.
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Internal working of CPU
Opcode Operand

If the program to perform the actions listed above is stored in memory locations
starting at 1400H we’ll have:

ROM

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 Internal working of CPU
1. PC=1400 is moved to bus address.
2. MEMR= 1
3. IR= B0 + decode => Move
4. Execute => we need data!!
5. Increment PC , PC = 1401
6. PC=1401 is moved to bus address.
7. MEMR= 1
8. IR= 21 + decode => 21 data to be loaded
9. Execute
10. Increment PC , PC = 1402
11. ……

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Internal working of CPU

1400H

MEMR

34
Internal working of CPU

1400H

B0

35
Internal working of CPU

1401H

Decode MEMR
B0

21

36
Internal working of CPU

1402H

04
MEMR

21

37
Internal working of CPU

1403H

04
Decode MEMR
42 04
21
63

38
Internal working of CPU

1404H

04
MEMR

63

39
Internal working of CPU

1405H

04
Decode MEMR
12 04
63
75

40
Microprocessor Architecture

41
Harvard and Von Neumann Architecture

42
Harvard and Von Neumann Architecture
• Von Neumann also called Princeton architecture provides the same
bus for accessing both the code and data.
• One has to wait for the other to finish fetching resulting in a slow
down in the processing speed of the CPU.
• Harvard architecture provides separate buses for the code and data
memory which speed up the process of program execution.

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