IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 11, NO.
11, NOVEMBER 2021 1971
Equivalent Circuit Synthesis of Multiport S
Parameters in Pole–Residue Form
Chiu-Chih Chou , Member, IEEE, and José E. Schutt-Ainé, Fellow, IEEE
Abstract— Equivalent circuit synthesis of an interconnect
macromodel is commonly used as an intermediate step before
conducting transient simulation of the channel. Depending on
the type, for example, S, Y , and Z parameters, and form, for
example, pole–residue, state-space, of the macromodel, various
circuit topologies have been proposed in the literature. In this
article, we focus on the synthesis of multiport S parameters in
the pole–residue form. A topology widely used in commercial
software is to convert the pole–residue model into a sparse
state-space model and then realize the state equations and output
equations using capacitors, resistors, and controlled sources.
Another topology, based on the generalized pi-model, has also
been proposed. In this article, we show that although these
conventional methods work well for the multi-input multi-output
(MIMO) case (all Si j share a common set of poles), they are
not optimal in terms of circuit complexity for the multi- single-
input-single-output (SISO) case (each Si j has its own distinct
poles). A new topology is proposed accordingly, which has smaller
complexity than the conventional ones. Transient simulation
on four different circuit solvers is performed to compare the
efficiencies of the various topologies. It is found that the proposed
topology can achieve more than 1.3 times speedup against the
conventional topologies (except the one with explicit pole/residue
specification) on most simulators, in terms of the normalized time
per step.
Index Terms— Circuit synthesis, equivalent circuit, macromod-
eling, scattering parameters, vector fitting (VF).
I. I NTRODUCTION
I N THE design of high-speed interconnects, the responses
of packaging and printed circuit board (PCB) channels are
often characterized by the S parameters sampled at a set of
discrete frequency points, which are obtained by either full-
wave electromagnetic simulation or vector network analyzer
(VNA) measurement. Such tabulated network responses are
then combined with the transmitter and receiver models to
perform a complete signal integrity analysis. Due to the
nonlinearity of the integrated circuits, time-domain simulation
is required. Conventional approaches to perform transient
simulation for sampled S parameters can be categorized into
two groups: convolution-based and macromodeling-based [1].
Manuscript received March 31, 2021; revised July 12, 2021; accepted
August 28, 2021. Date of publication September 23, 2021; date of current
version November 24, 2021. This work was supported in part by the Ministry
of Science and Technology of Taiwan under Grant 109-2917-I-564-018.
Recommended for publication by Associate Editor M. Nakhla upon evaluation
of reviewers’ comments. (Corresponding author: Chiu-Chih Chou.)
Chiu-Chih Chou is with the Department of Electrical Engineering, National
Central University, Taoyuan 320, Taiwan (e-mail: ccchou@ee.ncu.edu.tw).
José E. Schutt-Ainé is with the Department of Electrical and Com-
puter Engineering, University of Illinois at Urbana-Champaign, Champaign,
IL 61801 USA (e-mail: jesa@illinois.edu).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TCPMT.2021.3115113.
Digital Object Identifier 10.1109/TCPMT.2021.3115113
2156-3950 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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In the convolution-based methods, the impulse responses of the
network are computed via inverse Fourier transform, and being
convolved with the excitation signals at the ports to obtain the
corresponding output waveforms. This kind of methods is best
suited for channels where the impulse responses decay quickly,
since the computational overhead of convolution scales as
O(n 2 ), where n is the number of nonzero points in the
discretized impulse response. In the macromodeling-based
methods, the channel S parameters are first fit by a rational
function, which could be in polynomial-ratio form [2], pole–
residue form [3], state-space description [4], and so on. Such
rational representation is then imported into circuit simulators
in various ways, to be discussed immediately. The advantage
of macromodeling is that the rational representation enables
the network to be simulated via the highly efficient recursive
convolution [5]. Another favorable feature of macromodeling
is that, during or after the fitting process, there exist various
systematic algorithms to assess and enforce the stability,
causality, and passivity of the rational model [6], which are
important properties for a physically meaningful channel.
Among the various macromodeling methods, the vector fitting
(VF) [3] is known for its robustness and high efficiency [7],
and is one of the most prominent algorithms in rational
fitting [6]. The raw model delivered by VF is in pole–residue
form, while it can be converted to a diagonal state-space form
straightforwardly.
Once a macromodel is constructed, the best way to uti-
lize it should be directly using the rational representation
such as poles and residues for transient simulation. Indeed,
some circuit simulators do allow the user to specify rational
functions in the netlist [8], [9]. In general, however, not all
circuit simulators have this feature, and among those that
accept rational forms, the allowed format varies from tool to
tool. Instead of direct use of the rational fit, another common
approach is to synthesize equivalent circuits, composed of R,
L, C, and possibly linear controlled sources, which match the
rational function exactly. Since only standard components are
used, the resulting circuit is not tool-specific and can be run
by almost all simulators. Because of this wide applicability,
the circuit synthesis option is offered by many macromodeling
tools [10], [11].
There has been a variety of approaches for circuit synthesis
based on rational representation [12]–[22]. A detailed review
of some of these methods that are relevant to this article will be
provided in Section II. At this point, we note that the existing
methods work well for the case where each element Si j of
the scattering matrix share a common set of poles, which
is often called multi-input multi-output (MIMO) modeling in
1972 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 11, NO. 11, NOVEMBER 2021

Fig. 1. Synthesis of one-port Y parameter [14], for the case of (a) one constant term, (b) one real pole, (c) a pair of complex conjugate poles, in the form of
RLCR, (d) again a pair of complex conjugate poles, but in the form of RLCG, where G represents a VCCS, and (e) N terms of pole–residue pairs, in which
the admittance blocks of each term are simply connected in parallel. In the above equations, the subscripts r and i denote the real and imaginary parts of the
quantity, respectively.

VF literature [6]. However, for the multi-single-input-single-

output (SISO) modeling, where each Si j has its own distinct
poles, we find that the synthesized circuits of existing methods
are more complex than necessary, where the complexity may
be in terms of the number of circuit elements, number of
nodes, and so on.
The MIMO modeling, multi-SISO modeling, and also the
multi-SIMO modeling, where each element in the same col-
umn of the S matrix share a common set of poles, are
the three most commonly used pole-assignment schemes in
VF [6]. While MIMO fitting is perhaps the most often adopted
strategy among the three, each of them has its pros and cons.
For example, MIMO modeling delivers the smallest state- Fig. 2. Synthesis of multiport Y parameters (here, a four-port) via the
generalized pi-model [22]. Each branch in the figure can be realized based
space realization, which makes it easier for subsequent passiv- on the topology in Fig. 1.
ity enforcement if needed. Conversely, multi-SISO modeling
results in the largest state-space realization among the three. will be presented in Section III, while the simulation results
On the other hand, multi-SISO fitting can be trivially paral- in Section IV verify that the complexity reduction can indeed
lelized, making it highly efficient on a multithread computer. shorten the simulation time by a ratio ranging from 1.3 to 2,
In addition, since only one single Si j is being fit each time, depending on how the results are compared.
it is easier for multi-SISO VF to achieve higher accuracy, pos-
sibly with fewer poles than MIMO modeling. In the extreme II. R EVIEW OF C IRCUIT S YNTHESIS A PPROACHES
(hypothetical) case, where all Si j are obtained from rational
We start from a pole–residue representation of the S para-
functions of totally different poles, the MIMO fitting, having
meters of a P-port network
to account for (almost) all these distinct poles in its (only)
global pole set, would be much slower than the multi-SISO 
N (i j )
rk 
N

and also face the problem of overfitting because the number Si j = d (i j ) + (i j )

of poles used to fit each Si j is far greater than that is actually
needed. Consequently, there are certainly situations where the
multi-SISO is preferred, and, indeed, some macromodeling
tools offer the option of multi-SISO fitting [10].
We must clarify, however, that the purpose of this article
is not to advocate the use of multi-SISO modeling. Instead,
we simply propose a new circuit topology that is 1.5–2 times
smaller in complexity than the existing approaches, under
multi-SISO fitting. Whenever the multi-SISO is preferred
over MIMO fitting, for any reason, the proposed synthesis
method can be used to construct equivalent circuits that exactly
represent the rational functions, which can then be imported
into general simulators for further analysis. The new topology
= d (i j ) + Si j,k (1)
k=1 s − pk k=1
where N is the number of poles used to fit each Si j . For MIMO
(i j )
modeling, the poles pk = pk , that is, independent of i and j .
Since this article targets at multi-SISO synthesis, we assume
each Si j has different poles.
If, instead of modeling the S parameters, we were fitting a
one-port Y parameter, then the pole–residue representation can
be realized as in Fig. 1 [14]. For multiport Y parameters, the
circuit can be realized via the generalized pi-model; a four-port
example is shown in Fig. 2.
Based on the topology shown in Fig. 2, an equivalent circuit
for the multiport S parameters in the pole–residue form (1) can
be realized as shown in Fig. 3 [22]. In this topology, the main

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CHOU AND SCHUTT-AINÉ: EQUIVALENT CIRCUIT SYNTHESIS OF MULTIPORT S PARAMETERS IN POLE–RESIDUE FORM 1973

circuit is in the dashed box, which is completely the same as

Fig. 2. Some additional controlled sources are used to convert
the Y matrix to the S matrix.
The complexity of the realization in Fig. 3 can be computed
as follows. For simplicity, we assume most of the poles are in
complex conjugate pairs, that is, there are few real poles. This
assumption is usually qualified if the pole–residue model (1) is
obtained from VF. If the RLCR form in Fig. 1(c) is used, then
each pole-pair adds in four circuit components, two nodes,
and one inductor. Equivalently, we say each pole requires
two components, one node, and 0.5 inductors. The number
of inductors is highlighted here because, in the modified
nodal analysis (MNA) formulation, the unknown variables
are the node voltages and selected branch currents [23]. For
example, the currents flow through resistors and capacitors
are not selected, while currents through inductors and con- Fig. 3. Synthesis of multiport S parameters (here, a four-port) via the
trolled sources are generally selected. If the RLCG form Y -parameter pi-model [22]. The core circuit in the dashed box is realized
in Fig. 1(d) is used, then each pole needs two components, one in the same way as Fig. 2. The controlled sources are for the conversion
between the incident/reflected waves at the ports and the voltages/currents at
node, 0.5 inductors, and 0.5 voltage-controlled current source the terminals of the dashed box.
(VCCS). In Fig. 2, there are ∼ P 2 /2 Yi j (i = j ) branches,
each one in the form of Fig. 1(e) with N poles. Thus, there
are totally NP2 /2 poles in the Yi j branches. In Fig. 2, there
are also P Ȳii branches. Under multi-SISO fitting, however,
each Ȳii branch contains P terms and each term has N poles
that are generally different. Thus, the Ȳii branches in total
contribute to NP2 poles. Therefore, the leading orders of the
complexity of Fig. 3 are 3NP2 components, 1.5NP2 nodes,
0.75NP2 inductors, and additionally 0.75NP2 VCCSs if the
RLCG form is used. We note that if MIMO fitting were used
instead, then the Ȳii branches would only have NP poles, and
the complexity would be dominated by the Yi j branches.
A second way to construct equivalent circuits of (1) is based
on state-space synthesis [6], [12], [13]. As mentioned earlier,
the pole–residue form (1) can be converted to a state-space
model (A, B, C, D) directly, which is given by
(i j )
A = diag pk (2)
j =1,...,P
i=1,...,P Fig. 4. Illustration of the state-space model of (1) based on (2)–(5).
k=1,...,N
Bn j = 1{( j −1)N P<n≤ j N P} (3) √
Cin =
(i j )
rk · 1{n=( j −1)N P+(i−1)N +k} (4) where i = −1. Then, after the transformation A ← TAT −1 ,
(i j ) B ← TB, and C ← CT −1 , the corresponding entries in the A,
Di j = d (5) B, and C matrices become
where A ∈ C N P ×N P , B ∈ R N P ×P , C ∈ C P×N P , D ∈
2 2 2 2
   
σ1 ω1 2
C P×P , and 1{·} is the indicator function that assumes the A1:2,1:2 = B1:2,1 =
−ω1 σ1 0
value 1 if the condition is satisfied and 0 otherwise. The  
triple diagonal operation of (2) can be regarded as a triple for C1,1:2 = r1r r1i (7)
loop, where k is in the innermost loop while j the outermost.
An illustration of (2)–(5) is shown in Fig. 4. which are purely real. In this manner, all complex conju-
Usually a real-valued state-space is preferred, which can be gate poles originally in (2)–(5) can be transformed into the
realized by a similarity transformation of (2)–(5). Suppose the form (7), giving a real-valued state-space realization. Subse-
first two poles, p1(11) = σ1 + j ω1 and p2(11) = σ1 − j ω1 , are quently, the equivalent circuit can be synthesized as shown in
Fig. 5.
complex conjugates. By (3) and (4), initially C11 = r1(11) =
To compute the complexity of Fig. 5, we again assume that
r1r + jr1i , C12 = r1r − jr1i , and B11 = B21 = 1. Let T be a
all poles are complex. Each pole requires 3.5 components, one
block-diagonal transformation matrix whose upper-left 2 × 2
node, and 1.5 VCCSs at the state-equation section, and one
block is given by
  VCCS at the output section. Hence, the state-space synthesis
1 1 in total needs 4.5NP2 components, NP2 nodes, and 2.5NP2
T1:2,1:2 = (6)
1i −1i VCCSs.

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1974 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 11, NO. 11, NOVEMBER 2021
Fig. 5. Synthesis of multiport S parameters based on state-space
model [6], [12], [13]. The input-equation blocks convert port voltages/currents
to incident waves a j . The state-equation and output-equation blocks are based
on (7).
Fig. 6. Synthesis of multiport S parameters [16], [17] by realizing each
pole–residue term of each Si j as the reflection coefficient at an intermediate
stage.
A third approach to realize a multiport S parameter in
the pole–residue form is shown in Fig. 6 [16]–[18]. The
idea is to realize each pole–residue term of each Si j as the
reflection coefficient at an intermediate stage. The reflected
wave, which equals the incident wave a j times the kth term
of (1), is reconstructed using controlled sources that connect
directly to the output ports (all in parallel). To realize a
(i j )
pole–residue pair, the Yk branch can be in the form as shown
at the bottom part of Fig. 6. There are other possible topologies
(i j )
for realizing a complex-pole Yk [17], with the same level of
complexity. The incident waves a j at the reflection-coefficient
stages can be implemented in the same way as in Fig. 5, and
the controlled source for the incident wave at the reflection-
coefficient stages can be shared.
Assume all poles are complex. At each reflection-coefficient
stage, there are seven components, four nodes, and one induc-
tor. To feed the reflected waves to the output ports, two
additional controlled sources are needed. Hence, in total this
topology requires 4.5NP2 components, 2NP2 nodes, 0.5NP2
inductor, and 1NP2 controlled sources.
Another way to synthesize equivalent circuits is by explic-
itly transforming the rational representation of S parameters
into a rational representation of Y parameters and then base
the circuit on the topology of Fig. 2 without the need for
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additional controlled sources as in Fig. 3. The transformation
can be accomplished through the state-space model (2)–(7).
Specifically, once we have a state-space ( A, B, C, D) for S
parameters, the state-space (A’, B’, C’, D’) for Y parameters
can be obtained as [22], [24]
A = A − B(I + D)−1 C
1
B  = √ B(I + D)−1
Z0
−2
C  = √ (I + D)−1 C
Z0
 1
D = (I − D)(I + D)−1 . (8)
Z0
The poles of ( A’, B’, C’, D’) are the eigenvalues of A’.
The residues can be obtained through [25]
 
(i j )
Rk = r k = C  x k ykT B  (9)
where x k and yk are the normalized (ykT xl = δkl ) right and
left eigenvectors of A’ corresponding to the eigenvalue pk ,
respectively. The benefit of this method is the removal of all
controlled sources, which may be necessary for some specific
solvers where controlled sources are not supported [21]. The
drawback of this method is the need to compute the inverse
of (I + D) in (8), which may be problematic if the D matrix
has an eigenvalue close to −1, such as when there is a shunt
capacitor connected directly to a port. The complexity of this
method is the same as Fig. 3, because the core block in Fig. 3
is the same as Fig. 2, while the number of controlled sources
is second-order.
We note that it is also possible to synthesize the circuits
based directly on the state-space model of Y parameters (A’,
B’, C’, D’), such as using the methods in [15] and [21].
However, as is evident from (8), the transformed state-space is
dense, in general, thus increasing the circuit complexity. Even
though the A’ matrix can be made sparse by diagonalization,
the input matrix B’ will still be full.
In summary, among these existing methods, the topology of
Fig. 3 has the smallest complexity in terms of total number
of components, while the state-space synthesis (Fig. 5) has
the smallest number of nodes. Another point of concern is
the occurrence of negative circuit components (R, L, and C).
In the topology of Fig. 3, since the pole–residues are realized
based on Fig. 1, there is no guarantee that the RLC values
will be positive. Occurrence of negative RLC is fine for some
circuit simulators, while some may require purely positive
elements [21]. The state-space method (Fig. 5), on the other
hand, only has positive C and positive R, provided all poles
are stable, that is, real part < 0. We note that the state-space
synthesis of Fig. 5 (or its variants) is widely adopted in many
commercial macromodeling tools [10], [11]. Finally, we note
that all the topologies presented so far are applicable for both
passive and nonpassive blocks, as no passivity restriction is
put on the rational macromodel (1).
III. P ROPOSED T OPOLOGY
The proposed circuit topology for synthesis of multiport
S parameters in multi-SISO pole–residue form (1) is shown
CHOU AND SCHUTT-AINÉ: EQUIVALENT CIRCUIT SYNTHESIS OF MULTIPORT S PARAMETERS IN POLE–RESIDUE FORM 1975

TABLE I
C OMPARISON OF C IRCUIT C OMPLEXITY OF D IFFERENT M ETHODS

a negative R, L, or C occur, their values are negated to make

them positive, and an additional voltage-controlled voltage
source (VCVS, E element) is used, which feeds two times
Fig. 7. Proposed circuit topology for synthesis of multiport S parameters in the voltage across those (originally) negative elements back
the pole–residue form.
to the branch. In this manner, the effective admittance of the
RLC branch is the same, while all RLC values are ensured to
in Fig. 7. Here, we assume that the i th port has reference be positive. Also, note that when C < 0, the G value has to
impedance Z i that is real and frequency-independent. The be negated accordingly. Because of the use of the additional E
main circuits are P intermediate stages, each of which realizes element, we call this topology RLCGE, to be compared with
the responses to the incident power wave from a particular the RLCR and RLCG in Fig. 1. Finally, we note that it is
port. Each intermediate stage contains P subblocks that realize also possible to apply this technique to the RLCR topology
one Si j . Each subblock in turn has N terms, corresponding of Fig. 1(c). However, for some cases (e.g., R1 < 0 and
to (1). Each term is realized using the topology of Fig. 1, R2 < 0), one single VCVS is not sufficient. We need two
that is, the scattering parameters in (1) are treated as if they VCVSs to ensure positive RLC values for all situations. Hence,
were admittance parameters. By the two controlled sources the complexity is higher than the RLCGE form.
at the left of each intermediate stage, the voltage at the top The complexity of the proposed topology is dominated by
node of each stage is proportional to the incident power wave. the realization of the NP2 Y-branches. All other controlled
Consequently, the current Ii j flowing through the i th 0-V sources are of second order. Comparison of the complexity
voltage source is proportional to the incident power wave a j with the state-space method (Fig. 5) and pi-model (Fig. 3)
times Si j . This current is then sampled by a current-controlled is listed in Table I. As is evident, the RLCG form of the
current source (CCCS, F element) and fed to the corresponding proposed topology is 1.5 times smaller than the RLCG form
output port. of the pi-model in terms of all items of comparison, whereas
Each admittance branch has the value it is roughly two times smaller than the state-space form in
1 terms of total circuit components. The RLCGE form, trading
Ỹi j,k = √ Si j,k . (10)
Zi complexity for positive element values, is still smaller than the
existing methods.
To verify this topology indeed realizes the relation (1),
consider the output power wave at the i th port
IV. V ERIFICATION
√
Zi 
P
Vi − Z i Ii In this section, we use two pole–residue macromodels to
bi = √ = Ii j
2 Zi 2 j =1 compare the efficiency of the six circuit topologies listed
√ in Table I. The first model is generated from the measured
Zi  √ 
P N
Vj S parameters of a differential channel (P = 4) on a PCB with
= √ + Ij Z j Ỹi j,k
2 j =1 Zj the FR4 substrate, from 10 MHz to 20 GHz with 2000 points.
k=1
√ We denote this model as fr4_channel. The second model is
Zi  √ 
P N
Vj Si j,k generated from the response of ten coupled microstrip lines
= √ + Ij Z j √
2 j =1 Zj Zi (P = 20) simulated by Keysight ADS, from 10 kHz to
k=1
20 GHz with 1001 points. We denote this model coupled_line.

P 
N 
P
The multi-SISO VF, written in Python, is applied to the
= aj Si j,k = a j Si j . (11)
S parameters to obtain macromodels in the form of (1).
j =1 k=1 j =1
For fr4_channel, we use 300 poles (N = 300), while for
Therefore, the circuit of Fig. 7 is indeed a realization of (1). coupled_line we use N = 77. In addition to the six topologies
Since the proposed topology adopts the Y-branch synthesis in Table I, we also synthesize equivalent circuits based on the
of Fig. 1, negative RLC may occur. When only positive POLE-element VCCS in the Hspice format [8], which allows
elements are accepted, we can use a standard simple technique direct specification of the pole and residue values in the netlist.
to make all RLC values positive, as shown in Fig. 8. Whenever As mentioned earlier, this is usually the preferred approach to

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1976 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 11, NO. 11, NOVEMBER 2021

Fig. 8. Technique to make all RLC values in the RLCG form of Fig. 1 (d) positive. Because an additional VCVS (E element) is used, this topology is called
RLCGE.

Fig. 9. Testing procedure. The circuits “PI-model-RLCR” and

“PI-model-RLCG” denote the topology in Fig. 3 where the complex poles are
realized using Fig. 1(c) and (d), respectively. The circuit “sparse state-space”
denotes the topology in Fig. 5. The proposed topologies are shown in Fig. 7,
with complex poles realized by RLCR [Fig. 1 (c)], RLCG [Fig. 1 (d)], and
RLCGE (Fig. 8). The “POLE element” denotes the circuit that uses the
pole-zero VCCS in Hspice format, which directly specifies the residues and
poles in the netlist, rather than synthesizing equivalent circuits. Note that the
POLE element can only be simulated in a few commercial solvers.

simulate a rational macromodel, if supported by the simulator.

Below, we also record the CPU time of this circuit (denoted as
POLE-element), for reference purpose. However, we note that
the proposed circuit of this article is not aiming at being more
efficient than direct rational simulation. Instead, it is targeted at
the situation where direct rational simulation is not permitted. Fig. 10. (a) S11 of the seven circuit realizations of fr4_channel simulated
by AEDT, as well as the original measurement data. The difference between
In summary, we have two macromodels, each is synthesized the circuits and measurement is due to the VF process and is irrelevant here.
using seven topologies, resulting in 14 circuits in comparison. The difference between the seven circuits is too small to be visible on this
The testing procedure is summarized in Fig. 9. plot. (b) Take the POLE-element as reference. This plot shows the absolute
difference of S11 of the other six topologies against the reference.
First, we need to verify that the circuits are correctly
implemented. The S11 of the seven circuit realizations of the
fr4_channel, as well as the original measurement data, are
shown in Fig. 10(a). It is observed that the S11 of all seven
circuits overlap each other. Indeed, since all seven topologies
are exact realizations of the pole–residue macromodel (1),
the difference of their external responses should be solely
due to numerical error. For example, we take the S11 of
POLE-element as reference, and compute its absolute differ-
ence with the S11 of the other six topologies. The results Fig. 11. Voltage at port 12 (far end crosstalk) of the seven 77-pole circuit
realizations of coupled_line, simulated by AEDT. The seven curves overlap
are shown in Fig. 10(b). Indeed, for most frequencies, the each other; their difference is too small to be visible on this plot. These results
difference is of the order 10−13 or smaller, which is close to verify that the circuits are correctly implemented.
machine precision. Occasionally, the difference is larger due
to the numerical conditioning associated with each topology, transient waveforms at port 12 (far end crosstalk) of cou-
but never greater than 10−8 , which is practically acceptable. pled_line when port 1 is excited by a pulse source. Again,
In Fig. 10(a), there is some small difference between measure- the seven curves overlap each other; their difference is too
ment and macromodel, which is due to the VF process, and small to be visible on this voltage scale. The above results
is not relevant to this article. Similarly, we plot in Fig. 11 the verify that the circuits are correctly generated.

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CHOU AND SCHUTT-AINÉ: EQUIVALENT CIRCUIT SYNTHESIS OF MULTIPORT S PARAMETERS IN POLE–RESIDUE FORM 1977

TABLE II
C OMPARISON OF S IMULATION T IME FOR 100-ns T RANSIENT S IMULATION

To compare the transient simulation time, we use four circuit and LTspice [27]. All simulators are run in sequential mode
solvers: Ansys AEDT [11], Keysight ADS [10], Ngspice [26], (nonparallel). Because each engine has its own specific

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1978 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 11, NO. 11, NOVEMBER 2021
implementation of the transient algorithm, the runtimes differ.
Through the comparison across different solvers, we can
understand the efficiency of the circuit topologies more com-
prehensively. The results are listed in Table II.
For the cases denoted by “linear termination,” a periodic
pulse voltage source is applied to port 1, while all the other
ports are terminated by resistors. For the cases denoted by
“CMOS,” the same pulse source is applied to a CMOS inverter
first which drives port 1 of the channel, and the receiving port
is terminated by an inverter as well. The simulation is run to
100 ns.
Typical transient solvers use variable instead of fixed time
step to achieve faster speed; when the waveform is relatively
smooth, the solver may try to increase the time step for
acceleration. Consequently, the total number of steps required
to march to 100 ns differs. In Table II, we record not only
the total simulation time, but also the number of time steps,
and the normalized time per step for comparison. For AEDT,
Ngspice, and LTspice, we set the maximum time step (delmax)
to 10 ps, while the actual time step is typically around 4–9 ps.
ADS, on the other hand, offers the option of fixed time step,
and we set it as 1 ps. All simulations are performed on the
same computer.
We note that, primarily, the numbers in Table II should
be compared horizontally, because they correspond to the
same macromodel and same solver settings, and thus the
difference in runtime solely reflects the effects of the circuit
topologies. Different solvers, on the other hand, have different
transient algorithms, which affect the timing results signifi-
cantly. We summarize the observations from Table II into the
following points.
A. Normalized Time Per Step
For AEDT, ADS, and LTspice, the normalized time per
step of the proposed topologies (RLCR and RLCG) are both
smaller than the conventional topologies (not including the
POLE element). The speedup factors against the PI topologies
are at least 1.5, sometimes much larger. The speedup factors
against the state-space topology ranges from 1.3 to 2.
For Ngspice, the proposed topologies have nearly the same
runtime as the state-space topology for the coupled_line case,
while for the fr4_channel case, the proposed topologies are
slower than the state-space by roughly 1.2 times.
B. Total Simulation Time
In terms of the total simulation time, we observe sim-
ilar results. For most cases, either the proposed-RLCR or
proposed-RLCG runs fastest. The only exception is the case of
fr4_channel solved by Ngspice, where the state-space topology
outperforms the proposed-RLCG by 1.16 times.
We also observe that, for most cases, the proposed-RLCG is
faster than the proposed-RLCR topology. The only exception
is LTspice, partly due to the smaller number of total steps
required.
C. Number of Time Steps
The total number of time steps, apparently, is a very solver-
dependent quantity. We can hardly say one topology will
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definitely result in more time steps than one another. For
example, for the coupled_line (linear) case, the number of time
steps of PI-RLCR is the second smallest in LTspice (11 337)
among the six topologies, but the largest in AEDT (22 999).
As another example, in LTspice, the PI-RLCG has the smallest
number of steps for the coupled_line case (11 208), while the
largest for fr4_channel (49 158) (among the six topologies).
In this regard, the total simulation time, due to its dependence
on the number of steps, may be less indicative of the circuit
complexity than the normalized time per step.
D. RLCGE Topology
The proposed-RLCGE topology, trading complexity for
positive circuit elements, is roughly 1.3 times slower than the
proposed RLCG in terms of normalized time per step. The
total simulation time, likewise, is more difficult to quantify
due to the solver-dependent time step control.
E. POLE-Element
The POLE-element, which directly specifies the pole/zero
values in the netlist, runs fastest on ADS, and the normalized
time per step can be ten times smaller than other circuit
synthesis approaches. This is to be expected, however, since
explicit pole/zero specification allows the solver to use the
highly efficient recursive convolution. AEDT, on the other
hand, is less efficient in handling the POLE-element circuit
and is even slightly slower than the proposed-RLCR synthesis
approach in terms of normalized runtime.
In summary, from the results in Table II, we could say
that the proposed topology can indeed reduce the circuit
complexity and thus the transient simulation time. Four
different solvers were used to compare the transient time,
and it was observed that either the proposed-RLCR or
proposed-RLCG topology has the smallest runtime per step on
most simulators. In particular, when compared with the widely
adopted state-space topology, the proposed-RLCG form can
achieve 1.3–2 times speedup. The only exception is Ngspice,
on which the proposed topologies are roughly the same
or slightly slower than the state-space topology. If negative
circuit elements are not permitted, then the proposed-RLCGE
can be used, which is roughly 1.3 times slower than the
proposed-RLCG topology.
V. C ONCLUSION
Equivalent circuit synthesis of pole–residue macromodels
is an important step in the signal integrity analysis of high-
speed links. In this article, a new topology suitable for multi-
SISO macromodels was proposed, which has complexity that
is smaller than the conventional approaches. Simulation results
of two macromodels on four solvers verified that the proposed
topology can achieve a speedup ratio of 1.3–2 on most
simulators, compared with the conventional topologies.
ACKNOWLEDGMENT
The authors like to thank the National Center for High-
performance Computing (NCHC) for providing computational
and storage resources.
CHOU AND SCHUTT-AINÉ: EQUIVALENT CIRCUIT SYNTHESIS OF MULTIPORT S PARAMETERS IN POLE–RESIDUE FORM
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Chiu-Chih Chou (Member, IEEE) received the
Ph.D. degree in electrical engineering from the
National Taiwan University, Taipei City, Taiwan,
in 2019.
He is currently an Assistant Professor with the
Department of Electrical Engineering, National Cen-
tral University, Taoyuan, Taiwan. His research inter-
ests include electromagnetic compatibility, signal
integrity, macromodeling, and circuit simulation.
José E. Schutt-Ainé (Fellow, IEEE) received the
B.S. degree in electrical engineering from Massa-
chusetts Institute of Technology, Cambridge, MA,
USA, in 1981, and the M.S. and Ph.D. degrees
from the University of Illinois at Urbana-Champaign
(UIUC), Urbana, IL, USA, in 1984 and 1988,
respectively.
He joined the Hewlett-Packard Technology Center,
Santa Rosa, CA, USA, as an Application Engineer,
where he was involved in research on microwave
transistors and high-frequency circuits. In 1983,
he joined UIUC and then joined the Electrical and Computer Engineering
Department as a member of the Electromagnetics and Coordinated Science
Laboratories, where he is currently involved in research on signal integrity
for high-speed digital and high-frequency applications. He is a consultant for
several corporations. His current research interests include the study of signal
integrity and the generation of computer-aided design tools for high-speed
digital systems.
Dr. Schutt-Ainé was a recipient of several research awards, including the
1991 National Science Foundation (NSF) MRI Award, the NASA Faculty
Award for Research in 1992, the NSF MCAA Award in 1996, and the
UIUC-National Center for Superconducting Applications Faculty Fellow
Award in 2000. He served as Coeditor-in-Chief for the IEEE T RANSACTIONS
ON C OMPONENTS , PACKAGING AND M ANUFACTURING T ECHNOLOGY
(T-CPMT) from 2007 to 2018.