INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Int. J. Circ. Theor. Appl. (2011)

Published online in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.776

Power-efficient analog design based on the class AB super source

follower

Antonio J. Lopez-Martin1,∗, † , Lucia Acosta2 , Coro Garcia-Alberdi1,

Ramon G. Carvajal2 and Jaime Ramirez-Angulo3
1 Department of Electrical and Electronic Engineering, Public University of Navarra, Pamplona, Spain
2 Department of Electronic Engineering, School of Engineering, University of Seville, Sevilla, Spain
3 Klipsch School of Electrical Engineering, New Mexico State University, Las Cruces, NM, U.S.A.

SUMMARY
A class AB version of the conventional super source follower (SSF) is described. The circuit greatly
increases slew rate (SR) and current efficiency, maintaining the low distortion and low output resistance
of the SSF. Class AB operation is achieved without extra power dissipation or supply requirements, and
without bandwidth or noise degradation. The circuit can advantageously replace the SSF in a wide variety
of analog systems, opening a new research line in analog design. To illustrate the widespread application
of this cell, a class AB differential unity-gain buffer, a class AB differential current mirror and two
class AB differential transconductors are designed, fabricated in a 0.5 m CMOS technology and tested.
Measurement results using a dual supply of ±1.65 V show that the proposed class AB version of the
SSF improves SR by a factor 21.5 and increases bandwidth by 10%, keeping noise level, input range,
power consumption, and supply requirements unaltered. The fabricated class AB current mirror features
a THD at 100 kHz of −62 dB for signal currents 20 times larger than the bias current. The fabricated
transconductors feature an IM3 at 1 MHz of −56.6 dB for output currents more than 13 times larger than
the bias currents. Copyright 䉷 2011 John Wiley & Sons, Ltd.

Received 1 August 2010; Revised 30 December 2010; Accepted 15 February 2011

KEY WORDS: low-voltage CMOS circuits; analog CMOS circuits; class AB amplifiers; transconductors;
super source follower; quasi-floating-gate MOSFET

1. INTRODUCTION

Nowadays CMOS technology downscaling and demands of wireless equipment have promoted the
design of mixed-mode integrated circuits able to operate with low supply voltage and low power
consumption [1–4]. This trend requires new design techniques, since many of the conventional
ones are not suited to this scenario. The aim of this work is to fulfill this requirement by proposing
a new style for analog design based on a simple basic building block with nearly ideal power
efficiency.
One of the most widely used single-transistor configurations in the traditional analog design
is the common-drain transistor, also named source follower (SF), and shown in Figure 1(a). The
input signal is applied at a high-impedance gate and the output signal, equal to the input signal
minus the gate-source voltage VGS1 , is obtained at the low-impedance source terminal. SFs are
employed as voltage buffers and dc level shifters. Despite their simplicity and wide bandwidth,

∗ Correspondence to: Antonio J. Lopez-Martin, Department of Electrical and Electronic Engineering, Public University
of Navarra Campus Arrosadía, E-31006 Pamplona, Spain.
† E-mail: antonio.lopez@unavarra.es

Copyright 䉷 2011 John Wiley & Sons, Ltd.

 A. J. LOPEZ-MARTIN ET AL.

IB1 M2 IB1+IB2
Iout Iout Vout Iout V
Vout out

Vin M1 Vin M1
Vin M1
(a) M2
IB1 IB1
(b) (c)

Rlarge Rlarge
VB
M3 M4
Vout
Iout
IB1+IB2 Cbat
Vin M1
M2 Isubth
(d) IB1 (e)

Figure 1. (a) Source follower; (b) flipped voltage follower; (c) super source follower; (d) class AB super
source follower; and (e) two possible implementations of Rlarge .

they also have important drawbacks. The MOS transconductance is not very high, which leads to
an output resistance Rout not too small (typically of a few k), given by
1
Rout = (1)
gm1 + gmb1
where gm1 and gmb1 are the transconductance and back-gate transconductance, respectively, of
transistor M1 . To decrease Rout larger bias current and W/L ratio are required, thus increasing area
and power dissipation. Besides linearity is modest mainly because current in the SF transistor is
signal-dependent, making VGS1 also signal dependent. This is unavoidable as in this configuration
two simultaneous tasks are required for transistor M1 : setting the output voltage and driving
the load. To solve these drawbacks, the key idea is using an additional transistor M2 to drive
the load. This additional transistor M2 is arranged in a negative feedback loop, thus reducing
output resistance. Current in transistor M1 now is constant, improving linearity. Figure 1(b) shows
a possible arrangement of this idea, named flipped voltage follower (FVF) in [5]. The output
resistance, which is typically of a few Ohms, is
1
Rout = (2)
(gm1 + gmb1 )gm2 (ro1 rB1 )
where resistance ro1 is the drain-source resistance of M1 and rB1 the output resistance of the current
source IB1 . Since current in M1 is constant, neglecting channel length modulation and body effect
VGS1 is also constant, improving linearity. The body effect can be avoided by embodying M1 in
an independent well connected to the source terminal, but in this case the term gmb1 in Equations
(1) and (2) disappears and the well to substrate capacitance may reduce bandwidth.
The FVF is widely used in low-voltage applications, but it has an important shortcoming: the
input and output ranges are very small, given by |VTH1 |−|VDS1sat |, where VTH1 and VDS1sat are
the threshold voltage and drain-source saturation voltage of transistor M1 , respectively. Note that
this headroom relies on VTH , which is strongly technology-dependent and can be very small in
modern deep-submicron processes. Besides, this voltage range does not increase with the supply
voltage. It can be increased by adding a dc level shift in the feedback loop of the FVF (e.g.
using a source follower) [5], but then an additional pole is introduced into the loop, extra area
and quiescent power is required, and the two shortcomings mentioned (technology-dependent and
supply-independent headroom) still remain. A better solution, particularly for not very low supply
voltages, is the alternative arrangement of M2 shown in Figure 1(c). This topology was named
super source follower (SSF) in [6] and has been widely used in the last two decades. As for the FVF,

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 POWER-EFFICIENT ANALOG DESIGN

the output resistance is also given by Equation (2) and VGS1 is constant neglecting second-order
effects. However, in this case the input voltage range is VDD − VIB −|VDS1sat |− VGS2 − VSS , where
VIB is the voltage headroom required for the upper current source to operate (VIB = |VDSsat | if the
current source is just a transistor). Note how the input range now increases with VDD . However,
the additional branch increases quiescent power compared with the FVF.
In summary, the SSF features higher linearity and much lower output resistance than the SF
of Figure 1(a), and does not have the input range restrictions of the FVF. However, it still has
an important drawback. Like the SF and the FVF, it has limited current driving capability as the
maximum current that can be delivered to the load is limited by the bias current. The SF and SSF
in Figure 1 can sink a large current from the load, but the maximum current they can source is
limited to IB1 for the SF and IB1 + IB2 for the SSF. In the FVF of Figure 1, the maximum current
it can source to the load is not limited by IB1 , but the maximum current sunk from the load is IB1 .
The NMOS versions of the followers feature output currents limited by the bias currents in the
opposite direction. As a consequence, there is a trade-off between quiescent power consumption
and slew-rate (SR) performance in the SSF, just like the SF and FVF.
In this paper, a class AB version of the SSF is described that solves this SR limitation without
degrading other performance parameters of the SSF. More specifically, it preserves quiescent
power consumption, accuracy in the quiescent currents, bandwidth, noise level, and supply voltage
requirements. The only price paid is a small increase in silicon area (typically about 20%). It
employs quasi-floating gate (QFG) techniques [7, 8] to achieve this goal. The operation of the class
AB SSF is analyzed in detail and its suitability as basic building block for low-voltage micropower
analog design is evidenced. To this end the application of this cell in various analog circuits is
explored, such as in class AB buffers, class AB current mirrors, and class AB transconductors.
These applications are just an example of the usefulness of the class AB SSF proposed, which can
replace the SSF in virtually any circuit proposed to date providing improved dynamic operation
without degrading other performance parameters. Hence, it can be regarded as a way to increase
the power efficiency of the existing SSF-based circuits.

2. THE CLASS AB SSF

Figure 1(d) shows the class AB version of the SSF of Figure 1(c), based on the use of QFG
techniques [7, 8]. In ac operation, this topology simply results from the overlapping of the topologies
in Figures 1(b) and (c). A brief review of QFG techniques is presented first. Then the class AB
SSF is analyzed.

2.1. QFG transistor

In an analogous way to the idea of the SSF, which results from splitting the two tasks performed
by M1 in the SF (setting the output voltage and driving the load) into two different transistors, the
QFG technique results from splitting the two tasks performed usually at the gate terminal (setting
dc bias and signal voltages) into two independent terminals. The idea is illustrated in Figure 2.
The conventional way of driving a transistor is shown in Figure 2(a). Both dc bias and ac signal
coming from the driving stage are applied to the gate; hence, they cannot be independently set.
In Figure 2(b), two different terminals are used for setting independently the dc bias and signal,
thanks to a resistor R and a capacitor C. This technique is widely used in RF circuits [9], where
R needs not be too large due to the very high-frequency narrowband signals employed. To extend
this technique to baseband applications with reasonably small C, resistance R must be extremely
large so that only the dc level is blocked at the terminal where the signal is applied, and all signal
frequency components are translated to the gate terminal. Owing to this extremely large value of
R, the gate becomes a quasi-floating node, with well-defined dc voltage but floating from a signal
viewpoint, hence the name of this technique.

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 A. J. LOPEZ-MARTIN ET AL.

Vg
Vac
Vg
Vdc
(a) t
V1
Vdc V1 R Vg
t
V2 C Vg V
Vac V2 ac
V'dc
(b) Vdc
t
t

Figure 2. (a) Conventional biasing of a transistor and (b) quasi-floating gate transistor.

Note from Figure 2(b) that an RC high-pass filtering takes place between the input node where
V2 is applied and the gate, which is given by
VG (s) s R(C +CG )
= (3)
V2 (s) s R(C +CG )+1
where  = C/(C +CG ) and CG is the parasitic capacitance at the gate terminal. Attenuation 
from the input signal terminal to the gate is due to CG , and determines the minimum required
value for C. Capacitance CG is dominated by the intrinsic gate-source capacitance CGS , and to
reduce the contribution due to capacitor C in CG , the top plate of C should be connected to
the gate. Resistance R does not require to be linear or to have a precise value, but it should be
high enough to provide a cutoff frequency f −3 dB = 1/[2R(C +CG )] lower than the minimum
frequency component of the input signal. In baseband applications, usually only the dc component
should be blocked, requiring a resistance of GigaOhms to achieve a cutoff frequency f −3 dB <1 Hz
with a C not much larger than CG . Owing to the mentioned tolerance to the exact value or R,
process, voltage, or temperature variations affecting this resistance are not relevant and it can
be implemented by the leakage resistance of a minimum-size diode-connected MOS transistor in
cutoff region or a minimum-size transistor biased by another identical transistor in subthreshold
region [7], as shown in Figure 1(e), leading to a compact implementation that does not demand
extra power consumption.
The transfer function from the other input terminal V1 in Figure 2(b) is
VG (s) 1
= (4)
V1 (s) 1+s R(C +CG )
i.e. an RC lowpass filtering with the same cutoff frequency f −3 dB = 1/[2R(C +CG )] as the high-
pass filtering in Equation (3). Hence due to the large value of R employed in QFG transistors, the
dc bias of the gate terminal is set by this input V1 and any ac noise or interference appearing at
this input terminal is filtered out.
The independent control of static and dynamic performance by two different input terminals
in QFG transistors, shown in Figure 2(b), is the key idea to achieve class AB operation in an
efficient way. The dc level is precisely set by the input V1 , as C has no effect in static conditions.
This allows an accurate control of the quiescent current. Concerning dynamic operation, signal is
transferred from the other input V2 , as the gate voltage can freely swing due to the large value of
resistance R.

2.2. Class AB SSF

The proposed class AB version of the SSF is shown in Figure 1(d), and it is just making the
gate of M4 in the SSF a QFG. To do so, a floating capacitor Cbat is placed between the gates
of M4 and M2 , and a large-valued resistive device Rlarge between the gate of M4 and the node
that sets the dc bias to VB . Note that class AB operation is obtained without altering the SSF
static behavior, since capacitance Cbat has no effect in quiescent conditions and there is no voltage

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 POWER-EFFICIENT ANALOG DESIGN

drop in resistance Rlarge . Therefore, the quiescent current of M4 is accurately controlled by the
current mirror M3 –M4 , and is supply, process, and temperature independent if IB1 and IB2 are
too, just like the SSF. This static current can be made small to save static power, as it does not
limit dynamic currents as opposed to the SSF. In summary, the QFG technique has no impact on
static performance. However, it improves dynamic performance by allowing class AB operation.
To illustrate it, assume an increase vin in the input voltage. This leads to a decrease at the gate of
M2 of value – gm1ro1 vin , which is propagated at the gate of M4 since the floating capacitor Cbat
acts as a floating battery (it cannot charge or discharge rapidly). Hence, the VSG of M4 increases
by gm1ro1 vin , increasing the drain current beyond the bias current. At the same time the voltage
drop at the gate of M2 also decreases current in M2 below its bias current, thus also contributing
to increasing the output current. In a similar way, a decrease in the input voltage leads to a current
sunk from the load not bounded by the bias current.

2.3. Small-signal analysis

As mentioned above, the static performance of the class AB SSF of Figure 1(d) is identical to that
of the conventional SSF of Figure 1(c); hence, small-signal device parameters are also the same
for identical device dimensions and bias conditions. The only difference in small-signal operation
is due to the different task of M4 , which is just a current source in the conventional SSF but
that provides additional transconductance gain at the output stage in the class AB SSF. Using
conventional small-signal analysis, the small-signal gain of the class AB SSF results in
Vout 1
Adc = = (5)
Vin gmb1 1
1+ +
gm1 gm1ro1 (gm2 +gm4 )(ro2 ro4 )
and the output resistance is
1
Rout ≈ (6)
(gm1 + gmb1 )(gm2 +gm4 )ro1
Note that the class AB SSF decreases Rout even further as compared with the SSF, thanks to the
additional term gm4 where, as mentioned before,  = Cbat /(Cbat +CG ). The dc gain is also closer
to 1 for the same reason, although if VSB = 0 V the body effect makes this increase unnoticeable.
As for the conventional SSF, the class AB SSF is a two-pole negative feedback loop and proper
design is required to enforce stability. The dominant pole corresponds to the high-impedance
internal node (gate of M2 ) and is
1
fd ≈ (7)
2[(gm1 + gmb1 )ro1 ro2 rB1 ]CG2
where CG2 is the intrinsic capacitance at this node, which is approximately
Cbat CGS4
CG2 ≈ CGS2 +CCb + (8)
Cbat +CGS4
with CCb the bottom-plate to substrate capacitance of Cbat . The non-dominant pole is set by the
output node and is
gm1 + gmb1
f nd ≈   (9)
rB1
2 1+ CL
ro1
where CL is the load capacitance (which includes the parasitic capacitance at the output node).
The open-loop gain of the shunt feedback loop is
(gm2 +gm4 )rB1
Aol = − ro1 +rB1 ≈ −(gm2 +gm4 )rB1 (10)
1+
(gm1 + gmb1 )ro1 (ro2 ro4 )

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 A. J. LOPEZ-MARTIN ET AL.

To enforce stability, f nd should be at least twice the gain-bandwidth product of the loop, i.e.
f nd >2|Aol | f d . From Equations (7)–(10), this leads to
1 gm1 + gmb1
CL <   CG2 (11)
2 rB1
(gm2 +gm4 ) 1+
ro1
Note that for low load capacitances, proper dimensioning of the class AB SSF transistors allows
enforcing stability just like for the FVF [5] and SSF topologies. Note also that if M1 is embodied
in an individual well connected to the source terminal, then gmb1 does not appear in the above
expressions, and the well-to-substrate capacitance of M1 increases the parasitic capacitance at the
output node. Therefore, the maximum value allowed for the load capacitor to achieve Equation
(11) is reduced in this case.
If condition (11) is not met, then a compensation capacitor connected to the gate of M2 can be
used to increase the capacitance at this node. In this case, the value of this compensation capacitor
to meet the stability condition mentioned should be:
  
gm2 +gm4 rB1
Cc >2 1+ CL −CG2 (12)
gm1 + gmb1 ro1
Miller compensation could also be used to reduce the value of Cc required, by connecting it
between the gate and drain of M2 .
If f nd is higher enough than f d , the closed-loop bandwidth is approximately
 
gm2 +gm4 rB1
f −3 dB ≈ |Aol | f d ≈ 1+ (13)
2(Cc +CG2 ) (gm1 + gmb1 )ro1 ro2
In the conventional SSF, the dominant pole is approximately the same, given by Equation (7),
but the term CCb in Equation (8) does not appear. However, the higher transconductance gain of the
output stage in the class AB SSF, which is reflected in the term gm4 in the expressions above, leads
to higher open-loop gain as compared with the SSF. As a consequence the closed-loop bandwidth
of the class AB SSF is slightly larger than that of the conventional SSF, as experimentally evidenced
in Table I. This is also observed in other QFG output stages [10].

2.4. Large-signal analysis

The maximum current that the SSF can deliver to the load is IB1 + IB2 , hence limiting positive SR to
IB1 + IB2
SR+,SSF ≈ (14)
CL

Table I. Measured performance of the voltage followers.

Parameter SF SSF Compensat. SSF Class AB SSF Compensat. class AB SSF
SR+ (V/s) 0.8 1.9 1.3 41 24
SR− (V/s) −23 −130 −114 −135 −119
THD @ 1 Vpp, >−10 >−10 >−10 −57 −57
100 kHz (dB)
Bandwidth 0.7 12 5 13.1 8
(MHz)
Eq. input noise 13 12 12 12 12
@ 1 MHz
√
(nV/ Hz)
Power (W) 33 66 66 66 66
Silicon area 5000 7200 9200 8700 10700
(m2 )

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 POWER-EFFICIENT ANALOG DESIGN

evidencing a tradeoff between SR+ and static power dissipation. The class AB SSF of Figure 1(d)
overcomes this drawback. An analytical demonstration based on the approximate MOS square law
follows. In static conditions, current in M4 is I4 = IB1 + IB2 and

Q 2(IB1 + IB2 )
VSG4 = VSG4 = +|VTH4 | (15)
4

where 4 = n Cox (W/L)M4 is the transconductance gain factor of M4 and the superscript Q
indicates quiescent value. Now assume that a large positive input step Vstep is applied to the
input. Then M1 enters cutoff and voltage at the gate of M2 becomes VSS . This sets M2 also
Q
in cutoff and decreases voltage at the gate of M4 by (VG2 +|VSS |), leading to an output
current:

4 Q Q
Iout ≈ I4 = (V +VG2 +|VSS |−|VTH4 |)2
2 SG4
  2
4 2(IB1 + IB2 ) 2IB2
= + + VTH2 (16)
2 4 2

which becomes larger than IB1 + IB2 . This leads to an SR+ increase versus the SSF of

  2
SR+,AB SSF IMAX,AB 4 2(IB1 + IB2 ) 2IB2
= ≈ + + VTH2
SR+,SSF IMAX,A 2(IB1 + IB2 ) 4 2
   2
4 2IB2
≈ 1+ + VTH2 (17)
2(IB1 + IB2 ) 2

In practice SR may be limited to lower values due to the need to drive the gate of M2 fast enough,
particularly if a compensation capacitor is connected to this gate.
Class AB circuits allow saving quiescent power without degrading dynamic performance, by
boosting the output current when required. This increase is quantitatively reflected in the SR increase
factor in Equation (17). However, not all class AB topologies are power-efficient. Power efficiency
not only implies low static power consumption, but also that most of the power taken from the
supplies in dynamic conditions is actually reaching the load. This latter aspect is quantified by a
factor named current utilization [11] or current efficiency (CE) and is defined as the ratio of the
load current to the supply current, i.e. CE = Iout /Isupply . This parameter is essential for optimum
power management. CE for the class AB SSF is approximately given by

|Iout | 1
CE = = (18)
|Iout |+ IB1 + IB2 IB1 + IB2
1+
|Iout |

Since under dynamic conditions |Iout |  IB1 + IB2 also for Vin >0 V as shown in Equation (16),
current efficiency approaches the ideal value of 1. This high CE is because in the class AB SSF, the
large dynamic currents are generated directly in the output transistors, without internal replication.
This is in contrast to other class AB topologies where internal replication of the large dynamic
currents generated drops CE below 0.5 [11].
Besides current efficiency, other quality factors can be used to characterize the operation of
the class AB SSF. Three interesting ones are defined in [12, 13], named Q C , Q B and Q D . They
represent by a single number the efficiency in terms of quiescent current consumption, bandwidth–
power tradeoff and linearity–power tradeoff, respectively. The corresponding values for the class

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 A. J. LOPEZ-MARTIN ET AL.

AB SSF are

IB1 1
QC = = (19a)
IB1 + IB2 1+ IB2 /IB2

1 IB2 1
QB =  +  (19b)
4 IB1 + IB2 2
1+ 1+
2 4

4 gm4 − gm2 IB1 + IB2

QD ≈ (19c)
3 gm4 + gm2 |Iout,MAX |

Factors Q C and Q D should be as low as possible, while Q B should be as high as possible. Note
that, as expected, reducing IB1 versus IB2 increases bias efficiency as the current used to bias M1
is minimized; hence, most of the bias current is used in the output transistors. This also increases
Q B . Besides, attenuation  should be as close to 1 as possible to improve both Q B and Q D .

2.5. Second-order effects and noise analysis

Geometric and parametric mismatches, as well as temperature and supply voltage variations may
occur in practice and robust design must consider them. As mentioned above, the class AB SSF
allows well-controlled quiescent currents regardless of supply or temperature variations. This is
because quiescent currents are set by current mirroring; hence, provided that IB1 and IB2 are
independent of these variations, quiescent currents are too. However, mismatch in transistors M3
and M4 or in the transistors implementing the current sources modifies the quiescent currents;
hence, proper layout techniques are required to minimize it. Note however that the situation is
exactly the same as for the conventional SSF, and the class AB version does not make this cell
more sensitive to mismatch, process, or temperature variations. Variations in the value of Rlarge or
Cbat due to process or temperature changes do not affect static performance; they just modify the
cutoff frequency in Equations (3) and (4), which is not relevant as long as the resulting frequency
remains below the minimum frequency component of the signal.
However, dynamic operation is affected by absolute process variations, as reflected by the
expression of the maximum output current in Equation (16) which is dependent on the transcon-
ductance factor and threshold voltage. As a result, SR+ is slightly process dependent. This fact is
not critical since the exact maximum output current obtained is not very important provided that it
is high enough to achieve a given settling performance. Nevertheless, process tolerances must be
considered at the design stage in order to reach specifications within reasonable safety margins.
The body or bulk effect is another issue that deserves consideration. It is due to the influence
of the bulk voltage on the MOSFET inversion layer, and is usually modeled as an increase in the
absolute value of the threshold voltage VTH given by

VTH = VTH0 +[ F + VSB − F ] (20)

where all the terms have the usual meaning [14]. This variation is also reflected in an additional
small-signal transconductance term given by gmbvsb . If source and bulk terminals are connected,
this effect is not present. Hence in the class AB SSF, only M1 may experience this effect, if it is
not embodied in an individual well connected to the source terminal. The influence in the small-
signal performance is reflected in the gmb1 term in Section 2.3. In large-signal operation, it makes
the dc level shift between input and output terminals dependent on the input signal, degrading
linearity. These problems are overcome as mentioned by using an individual n-well for M1 , but in
this case the additional source-to-substrate nonlinear capacitance increases parasitic capacitance
at the output node and distortion, and should be considered when compensation is designed, as
mentioned in Section 2.3.

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 POWER-EFFICIENT ANALOG DESIGN

Concerning noise, the main sources in CMOS analog circuits are thermal and Flicker noise.
Considering thermal noise and assuming as usual that noise sources are uncorrelated, the approx-
imate expression for the equivalent input noise density of the class AB SSF is

8 1 1 gm4 gmB1
vN,in ( f ) ≈ kB T
2 + + + 2 (21)
3 gm1 gm2 gm1 2 (r r )2
B1 o1 [gm1 (gm2 +gm4 )(rB1 ro1 )]2 gm1

where kB is the Boltzmann constant and T the absolute temperature. Parameters gmB1 and rB1
are the transconductance and output resistance, respectively, of current source IB1 . The equivalent
input noise is dominated by the thermal noise of the input transistor and the current source IB1 .
Both noise contributions are reduced by increasing gm1.
Concerning Flicker noise and assuming again uncorrelated noise sources, the equivalent input
noise density becomes

1 K1 1 K2 1+ IB2 /IB1 K4 L 1
vN,in
2 (f)≈ + 2 +
Cox f W1 L 1 gm1(rB1 ro1 ) W2 L 2 (gm2 +gm4 ) (rB1 ro1 ) W1 L 24
2 2 2


n K B1 L 1
+ (22)
 p W1 L 2B1

where the constant K i is dependent on transistor Mi and can vary widely for different devices in
the same process. Cox is the capacitance per unit area, Wi and L i the width and length, respectively,
of transistor Mi , while n and  p are the mobility of electrons and holes, respectively. As for
the thermal noise, the main noise contribution is due to M1 and the transistor (with aspect ratio
WB1 /L B1 ) implementing current source IB1 . For L 1 = L B1 , and noting that n > p and K B1 >K 1
(as NMOS transistors usually have larger Flicker noise than PMOS transistors), Flicker noise
is dominated by IB1 . Taking L B1 longer greatly reduces the input-referred Flicker noise, but it
increases the minimum voltage required in IB1 to operate in saturation. Besides, taking W1 larger
decreases both the input-referred Flicker noise and the thermal noise, as shown in Equations (21)
and (22), and from Equation (9) it also increases the frequency of the non-dominant pole.
For the conventional class A SSF, the equivalent input noise is similar to Equations (21) and
(22) but the term gm4 disappears and there is an additional term due to the noise of M3 . However,
both modifications do not influence the dominant noise terms in Equations (21) and (22) given by
the input transistor and IB1 ; hence, the input noise density is essentially the same for the class A
and class AB SSF, as experimentally verified below. This is in contrast with other techniques to
achieve class AB operation, which require additional circuitry that may increase noise level. The
analysis made to obtain Equations (21) and (22) is presented in Appendix A.

2.6. Measurement results

The SF of Figure 1(a), the SSF of Figure 1(c) and the class AB SSF of Figure 1(d) were fabricated
in a 0.5-m CMOS n-well process with nominal NMOS and PMOS threshold voltages of 0.67
and −0.96 V, respectively. Capacitor Cbat was a poly-poly capacitor of 1 pF. High-swing cascode
current sources were employed. Transistor dimensions W/L (in m/m) were 0.6 72
(M1 ), 60
1 (M2 )
and 1 (M3 , M4 ). Resistance Rlarge is implemented by a diode-connected PMOS transistor of
200

W/L = 1.5/1. The supply voltages employed for all the measurements were VDD = 1.65 V and
VSS = −1.65 V. The bias currents were IB1 = IB2 = 10 A. To clearly highlight the class AB driving
capability of the proposed circuit, a large load capacitance is employed. It includes the pad, board
and test probe capacitance, and its estimated value is CL ≈ 50 pF. The silicon area employed is
5000 m2 for the SF, 7200 m2 for the SSF and 8700 m2 for the class AB SSF (i.e. a 20% increase
versus the class A version).
Figure 3(a) shows the measured response of the three followers to a 1 MHz periodic input
square waveform with peak-to-peak amplitude of 1.8 V and dc level of −0.6 V. Note the limited
positive SR of the class A SF and SSF, which makes them unable to track the input voltage. The

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 A. J. LOPEZ-MARTIN ET AL.

1.5
Class AB
super follower
1

Class A
0.5 super follower

Voltage (V)
0

Class A
-0.5 source
follower

-1
Input

-1.5
0 0.5 1 1.5 2
(a) Time (us)
1.5
Class AB
super follower
1

Class A
0.5 super follower
Voltage (V)

Class A
-0.5 source
follower

-1
Input

-1.5
0 0.5 1 1.5 2
(b) Time (us)

Figure 3. Measured response to an input square waveform: (a) uncompensated followers

and (b) compensated followers.

proposed class AB SSF (output in solid line) features a much larger positive SR not limited by
the bias current. From Equation (18), the measured maximum current efficiency charging the load
capacitor of the class AB SSF is approximately 0.99, whereas the theoretical one for the SSF is
only 0.5. Note however that settling performance is degraded due to the large load capacitance
value. Another version of the class A SSF and class AB SSF was fabricated in the same chip, using
a Miller compensation capacitor of 1.8 pF between the gate of M2 and the output node to split the
dominant and non-dominant poles. Also a nulling resistor of 20 k was included in series with the
compensation capacitor. Figure 3(b) shows the measured transient response of the compensated
SSFs, for the same input waveform as before. It can be seen that ringing in the class AB super
follower is reduced at the expense of a decrease in SR, which evidences that SR is limited by the
ability to drive the compensation capacitor in this case. Current efficiency also slightly decreases
to 0.98. Note from Equation (11) that for small capacitive loads, like those normally employed
on-chip, compensation is not required.
Table I summarizes the main measured performance parameters of the three voltage followers.
Note that the proposed class AB SSF shows an increase factor in SR+ of 21.5 for the uncompensated
version and of 18.5 for the compensated version as compared with the conventional class A SSF.
Note also that total harmonic distortion (THD) of the class AB SSF is −57 dB for an input voltage

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 POWER-EFFICIENT ANALOG DESIGN

Table II. Theoretical, simulated and measured performance of the class AB SSF.
Parameter Measured Simulated Theoretical
Gain ≈ 0.99 0.985 0.99998
Rout () — 11 7.7
SR+ (V/s) 41 36 45
THD @ 1 Vpp, 100 kHz (dB) −57 −66 —
Bandwidth (MHz) √ 13.1 13.3 14.2
Eq. input noise @ 1 MHz (nV/ Hz) 12 11 9.8

MRlage

2x
VB MRlage 2x
M3 M4 M4
M3C M4C
M4C
VCP
IB Vout+ Vout- IB

Cc M2C VCN Cc M1 Vin-

Vin+ M1 Cbat Cbat
Rc Rc
M2C
M2
M2 IB
IB IB
M5C M5C
M6C
M5C
M6 M5
M5 M5

Figure 4. Class AB differential SSF.

Table III. Main measured performance parameters of the buffer of Figure 4.

Parameter Value
Technology 0.5- m CMOS
Supply voltages ±1.65 V
Bias current IB 10 A
THD @ 100 Hz, 1 Vpp −69 dB
Bandwidth 8 MHz
√
Equivalent input noise @ 3 MHz 28 nV/ Hz
CMRR @ 100 kHz 62 dB
Quiescent power consumption 132 W
Silicon area 0.02 mm2

of 1 Vpp . The dominant distortion term is the second-order one, which can be notably reduced
using a differential configuration as will be seen below. For this load and input voltage, the class A
SF and SSF have THD values worse than −10 dB as they are unable to track the input waveform
due to positive SR limitation, leading to a strongly distorted output waveform.
Table II allows comparison between the theoretical results obtained in this section and simulation
and measurement results. It can be seen that despite the use of simple first-order models for the
transistors, the theoretical analysis presented here is reasonably accurate.

3. SOME APPLICATIONS OF THE CLASS AB SSF

In this section different applications of the class AB SSF are described, which illustrates the
versatility of this cell. All the circuits described have been fabricated in the same technology cited
above, and measurement results are provided along with the description of the circuits.

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DOI: 10.1002/cta
 A. J. LOPEZ-MARTIN ET AL.

(a)

(b)

(c)

Figure 5. Class AB current mirror: (a) basic idea; (b) detailed schematic of a differential version; and
(c) microphotograph of the differential current mirror.

3.1. Differential unity-gain buffer

A disadvantage of the class AB SSF of Figure 1(d) is the high second-order distortion term, which
limits linearity as shown in Section 2. Another drawback is the input–output dc level shift equal
to the VSG of transistor M1 , which is process and technology dependent. Both shortcomings can
be alleviated with a differential arrangement. The differential class AB SSF is shown in Figure 4.
Compensation was required as the follower has been designed to drive large off-chip capacitive
loads. Transistor dimensions and capacitor values are the same as for the single-ended version.
Cascode transistors M2C and M4C were included to increase the loop gain and to improve accuracy
of the quiescent currents, respectively. The total area of the circuit is 0.02 mm2 . Table III shows the
main performance parameters, which were obtained using the same supply, load and bias currents
as for the single-ended buffers.

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DOI: 10.1002/cta
 POWER-EFFICIENT ANALOG DESIGN

(a)

(b)

Figure 6. (a) Class AB transconductor and (b) microphotograph.

3.2. Class AB current mirror

Class AB current-mode circuits are well suited to process signals in a wide dynamic range under
low-supply-voltage and low-power constraints [15, 16]. A class AB current mirror with very low
input resistance can be easily obtained from the class AB SSF. The idea is shown in Figure 5(a). In
this case the input current is sensed by the class AB SSF, and copied to a high-impedance output
terminal by replicating transistors M2 and M4 . Input voltage is set by the dc voltage Vbias and bias
current IB1 , and is given by

2IB1
Vin = Vbias + VSG1 = Vbias +|VTH1 |+ (23)
1

The dc level shift VSG1 is temperature and process dependent, resulting in an inaccurate setting
of the input voltage. Usually it is not important in most applications, where the sensing node
does not require a very precise dc value. If this is not the case, a diode-connected transistor

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DOI: 10.1002/cta
 A. J. LOPEZ-MARTIN ET AL.

-35
--x-- HD2
-40
--+-- HD3

Harmonic Distortion (dB)

-45
--o-- THD

-50

-55

-60

-65

-70
0 0.5 1 1.5 2 2.5
Vin (V)

Figure 7. Measured harmonic distortion vs input voltage at 100 kHz.

matched with M1 can be employed [17] to compensate it, or a fully differential version can be
employed.
The input resistance corresponds to Equation (6). Owing to the use of the QFG technique, the
input and output currents can be much larger than the quiescent currents, which are accurately
set to IB2 in the input and output branches. Note that a class AB current amplifier with gain
K can also be obtained by choosing the W/L of M2M and M4M K times larger than that of
M2 and M4 .
In practice, the current mirror transistors of Figure 5(a) should be cascoded to improve the
accuracy of the current copy and to increase output resistance. This is shown in Figure 5(b), where
a fully differential version of the class AB current mirror is presented. In this case IB1 = IB2 = IB .
The microphotograph of the current mirror of Figure 5(b) is shown in Figure 5(c). The output
is directly connected to bonding pads. Measurements were carried out for a supply voltage of
±1.65 V and bias currents IB1 = IB2 = 10 A. A THD of −62 dB is measured for an input current
of 100 kHz and 200 App , i.e. 20 times larger than the bias current, reflecting the proper class
AB operation. Power consumption of the differential class AB current mirror is 264 W, and the
silicon area employed is 0.035 mm2 .
Thanks to the extremely low input resistance that performs as a signal ground at the input of the
current mirror, it can be used for precise class AB voltage-to-current conversion. It just requires
connecting a terminal of a passive resistor R to the current mirror input node and applying the
input voltage to the other terminal of the resistor. If the single-ended current mirror of Figure 5(a)
is used, the output current is Iout = (Vin − VSG1 − Vbias )/R. Owing to the temperature and process
dependence of VSG1 , either this dc level shift should be compensated [17] or a differential topology
should be used, where the term VSG1 is cancelled out in the differential output, i.e. Ioutd = Vid /R.
As before, cascode current mirrors should be used in practice. Applying various input voltages
through different passive resistors connected to the input node of the current mirror, a multiple-
input class AB V-I conversion is obtained where the transconductance for each input can be chosen
independently, yielding a precision summing circuit with independently weighted inputs.

3.3. Class AB transconductor

Class AB transconductors are required to achieve low quiescent power consumption in Gm-C
filters without degrading dynamic performance. A CMOS class AB transconductor based on the
class AB SSF is shown in Figure 6(a). It employs the differential follower of Figure 4 which is
used to translate the differential input voltage from the high-impedance input to the low impedance
follower output terminals where a passive resistor 2R is connected, thus performing V-I conversion.

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 POWER-EFFICIENT ANALOG DESIGN

Figure 8. Measured output amplitude spectrum for an input tone at 1 MHz.

The resistor current is translated to a high-impedance output node by mirroring the current in the
output branch of the differential buffer. The differential output current is Ioutd = 2IR = Vid /R. The
use of a passive resistor and the accuracy of the voltage follower due to the high-gain SSF feedback
loop provide high linearity. Besides, the class AB operation of the buffer allows using low quiescent
currents IB without constraining the maximum output current. The passive resistor is split into two
resistors to sense in their common terminal the common-mode voltage of the driving stage, which
can be used to simplify the design of the common-mode feedback circuit of such a driving stage
[18].
A microphotograph of the transconductor is shown in Figure 6(b). Poly-poly capacitor Cbat
was of 1 pF. Resistors R were implemented with high-resistance polysilicon and had a value of
3.75 k. Transistor dimensions W/L (in m/m) were 100 1 (M1 , M5C , M5CM ), 1 (M2 , M2M ),
60

0.6 (M2C , M2CM ), 0.6 (M3 , M4 , M4M , M6 ), 0.6 (M3C , M4C , M4CM , M6C ) and 3 (M5 , M5M ). The
60 100 200 100

silicon area employed is 0.05 mm2 .

Figure 7 shows the harmonic distortion measured for a differential input sinusoid of 100 kHz
and different amplitudes. Supply voltage was ±1.65 V, and the bias current was IB = 50 A.
Harmonic distortion is dominated by the third-order harmonic, as expected in a fully differential
transconductor. For peak-to-peak differential input voltages larger than 4R IB = 4·50 A·3.75 k=
0.7 V, the output currents are larger than the bias current IB . Note that beyond this point in
Figure 7, linearity is not degraded abruptly, confirming the class AB operation of the circuit.
For instance, THD <−55 dB is measured for an input of 1.2 Vpp (36% of the supply voltage),
which corresponds to output currents 60% larger than IB . If for this input IB is reduced to 10 A,
measurements show a THD still low (−49 dB), and in this case the output current is 800% larger
than IB . Figure 8 shows the magnitude spectrum of the output for an input of 1 Vpp and 1 MHz,
showing a THD = −59.47 dB. Figure 9 shows the measured spectrum when a two-tone input of
950 and 1050 kHz and 1 Vpp is applied, yielding an IM3 = −56.61 dB. When the input tones are
decreased to 0.5 Vpp , an IM3 = −68.55 dB is measured. Table IV summarizes the main performance
parameters of the transconductor.

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DOI: 10.1002/cta
 A. J. LOPEZ-MARTIN ET AL.

Figure 9. Measured output amplitude spectrum for two input tones at 950 and 1050 kHz.

Table IV. Main measured performance parameters of the

transconductor of Figure 6.
Parameter Value
Technology 0.5-m CMOS
Supply voltages ±1.65 V
Bias current IB 10 A
IM3 @ 1 MHz, 1 Vpp −56.61√dB
Equivalent input noise @ 3 MHz 39 nV/ Hz
CMRR @ 100 kHz 60 dB
Quiescent power consumption 230 W
Silicon area 0.05 mm2

3.4. Rail-to-rail tunable class AB transconductor

The class AB transconductor of Figure 6 has two main drawbacks. First, transconductance cannot
be adjusted, which is often required in Gm-C filters to compensate for process tolerances in the
value of the RC time constants. Besides input is not rail-to-rail, limiting input signal swing. Both
shortcomings are solved in the configuration of Figure 10. To achieve a rail-to-rail input swing,
two-input floating-gate MOS transistors [19] are employed at the input of the transconductor. This
way the gate of M1 is capacitively coupled to the input voltage by a capacitor C1 and to VSS by
another capacitor C2 . Assuming that the intrinsic capacitance at the gate terminal is much smaller
than C1 +C2 , the differential voltage at the input gates becomes:
C1 C2
VGd = Vid + VSS (24)
C1 +C2 C1 +C2

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DOI: 10.1002/cta
 POWER-EFFICIENT ANALOG DESIGN

(a)

(b)

Figure 10. (a) Rail-to-rail tunable class AB transconductor and (b) microphotograph.

yielding a gate voltage, which corresponds to the input voltage attenuated by a factor k = C1/(C1 +
C2 ) and level shifted by a dc voltage VSS C2 /(C1 +C2 ). By properly choosing C1 and C2 , a rail-
to-rail input swing can be adjusted to the voltage headroom available at the gate of M1 . Input
attenuation not only improves linearity, but it also increases the equivalent input noise voltage by
a factor 1/k.
Continuous tuning is obtained by using an MOS transistor MR in ohmic region as resistive
element for V-I conversion. To improve linearity, QFG techniques are also employed [20]. The
dc voltage VBias that sets the transconductance value is applied using a large resistive element
connected to the gate, so that the voltage at the gate of MR can freely swing in ac. Two capacitors
Cbat are connected between the drain and source terminals of MR and the gate terminal, leading
to an ac signal at the gate of MR equal to the mean of the ac drain and source voltages, which
allows linearizing the V-I conversion as analyzed in [20].

Copyright 䉷 2011 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. (2011)
DOI: 10.1002/cta
 A. J. LOPEZ-MARTIN ET AL.

100

50

Iout (uA)
0

-50

-100
-3 -2 -1 0 1 2 3
(a) Vid (V)

Transconductance (uA/V)
100

50

0
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
(b) Vid (V)

Figure 11. Measured dc transfer characteristics for VBias = 3.5, 4 4.5 and 5 V: (a) output
current and (b) transconductance.

Note that in this transconductor the way M1 is biased in the class AB SSF is slightly different.
Instead of using a PMOS current source at the source of M1 , as in the former topologies, in this
case the current IB that flows through M1 is directly taken from the PMOS transistor M4 that
adaptively biases the output stage. This way M4 has twice the W/L of the former class AB SSF,
increasing dynamic current boosting. As current in M4 is mirrored in M4M , and this current has
the term IB required to bias M1 , current IB must be subtracted from the output branch of the
transconductor, as shown in Figure 10(a).
To allow for a wide tuning range of the triode transistor in the technology employed, which
features large threshold voltages, a single supply voltage of 5 V was employed to test the fabri-
cated transconductor of Figure 10. Transistor and capacitor dimensions are the same as in the
transconductor of Figure 6. Aspect ratio of transistor MR is 31 , and poly-poly input capacitors were
C1 = 1 pF and C2 = 2 pF.
Figure 11 shows the measured dc transfer characteristics for different values of the tuning
voltage VBias , which were measured using a very low-frequency periodic input ramp. Note the
high linearity obtained for rail-to-rail input voltages. The measured output spectrum for two input
tones of 950 and 1050 kHz and 2 Vpp is shown in Figure 12, showing an IM3 of −52.13 dB.
When the input amplitude decreases to 0.5 Vpp , IM3 is −74.66 dB. Table V summarizes the main
performance parameters of the transconductor.

4. CONCLUSION

A class AB version of the widely employed SSF has been presented, which improves dynamic
performance without altering static operation, hence preserving accurately set quiescent currents.
Besides it does not require extra supply voltage or power consumption, and does not degrade other
performance parameters like noise or bandwidth. It just demands a modest increase in silicon
area. The cell can find widespread use in analog design, advantageously replacing the conventional
SSF in virtually any circuit proposed to date providing improved dynamic operation without
altering static operation. To illustrate this versatility, several circuit applications have been explored
including class AB voltage buffers, current mirrors, current amplifiers, V-I converters, weighted
addition circuits and transconductors. The ability of QFG circuits to reject dc offset and extremely
low-frequency signals (<1 Hz) in a simple and compact way can be applied e.g. for baseline

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DOI: 10.1002/cta
 POWER-EFFICIENT ANALOG DESIGN

Figure 12. Measured output amplitude spectrum for two input tones at 950 and 1050 kHz and 2 Vpp.

Table V. Main measured performance parameters of the

transconductor of Figure 10.
Parameter Value
Technology 0.5-m CMOS
Supply voltages 5V
Bias current IB 50 A
IM3 @1 MHz, 2 Vpp −52.13√dB
Equivalent input noise @1 MHz 98 nV/ Hz
CMRR @ 100 kHz 56 dB
Quiescent power consumption 2.2 mW
Silicon area 0.07 mm2

stabilization in biological signals sensed by electrodes (EEG, ECG, EMG, evoked potentials) [21]
and for dc offset removal in the baseband section of direct conversion receivers [22].

APPENDIX A: NOISE ANALYSIS OF THE CLASS AB SSF

The noise analysis that results in Equations (21) and (22) is presented here. The analysis method
followed is described in [23]. The thermal noise generated by an MOS transistor in saturation can
be modeled as a noise current source connected between drain and source, with spectral density

i n2 ( f ) = 4kB T gm (A1)

where  = 23 for transistors without very short channel, which is assumed for the 0.5 m technology
employed. Note that thermal noise is modeled as white noise. Alternatively, at low to medium

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DOI: 10.1002/cta
 A. J. LOPEZ-MARTIN ET AL.

frequencies thermal noise can be modeled instead as a voltage source at the gate of the transistor
with spectral density:

i n2 ( f ) 4kB T  8kB T
vn2 ( f ) = 2
= = (A2)
gm gm 3gm
To obtain the influence of the thermal noise of each transistor in the class AB SSF, a noise
voltage source is placed at its gate with spectral density (A2) and this value is multiplied by
the squared small-signal voltage transfer function from this gate to the output, yielding the noise
spectral density at the output due to this transistor. Since all noise sources are uncorrelated, the
output noise is the addition of all the individual noise contributions. This noise density can be
referred to the input by dividing it by the square of the voltage gain, which is approximately 1 for
a voltage follower. Hence, following this procedure, the input noise spectral density is
 2  2
1 gm4
vN,in
2 ( f ) ≈ v 2 ( f )+ vn,2
2 ( f )+ vn,4
2 (f)
n,1 gm1(rB1 ro1 ) gm1 (gm2 +gm4)(rB1 ro1 )
 2
gmB1
+ vn,B1
2 (f) (A3)
gm1

where vn,i
2 ( f ) is the noise density of transistor M , and current source I
i B1 is implemented by a
single transistor MB1 . Using Equation (A2) for the noise density of each transistor in Equation
(A3), expression (21) results.
Flicker noise of an MOS transistor Mi is also modeled by a voltage source at the gate, but in
this case with a spectral density that decreases with 1/ f :
Ki
vn,i
2 ( f )= (A4)
Wi L i Cox f
where all parameters were defined in Section 2.5. Hence, using Equation (A4) in Equation (A3)
the input-referred Flicker noise density results in:
 2  2
1 K1 1 K2 gm4 K4
vN,in
2 (f)≈ + +
Cox f W1 L 1 gm1 (rB1 ro1 ) W2 L 2 gm1 (gm2 +gm4)(rB1 ro1 ) W4 L 4
  
gmB1 2 K B1
+ (A5)
gm1 WB1 L B1

Now using the expression for the transconductance of transistor Mi ,

  
W
gm,i = 2Cox ID,i (A6)
L i

expression (22) results.

ACKNOWLEDGEMENTS
The work is supported by Spanish Ministerio de Ciencia e Innovación and FEDER under grants TEC2007-
67460-C03 and TEC2010-21563-C02.

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DOI: 10.1002/cta