SRFF

module SRFF(s,r,clk, q,qb);

input s,r,clk;

output q,qb;

reg [1:0] sr;

reg q,qb;

always @(posedge clk)

begin

sr={s,r};

case(sr)

2'b00:q=q;

2'b01:q=1'b0;

2'b10:q=1'b1;

2'b11:q=1'bx;

endcase

qb=~q;

end

endmodule

JK

module jk(j,k,clk, q,qb);

input j,k,clk;

output q,qb;

reg[1:0] jk;

reg q=0,qb=1;

always@(posedge clk)

begin

jk={j,k};

case (jk)

2'b00:q=q;

2'b01:q=1'b0;
2'b10:q=1'b1;

2'b11:q=~q;

endcase

qb=~q;

end

endmodule

DFF

module D(d,clk, q,qb);

input d,clk;

output q,qb;

reg q,qb;

always@(posedge clk)

begin

q=d;

qb=~d;

end

endmodule

alu

module ALU(a,b, y, en, sel);

input [31:0] a,b;

output [31:0] y;

input en;

input [2:0] sel;

reg[31:0] y;

always@(a,b,sel,en)

begin

if(en==1)

begin

case(sel)
 3'b000:y=a+b;

3'b001:y=a-b;

3'b010:y=a-1;

3'b011:y=a+1;

3'b100:y=~a;

3'b101:y=a&b;

3'b110:y=a|b;

3'b111:y=a^b;

default: y=32'b0;

endcase

end

else

y=32'bzz;

end

endmodule

Asynch UP/Down Conv

module Asyn(clk,rst, c);

input clk,rst;

output [3:0] c;

reg[3:0] c=4'b0000;

always@(posedge clk)

begin

if(rst==0)

c=c+1;

else

c=c-1;

end

endmodule
Parallel Adder

module fa(a,b,cin,sum,cout);

input a,b,cin;

output sum;

output cout;

assign sum=(a^b)^cin;

assign cout=((a&b)|(b&cin)|(cin&a));

endmodule

module parallel(a,b, cin, s, cout);

input [3:0] a,b;

input cin;

output [3:0] s;

output cout;

wire [2:0]c;

fa f1(a[0],b[0],cin,s[0],c[0]);

fa f2(a[1],b[1],c[0],s[1],c[1]);

fa f3(a[2],b[2],c[1],s[2],c[2]);

fa f4(a[3],b[3],c[2],s[3],cout);

endmodule