CECARRYIN

BCIN[17..0] CARRYIN_reg_out~0
0
CARRYIN
5 1

CARRYOUTF
RSTCARRYIN CARRYOUT
CARRYIN_reg_out~1 CARRYIN_reg_out CARRYOUT~0
0 0 CARRYOUT~1 CARRYOUT~reg0
0
1'h0 1 D 1
1'h0 1 D
CLK Q
1'h0 CLK Q
SCLR 1'h0
SCLR
CEP
Equal5
3:2 A[1..0]
OUT multiplixer_z_out~[47..0]
2'h2 B[1..0] = 0 P~[47..0]
0
1
1

Equal4 multiplixer_z_out~[95..48]
3:2 A[1..0] 0
OUT
2'h1 B[1..0] = 1 1'h0 CIN Add4 P~[95..48]

48{7}
0
A[48..0] OUT[48..0] post_adder_out[47..0]
PCIN[47..0] + 48:1 0 48'h0 1
47:0

B[48..0]
RSTP 47:0 1
CEC
PCOUT[47..0]
C_stg1~[47..0] Equal0
0 1:0 A[1..0] 1'h0 CIN Add2 1'h0 CIN Add3 P[0]~reg[47..0] P[47..0]

7
47:0

OUT
1 2'h0 B[1..0] = A[48..0] OUT[48..0] A[48..0] OUT[48..0] carryout
C[47..0] + + 49 0 D
C_stg1[47..0] multiplixer_x_out[47..0] B[48..0] B[48..0]
0 48 1 CLK Q
C_stg1~[95..48]
47:0

48'h0
0 D 48'h0 1 SCLR

RSTC 48'h0 1 CLK Q

48'h0 47:0 1'h0 CIN Add5
SCLR
Equal3 48:0 A[49..0] OUT[49..0]
3:2 A[1..0] +
OUT B[49..0]
2'h0 B[1..0] =
RSTA multiplixer_z_out[47..0]
0
A[17..0]
48'h0 1
D_stg1[17..0] Equal1
1:0 A[1..0]
OUT
D 2'h1 B[1..0] = A_stg2[17..0]
CLK Q multiplixer_x_out~[95..48]
18'h0 0 A_stg2~[35..18] D
SCLR 0
1 CLK Q
18'h0 1 18'h0
0:35

SCLR
multiplixer_x_out~[47..0]
0:17
0:11

Equal2
1:0 A[1..0] 0
OUT
0:17

2'h2 B[1..0] = 1
Mult0
B[17..0] A[17..0]
OUT[35..0]
18{6}

CEA B[17..0] x
A_stg2~[17..0] 1'h0 CIN Add0 pre_adder_out[17..0]
CED 0 0
A[17..0] OUT[17..0]
D_stg1~[17..0] 1 + 1
0 B[17..0] M[35..0]
D_stg1~[35..18]

18{4}
1 0 pre_adder_mux_out[17..0] M[0]~reg[35..0]
D[17..0] 0
18'h0 1
1 M~[35..0] D
1'h0 CIN Add1 0 M~[71..36]
17:0

RSTD 0 CLK Q
A[18..0] OUT[18..0] 1 36'h0
17:0

+ 36'h0 1 SCLR
B[18..0]
CEB
CLK B_stg2[17..0]
OPMODE_stg1[7..0]
CEOPMODE B_stg2~[17..0]
0 B_stg2~[35..18] D
OPMODE_stg1~[7..0] D 0
0 1 CLK Q BCOUT[17..0]
CLK Q 18'h0 1 18'h0
1 8'h0 SCLR
OPMODE[7..0] SCLR

RSTB

CEM
RSTOPMODE
OPMODE_stg1~[15..8]
0
8'h0 1

RSTM