PULSE AND DIGITAL

CIRCUITS
SECOND EDITION

A. ANAND KUMAR
Principal

College of Engineering

K.L. University

Green Fields, Vaddeswaram

Guntur District, Andhra Pradesh

New Delhi-110092
2014
PULSE AND DIGITAL CIRCUITS, Second Edition

A. Anand Kumar

© 2008 by PHI Learning Private Limited, Delhi. All rights reserved. No part of this book may be

reproduced in any form, by mimeograph or any other means, without permission in writing from the

publisher.

ISBN-978-81-203-3356-7

The export rights of this book are vested solely with the publisher.

Seventeenth Printing (Second

Edition).....................…....................…...................….....................January, 2014

Published by Asoke K. Ghosh, PHI Learning Private Limited, Rimjhim House, 111, Patparganj

Industrial Estate, Delhi-110092 and Printed by Jay Print Pack Private Limited, New Delhi-110015.
 To the memory of
my parents
Shri A. Nagabhushanam and Smt. A. Ushamani
(Freedom Fighters)
 Contents

Preface.........xi
Symbols, Notation and Abbreviations.........xv
1. LINEAR WAVE SHAPING.........1–103
1.1 The Low-Pass RC Circuit.........1
1.1.1 Sinusoidal Input.........2
1.1.2 Step-Voltage Input.........3
1.1.3 Pulse Input.........5
1.1.4 Square-Wave Input.........7
1.1.5 Ramp Input.........9
1.1.6 Exponential Input.........11
1.2 The Low-Pass RC Circuit as an Integrator.........12
1.3 The High-Pass RC Circuit.........31
1.3.1 Sinusoidal Input.........31
1.3.2 Step Input.........33
1.3.3 Pulse Input.........33
1.3.4 Square-Wave Input.........34
1.3.5 Ramp Input.........38
1.3.6 Exponential Input.........39
1.4 The High-Pass RC Circuit as a Differentiator.........42
1.5 Double Differentiation.........43
1.6 Attenuators.........65
1.6.1 Application of Attenuator as a CRO Probe.........69
1.7 RL Circuits.........76
1.8 RLC Circuits.........77
1.8.1 RLC Series Circuit.........77
1.8.2 RLC Parallel Circuit.........79
1.9 Ringing Circuit.........80
Short Questions and Answers.........81
Review Questions.........88
Fill in the Blanks.........89
Objective Type Questions.........91
Problems.........100
2. NONLINEAR WAVE SHAPING.........104–195
2.1 Clipping Circuits.........104
2.1.1 Diode Clippers.........104
2.1.2 Shunt Clippers.........105
2.1.3 Series Clippers.........108
2.1.4 Clipping at Two Independent Levels.........114
2.1.5 Series and Shunt Noise Clippers.........118
2.1.6 Compensation for Variation of Temperature.........120
2.1.7 Transistor Clippers.........121
2.1.8 Emitter-Coupled Clipper.........124
2.1.9 Comparators.........148
2.2 Clamping Circuits.........150
2.2.1 The Clamping Operation.........150
2.2.2 Negative Clamper.........151
2.2.3 Positive Clamper.........153
2.2.4 Biased Clamping.........154
2.2.5 Clamping Circuit Taking Source and Diode Resistances into Account.........156
2.2.6 Clamping Circuit Theorem.........161
2.2.7 Practical Clamping Circuit.........163
2.2.8 Effect of Diode Characteristics on Clamping Voltage.........165
2.2.9 Synchronized Clamping.........167
2.2.10 Design of a Clamping Circuit.........175
Short Questions and Answers.........181
Review Questions.........185
Fill in the Blanks.........186
Objective Type Questions.........188
Problems.........191
3. SWITCHING CHARACTERISTICS OF DEVICES.........196–222
3.1 Junction Diode—Switching Times.........196
3.2 Piece-Wise Linear Diode Characteristics.........200
3.3 Breakdown in p-n Junction Diodes.........200
3.4 Transistor as a Switch.........202
3.5 Transistor Switching Times.........203
3.6 Breakdown Voltages of a Transistor.........204
3.7 The Transistor Switch in Saturation.........207
3.8 Temperature Sensitivity of Saturation Parameters.........209
3.9 Design of Transistor Switch.........209
Short Questions and Answers.........216
Review Questions.........219
 Fill in the Blanks.........219
Objective Type Questions.........221
4. MULTIVIBRATORS.........223–331
4.1 Bistable Multivibrator.........224
4.2 A Fixed-Bias Bistable Multivibrator.........224
4.3 A Self-Biased Transistor Binary.........240
4.4 Commutating Capacitors.........252
4.5 A Non-Saturating Binary.........253
4.6 Triggering the Binary.........254
4.7 Triggering Unsymmetrically through a Unilateral Device
(Diode).........256
4.8 Triggering Symmetrically through a Unilateral Device.........257
4.9 A Direct-Connected Binary.........259
4.10 The Emitter-Coupled Binary (the Schmitt Trigger Circuit).........260
4.11 Monostable Multivibrator.........279
4.12 The Collector Coupled Monostable Multivibrator.........279
4.13 The Emitter-Coupled Monostable Multivibrator.........295
4.14 Triggering the Monostable Multivibrator.........297
4.15 Astable Multivibrator.........298
4.16 The Collector-Coupled Astable Multivibrator.........298
4.17 The Emitter-Coupled Astable Multivibrator.........312
Short Questions and Answers.........316
Review Questions.........322
Fill in the Blanks.........323
Objective Type Questions.........325
Problems.........330
5. TIME-BASE GENERATORS.........332–388
5.1 General Features of a Time-Base Signal.........332
5.2 Methods of Generating a Time-Base Waveform.........334
5.3 Exponential Sweep Circuit.........335
5.4 Unijunction Transistor.........338
5.5 Sweep Circuit Using UJT.........340
5.6 Sweep Circuit Using a Transistor Switch.........347
5.7 A Transistor Constant-Current Sweep.........348
 5.8 Miller and Bootstrap Time-Base Generators—Basic
Principles.........350
5.9 The Transistor Miller Time-Base Generator.........355
5.10 The Transistor Bootstrap Time-Base Generator.........356
5.11 Current Time-Base Generators.........373
5.12 A Simple Current Sweep.........373
5.13 Linearity Correction Through Adjustment of Driving
Waveform.........374
5.14 A Transistor Current Time-Base Generator.........377
Short Questions and Answers.........380
Review Questions.........383
Fill in the Blanks.........384
Objective Type Questions.........385
Problems.........387
6. SYNCHRONIZATION AND FREQUENCY DIVISION .........389–
406
6.1 Pulse Synchronization of Relaxation Devices.........389
6.2 Frequency Division in the Sweep Circuit.........391
6.3 Other Astable Relaxation Circuits.........392
6.4 Monostable Relaxation Circuits as Dividers.........396
6.5 Phase Delay and Phase Jitters.........398
6.6 Synchronization of a Sweep Circuit with Symmetrical
Signals.........399
6.7 Sine Wave Frequency Division with a Sweep Circuit.........401
Short Questions and Answers.........402
Review Questions.........404
Fill in the Blanks.........404
Objective Type Questions.........405
7. SAMPLING GATES.........407–430
7.1 Basic Operating Principles of Sampling Gates.........407
7.2 Unidirectional Diode Gate.........408
7.3 Unidirectional Diode Gates to Accommodate More than One Input
Signal.........410
7.4 Bidirectional Sampling Gates Using Transistors.........412
 7.5 Reduction of Pedestal in a Gate Circuit.........414
7.6 Bidirectional Diode Sampling Gate.........415
7.7 Four-Diode Sampling Gate.........419
7.8 Four-Diode Gate (Alternative Form).........420
7.9 Six-Diode Sampling Gate.........423
7.10 Applications of Sampling Gates.........424
7.11 Chopper Amplifier.........424
7.12 Sampling Scope.........426
Short Questions and Answers.........427
Review Questions.........429
Fill in the Blanks.........429
Objective Type Questions.........430
8. LOGIC GATES.........431–463
8.1 The Basic Gates.........432
8.1.1 The OR Gate.........432
8.1.2 The AND Gate.........435
8.1.3 The NOT Gate (Inverter).........438
8.2 The Universal Gates.........439
8.2.1 The NAND Gate.........439
8.2.2 The NOR Gate.........443
8.3 The Derived Gates.........446
8.3.1 The Exclusive-OR (X-OR) Gate.........446
8.3.2 The Exclusive-NOR (X-NOR) Gate.........447
8.4 Inhibit Circuits.........448
8.5 Pulsed Operation of Logic Gates.........453
Short Questions and Answers.........456
Review Questions.........459
Fill in the Blanks.........460
Objective Type Questions.........461
Problems.........463
9. LOGIC FAMILIES.........464–494
9.1 Digital IC Specification Terminology.........464
9.2 Logic Families.........465
9.3 Transistor Transistor Logic (TTL).........465
9.3.1 Two-Input TTL NAND Gate (Standard TTL).........466
9.3.2 Totem-Pole Output.........467
 9.3.3 Open-Collector Gates.........468
9.3.4 Tri-State (3-State) TTL.........469
9.3.5 Schottky TTL.........470
9.4 Integrated Injection Logic (IIL or I2L).........470
9.4.1 I2L Inverter.........471
9.4.2 I2L NAND Gate.........471
9.4.3 I2L NOR Gate.........472
9.5 Emitter-Coupled Logic (ECL).........472
9.5.1 ECL OR/NOR Gate.........473
9.6 Metal Oxide Semiconductor (MOS) Logic.........475
9.6.1 Symbols and Switching Action of NMOS and PMOS.........475
9.6.2 Resistor.........476
9.6.3 NMOS Inverter.........476
9.6.4 NMOS NAND Gate.........477
9.6.5 NMOS NOR Gate.........478
9.7 Complementary Metal Oxide Semiconductor (CMOS) Logic.........479
9.7.1 CMOS Inverter.........479
9.7.2 CMOS NAND Gate.........480
9.7.3 CMOS NOR Gate.........481
9.7.4 Transmission Gate.........482
9.8 Dynamic MOS Logic.........483
9.8.1 Dynamic MOS Inverter.........484
9.8.2 Dynamic MOS NAND Gate.........485
9.8.3 Dynamic MOS NOR Gate.........486
Short Questions and Answers.........487
Review Questions.........491
Fill in the Blanks.........492
Objective Type Questions.........493
10. BLOCKING OSCILLATORS .........495–517
10.1 Monostable Blocking Oscillator (Base Timing).........495
10.2 Monostable Blocking Oscillator (Emitter Timing).........499
10.3 Astable Blocking Oscillator (Diode Controlled).........502
10.4 Astable Blocking Oscillator (RC Controlled).........510
10.5 Applications of Blocking Oscillators.........513
Short Questions and Answers.........513
Review Questions.........515
Fill in the Blanks.........516
Objective Type Questions.........517
 Problems.........517
Glossary.........519–526
Answers to Fill in the Blanks.........527–530
Answers to objective Type Questions.........531–532
Answers to Problems.........533–550
Index.........551–554
 Preface
After nearly thirty years of my experience in the classroom, I have strived
to develop this comprehensive text on pulse circuitry in order to provide
students with a solid grounding in the foundations of analysis and design of
pulse and digital circuits. The second edition of this textbook with various
new features is suitable for use as one-semester course material by
undergraduate students of Electronics and Communication Engineering,
Electrical and Electronics Engineering, Electronics and Instrumentation
Engineering, and Telecommunication Engineering. Appropriate for self-
study, the book will also be useful to AMIE and IETE students.
The text is organised in 10 chapters. The outline of the book is as follows.
When non-sinusoidal signals are transmitted through a linear network, the
shape of the waveform undergoes a change. This process, called linear wave
shaping is discussed in Chapter 1. In particular how signals like step, ramp,
exponential, pulse and square wave undergo change of shape when passed
through low-pass and high pass RC circuits is illustrated elaborately. RL
low-pass and high pass circuits, RLC circuits and attenuators are also
discussed in this chapter.
Particularly in communication systems, quite often, it is required to
remove a part of the waveform above or below some reference level. This
process is called clipping. In many pulse systems, quite often a dc level is
required to be added to a waveform to fix the top or bottom of the
waveform at some reference level. This process is called clamping.
Clipping and clamping together is called nonlinear wave shaping. Chapter 2
deals with the various clipping circuits-one level, two level, series, shunt,
transistor and clamping circuits—
Unbiased, biased and synchronised. The analysis and design of clipping and
clamping circuits are illustrated with examples.
The switching characteristics of junction diodes and transistors as
required for a clear understanding of the pulse circuits are covered in
Chapter 3.
 Memory is the basic requirement of all computers. The basic memory
element is a flip-flop, i.e. the bistable multivibrator. The monostable
multivibrator is the basic gating circuit. The astable multivibrator is used as
a master oscillator, and the Schmitt trigger circuit as a basic voltage
comparator. The various types of multivibrators-Bistable (Collector
coupled-Fixed bias type and Self bias type, Emitter coupled type, i.e.
Schmitt trigger), Monostable (Collector coupled, Emitter coupled) and
Astable are discussed in Chapter 4. The analysis and design of all these
multivibrators are also illustrated with examples in this chapter.
Time-base generators are essential for display of signals on the screen.
Time base generators may be voltage time base generators or current time-
base generators. Various methods of generating time base waveforms,
transistor voltage time base generators—Miller type and Bootstrap type and
current time base generators are discussed Chapter 5. The analysis and
design of time base generators are also illustrated with examples.
A large pulse and digital system consists of a number of waveform
generators which need to be synchronized with or without frequency
division. Synchronization and frequency division of various generators with
pulse type as well as symmetrical signals are the topics treated in Chapter 6.
When signals are to be transmitted only for specified intervals of time and
are to be blocked during other intervals of time, we require sampling gates
which may be unidirectional or bidirectional. Unidirectional diode sampling
gates, Bidirectional diode sampling gates, Bidirectional transistor sampling
gates, Two-diode gates, Four-diode gates and Six-diode gates and also
applications of sampling gates are discussed in Chapter 7.
Logic gates are the fundamental building blocks of any digital system.
The basic gates—AND, OR and NOT, the Universal gates—NAND and
NOR, the derived gates—
X-OR and X-NOR and the Realization of logic gates using diodes and
transistors are discussed in Chapter 8. Inhibit circuits and pulsed operation
of logic gates are also discussed in this chapter.
Most of the logic gates, flip-flops, counters, shift registers, arithmetic
circuits, encoders, decoders, etc. are available in several digital families.
The TTL, ECL, IIL, MOS and CMOS class of logic families and basic logic
circuits in those families are discussed in Chapter 9. Transmission gate and
dynamic MOS logic are also discussed in this chapter.
 When pulses of very large peak power are to be generated, we require
blocking oscillators which may be monostable type or astable type.
Monostable blocking oscillators-base timing, and emitter timing and astable
blocking oscillators-diode controlled and RC controlled are discussed in
Chapter 10. The analysis and design of blocking oscillators are also
illustrated with examples.
A large number of design examples have been worked out to help
students understand each new concept or analysis method as it is
introduced. Extensive short questions and answers and also review
questions are included at the end of each chapter to enable the students to
prepare for examinations confidently. Fill-in-the-blank type questions,
objective type multiple choice questions and numerical problems are
provided at the chapter-end to enable students to build a clear understanding
of the subject matter discussed in the text and also to assess their learning.
Answers to fill-in-the-blanks, objective type questions and numerical
problems are given at the end of the book. Most of the solved and unsolved
problems presented in this book have been classroom tested.
I express my profound gratitude to all those individuals without whose
assistance and cooperation this book would not have been completed. First
of all, I thank Sri. V. Srinivasa Rao, former Technician in EEE department
of Sir C.R. Reddy college of Engineering, Eluru, West Godavari (Dt),
Andhra Pradesh who typed the entire original manuscript and drew all the
figures in the first edition of this book. I also thank Mr. P. Venkateswara
Rao of SASI Institute of Technology and Engineering, Tadepalligudem,
West Godavari (Dt), Andhra Pradesh for typing the added material for
second edition.
I am grateful to Mr. Burugupalli Venugopala Krishna, President and Mr.
B. Ravi Kumar, Vice President, SASI Educational Society, Velivennu, West
Godavari (Dt), Andhra Pradesh for encouraging and providing me with all
the facilities for the revision of this book.
I thank Er. Mr.Koneru Satyanarayana, President and Er. Mr. Koneru
Lakshmana Havish and Er. Mr. Koneru Raja Harin, Vice Presidents, and
Smt. Koneru Siva Kanchana Latha, Secretary of Koneru Lakshmaiah
Education Foundation (KLEF), K.L. University Vijayawada, A.P. for their
constant encouragement.
 I express my sincere appreciation to my brother Mr. A. Vijaya Kumar and
to my friends, Dr. K. Koteswara Rao, Chairman, Gowtham Educational
Society, Gudivada, Krishna (Dt), Andhra Pradesh and Mr. Y. Ramesh Babu,
and Smt. Y. Krishna Kumari of Detroit for their encouragement.
I thank Dr. K. Raja Rajeswari, former Professor and Head of ECE
department and Dr. K.S. Lingamurthy, former Professor and Head of EEE
Department of Andhra University College of Engineering Visakhapatnam,
Andhra Pradesh for their constant words of encouragement.
I thank my publishers PHI Learning and their staff for encouraging me to
bring out the second edition of the book. In particular I wish to thank Mr.
Darshan Kumar, former Senior Editor who meticulously edited the
manuscript for the first edition and Mr. Sudarshan Das, former Senior
Editor who made this second edition possible. I also wish to express my
sincere appreciation to Ms. Babita Misra, Editorial Coordinator, Ms.
Shivani Garg, Senior Editor, and Mr. Ajai Kumar Lal Das, Assistant
Production Manager for their cooperation.
Finally, I am deeply indebted to my wife, Smt. A. Jhansi, for putting up
with my spending countless hours working on the manuscript. Our sons Dr.
A. Anil Kumar and
Mr. A. Sunil Kumar and daughters-in-law Dr. A. Anureet Kaur and A.
Apurupa and granddaughters Khushi Arekapudi and Shreya Arekapudi
supported me with their constant words of encouragement.
The author will gratefully acknowledge constructive criticism from both
students and teachers for further improvement of this book.
A. Anand Kumar
Symbols, Notations and
Abbreviations

SYMBOLS AND NOTATIONS

t Time constant
T Time period
n Nano
s Second
m Micro
p Pico
M Mega
m Milli
 Slope of ramp
h Intrinsic stand off ratio
q Charge
C Capacitance
R Resistance
L Inductance
i Current
v Voltage
D Diode
W Ohm
H Henry
F Farad
Hz Hertz
V Volt
A Ampere
v0 Output voltage
vi Input voltage
tr Rise time
tp Pulse width
f Frequency
f1 Lower-3dB frequency
f2 Upper-3dB frequency
Vg Cut in voltage
Rf Forward resistance of diode
Rr Reverse resistance of diode
f Tilt in forward direction
r Tilt in reverse direction
ts Storage time
tt Transition time
tf Fall time
td Delay time
es Slope error
ed Displacement error

et Transmission error
Ts Sweep time
Tr Retrace time

ABBREVIATIONS
AOI AND-OR-INVERT
BJT Bipolar junction transistor
BW Band width
CML Current-mode logic
CMOS Complimentary metal oxide semiconductor
CSL Current-steering logic
DCTL Diode coupled transistor logic
DL Diode logic
DTL Diode transistor logic
ECL Emitter coupled logic
GSI Giant scale integration
Hi-Z High impedance
HTL High threshold logic
IC Integrated circuit
IIL Integrated injunction logic
KVL Kirchhoff’s voltage law
LSI Large scale integration
LTP Lower triggering point
MOS Metal oxide semiconductor
MOSFET Metal oxide semiconductor field effect transistor
MSI Medium scale integration
NMOS N–Channel MOS
PMOS P–Channel MOS
RTL Resistor transistor logic
SBD Schottky Barrier diode
SSI Small scale integration
TTL Transistor transistor logic
UJT Unijunction transistor
ULSI Ultra large scale integration
UTP Upper triggering point
VLSI Very large scale integration
X–OR Exclusive OR
X–NOR Exclusive NOR
 Chapter 1
Linear Wave Shaping

A linear network is a network made up of linear elements only. A linear

network can be described by linear differential equations. The principle of
superposition and the principle of homogeneity hold good for linear
networks. In pulse circuitry, there are a number of waveforms, which appear
very frequently. The most important of these are sinusoidal, step, pulse,
square wave, ramp, and exponential waveforms. The response of RC, RL,
and RLC circuits to these signals is described in this chapter. Out of these
signals, the sinusoidal signal has a unique characteristic that it preserves its
shape when it is transmitted through a linear network, i.e. under steady-
state, the output will be a precise reproduction of the input sinusoidal signal.
There will only be a change in the amplitude of the signal and there may be
a phase shift between the input and the output waveforms. The influence of
the circuit on the signal may then be completely specified by the ratio of the
output to the input amplitude and by the phase angle between the output and
the input. No other periodic waveform preserves its shape precisely when
transmitted through a linear network, and in many cases the output signal
may bear very little resemblance to the input signal.
The process whereby the form of a non-sinusoidal signal is altered by
transmission through a linear network is called linear wave shaping.

1.1 THE LOW-PASS RC CIRCUIT

Figure 1.1 shows a low-pass RC circuit. A low-pass circuit is a circuit,
which transmits only low-frequency signals and attenuates or stops high-
frequency signals. At zero frequency, the reactance of the capacitor is
infinity (i.e. the capacitor acts as an open circuit) so the entire input appears
at the output, i.e. the input is transmitted to the output with zero attenuation.
So the output is the same as the input, i.e. the gain is unity. As the frequency
increases the capacitive reactance (XC = 1/2pfC) decreases and so the
output decreases. At very high frequencies the capacitor virtually acts as a
short-circuit and the output falls to zero.

Figure 1.1 The low-pass RC circuit.

1.1.1 Sinusoidal Input

The Laplace transformed low-pass RC circuit is shown in Figure 1.2(a). The
gain versus frequency curve of a low-pass circuit excited by a sinusoidal
input is shown in Figure 1.2(b). This curve is obtained by keeping the
amplitude of the input sinusoidal signal constant and varying its frequency
and noting the output at each frequency. At low frequencies the output is
equal to the input and hence the gain is unity. As the frequency increases,
the output decreases and hence the gain decreases. The frequency at which
the gain is (= 0.707) of its maximum value is called the cut-off
frequency. For a low-pass circuit, there is no lower cut-off frequency. It is
zero itself. The upper cut-off frequency is the frequency (in the high-
frequency range) at which the gain is , i.e. 70.7%, of its maximum
value. The bandwidth of the low-pass circuit is equal to the upper cut-off
frequency f2 itself.
 Figure 1.2 (a) Laplace transformed low-pass RC circuit and (b) its frequency response.

For the network shown in Figure 1.2(a), the magnitude of the steady-state
gain A is given by

Squaring both sides and equating the denominators,

1.1.2 Step-Voltage Input

A step signal is one which maintains the value zero for all times t < 0, and
maintains the value V for all times t > 0. The transition between the two
voltage levels takes place at t = 0 and is accomplished in an arbitrarily small
time interval. Thus, in Figure 1.3(a), vi = 0 immediately before t = 0 (to be
–
referred to as time t = 0 ) and vi = V, immediately after t = 0 (to be referred
+
to as time t = 0 ). In the low-pass RC circuit shown in Figure 1.1, if the
capacitor is initially uncharged, when a step input is applied, since the
voltage across the capacitor cannot change instantaneously, the output will
be zero at t = 0, and then, as the capacitor charges, the output voltage rises
exponentially towards the steady-state value V with a time constant RC as
shown in Figure 1.3(b).

Figure 1.3 (a) Step input and (b) step response of the low-pass RC circuit.

Let V be the initial voltage across the capacitor.

Writing KVL around the loop in Figure 1.1,
Taking the inverse Laplace transform on both sides,
–t/RC
vo(t) = V – (V – V)e

where V is the initial voltage across the capacitor (Vinitial) and V is the
final voltage (Vfinal) to which the capacitor can charge.
So, the expression for the voltage across the capacitor of an RC circuit
excited by a step input is given by
–t/RC
vo(t) = Vfinal – (Vfinal – Vinitial)e
–t/RC
If the capacitor is initially uncharged, then vo(t) = V(1 – e )
Expression for rise time
When a step signal is applied, the rise time tr is defined as the time taken by
the output voltage waveform to rise from 10% to 90% of its final value. It
gives an indication of how fast the circuit can respond to a discontinuity in
voltage. Assuming that the capacitor in Figure 1.1 is initially uncharged, the
output voltage shown in Figure 1.3(b) at any instant of time is given by
–t/RC
vo(t) = V(1 – e )

At t = t1, vo(t) = 10% of V = 0.1V

This indicates that the rise time tr is proportional to the time constant RC of
the circuit. The larger the time constant, the slower the capacitor charges,
and the smaller the time constant, the faster the capacitor charges.
Relation between rise time and upper 3-dB frequency
We know that the upper 3-dB frequency (same as bandwidth) of a low-pass
circuit is
Thus, the rise time is inversely proportional to the upper 3-dB frequency.
The time constant (t = RC) of a circuit is defined as the time taken by the
output to rise to 63.2% of the amplitude of the input step. It is same as the
time taken by the output to rise to 100% of the amplitude of the input step,
if the initial slope of rise is maintained. See Figure 1.3(b). The Greek letter t
is also employed as the symbol for the time constant.

1.1.3 Pulse Input

The pulse shown in Figure 1.4(a) is equivalent to a positive step followed
by a delayed negative step as shown in Figure 1.4(b). So, the response of
the low-pass RC circuit to a pulse for times less than the pulse width tp is
–t/RC
the same as that for a step input and is given by vo(t) = V(1 – e ). The
responses of the low-pass RC circuit for time constant RC >> tp, RC smaller
than tp and RC very small compared to tp are shown in Figures 1.5(a),
1.5(b), and 1.5(c) respectively.

Figure 1.4 (a) A pulse and (b) a pulse in terms of steps.

If the time constant RC of the circuit is very large, at the end of the pulse,
–tp/RC
the output voltage will be Vp(t) = V(1 – e ), and the output will
decrease to zero from this value with a time constant RC as shown in Figure
1.5(a). Observe that the pulse waveform is distorted when it is passed
through a linear network. The output will always extend beyond the pulse
width tp, because whatever charge has accumulated across the capacitor C
during the pulse cannot leak off instantaneously.
If the time constant RC of the circuit is very small, the capacitor charges
and discharges very quickly and the rise time tr will be small and so the
distortion in the wave shape is small. For minimum distortion (i.e. for
preservation of wave shape), the rise time must be small compared to the
pulse width tp. If the upper 3-dB frequency f2 is chosen equal to the
reciprocal of the pulse width tp, i.e. if f2 = 1/tp, then tr = 0.35tp and the
output is as shown in Figure 1.5(b), which for many applications is a
reasonable reproduction of the input. As a rule of thumb, we can say:

Figure 1.5 Pulse response for (a) RC >> tp, (b) RC < tp, and (c) RC << tp.
A pulse shape will be preserved if the 3-dB frequency is approximately
equal to the reciprocal of the pulse width.
Thus to pass a 0.25 s pulse reasonably well requires a circuit with an
upper cut-off frequency of the order of 4 MHz.

1.1.4 Square-Wave Input

A square wave is a periodic waveform which maintains itself at one
constant level V with respect to ground for a time T1 and then changes
abruptly to another level V, and remains constant at that level for a time
T2, and repeats itself at regular intervals of T = T1 + T2. A square wave
may be treated as a series of positive and negative steps. The shape of the
output waveform for a square wave input depends on the time constant of
the circuit. If the time constant is very small, the rise time will also be small
and a reasonable reproduction of the input may be obtained.
For the square wave shown in Figure 1.6(a), the output waveform will be
as shown in Figure 1.6(b) if the time constant RC of the circuit is small
compared to the period of the input waveform. In this case, the wave shape
is preserved. If the time constant is comparable with the period of the input
square wave, the output will be as shown in Figure 1.6(c). The output rises
and falls exponentially. If the time constant is very large compared to the
period of the input waveform, the output consists of exponential sections,
which are essentially linear as indicated in Figure 1.6(d). Since the average
voltage across R is zero, the dc voltage at the output is the same as that of
the input. This average value is indicated as Vdc in all the waveforms of
Figure 1.6.
 Figure 1.6 Response of a low-pass RC circuit to a square wave input: (a) square-wave input
waveform,
(b) output waveform for RC << T, (c) output waveform for RC T, and (d) output waveform for RC
>> T.

In Figure 1.6(c), the equation for the rising portion is

–t/RC
v01 = V – (V – V2)e

where V2 is the voltage across the capacitor at t = 0, and V is the level to

which the capacitor can charge.
 The equation for the falling portion is
–(t – T1)/RC
v02 = V – (V – V1)e

where V1 is the voltage across the capacitor at t = T1 and V is the level
to which the capacitor can discharge.

For a symmetrical square wave with zero average value,

1.1.5 Ramp Input
When a low-pass RC circuit shown in Figure 1.1 is excited by a ramp input,
i.e.
Taking the inverse Laplace transform on both sides,
–t/RC
vo(t) = – aRC + at + aRCe
–t/RC
= a(t – RC) + aRCe
–t/RC
If the time constant RC is very small, e 0

.............................................vo(t) = a(t – RC)

When the time constant is very small relative to the total ramp time T, the
ramp will be transmitted with minimum distortion. The output follows the
input but is delayed by one time constant RC from the input (except near the
origin where there is distortion) as shown in Figure 1.7(a). If the time
constant is large compared with the sweep duration, i.e. if RC/T >> 1, the
output will be highly distorted as shown in Figure 1.7(b).
Figure 1.7 Response of a low-pass RC circuit for a ramp input for (a) RC/T << 1 and (b) RC/T >> 1.

This shows that a quadratic response is obtained for a linear input and hence
the circuit acts as an integrator for RC/T >> 1.
The transmission error et for a ramp input is defined as the difference
between the input and the output divided by the input at the end of the
ramp, i.e. at t = T.
For RC/T << 1,

where f2 is the upper 3-dB frequency. For example, if we desire to pass a 2

ms pulse with less than 0.1% error, the above equation yields f2 > 80 kHz
and RC < 2 s.

1.1.6 Exponential Input

For the low-pass RC circuit shown in Figure 1.1, let the input applied as
–t/t
shown in Figure 1.8 be vi(t) = V(1 – e ), where t is the time constant of
the input waveform.

Figure 1.8 Exponential input.

Writing the KVL around the loop,

Taking the Laplace transform on both sides and neglecting the initial
conditions,
Taking the inverse Laplace transform on both sides and letting RC/t = n,

These are the expressions for the voltage across the capacitor of a low-pass
RC circuit excited by an exponential input of rise time tr1 = 2.2t.
If an exponential of rise time tr1 is passed through a low-pass circuit with
rise time tr2, the rise time of the output waveform tr will be given by an
empirical relation, This is same as the rise time obtained
when a step is applied to a cascade of two circuits of rise times tr1 and tr2
assuming that the second circuit does not load the first.
1.2 THE LOW-PASS RC CIRCUIT AS AN
INTEGRATOR
If the time constant of an RC low-pass circuit is very large, the capacitor
charges very slowly and so almost all the input voltage appears across the
resistor for small values of time. Then, the current in the circuit is vi(t)/R
and the output signal across C is

Hence the output is the integral of the input, i.e. if vi(t) = at, then

As time increases, the voltage drop across C does not remain negligible
compared with that across R and the output will not remain the integral of
the input. The output will change from a quadratic to a linear function of
time.
If the time constant of an RC low-pass circuit is very large in
comparison with the time required for the input signal to make an
appreciable change, the circuit acts as an integrator.
A criterion for good integration in terms of steady-state analysis is as
follows: The low-pass circuit acts as an integrator provided the time
constant of the circuit RC > 15T, where T is the period of the input sine
wave. When RC > 15T, the input sinusoid will be shifted at least by 89.4°
(instead of the ideal 90° shift required for integration) when it is transmitted
through the network.
 An RC integrator converts a square wave into a triangular wave.
Integrators are almost invariably preferred over differentiators in analog
computer applications for the following reasons:

1. It is easier to stabilize an integrator than a differentiator because the

gain of an integrator decreases with frequency whereas the gain of a
differentiator increases with frequency.
2. An integrator is less sensitive to noise voltages than a differentiator
because of its limited bandwidth.
3. The amplifier of a differentiator may overload if the input waveform
changes very rapidly.
4. It is more convenient to introduce initial conditions in an amplifier.

EXAMPLE 1.1 A pulse generator with an output resistance RS = 500  is

connected to an oscilloscope with an input capacitance Ci = 30 pF.
Determine the fastest rise time that can be displayed.

Solution: The circuit works as a low-pass filter with a time constant

RSCi = 500   30 pF = 15 ns

 Fastest rise time, tr = 2.2RC = 2.2  15 ns = 33 ns

EXAMPLE 1.2 A 10 V step is switched on to a 50 k resistor in series

with a 500 pF capacitor. Calculate the rise time of the capacitor voltage, the
time for the capacitor to charge to 63.2% of its maximum voltage, and the
time for the capacitor to be completely charged.

Solution: The circuit acts as a low-pass filter.

(a) The rise time of the capacitor voltage is
tr = 2.2RC = 2.2  50 k  500 pF = 55 s
 (b) The time for the capacitor to charge to 63.2% of the maximum voltage
is
t = RC = 50 k  500 pF = 25 s
(c) The time for the capacitor to be completely charged (99% value) is
5t = 5RC = 5  25 s = 125 s

EXAMPLE 1.3 An ideal 1 s pulse is fed to an amplifier. Calculate and

plot the output waveform under the following conditions: The upper 3-dB
frequency is:
(a) 10 MHz (b) 1 MHz (c) 0.1 MHz

Solution: The upper 3-dB frequency frequency indicates that the amplifier
acts as a low-pass circuit. So the pulse shown in Figure 1.9(a) is applied to
the RC low-pass circuit shown in Figure 1.9(b).

Figure 1.9 Example 1.3: (a) input waveform (b) circuit diagram.

(a) When the upper 3-dB frequency, f2 = 10 MHz:

Since, tp = 1 s and RC = 0.0159 s, RC << tp

Since the time constant is very small in comparison with the pulse
width, the capacitor C charges rapidly with a rise time,
 tr = 2.2  0.0159 s = 0.035 s

The output vo is given by vo = V(1 – e–t/RC) where V is the amplitude

of the pulse.
At..................................t = tp,

.................................. .......vo = V(1 – e–tp/RC) = V(1 – e–1/0.0159) = V

The output waveform is shown in Figure 1.10(a).
(b) When f2 = 1 MHz:
RC = 1/2pf2 = 1/2p  106 = 0.1591 s
tp = 1 s and RC = 0.1591 s
 RC < tp.
Since the time constant is small, the capacitor charges fast.
Rise time tr = 2.2 RC = 2.2  0.1591 s = 0.35 s
The output is given by vo = V(1 – e–t/RC)
At t = tp, vo = V(1 – e–tp/RC) = V(1 – e–1/0.1591) = 0.998 V
The output waveform is shown in Figure 1.10(b).
(c) When f2 = 0.1 MHz:

So tp = 1 s and RC = 1.591 s. RC is comparable to tp.

Since the time constant is comparable to the pulse width, in the interval
0 < t < tp, the capacitor charges exponentially according to the equation
–t/RC
vo = V(1 – e )

At t = tp, the output voltage vo = Vp

 –tp/RC –1/1.591
 Vp = V(1 – e ) = V(1 – e ) = 0.4668V

For t > tp, vo decreases according to the equation

The output waveform is shown in Figure 1.10(c).

Figure 1.10 Example 1.3: (a), (b) and (c) output waveforms.

EXAMPLE 1.4 A pulse is applied to a low-pass RC circuit. Prove by direct

integration that the area under the pulse is the same as the area under the
output waveform across the capacitor. Explain the result physically.

Solution: A pulse shown by the dotted line in Figure 1.11(b) is applied to

the RC low-pass circuit shown in Figure 1.11(a). The output waveform is
shown by the thick line in Figure 1.11(b).

Figure 1.11 Example 1.4: (a) circuit diagram and (b) output waveform.

During the pulse duration 0 < t < tp:

 Area under the output waveform is

For t > tp, the area under the output waveform is

Since the average voltage across R is zero, the dc voltage at the output is
the same as that at the input. So, the area under the output waveform is the
same as that under the pulse.

EXAMPLE 1.5 Sketch the output waveforms for an RC integrating circuit

when: (a) t = 10tp, (b) t = tp, and (c) t = 0.1tp.

Solution: The pulse shown by the dotted line in Figure 1.12(b) is applied to
the RC integrating circuit shown in Figure 1.12(a).
 Figure 1.12 Example 1.5: (a) circuit diagram and (b) output waveforms.

(a) t = 10tp:

The RC time constant is very large compared to the pulse width and so
the capacitor charges slowly to a voltage V at the end of the pulse
given by

or to 9.5% of the pulse amplitude.

(b) t = tp:

The RC time constant is comparable to the pulse width and so the

capacitor charges gradually to a voltage V given by

(c) t = 0.1tp:
The RC time constant is very small compared to the pulse width and so
the capacitor charges rapidly to a voltage V given by

with a rise time tr = 2.2RC = 0.22tp

The output waveforms are sketched in Figure 1.12(b).
EXAMPLE 1.6 A symmetrical square wave of amplitude  5 V and
frequency 2 kHz is impressed on an RC low-pass circuit. If R = 5 k, C =
0.1 F, calculate and plot the steady-state output with respect to time.
Solution: When the input waveform shown by the dotted line in Figure
1.13(b) is applied to the RC low-pass circuit of Figure 1.13(a), the output
waveform shown by the thick line in Figure 1.13(b) results.

Figure 1.13 Example 1.6: (a) circuit diagram and (b) output waveforms.

EXAMPLE 1.7 A symmetrical square wave whose average value is zero

has a peak-to-peak amplitude of 20 V and a period of 2 s. This waveform
is applied to a circuit whose upper 3-dB frequency is MHz. Calculate
and sketch the steady-state output waveform. In particular what is the peak-
to-peak output amplitude?
Solution: Since the upper cut-off frequency is specified, the circuit must be
a low-pass filter.

When the input waveform shown by dotted lines in Figure 1.14(b) is

applied to the RC low-pass circuit of Figure 1.14(a), the output waveform
shown by thick lines in Figure 1.14(b) results.

Figure 1.14 Example 1.7: (a) circuit diagram and (b) output waveforms.

Since RC is comparable to T/2, the output rises and falls exponentially.

Since the input is a symmetrical square wave
EXAMPLE 1.8 A symmetrical square wave whose peak-to-peak amplitude
is 2 V and whose average value is zero is applied to an RC integrating
circuit. The time constant of the circuit is equal to half the period of the
square wave. Find the peak-to-peak value of the output amplitude.

Solution: The input waveform shown by dotted line in Figure 1.15(b) is

applied to the RC integrating circuit shown in Figure 1.15(a). Since the time
constant RC of the circuit is comparable to the period of the input
waveform, the output voltage grows considerably. Since the input is a
symmetrical square wave with zero dc value, the output must also be
symmetrical with respect to the zero level and the positive and negative
peaks of the output must be equal in amplitude and opposite in sign. The
output waveform under steady-state conditions is shown in Figure 1.15(b).

Figure 1.15 Example 1.8: output waveform.

EXAMPLE 1.9 A square wave whose peak-to-peak amplitude is 2 V
extends 1 V with respect to ground. The duration of the positive section is
0.1 s and that of the negative section 0.2 s. If this waveform is impressed
upon an RC integrating circuit whose time constant is 0.2 s, what are the
steady-state maximum and minimum values of the output waveform?

Solution: When the input waveform shown by dotted lines in Figure

1.16(b) is applied to the RC integrating circuit shown in Figure 1.16(a)
under steady-state conditions the output waveform is as shown by the thick
line in Figure 1.16(b).

Figure 1.16 Example 1.9: (a) circuit diagram and (b) output waveform.
 The steady-state maximum value of output V1 = 0.014 V. The steady-
state minimum value of output V2 = – 0.6271 V.

 Peak-to-peak output voltage = V1 – V2 = 0.014 – (– 0.6271) = 0.6411 V

EXAMPLE 1.10 The periodic waveform shown in Figure 1.17(b) is

applied to an RC integrating network shown in Figure 1.17(a) whose time
constant is 10 s. Sketch the output waveform. Calculate the maximum and
minimum values of the output voltage with respect to ground under steady-
state conditions. Also, calculate and plot the output for the first two cycles
of the input.
 Figure 1.17 Example 1.10: (a) circuit diagram and (b) input waveform.

Solution: The input waveform shown in Figure 1.17(b) is applied to the RC

integrating circuit shown in Figure 1.17(a).
Steady-state analysis. Under steady-state conditions, the capacitor
charges and discharges to the same level in each cycle, i.e. V1 and V2 are
constants.
Given......................................RC = 10 s, TON = 10 s, TOFF = 1 s

Since the time constant is comparable to the period of the waveform, the
capacitor charges and discharges gradually and the output waveform is as
shown in Figure 1.18.

Figure 1.18 Example 1.10: output waveform under steady state.

In the interval 0 < t < 10 s, when input = 100 V

Transient analysis. The output waveform for the first two cycles of the
input waveform is shown in Figure 1.19.

Figure 1.19 Example 1.10: transient response.

Let the capacitor be initially uncharged, i.e. vo = 0 V at t = 0. Since the

voltage across the capacitor cannot change instantaneously, the output
voltage rises from 0 V at t = 0, goes exponentially to at t = 10 s, to
at t = 11 s, to at t = 21 s and to at t = 22 s, and so on, as shown in
Figure 1.19.
EXAMPLE 1.11 For the circuit and the input shown in Figure 1.20:

(a) Determine the level of vo and IC at t = 2.5 ms. (b) Sketch the settled
waveform of VC.

Figure 1.20 Example 1.11: (a) circuit diagram and (b) the input waveform.

Solution: The waveform shown in Figure 1.20(b) is applied to the RC low-

pass circuit shown in Figure 1.20(a). Given TON = 1 ms, TOFF = 1 ms, T =
3 –6
2 ms. The time constant of the circuit is RC = 27  10  0.1  10 = 2.7
ms.
Since the time constant is comparable to the period of the waveform, the
output rises gradually.

Transient analysis. The transient response of the circuit is shown in Figure

1.21. Initially the capacitor is uncharged, so the output starts from zero at t
= 0. The output rises to V at t = 1 ms, falls to V at t = 2 ms and rises to
V at t = 2.5 ms.

Figure 1.21 Example 1.11: transient response.

Steady-state analysis. Under steady-state, the capacitor charges and

discharges to the same level in each cycle. So the shape of the output
waveform in each cycle is fixed. The steady-state output waveform is
shown in Figure 1.22.
 Figure 1.22 Example 1.11: steady-state response.

EXAMPLE 1.12 The square wave shown in Figure 1.23 is fed to an RC

integrating circuit. Compute and plot the output waveforms if (a) RC is
large, say, RC = 2.5T, and (b) RC is small, say RC = T/2.5.

Figure 1.23 Example 1.12: (a) circuit diagram and (b) input waveform.

Solution: The waveform shown in Figure 1.23(b) is applied to the RC

integrating circuit shown in Figure 1.23(a).
(a) When RC = 2.5T, the capacitor charges slowly. The transient response
is as shown in Figure 1.24. Assuming that the capacitor is uncharged
initially,
 –T/2.5T
V1 = 300 – (300 – 0)e = 98.91 V
–T/2.5T
V2 = 200 – (200 – 98.91)e = 132.239 V
–T/2.5T
V3 = 300 – (300 – 132.239)e = 187.55 V
–T/2.5T
V4 = 200 – (200 – 187.55)e = 191.654 V
–T/2.5T
V5 = 300 – (300 – 191.654)e = 227.37 V
–T/2.5T
V6 = 200 – (200 – 227.37)e = 218.35 V
–T/2.5T
V7 = 300 – (300 – 218.35)e = 245.27 V

Figure 1.24 Example 1.12: transient response when RC = 2.5T.

The steady-state response for RC = 2.5T is shown in Figure 1.25. Under

steady-state conditions, the shape of the waveform is fixed because the
capacitor charges and discharges to the same levels in each cycle, i.e.
–T/2.5T
V1 = 300 – (300 – V2)e = 300 – (300 – V2)  0.670 = 99 +
0.67V2
–T/2.5T
V2 = 200 – (200 – V1)e = 200 – (200 – V1)  0.670 = 66 +
0.67V1
 Figure 1.25 Example 1.12: steady-state response when RC = 2.5T.

Solving the above equations for V1 and V2,

The maximum and minimum values of output are

V1 = 259.88 V.......and.......V2 = 240.12 V

(b) When RC = T/2.5 = 0.4T, the capacitor charges and discharges

rapidly. The transient response will be as shown in Figure 1.26. Assuming
that the capacitor is uncharged initially,
–T/0.4T
V1 = 300 – (300 – 0)e = 275.37 V
–T/0.4T
V2 = 200 – (200 – 275.37)e = 206.2 V
–T/0.4T
V3 = 300 – (300 – 206.2)e = 292.3 V
–T/0.4T
V4 = 200 – (200 – 292.3)e = 207.56 V
–T/0.4T
V5 = 300 – (300 – 207.56)e = 292.42 V
–T/0.4T
V6 = 200 – (200 – 292.42)e = 207.57 V
–T/0.4T
V7 = 300 – (300 – 207.57)e = 292.42 V
 Figure 1.26 Example 1.12: transient response when RC = T/2.5.

The steady-state response for RC = T/2.5 is shown in Figure 1.27.

–T/0.4T
V1 = 300 – (300 – V2)e = 275.37 + 0.082V2
–T/0.4T
V2 = 200 – (200 – V1)e = 183.6 + 0.082V1

Solving the equations for V1 and V2,

So the steady-state maximum and minimum values of output are

V1 = 292.37 V.......and.......V2 = 207.5 V

These results indicate that when the time constant is small, the output
reaches its steady values very quickly.

Figure 1.27 Example 1.12: steady-state response for RC = 0.4T.

EXAMPLE 1.13 Assuming that the capacitor is initially uncharged,

determine the output response of the low-pass RC circuit with time constant
0.05 ms, to the input waveform shown in Figure 1.28(a).

Figure 1.28 Example 1.13: (a) input waveform and (b) output waveform.

Solution: The input waveform shown in Figure 1.28(a) is applied to the RC

low-pass circuit shown in Figure 1.1. The output waveform is as shown in
Figure 1.28(b).

EXAMPLE 1.14 The periodic ramp voltage shown in Figure 1.29(a) is

applied to a low-pass RC circuit.

(a) Find the equations from which to determine the steady-state output
waveform.
(b) If T1 = T2 = RC, find the maximum and minimum values of the
output voltage and plot the waveform.
(Note: The minimum value does not occur at the beginning of interval
T1).
 Figure 1.29 Example 1.14: (a) input waveform and (b) output waveform.

Solution: The input waveform shown in Figure 1.29(a) is applied to the RC

low-pass circuit shown in Figure 1.1. Under steady-state conditions, V1 
0, the capacitor charges from V1 to V2 in the interval 0 to T1. During that
interval, vi(t) = at. Writing KVL for the low-pass RC circuit, we have
vo(t) = V2 at t = T1, i.e. the capacitor charges from V1 to V2 in time T1.
Between T1 and T1 + T2, i.e. during T2 when the input is zero, the capacitor
discharges from V2 to V1 according to the equation
–t/RC
vo(t) = V2e

(b) When T1 = T2 = RC, the minimum value of output does not occur at t
= 0, that is, V1 is not the minimum.

At t = T1, vo(t) = V2
 When the ramp input is reduced to zero,

–t/RC
Substituting this value of e in the expression for vo(t),

Vo(min) = V  0.145 – V(1 – 0.865) + 0.1563V  0.865

i.e..................Vo(min) = 0.145V

The output waveform is shown in Figure 1.29(b).

EXAMPLE 1.15 Prove that an RC low-pass circuit behaves as a reasonably
good integrator if RC > 15 T, where T is the period of the input sinusoid Em
sin wt.
Solution: Consider the RC low-pass circuit shown in Figure 1.1.
It has been shown earlier that for a large time constant the output and
input voltages of an RC low-pass circuit are related as

Comparison of the equations for vo reveals that for the RC low-pass

circuit to act as an integrator, it is essential that the angle q must be equal to
radians, i.e. 90°.
 That means if RC > 15 T, angle q becomes almost 90°. So this is the
condition to be satisfied for the RC low-pass circuit to behave like a
reasonably good integrator.

1.3 THE HIGH-PASS RC CIRCUIT

Figure 1.30 shows a high-pass RC circuit. At zero frequency the reactance
of the capacitor is infinity and so it blocks the input and hence the output is
zero. Hence, this capacitor is called the blocking capacitor and this circuit,
also called the capacitive coupling circuit, is used to provide dc isolation
between the input and the output. As the frequency increases, the reactance
of the capacitor decreases and hence the output and gain increase. At very
high frequencies, the capacitive reactance is very small so a very small
voltage appears across C and, so the output is almost equal to the input and
the gain is equal to 1. Since this circuit attenuates low-frequency signals
and allows transmission of high-frequency signals with little or no
attenuation, it is called a high-pass circuit.

Figure 1.30 The high-pass RC circuit.

1.3.1 Sinusoidal Input

Figure 1.31(a) shows the Laplace transformed high-pass RC circuit. The
gain versus frequency curve of a high-pass circuit excited by a sinusoidal
input is shown in Figure 1.31(b). For a sinusoidal input vi, the output signal
vo increases in amplitude with increasing frequency. The frequency at
which the gain is of its maximum value is called the lower cut-off or
lower 3-dB frequency. For a high-pass circuit, there is no upper cut-off
frequency because all high frequency signals are transmitted with zero
attenuation. Therefore, f2 = . Hence bandwidth = f2 – f1 = .

Figure 1.31 (a) Laplace transformed high-pass circuit and (b) gain versus frequency plot.

Expression for the lower cut-off frequency

For the high-pass RC circuit shown in Figure 1.31(a), the magnitude of the
steady-state gain A, and the angle q by which the output leads the input are
given by
This is the expression for the lower cut-off frequency of a high-pass circuit.
Relation between f1 and tilt

The lower cut-off frequency of a high-pass circuit is f1 = 1/2pRC. The

lower cut-off frequency produces a tilt.
For a 10% change in capacitor voltage, the time or pulse width involved
is
This equation applies only when the tilt is 10% or less. When the tilt
exceeds 10%, the voltage should be treated as exponential instead of linear
and the equation
–t/RC
Vo = Vf – (Vf – Vi)e

should be applied.

1.3.2 Step Input

When a step signal of amplitude V volts shown in Figure 1.32(a) is applied
to the high-pass RC circuit of Figure 1.30, since the voltage across the
capacitor cannot change instantaneously the output will be just equal to the
input at t = 0 (for t < 0, vi = 0 and vo = 0). Later when the capacitor charges
exponentially, the output reduces exponentially with the same time constant
RC. The expression for the output voltage for t > 0 is given by
–t/RC –t/RC –t/RC
vo(t) = Vf – (Vf – Vin)e = 0 – (0 – V)e = Ve

Figure 1.32(b) shows the response of the circuit for large, small, and very
small time constants.
For t > 5t, the output will reach more than 99% of its final value. Hence
although the steady-state is approached asymptotically, for most
applications we may assume that the final value has been reached after 5t. If
the initial slope of the exponential is maintained, the output falls to zero in a
time t = t.
The voltage across a capacitor can change instantaneously only when an
infinite current passes through it, because for any finite current i(t) through
the capacitor, the instantaneous change in voltage across the capacitor is
given by

Figure 1.32 (a) Step input and (b) step response for different time constants.

1.3.3 Pulse Input

A pulse of amplitude V and duration tp shown in Figure 1.4(a) is nothing
but the sum of a positive step of amplitude V starting at t = 0 and a negative
step of amplitude V starting at tp as shown in Figure 1.4(b). So, the
response of the circuit for 0 < t < tp for the pulse input is the same as that
–t/RC
for a step input and is given by vo(t) = Ve . At t = tp, .
At t = tp, since the input falls by V volts suddenly and since the voltage
across the capacitor cannot change instantaneously, the output also falls
suddenly by V volts to Vp – V. Hence at . Since Vp <
V, Vp – V is negative. So there is an undershoot at t = tp and hence for t >
tp, the output is negative. For t > tp, the output rises exponentially towards
zero with a time constant RC according to the expression
.
The output waveforms for RC >> tp, RC comparable to tp and RC << tp
are shown in Figures 1.33(a), (b), and (c) respectively. There is distortion in
the outputs and the distortion is the least when the time constant is very
large. Observe that there is positive area and negative area in the output
waveforms. The negative area will always be equal to the positive area. So
if the time constant is very large the tilt (the almost linear decrease in the
output voltage) will be small and hence the undershoot will be very small,
and for t > tp, the output rises towards the zero level very very slowly. If the
time constant is very small compared to the pulse width (i.e. RC/tp << 1),
the output consists of a positive spike or pip of amplitude V volts at the
beginning of the pulse and a negative spike of the same amplitude at the end
of the pulse. Hence a high-pass circuit with a very small time constant is
called a peaking circuit and this process of converting pulses into pips by
means of a circuit of short time constant is called peaking.

Figure 1.33 Pulse response for (a) RC >> tp, (b) RC comparable to tp, and (c) RC << tp.

1.3.4 Square-Wave Input

A square wave shown in Figure 1.34(a) is a periodic waveform, which
maintains itself at one constant level V with respect to ground for a time
T1 and then changes abruptly to another level V and remains constant at
that level for a time T2, and then repeats itself at regular intervals of T = T1
+ T2. A square wave may be treated as a series of positive and negative
steps. The shape of the output depends on the time constant of the circuit.
Figures 1.34(b), 1.34(c), 1.34(d), and 1.34(e) show the output waveforms of
the high-pass RC circuit under steady-state conditions for the cases (a) RC
>> T, (b) RC > T, (c) RC = T, and (d) RC << T respectively.
Figure 1.34 (a) A square wave input, (b) output when RC is arbitrarily large, (c) output when RC > T,
(d) output when RC is comparable to T, and (e) output when RC << T.
 When the time constant is arbitrarily large (i.e. RC/T1 and RC/T2 are very
very large in comparison to unity) the output is same as the input but with
zero dc level. When RC > T, the output is in the form of a tilt. When RC is
comparable to T, the output rises and falls exponentially. When RC << T
(i.e. RC/T1 and RC/T2 are very very small in comparison to unity), the
output consists of alternate positive and negative spikes. In this case the
peak-to-peak amplitude of the output is twice the peak-to-peak value of the
input.
In fact, for any periodic input waveform under steady-state conditions,
the average level of the output waveform from the high-pass circuit of
Figure 1.30 is always zero independently of the dc level of the input. The
proof is as follows:
Writing KVL around the loop of Figure 1.30,

Under steady-state conditions, the output waveform (as well as the input
signal) is repetitive with a period T so that vo(T) = vo(0) and vi(T) = vi(0).
 Hence Since this integral represents the area under the output
waveform over one cycle, we can say that the average level of the steady-
state output signal is always zero.
This can also be proved based on frequency domain analysis as follows.
The periodic input signal may be resolved into a Fourier series consisting
of a constant term and an infinite number of sinusoidal components whose
frequencies are multiples of f = 1/T. Since the blocking capacitor presents
infinite impedance to the dc input voltage, none of these dc components
reach the output under steady-state conditions. Hence the output signal is a
sum of sinusoids whose frequencies are multiples of f. This waveform is
therefore periodic with a fundamental period T but without a dc component.
With respect to the high-pass circuit of Figure 1.30, we can say that:

1. The average level of the output signal is always zero, independently of

the average level of the input. The output must consequently extend in
both negative and positive directions with respect to the zero voltage
axis and the area of the part of the waveform above the zero axis must
equal the area which is below the zero axis.
2. When the input changes abruptly by an amount V, the output also
changes abruptly by an equal amount and in the same direction.
3. During any finite time interval when the input maintains a constant
level, the output decays exponentially towards zero voltage.

Under steady-state conditions, the capacitor charges and discharges to the

same voltage levels in each cycle. So the shape of the output waveform is
fixed.
Expression for the percentage tilt
We will derive an expression for the percentage tilt when the time constant
RC of the circuit is very large compared to the period of the input
waveform, i.e. RC >> T.
For a symmetrical square wave with zero average value

Figure 1.35 Linear tilt of a symmetrical square wave when RC >> T.

1.3.5 Ramp Input
A waveform which is zero for t < 0 and which increases linearly with time
for t > 0 is called a ramp or sweep voltage.
When the high-pass RC circuit of Figure 1.30 is excited by a ramp input
vi(t) = at, where a is the slope of the ramp, then
 Figure 1.36 shows the response of the high-pass circuit for a ramp input
when (a) RC >> T, and (b) RC << T, where T is the duration of the ramp.
For small values of T, the output signal falls away slightly from the input as
shown in the Figure 1.36(a).

Figure 1.36 Response of the high-pass circuit for a ramp input when (a) RC >> T and (b) RC << T.

When a ramp signal is transmitted through a linear network, the output

departs from the input. A measure of the departure from linearity expressed
as the transmission error et is defined as the difference between the input
and the output divided by the input. The transmission error at a time t = T is
then
 For large values of t in comparison with RC, the output approaches the
constant value aRC as indicated in Figure 1.36(b).

1.3.6 Exponential Input

When the high-pass RC circuit of Figure 1.30 is excited by an exponential
–t/t
input vi(t) = V(1 – e ) shown in Figure 1.8, where t is the time constant of
the input, the output taken across the resistor is given by
vR(t) = vi(t) – vC(t)
–t/t
For an exponential input vi(t) = V(1 – e ), the expression for the voltage
across the capacitor (derived earlier while dealing with RC low-pass circuit)
is
If the time constant of the circuit is very high, n is high and the second term
of the equation for n  1 is negligible compared to the first term except for
small values of time.

This equation agrees with the way the circuit should behave for an ideal
step voltage. The response of the high-pass circuit for different values of n
is shown in Figure 1.37.

Figure 1.37 Response of high-pass circuit for exponential input.

 Near the origin of time the output follows the input. Also, the smaller the
circuit time constant, the smaller will be the output peak and the narrower
will be the pulse. The larger the circuit time constant, the larger will be the
peak output and also the wider will be the pulse.
The maximum output occurs when

Since x = t/t, the time to rise to peak tp is given by

To obtain the maximum value of output, substitute this value of –x in the

expression for vo(t)
1.4 THE HIGH-PASS RC CIRCUIT AS A
DIFFERENTIATOR
When the time constant of the high-pass RC circuit is very very small, the
capacitor charges very quickly; so almost all the input vi(t) appears across
the capacitor and the voltage across the resistor will be negligible compared
to the voltage across the capacitor. Hence the current is determined entirely
by the capacitance. Then the current

and the output signal across R is

Thus we see that the output is proportional to the derivative of the input.

The high-pass RC circuit acts as a differentiator provided the RC time

constant of the circuit is very small in comparison with the time required
for the input signal to make an appreciable change.

The derivative of a step signal is an impulse of infinite amplitude at the

occurrence of the discontinuity of step. The derivative of an ideal pulse is a
positive impulse followed by a delayed negative impulse, each of infinite
amplitude and occurring at the points of discontinuity. The derivative of a
square wave is a waveform which is uniformly zero except at the points of
discontinuity. At these points, precise differentiation would yield impulses
of infinite amplitude, zero width and alternating polarity. For a square wave
input, an RC high-pass circuit with very small time constant will produce an
output, which is zero except at the points of discontinuity. At these points of
discontinuity, there will be peaks of finite amplitude V. This is because the
voltage across R is not negligible compared with that across C.
An RC differentiator converts a triangular wave into a square wave.
For the ramp vi = at, the value of RC(dvi/dt) = aRC. This is true except
near the origin. The output approaches the proper derivative value only after
a lapse of time corresponding to several time constants. The error near t = 0
is again due to the fact that in this region the voltage across R is not
negligible compared with that across C.
If we assume that the leading edge of a pulse can be approximated by a
ramp, then we can measure the rate of rise of the pulse by using a
differentiator. The peak output is measured on an oscilloscope, and from the
equation vo = aRC, we see that this voltage divided by the product RC gives
the slope a.
A criteria for good differentiation in terms of steady-state sinusoidal
analysis is, that if a sine wave is applied to the high-pass RC circuit, the
output will be a sine wave shifted by a leading angle q such that:

with the output being proportional to sin(wt + q). In order to have true
differentiation, we must obtain cos wt. In other words, q must equal 90°.
This result can be obtained only if R = 0 or C = 0. However, if wRC = 0.01,
then 1/wRC = 100 and q = 89.4°, which is sufficiently close to 90° for most
purposes. If wRC = 0.1, then q = 84.3° and for some applications this may
be close enough to 90°.
If the peak value of input is Vm, the output is

and if wRC << 1, then the output is approximately VmwRC cos wt. This
result agrees with the expected value RC(dvi/dt). If wRC = 0.01, then the
output amplitude is 0.01 times the input amplitude.

1.5 DOUBLE DIFFERENTIATION

Figure 1.38 shows two RC coupling networks in cascade separated by an
amplifier A. It is assumed that the amplifier operates linearly and that its
output impedance is small relative to the impedance of R2 and C2 so that
this combination does not load the amplifier. Let R1 be the parallel
combination of R and the input impedance of the amplifier. If the time
constants R1C1 and R2C2 are small relative to the period of the input
waveform, then this circuit performs approximately a second-order
differentiation.
This circuit (Figure 1.38) can convert a ramp voltage into a pulse. The
initial slope of the output wave is the initial slope of the input multiplied by
the gain of the amplifier. For this reason this circuit is also called a rate-of-
rise amplifier.

Figure 1.38 A rate-of-rise amplifier.

EXAMPLE 1.16 An oscilloscope has a coupling capacitor Cc = 1 F.

When the input resistance Ri = 1 M, determine the minimum square wave
frequency that can be displayed if the tilt is not to exceed 1%.

Solution: The circuit works as a high-pass filter shown in Figure 1.30.

Pulse width (PW) = Fractional tilt  RiCc = 0.01  1 M  1 F = 0.01
s.
EXAMPLE 1.17 A 10 Hz square wave is fed to an amplifier. Calculate and
plot the output waveform under the following conditions. The lower 3-dB
frequency is (a) 0.3 Hz, (b) 3 Hz, and (c) 30 Hz.
Solution: Since the lower cut-off frequency is specified, the amplifier acts
as an RC high-pass circuit shown in Figure 1.30.

Since RC is comparable to T, the output rises and decays exponentially as

shown in Figure 1.34(d).
Since the time constant is very small compared to the period, the output is
in the form of spikes as shown in Figure 1.34 (e).
EXAMPLE 1.18 A dc voltmeter indicates 2 V when measuring a square
wave with a peak-to-peak amplitude of 6 V. Calculate the positive and
negative peak amplitudes of the square wave.
Solution: The square wave is shown in Figure 1.39.

Figure 1.39 Example 1.18 : waveform.

EXAMPLE 1.19 Calculate the lowest square wave frequency that can be
passed by an amplifier with a lower cut-off frequency of 10 Hz, if the
output tilt is not to exceed 2%.
Solution: Since the lower cut-off frequency is given, the circuit is a high-
pass filter shown in Figure 1.30.

EXAMPLE 1.20 A 1 kHz symmetrical square wave of  10 V is applied to

an RC circuit having 1 ms time constant. Calculate and plot the output for
the RC configuration as (a) high-pass circuit and (b) low-pass circuit.
 Since RC is comparable to T, the capacitor charges and discharges
exponentially.
(a) High-pass circuit. When the 1 kHz square wave shown by dotted
lines in Figure 1.40(b) is applied to the RC high-pass circuit shown in
Figure 1.40(a), under steady-state conditions the output waveform will be as
shown by the thick line in Figure 1.40(b).

Figure 1.40 Example 1.20 (High-pass circuit): (a) circuit diagram and (b) output waveform.

Since the input signal is a symmetrical square wave, we have

(b) Low-pass circuit. When the 1 kHz square wave shown by dotted lines
in Figure 1.41(b) is applied to the RC low-pass circuit shown in Figure
1.41(a), under steady-state conditions, the output waveform will be as
shown by the thick line in Figure 1.41(b).
Since the input is a symmetrical square wave V2 = – V1

Figure 1.41 Example 1.20 (Low-pass circuit): (a) circuit diagram and (b) output waveform.

EXAMPLE 1.21 A pulse of 5 V amplitude and 0.5 ms duration is applied

to an RC high-pass circuit with R = 22 k and C = 0.47 F. Sketch the
output waveform and determine the percentage tilt in the output.
Solution: When the pulse shown by the dotted line in Figure 1.42(b) is
applied to the RC high-pass circuit shown in Figure 1.42(a), the output
waveform will be as shown by the thick line in Figure 1.42(b).
 Figure 1.42 Example 1.21: (a) circuit diagram and (b) output waveform.

Time constant of the circuit RC = 22  103  0.47  10–6 = 10.34 ms.

Pulse width tp = 0.5 ms
...........................................................RC >> tp
Since the time constant of the circuit is very large compared to the pulse
width, the output falls almost linearly in the interval 0 < t < tp.
The expression for output voltage is vo = V e–t/RC = 5 e–t/RC

At......................................t = tp, vo = 5 e–tp/RC = 5 e–0.5/10.34 = 4.763

volts
Also at t = tp, the input falls by 5 volts. So the output also falls by 5 volts.
.....................................VC = 4.763 – 5 = – 0.237 V
VC represents the undershoot at t = tp.
For t > tp, the expression for the output voltage is

vo = VC e–(t–tp)/RC
= – 0.237 e–(t–0.510–3)/10.3410–3
Percentage tilt. In the interval 0 < t < tp, the input voltage maintains a
constant level and since RC > tp, a tilt in the output voltage occurs at the
end of the pulse and it is given by AB.

EXAMPLE 1.22 If a square wave of 5 kHz is applied to an RC high-pass

circuit and the resultant waveform measured on a CRO was tilted from 15
V to 10 V, find out the lower 3-dB frequency of the high-pass circuit.
Solution: The input and output waveforms of the RC high-pass circuit of
Figure 143(a) are shown in Figure 1.43(b).
 Figure 1.43 Example 1.22: (a) circuit diagram and (b) output waveform.

EXAMPLE 1.23 A symmetrical square wave is applied to a high-pass

circuit having R = 20 k and C = 0.05 F.
 (a) If the frequency of the input signal is 1 kHz and the signal swings
between 5 V, draw the output waveform and indicate the voltages.
(b) What happens if the frequency of the signal is reduced to 100 Hz?
Show the output waveform.
Solution: The square wave shown in Figure 1.44(b) is applied to the RC
high-pass circuit shown in Figure 1.44(a).

Figure 1.44 Example 1.23: (a) circuit diagram and (b) input waveform.
 When the input signal frequency is reduced from 1 kHz to 100 Hz, the
circuit acts as a differentiator as RC (1ms) < T (10ms). The output
waveforms are shown in Figures 1.45(a) and (b).
 Figure 1.45 Example 1.23: output waveforms.

EXAMPLE 1.24 In the circuit shown in Figure 1.46 determine how long it
will take the output voltage to read 20 V after the switch is closed.

Figure 1.46 Example 1.24: circuit diagram.

Solution: When the switch is closed, the circuit in Figure 1.46 works as a
high-pass filter. The expression for the output is

So it takes 26.4 ms to read 20 V after the switch is closed.

EXAMPLE 1.25 A 10 Hz symmetrical square wave whose peak-to-peak

amplitude is 2 V is impressed upon a high-pass RC circuit whose lower 3-
dB frequency is 5 Hz. Calculate and sketch the output waveform for the
first two cycles. What is the peak-to-peak output amplitude under steady-
state conditions?

Solution: The square wave shown in Figure 1.47(b) is applied to the RC

high-pass circuit shown in Figure 1.47(a). The lower 3-dB frequency,
 RC is comparable to T/2, so the capacitor charges and discharges
appreciably in each half cycle.

Figure 1.47 Example 1.25: (a) circuit diagram and (b) input waveform.

Transient response. The transient response is as shown in Figure 1.48(a).

Assume that the capacitor is uncharged initially. So vo = 0 for t < 0. Since at
t = 0, the input rises to +1V abruptly, the output also rises abruptly by +1V.
Steady-state analysis. The steady-state output is as shown in Figure
1.48(b). Under steady-state conditions, the capacitor charges and discharges
to the same levels in each cycle.
Since the input is a symmetrical square wave,

The peak-to-peak value of input = V

 Figure 1.48 Example 1.25: (a) transient response and (b) steady-state response.

EXAMPLE 1.26 A square-wave whose peak-to-peak value is 1 V extends

0.5 V, with respect to ground. The duration of the positive section is 0.1 s
and of the negative section 0.2 s. If this waveform is impressed upon an RC
differentiating circuit whose time constant is 0.2 s, what are the steady-state
maximum and minimum values of the output waveform? Prove that the area
under the positive section equals that under the negative section of the
output waveform. What is the physical significance of this result?

Solution: The given square wave shown by dotted lines in Figure 1.49(b) is
applied to the RC high-pass circuit shown in Figure 1.49(a).

Figure 1.49 Example 1.26: (a) circuit diagram and (b) steady-state output.
The steady-state output waveform is shown by the thick line in Figure
1.49(b).

The capacitor blocks the dc component of the input. Hence the average
value of the output must be zero. So under steady-state, the area A1 under
the positive section of the output curve is equal to the area A2 under the
negative section.
EXAMPLE 1.27 The square wave shown in Figure 1.50(b) is fed to an RC
coupling network. What are the output voltage waveforms if (a) RC is very
large, say, RC = 10T, and (b) RC is very small, say, RC = T/10.

Figure 1.50 Example 1.27: (a) circuit diagram and (b) square waveform.

Solution: The square wave shown in Figure 1.50(b) is applied to the RC

high-pass circuit shown in Figure 1.50(a).
(a) When the time constant is very large (RC = 10T) the capacitor charges
and discharges very slowly. The output is in the form of a tilt. The output
waveform under transient and steady-state conditions is shown in Figure
1.51.
Transient response. The transient response is shown in Figure 1.51(a).
For t < 0, vi = 0, and hence vo = 0 and the capacitor is uncharged.
At t = 0, vi = 300 V
 Figure 1.51 Example 1.27: (a) transient response and (b) steady-state response.

Since the voltage across the capacitor cannot change instantaneously, vo

is also equal to 300 V at t = 0

Steady-state response. The steady-state response is shown in Figure

1.51(b). Under steady-state, the output waveform is symmetrical with
respect to zero voltage line because the capacitor blocks dc and the average
value of the output is 0 volts.
 Since the time constant is very small, the capacitor charges and
discharges very fast. The output is in the form of peaks as shown in Figure
1.52.

Figure 1.52 Example 1.27: response of RC coupling network when RC = T/10.

EXAMPLE 1.28 Determine the steady-state response of a high-pass RC

circuit with time constant 1 ms to a square wave input shown in Figure
1.53.

Figure 1.53 Example 1.28: square wave input waveform.

Solution: The square wave shown in Figure 1.53 is applied to the RC high-
pass circuit shown in Figure 1.54(a). Since the RC high-pass circuit has a
blocking capacitor, the dc or average value of the output is zero. Therefore,
the positive area of the output is equal to the negative area of the output
over one cycle, i.e. the output alternates with respect to the zero voltage
line. The output waveform under steady-state conditions is shown in Figure
1.54. The voltage levels on the output waveform are calculated as follows:

Figure 1.54 Example 1.28: steady-state response of the high-pass RC circuit.

EXAMPLE 1.29 A 1 kHz square wave output from an amplifier has rise
time tr = 350 ns and tilt = 5%. Determine the upper and the lower 3-dB
frequencies.

Solution: The amplifier has upper and lower 3-dB frequencies. So it acts as
a combination of low-pass and high-pass filters, that is, as a band-pass filter.
The upper cut-off frequency of a low-pass filter can be determined from the
information about the rise time tr. The lower cut-off frequency of a high-
pass filter can be determined from the information about % tilt.
EXAMPLE 1.30 The pulse from a high voltage generator rises linearly for
0.05 s, and then remains constant for 1 s. The rate of rise of the pulse is
measured with an RC differentiating circuit whose time constant is 250 ps.
If the positive output voltage from the differentiator has a maximum value
of 50 V, what is the peak voltage of the generator?

Solution: The pulse shown by the dotted line in Figure 1.55(b) is applied to
the RC high-pass circuit shown in Figure 1.55(a). The output waveform is
shown by the thick line in Figure 1.55(b).
–12
The time constant RC = 250 ps = 250  10 s

Vo(max) = 50 V

The time constant is very small compared to the duration of the ramp, i.e.
RC << T.
 Figure 1.55 Example 1.30: (a) circuit diagram and (b) output waveform.

EXAMPLE 1.31 The limited ramp shown in Figure 1.56 (by dotted line) is
applied to an RC differentiator. Draw the output waveforms for the cases:
(a) T = 0.2RC, (b) T = RC, and (c) T = 5RC.

Solution: The limited ramp shown by the dotted line in Figure 1.56(b) is
applied to the RC high-pass circuit shown in Figure 1.56(a). For the ramp
input, slope where T is the duration of the ramp and V the amplitude

of the ramp at t = T. The output for a ramp input is given by

 Figure 1.56 Example 1.31: (a) circuit diagram and (b) input and output waveforms of an RC
differentiator.

EXAMPLE 1.32 A 100 Hz triangular wave with peak-to-peak amplitude of

9 V is applied to a differentiating circuit with R = 1 M and C = 100 pF.
Calculate and sketch the waveform of the output.

Solution: The triangular wave shown by the dotted line in Figure 1.57 is
applied to the RC high-pass circuit shown in Figure 1.30. The time constant
of the RC circuit is
6 –12
RC = 1  10  100  10 = 100 s

Frequency of the triangular wave, f = 100 Hz

 Since the time constant of the circuit is very small compared to the period
of the input waveform, the circuit acts as a differentiator and the output
waveform is in the form of a square wave having excursions from aRC
(when slope is positive) to – aRC (when slope is negative), i.e.

The output is a square wave with levels +aRC and –aRC as shown in
Figure 1.57.

Figure 1.57 Example 1.32: input and output waveforms of a differentiating circuit.

EXAMPLE 1.33 A pulse with a rise time tr = 500 ns and a fall time tf = 1
s, pulse amplitude = 12 V, and pulse width = 10 s is applied to a
differentiating circuit with C = 200 pF and R = 470 . Determine the
amplitude of the differentiated output. Sketch the waveforms across R and
C.

Solution: The pulse shown in Figure 1.58(b) is applied to the RC high-pass

circuit shown in Figure 1.58(a). The input is exponential. The time constant
of the rising waveform is
Figure 1.58 Example 1.33: output waveforms (a) circuit diagram,
(b) voltage across R, and (c) voltage across C.
 The waveforms across R and C are shown in Figures 1.58(b) and (c)
respectively.

EXAMPLE 1.34 A step generator of 50  impedance applies a 10 V step

of 2.2 ns rise time to a series combination of a capacitance C and a
resistance R = 50 . There appears across R a pulse of amplitude 1 V. Find
the value of the capacitance C.

Solution: The actual step shown in Figure 1.59(b) is applied to the RC high-
pass circuit shown in Figure 1.59(a). The output waveform is as shown in
Figure 1.59(b).
 Figure 1.59 Example 1.34: (a) circuit diagram and (b) output waveform.

EXAMPLE 1.35 Prove that for the same input, the output from the two
differentiating circuits shown in Figure 1.60 will be the same if RC = L/R.
Assume zero initial conditions.

Figure 1.60 Example 1.35: RC and RL differentiating circuits.

 From the above equations for vi, we can see that if RC = L/R, the
outputs from the differentiator circuits are the same.

1.6 ATTENUATORS
Attenuators are resistive networks, which are used to reduce the amplitude
of the input signal. The simple resistor combination of Figure 1.61(a) would
multiply the input signal by the ratio a = R2/(R1 + R2) independently of the
frequency. If the output of the attenuator is feeding a stage of amplification,
the input capacitance C2 of the amplifier will be the stray capacitance
shunting the resistor R2 of the attenuator and the attenuator will be as
shown in Figure 1.61(b), and the attenuation now is not independent of
frequency. Using Thevenin’s theorem, the circuit in Figure 1.61(b) may be
replaced by its equivalent circuit shown in Figure 1.61(c), in which R is
equal to the parallel combination of R1 and R2. Normally R1 and R2 must
be large so that the nominal input impendence of the attenuator is large
enough to prevent loading down the input signal. But if R1 and R2 are large,

the rise time tr = 2.2 will be large and a large rise time is

normally unacceptable.
The attenuator may be compensated by shunting R1 by a capacitor C1 as
shown in Figure 1.61(d), so that its attenuation is once again independent of
frequency. The circuit has been drawn in Figure 1.61(e) to suggest that the
two resistors and the two capacitors may be viewed as the four arms of a
bridge. If R1C1 = R2C2, the bridge will be balanced and no current will
flow in the branch connecting the point X to the point Y. For the purpose of
computing the output, the branch X-Y may be omitted and the output will
again be equal to avi independent of the frequency. In practice, C1 will
ordinarily have to be made adjustable.
 Figure 1.61 An attenuator: (a) ideal circuit, (b) actual circuit, (c) equivalent circuit,
(d) compensated attenuator, and (e) compensated attenuator redrawn as a bridge.

Suppose a step signal of amplitude V volts is applied to the circuit. As the

input changes abruptly by V volts at t = 0, the voltages across C1 and C2
will also change abruptly. This happens because at t = 0, the capacitors act
as short-circuits and a very large (ideally infinite) current flows though the
capacitors for an infinitesimally small time so that a finite charge
is delivered to each capacitor. The initial output voltage is
determined by the capacitors.
 Since the same current flows through the capacitors C1 and C2, we have

The final output voltage is determined by the resistors R1 and R2,

because the capacitors C1 and C2 act as open circuits for the applied dc
voltage under steady-state conditions. Hence

Looking back from the output terminals (with the input short circuited)
we see a resistor R = R1R2/(R1 + R2) in parallel with C = C1 + C2. Hence
the decay or rise of the output (when the attenuator is not perfectly
compensated) from the initial to the final value takes place exponentially
with a time constant t = RC. The responses of an attenuator for C1 equal to,
greater than, and less than R2C2/R1 are indicated in Figure 1.62.

Figure 1.62 Response of compensated attenuator: (a) perfect compensation,

(b) over compensation, and (c) under compensation.

+
Perfect compensation is obtained if vo(0 ) = vo(), that is, if the rise
time tr = 0
 +
This is the balanced bridge condition. The extreme values of vo(0 ) are 0
for C1 = 0 and V for C1 = .
In the above analysis we have assumed that an infinite current flows
+
through the capacitors at t = 0 and hence the capacitors get charged
instantaneously. This is valid only if the generator resistance is zero. In
general, the output resistance of the generator is not zero but is of some
finite value. Hence the impulse response is physically impossible. So, even
though the attenuator is compensated, the ideal step response can never be
obtained. Neverthless, an improvement in rise time does result if a
compensated attenuator is used. For example, if the output is one-tenth of
the input, then the rise time of the output using the attenuator is one-tenth of
what it would be without the attenuator.
The compensated attenuator will reproduce faithfully the signal, which
appears at its input terminals. However, if the output impedance of the
generator driving the attenuator is not zero, the signal will be distorted right
at the input to the attenuator. This situation is illustrated in Figure 1.63(a) in
which a generator of step voltage V and of source resistance RS is
connected to the attenuator. Since the lead which joins the point X and point
Y may be open circuited, the circuit may be redrawn as in Figure 1.63(b).
Usually RS << R1 + R2, so the input to the attenuator will be an exponential
of time constant RSC, where C is the capacitance of the series

combination of C1 and C2, i.e. C = C1C2/(C1 + C2). It is this exponential

waveform rather than the step, which the attenuator will transmit faithfully.
 Figure 1.63 (a) Compensated attenuator including source resistance RS and
(b) its equivalent circuit with vi = V(R1 + R2)/(RS + R1 + R2).

If the generator terminals were connected directly to the terminals to

which the attenuator output is connected, the generator would see a
capacitance C2. In this case the waveform at these terminals would be an
exponential with time constant t = RSC2. When the attenuator is used, the
time constant is t = RSC.

an improvement in waveform results. For example, if the attenuation is

equal to 10(a = 1/10), then the rise time of the waveform would be divided
by a factor 10.

1.6.1 Application of Attenuator as a CRO Probe

To measure the signal at a point in the circuit, the input terminals of the
oscilloscope are connected to the signal point. Normally the point at which
the signal is available will be at some distance from the oscilloscope
terminals and if the signal appears at a high impedance level, a shielded
cable is used to connect the signal to the oscilloscope. The shielding is
necessary in this case to isolate the input lead from stray fields such as those
of the ever-present power line. The capacitance seen looking into several
feet of cable may be as high as 100 to 150 pF. This combination of high
input capacitance together with the high output impedance of the signal
source will make it impossible to make faithful observations of waveforms.
A probe assembly, which permits the use of shielded cable and still keeps
the capacitance low, is indicated in Figure 1.64.

Figure 1.64 A cathode ray oscilloscope probe.

EXAMPLE 1.36 Compute and draw to scale the output waveform for (a)
C1 = 50 pF, (b) C1 = 75 pF, and (c) C1 = 25 pF respectively for the circuit
shown in Figure 1.65. The input is a 20 V step.
 Figure 1.65 Example 1.36: (a) circuit diagram and (b) output waveforms.

Solution: In the circuit shown in Figure 1.65(a), for perfect compensation

Therefore,
(a) When C1 = 50 pF, the attenuator would be perfectly compensated.
The rise time of the output waveform tr = 0. So the output would be an
exact replica of the input but with reduced amplitude.
 Rise time, tr = 2.2RC = 2.2  37.5 = 82.5 s

The output waveforms for the above three cases are shown in Figure
1.65(b).

EXAMPLE 1.37 An oscilloscope test probe is indicated in Figure 1.66.

Assume that the cable capacitance is 100 pF. What is (a) the attenuation of
the probe, (b) the value of C for best response, and (c) the input impedance
of the compensated probe?
 Figure 1.66 Example 1.37: an oscilloscope test probe.

Solution: In Figure 1.66 the cable can be replaced by a capacitance of 100

pF. This cable capacitance of 100 pF is in parallel with the 10 pF input
capacitance of the oscilloscope as shown in Figure 1.67. Also, 0.28 M
resistance of the probe is in parallel with the 2 M input resistance of the
oscilloscope.

Figure 1.67 Example 1.37: equivalent circuit of Figure 1.66.

 (c) The input impedance of the compensated probe, Zi = 4.7 + 0.245 =
4.945 M

Figure 1.68 Example 1.37: equivalent circuit of Figure 1.67.

EXAMPLE 1.38 A 50  pulse generator produces 500 s pulses with

negligible rise time and 5 V positive amplitude into an open circuit. If the
bottom of the pulse train is zero and duty cycle is 25%, determine the pulse
shape, i.e. the amplitude, the rise time and the fall time after it has passed
through the circuits shown in Figures 1.56(b) and (c).

Figure 1.69 Example 1.38: (a) input waveform, and (b) and (c) circuit diagrams.
Solution: For the waveform shown in Figure 1.69(a),

The rise time of the pulse is negligible. So, it is treated as ideal as shown in
Figure 1.69(a).
Figure 1.70 Example 1.38: (a) output waveform of Figure 1.69(b) and (b) output waveform of Figure
1.69(c).

EXAMPLE 1.39 For the circuit shown in Figure 1.58(a), the input is a 20
V step. Calculate and plot to scale the output voltage.

Solution: In the circuit shown in Figure 1.71(a), for perfect compensation,

the required value of

Though the input is a step, it is not impressed on the attenuator network

due to source resistance. The input to the attenuator is, therefore, given by
 Figure 1.71 Example 1.39: (a) circuit diagram and (b) the output waveforms.

EXAMPLE 1.40 For the circuit and the input waveform shown in Figure
1.72(a), draw roughly the output waveform vo. Make reasonable
approximations and estimate the rise time of the waveforms, the magnitude
of the overshoot and the time constant of the decay to the final value.

Figure 1.72 Example 1.40: (a) the circuit diagram and (b) the output waveforms.

Solution: In the circuit shown in Figure 1.72(a), for perfect compensation,

the required value of
 Since actual C1 is 60 pF, the attenuator is overcompensated. Because RS
 0, the step input of 1 V will be distorted and will not appear at the input
to the attenuator with zero rise time.

1.7 RL CIRCUITS
In Sections 1.1 and 1.2, we discussed the behaviour of RC low-pass and
high-pass circuits for various types of input waveforms. Suppose the
capacitor C and resistor R in those circuits are replaced by a resistor R and
an inductor L respectively, then, if the time constant L/R equals the time
constant RC, all the preceding results remain unchanged.
When a large time constant is required, the inductor is rarely used
because a large value of inductance can be obtained only with an iron-core
inductor which is physically large, heavy and expensive relative to the cost
of a capacitor for a similar application. Such an iron-cored inductor will be
shunted with a large amount of stray distributed capacitance. Also the
nonlinear properties of the iron cause distortion, which may be undesirable.
If it is required to pass very low frequencies through a circuit in which L is
a shunt element, then the inductor may become prohibitively large. Of
course in circuits where a small value of R is tolerable, a more reasonable
value of inductance may be used. In low time constant applications, a small
inexpensive air-cored inductor may be used.
Figure 1.73(a) shows the RL low-pass circuit. At very low frequencies the
reactance of the inductor is small, so the output across the resistor R is
almost equal to the input. As the frequency increases, the reactance of the
inductor increases and so the signal is attenuated. At very high frequencies
the output is almost equal to zero. So the circuit in Figure 1.73(a) acts as a
low-pass filter.
The circuit of Figure 1.73(b) acts as a high-pass circuit because at low
frequencies, since the reactance of the inductor is small, the output across
the inductor is small and the output increases as the frequency increases
because the reactance of the inductor increases as the frequency increases
and at high frequencies the output is almost equal to the input.

Figure 1.73 (a) RL low-pass circuit and (b) RL high-pass circuit.

 Figure 1.74 shows how a square wave may be converted into pulses by
means of the peaking coil L. It is assumed that the bias voltage and the
magnitude of the input are such that the transistor operates linearly. Since
the instantaneous voltage L(di/dt) across an inductor cannot be infinite, the
current through an inductor cannot change instantaneously. Hence the
inductor acts as an open circuit at the time of an abrupt change in voltage.
Figure 1.74(a) shows a transistor peaking circuit. The input current
waveform is shown in Figure 1.74(b). The output voltage waveform is
shown in Figure 1.74(c).
If the base input is a square wave of current whose peak-to-peak value is
I, then the output voltage will have the waveform as in Figure 1.74(c). The
peak voltage is now hfeI/hoe and the time constant is hoeL assuming that
the transistor can be replaced by its low-frequency hybrid parameter model.
 Figure 1.74 (a) Peaking circuit, (b) its input waveform, and (c) its output waveform.

1.8 RLC CIRCUITS

1.8.1 RLC Series Circuit
Consider a series RLC circuit shown in Figure 1.75.

Figure 1.75 A series RLC circuit.

Writing the KVL around the loop, we obtain

 2
If (R/2L) > 1/LC, i.e. , both the roots are real and different. The
2
circuit is overdamped and there are no oscillations in the output. If (R/2L)
= 1/LC, i.e. , both the roots are real and equal. The circuit is
2
critically damped. If (R/2L) < 1/LC, i.e. , the roots are complex
conjugate of each other. The circuit is underdamped and there will be
oscillations in the output. The output is a sinusoid whose amplitude decays
with time.
The current response is:

The response of i(t) and the response of vo(t) for the above three cases are
shown in Figures 1.76(a) and 1.76(b) respectively.
 Figure 1.76 (a) Current response and (b) voltage response of series RLC circuit to a step voltage.

1.8.2 RLC Parallel Circuit

In the RL circuit shown in Figure 1.73(b), to include the effect of coil
winding capacitance, output capacitance and stray capacitance to ground, a
capacitor is added across the output. So, the RLC circuit shown in Figure
1.77(a) results. In terms of a current source, the equivalent circuit shown in
Figure 1.77(b) results.
The transfer function of the network of Figure 1.77(a) is
 In the series RLC network, the current response to a step input voltage
ultimately dies to zero because of the capacitor in series. In the parallel RLC
circuit the voltage across the RLC network is zero because of the
inductance.

Figure 1.77 (a) vi is applied through R to a parallel LC circuit and

(b) parallel RLC circuit driven by a current source.

1.9 RINGING CIRCUIT

In a previous section it was seen that to obtain a pulse from a step voltage
(peaking) the circuit should operate in the neighbourhood of critical
damping. In some applications almost undamped oscillations are required.
A circuit, which can provide as nearly undamped oscillations as possible is
called a ringing circuit. If the damping is very small the circuit will ring for
many cycles. Many times the value of Q of a circuit which has to ring for a
given number N of cycles before the amplitude decreases to 1/ of its
initial value needs to be known. This is given by Q = pN.
Thus, a circuit with Q = 12 will ring for Q/p = 4 cycles before the
amplitude of the oscillation decreases to 37 per cent of its initial value. A
ringing circuit may be used to generate a sequence of pulses regularly
spaced in time. These pulses find application in many timing operations.
 SHORT QUESTIONS AND ANSWERS
1. What do you mean by a linear network?
A. A linear network is a network made up of linear elements only. It
can be described by linear differential equations. The principle of
superposition and the principle of homogeneity hold good for linear
networks.
2. Name the signals which are commonly used in pulse circuits?
A. The signals which are commonly used in pulse circuitry are: (a) sine
wave, (b) step, (c) pulse, (d) square wave, (e) ramp and (f) exponential.
3. Define the following types of waveforms: (a) sine, (b) step, (c) pulse,
(d) square, (e) ramp, and (f) exponential.
A. (a) A sinusoidal signal is a periodic signal given by
e(t) = Em sinwt
where e(t) is the instantaneous value, Em is the maximum value and w
is the frequency of oscillation of the signal.
(b) A step signal is one which maintains the value zero for all times t <
0, and maintains the value V for all times t > 0. The transition
between the voltage levels takes place at t = 0 and is accomplished in
an arbitrarily small time interval.
v(t) = 0 for t < 0
= V for t ≥ 0
(c) A pulse signal is one which maintains the value zero for all times t
< 0 and t > tp, and maintains the value V for 0 < t < tp. The transition
between the two voltage levels takes place at t = 0 and t = tp and is
accomplished in an arbitrarily small time interval.
v(t) = 0 for t < 0 and for t > tp
= V for 0 < t < tp
(d) A square wave is a periodic waveform which maintains itself at one
constant level V with respect to ground for a time T1 and then
changes abruptly to another level V and remains constant at that
level for a time T2, and repeats itself at regular intervals of T1 + T2.
v(t) = V for 0 < t < T1
 = V≤ for T1 < t < T1 + T2
(e) A ramp signal is one which maintains the value zero for t < 0, and
which increases linearly with time for t > 0.
v(t) = 0 for t < 0
= at for t > 0
(f) An exponential signal is one which maintains the value zero for t <
0, and rises exponentially for t > 0
v(t) = 0 for t < 0
= V(1 – e–t/t) for t > 0
4. What is the unique characteristic of sinusoidal waveform with respect
to linear wave shaping?
A. The unique characteristic of sinusoidal waveform with respect to
linear wave shaping is that it preserves its shape when it is transmitted
through a linear network, i.e. under steady-state, the shape of the output
will be a precise reproduction of the input sinusoidal signal.
5. Why are sinusoidal waveforms popular?
A. Sinusoidal signals are very popular because:
1. Most of the physical signals available in nature are of sinusoidal
type.
2. Signal generators and precise measuring instruments are readily
available for various ranges of frequencies.
3. Sinusoidal signals can be measured easily and accurately.
4. Any non-sinusoidal signal can be resolved into a dc component and
a number of sinusoids of different harmonic frequencies.
5. They preserve their shape when transmitted through a linear
network.
6. What do you mean by linear wave shaping?
A. Linear wave shaping is the process whereby the form of a non-
sinusoidal signal is altered by transmission through a linear network.
7. Which signals can preserve their shape when transmitted through a
linear network?
A. Except sinusoidal signal, no other periodic waveform can preserve
its shape precisely when transmitted through a linear network, and in
 many cases the output signal may bear very little resemblance to the
input signal.
8. How does a capacitor behave at very low and very high frequencies?
A. At very low frequencies, the capacitor acts as an open circuit and at
very high frequencies, it acts as a short circuit.
9. How does an inductor behave at very low and very high frequencies?
A. At very low frequencies, the inductor acts as a short circuit and at
very high frequencies, it acts as an open circuit.
10. What do you mean by a low-pass circuit?
A. A low-pass circuit is a circuit which transmits only low frequency
signals and attenuates or stops high frequency signals.
11. When can the voltage across a capacitor change instantaneously?
A. The voltage across a capacitor can change instantaneously only
when an infinite current is passed through it.
12. What do you mean by cut-off frequency?
A. The cut-off frequency is the frequency at which the gain is 1/2, i.e.
0.707 of its maximum value.
13. Write the expression for the upper cut-off frequency of a low-pass
filter.
A. The expression for the upper cut-off frequency of a low-pass filter is
f2 = 1/2pRC.
14. What is the lower cut-off frequency of a low-pass circuit?
A. There is no lower cut-off frequency for a low-pass circuit. It is zero
itself.
15. How much is the bandwidth of a low-pass circuit?
A. The bandwidth of a low-pass circuit is finite. It is equal to its upper
cut-off frequency.
16. What do you mean by time constant of a circuit?
A. The time constant t of a circuit is defined as the time taken by the
output waveform to reach its final value if the initial slope is
maintained when a step signal is applied.
The time constant of a circuit is also defined as the time taken by the
output waveform to rise to 63.2% of its final value for a step input. For
RC circuits t = RC, and for RL circuits t = L/R.
17. When do you say that steady-state condition is reached?
 A. For most applications, steady-state condition is assumed to be
reached at t = 5t.
18. Write the expression for the output of a low-pass circuit excited by a
step input?
A. The expression for the output of a low-pass circuit excited by a step
input is
vo = vfinal – (vfinal – vinitial)e–t/RC
19. Define the term ‘rise time’.
A. The rise time tr is defined as the time taken by the output voltage
waveform of a low-pass circuit excited by a step input to rise from 10%
to 90% of its final value.
20. Write the expression for the rise time of a low-pass circuit?
A. The rise time of the output of a low-pass circuit excited by a step
input is given by
tr = 2.2 RC = 0.35/f2 = 0.35/BW
21. What is the relation between rise time and bandwidth of a low-pass
circuit?
A. The relation between rise time and bandwidth of a low-pass circuit
is tr = 0.35/BW, i.e. rise time is inversely proportional to bandwidth.
22. When does a low-pass circuit preserve the pulse shape?
A. A low-pass circuit preserves the pulse shape if the 3-dB frequency is
approximately equal to the reciprocal of the pulse width.
23. Write the expression for the output of a low-pass circuit excited by a
symmetrical square wave?
A. The peak value of the output of a low-pass circuit excited by a
symmetrical square wave is

24. Write the expression for the output of a low-pass circuit excited by a
ramp input?
A. The output of a low-pass circuit excited by a ramp input is given by
 vo(t) = at – aRC + aRC e–t/RC
When RC is very small, vo(t) = a(t – RC)
When RC is very large, vo(t) = at2/2RC
25. Write the expression for the transmission error of a low-pass circuit.
A. The transmission error of a low-pass circuit is et = RC/T = 1/2pf2T.
26. When does a low-pass circuit act as an integrator?
A. A low-pass circuit acts as an integrator if its time constant is very
large in comparison with the time required for the input signal to make
an appreciable change.
27. What is the criterion for good integration in terms of steady-state
analysis?
A. A criterion for good integration in terms of steady-state analysis is
that the low-pass circuit acts as an integrator provided the time constant
of the circuit RC > 15T, where T is the period of the input sine wave.
28. What must be the phase shift between sinusoidal input and steady-
state output of a perfect integrator?
A. The phase shift between the sinusoidal input and steady-state output
of a perfect integrator must be 90°.
29. Why are integrators almost invariably preferred over differentiators in
analog computer applications?
A. Integrators are almost invariably preferred over differentiators in
analog computer applications because:
1. It is easier to stabilize an integrator than a differentiator because, the
gain of an integrator decreases with frequency, whereas the gain of a
differentiator increases with frequency.
2. An integrator is less sensitive to noise voltages than a differentiator
because of its limited bandwidth.
3. The amplifier of a differentiator may overload if the input waveform
changes very rapidly.
4. It is more convenient to introduce initial conditions in an integrator.
30. What do you mean by a high-pass circuit?
A. A high-pass circuit is a circuit which attenuates low frequency
signals and allows transmission of high frequency signals with little or
 no attenuation.
31. What is the upper cut-off frequency of a high-pass circuit?
A. There is no upper cut-off frequency for a high-pass circuit. It is
equal to infinity itself.
32. Write the expression for the lower cut-off frequency of a high-pass
circuit?
A. The expression for the lower cut-off frequency of an RC high-pass
circuit is f1 = 1/2pRC.
33. Why is the capacitor in an RC high-pass circuit called a blocking
capacitor?
A. The capacitor in an RC high-pass circuit is called a blocking
capacitor because it blocks the dc components from going from input to
output.
34. Which circuit is called a capacitive coupling circuit?
A. An RC high-pass circuit is called a capacitive coupling circuit.
35. What must be the time constant of a high-pass circuit for the output to
be in the form of a tilt for a square wave input?
A. For the output of a high-pass circuit to be in the form of a tilt for a
square wave input, the time constant must be large compared to the
period of the input waveform.
36. What must be the time constant of a high-pass circuit for the output to
be in the form of spikes for a square wave input?
A. For the output of a high-pass circuit to be in the form of spikes for a
square wave input, the time constant of the circuit must be very small
compared to the period of the input waveform.
37. Why does the output of a high-pass circuit contain zero dc value
independent of the dc value of the input?
A. The output of a high-pass circuit contains zero dc value independent
of the dc value of the input because the capacitor in the series arm
blocks all input dc components from going to the output.
38. Write the expression for the % tilt of a high-pass circuit excited by a
symmetrical square wave.
A. The expression for the % tilt of a high-pass circuit excited by a
symmetrical square wave is
39. What conclusions can be drawn with respect to a high-pass circuit?
A. The following conclusions can be drawn with respect to a high-pass
circuit:
1. The average value of the output signal is always zero, independent of
the average level of the input. The output must consequently extend
in both negative and positive directions with respect to the zero
voltage axis, and the area of the part of the waveform above the zero
axis must equal the area which is below the zero axis.
2. When the input changes abruptly by an amount V, the output also
changes abruptly by an equal amount and in the same direction.
3. During any finite time interval when the input maintains a constant
level, the output decays exponentially towards zero voltage.
40. Write the expression for the output of a high-pass circuit excited by a
ramp input?
A. The output of a high-pass circuit excited by a ramp input is
vo(t) = aRC(1 – e–t/RC), for t < RC, vo(t) = at (1 – t/2RC)
41. What do you mean by transmission error?
A. When a ramp signal is transmitted through a linear network, the
output departs from the input. Transmission error et is a measure of this
departure from linearity.
42. Define transmission error?
A. The transmission error is defined as the difference between the input
and the output divided by the input at the end of the sweep.
43. Write the expression for the transmission error of high-pass circuit
excited by a ramp input.
A. The transmission error of a high-pass circuit excited by a ramp input
is et = pf1T.
44. When does a high-pass circuit act as a differentiator?
A. A high-pass circuit acts as a differentiator when the time constant of
the circuit is very small in comparison with the time required for the
input signal to make an appreciable change.
45. What is the criterion for good differentiation in terms of steady-state
analysis?
A. The criterion for good differentiation in terms of steady-state
analysis is that the phase-shift between the input and output sinusoids
must be at least 89.4°, i.e. wRC  0.01.
46. What is the derivative of a step signal?
A. The derivative of a step signal is an impulse of infinite amplitude at
the occurrence of the discontinuity of the step.
47. What is the derivative of an ideal pulse?
A. The derivative of an ideal pulse is a positive impulse followed by a
delayed negative impulse, each of infinite amplitude and occurring at
the points of discontinuity.
48. What is the derivative of a square wave?
A. The derivative of a square wave is a waveform which is uniformly
zero except at the points of discontinuity where impulses of infinite
amplitude, zero width and alternating polarity occur.
49. When can the current through an inductor change instantaneously?
A. The current through an inductor can change instantaneously only if
the instantaneous voltage across it can be made infinite.
50. Why are RC circuits commonly used compared to RL circuits?
A. RC circuits are commonly used compared to RL circuits because
when a large time constant is required, the inductor is rarely used
because a large value of inductance can be obtained only with an iron
core inductor which is physically large, heavy and expensive relative to
the cost of a capacitor for a similar application. Such an iron-cored
inductor will be shunted with large distributed capacitance. Also the
nonlinear properties of the iron cause distortion which may be
undesirable. If it is required to pass very low frequencies through a
circuit in which L is a shunt element, then the inductor may become
prohibitively large.
51. What do you mean by a peaking coil?
A. A peaking coil is a coil connected in the collector terminal of a
transistor peaking circuit to convert the input waveform into peaks at
the points of discontinuity.
52. What do you mean by an attenuator?
 A. An attenuator is a resistive network used to reduce the amplitude of
the input signal.
53. Why does a resistive attenuator need to be compensated?
A. A resistive attenuator needs to be compensated inorder to reduce or
eliminate the rise time of the output waveform.
54. How is an attenuator compensated?
A. An attenuator may be compensated by shunting R1 by a capacitor
C1 so that the attenuation is independent of frequency.
55. What do you mean by (a) perfect compensation, (b) over
compensation, and (c) under compensation?
A. (a) Perfect compensation means, the value of C1 selected is such
that
vo(0+) = vo() : C1 = R2C2/R1, i.e. R1C1 = R2C2
(b) Over compensation means, the value of C1 selected is such that

vo(0+) > vo() : C1 > R2C2/R1

(c) Under compensation means, the value of C1 selected is such that

vo(0+) < vo() : C1 < R2C2/R1

56. Why is the initial voltage distribution in an attenuator determined by
the capacitors?
A. The initial voltage distribution in an attenuator is determined by the
capacitors because at t = 0, they act as short circuits and so a very large
current passes through them and no current passes through the resistors.
57. Why is the final voltage distribution in an attenuator determined by
the resistors?
A. The final voltage distribution in an attenuator is determined by the
resistors because at t = , the capacitors act as open circuits, no current
passes through them and all the current passes through the resistors
only.
58. What is the effect of the output resistance of the generator on an
attenuator output?
A. The effect of the output resistance of the generator on an attenuator
output is, the output waveform gets distorted.
59. If the output of an attenuator is 1/10 of its input, what is the rise time
of the output if the rise time of the input is tr?
A. If the output of an attenuator is 1/10 of its input, the rise time of the
output will be tr/10 for an input rise time of tr.
60. In low time constant applications, what type of inductor is used?
A. In low time constant applications, a small inexpensive air cored
inductor is used.
61. What do you mean by peaking?
A. The process of converting pulses into pips by means of a circuit of
very short time constant is called peaking.
62. What do you mean by a ringing circuit?
A. A ringing circuit is a circuit which can provide as nearly undamped
oscillations as possible.
63. What is the use of a ringing circuit?
A. A ringing circuit may be used to generate a sequence of pulses
regularly spaced in time.
64. In series RLC network, why does the current response to a step input
voltage ultimately die to zero?
A. In the series RLC network, the current response to a step input
voltage ultimately dies to zero because the capacitor acts as an open
circuit for dc.
65. Why does the voltage across the parallel RLC network become zero
for a step input?
A. The voltage across the parallel RLC network becomes zero for a step
input because the inductor acts as a short circuit for dc.

REVIEW QUESTIONS
1. With the help of circuit diagrams, explain the working of RC and RL
low-pass circuits.
2. Derive an expression for the upper cut-off frequency of a low-pass
circuit.
3. Derive an expression for the output of a low-pass circuit excited by a
step input.
 4. Derive an expression for the rise time of the output of a low-pass
circuit excited by a step input.
5. Obtain the relation between rise time and bandwidth of a low-pass
circuit.
6. Derive an expression for the output voltage levels under steady-state
conditions of a low-pass circuit excited by a square wave input.
7. Derive an expression for the output of a low-pass circuit excited by a
ramp input.
8. Derive an expression for the output of a low-pass circuit excited by an
exponential input.
9. Draw the output waveforms of a low-pass circuit excited by step,
pulse, square wave, ramp and exponential waveforms for different time
constants.
10. Show that a low-pass circuit with a large time constant acts as an
integrator.
11. With the help of circuit diagrams explain the working of high-pass RC
and RL circuits.
12. Derive an expression for the lower cut-off frequency of a high-pass
circuit.
13. Derive an expression for the percentage tilt of the output of a high-pass
circuit with large time constant excited by a symmetrical square wave
with zero average value.
14. Show that for any periodic input waveform, the average level of the
steady-state output waveform of the RC high-pass circuit is always
zero independent of the dc level of the input.
15. Derive an expression for the output of a high-pass circuit excited by a
ramp input.
16. Derive an expression for the output of a high-pass circuit excited by an
exponential input.
17. Draw the output waveforms of a high-pass circuit excited by step,
pulse, square wave, ramp and exponential waveforms for different time
constants.
18. Show that a high-pass circuit with a small time constant acts as a
differentiator.
19. How can the rate of rise of a pulse be measured by using a
differentiator?
20. Draw the circuit of the double differentiator.
21. Derive the condition for perfect compensation of an attenuator.
22. Discuss the application of an attenuator as a CRO probe.
23. Write short notes on (a) RL circuits, (b) RLC series circuits, (c) RLC
parallel circuits, and (d) ringing circuits.

FILL IN THE BLANKS

1. A network which can be mathematically described by linear constant
coefficient differential equations is called a .
2. The process whereby the form of a non-sinusoidal signal is altered by
transmission through a linear network is called .
3. Except for the signal, no other signal can preserve its form
when it is transmitted through a linear network.
4. A circuit passes low frequency signals and attenuates high
frequency signals.
5. The frequency at which the gain is of its maximum value
is called the cut-off frequency.
6. The lower cut-off frequency of a low-pass circuit is .
7. The upper cut-off frequency of a low-pass circuit is and is
equal to its and is given by f2 = .
8. At very high frequencies, the capacitor acts almost as a
and at very low frequencies, the capacitor acts almost as an
.
9. The capacitor the dc signal.
10. At the cut-off frequency of the RC circuit, the reactance is
equal to the and the gain is .
11. A signal which maintains the value zero for all times t < 0, and
maintains the value V for all times t ≥ 0, is called a .
12. The expression for the output of a low-pass circuit excited by a step
input is vo = .
13. is defined as the time taken by the output to rise from 10%
to 90% of its final steady-state value for a step input.
14. The rise time of a waveform is directly proportional to the
and inversely proportional to the .
15. The rise time tr of a waveform is given by tr = .
16. In an RC circuit, for a step input, if the initial slope of the output
voltage across the capacitor is maintained constant, the output reaches
its final value in one .
17. For most applications, the steady-state condition is assumed to be
reached at t = .
18. A pulse may be treated as the sum of a followed by a
delayed of the same amplitude.
19. A pulse shape is preserved when it is passed through a low-pass
circuit, if the 3-dB frequency is approximately equal to the
of the pulse width.
20. A periodic waveform which maintains itself at one constant level V
with respect to ground for a time T1, and then changes abruptly to
another level V≤ and remains constant at that level for a time T2, and
repeats itself with a period T = T1 + T2 is called a .
21. Under conditions, the capacitor in the RC circuit charges
and discharges to the same level in each cycle. So the shape of the
output waveform is fixed.
22. A waveform which is zero for t < 0, and which increases linearly with
time for t > 0 is called a or .
23. At the end of a ramp input, the difference between the input and the
output divided by the input is called the .
24. If two stages whose individual rise times are tr1 and tr2 respectively
are cascaded, the rise time of the output waveform will be tr =
.
25. A low-pass circuit acts as if the time constant of the
circuit is very large in comparison with the time required for the input
signal to make an appreciable change.
26. For an RC low-pass circuit to act as an integrator, it is necessary that
RC where T is the period of the sine wave.
27. A attenuates all low frequency signals and transmits only
signals of high frequency.
28. The lower cut-off frequency of a high-pass circuit is and
is given by f1 = .
29. The upper cut-off frequency of a high-pass circuit is and
hence its bandwidth = .
30. The capacitor in the high-pass circuit blocks the dc component of the
input from going to the output. Hence it is called a .
31. The high-pass RC circuit is called a circuit.
32. The process of converting pulses into pips by means of a circuit of
very short time constant is called .
33. A high-pass circuit with a very small time constant is called a
.
34. The output of a circuit excited by a square wave input
exhibits a tilt when the time constant of the circuit is high.
35. A high-pass circuit acts as a if the time constant of the
circuit is very small in comparison with the time required for the input
signal to make an appreciable change.
36. The derivative of a step signal is at the occurrence of the
discontinuity.
37. The derivative of an ideal pulse is a followed by a
, each of infinite amplitude and occurring at the points of
discontinuity.
38. The derivative of a square wave is a waveform which is uniformly zero
except at the points of discontinuity, where occur.
39. A high-pass circuit is treated as a differentiator if the phase shift
between the input and the output is at least .
40. For an RC high-pass circuit to act as a differentiator, it is necessary that
wRC < .
41. For double differentiation, two networks with small time
constants are connected in .
42. are almost invariably preferred over in analog
computer applications.
43. The gain of a increases with frequency but the gain of an
decreases with frequency.
44. An is less sensitive to noise voltages than a
because of its limited bandwidth.
45. If the input waveform changes very rapidly, the amplifier of a
may get overloaded.
46. It is more convenient to introduce initial conditions in
than in .
47. Attenuators are used to reduce the amplitude of the input
signal.
48. The attenuation of an ideal attenuator is of frequency.
49. The attenuator is to make the output independent of
frequency.
50. In a compensated attenuator, the initial output voltage is determined by
the and the final output voltage is determined by the
.
51. For a perfectly compensated attenuator, vo(0+) vo().
52. For an over compensated attenuator, vo(0+) vo().
53. For an under compensated attenuator, vo(0+) vo().
54. If the output of an attenuator is a times the input, the rise time of the
output will be times the rise time of the input.
55. If C and R of the low-pass and high-pass RC circuits are replaced by
R and L respectively and if = RC, then all the results of
the RC circuits are valid for the RL circuits as well.
56. RL circuits are rarely used when a time constant is
required.
57. The current through an inductor can change instantaneously if
is applied across it.
58. The voltage across a capacitor can change instantaneously if
passes through it.
59. An RLC circuit producing as nearly undamped oscillations as possible
is called a circuit.
60. A circuit may be used to generate a sequence of pulses
regularly spaced in time.

OBJECTIVE TYPE QUESTIONS

1. The waveform which preserves its form when transmitted through a
linear network is a/an
(a) sine wave
(b) step signal
(c) impulse signal
(d) ramp signal
2. The process whereby the form of a non-sinusoidal signal is altered by
transmission through a linear network is called
(a) non-sinusoidal wave shaping
(b) nonlinear wave shaping
(c) linear wave shaping
(d) none of these
3. At very low frequencies, the capacitor acts as a/an
(a) short circuit
(b) open circuit
(c) constant reactance
(d) none of these
4. At very high frequencies, the capacitor acts as a/an
(a) short circuit
(b) open circuit
(c) constant reactance
(d) none of these
5. Any constant (dc) input voltage is by a capacitor.
(a) passed
(b) blocked
(c) attenuated
(d) amplified
6. At the cut-off frequency, the capacitive reactance is equal to the
(a) resistance
(b) 2 times the resistance
(c) conductance
(d) 1/2 times the resistance
 7. For a sinusoidal input, the gain of a low-pass circuit is given by |A| =

8. If the instantaneous current through a capacitor is i, then the change in

voltage across the capacitor in time t1 is

9. At the cut-off frequency, the gain is

(a) 50 % of final value
(b) 70.7 % of final value
(c) times the final value
(d) none of these
10. The lower cut-off frequency of a low-pass RC circuit is
(a) zero
(b) 1/2pRC
(c) 
(d) none of these
11. The upper cut-off frequency of a low-pass RC circuit is
(a) zero
(b) 1/2pRC
(c) 
(d) none of these
12. An RC low-pass circuit has R = 1 k and C = 0.5 F. Its lower cut-off
frequency is
(a) zero Hz
(b) 318.3 Hz
(c) 1 kHz
(d) infinity
13. An RC low-pass circuit has R = 1 k and C = 0.1 F. Its upper cut-off
frequency is
 (a) zero Hz
(b) 159.15 Hz
(c) 687.3 Hz
(d) infinity
14. A 10 V step is applied to an RC low-pass circuit with R = 100 k and
C = 100 pF. The time for the capacitor to charge to 63.2% of final
value is
(a) 10 s
(b) 1 s
(c) 10,000 s
(d) none of these
15. A 5 V step is applied to an RC low-pass circuit with R = 10 k and C
= 100 pF. The time for the capacitor to fully charge is
(a) 1 s
(b) 0.1 s
(c) 10 s
(d) 5 s
16. The expression for the output of a low-pass circuit with time constant t
is
(a) vf – (vf – vin) e–t/t
(b) vf + (vf – vin) e–t/t
(c) vf – (vin – vf) e–t/t
(d) none of these
17. The rise time of the output of a low-pass circuit excited by a step input
is the time taken by the output to rise from
(a) 0% to 90% of its final value
(b) 10% to 90% of its final value
(c) 0% to 100% of its final value
(d) none of these
18. The time required for vo to reach 10% of the final value is given by
(a) 10RC
(b) 0.1RC
(c) 0.01RC
(d) RC
19. The time required for vo to reach 90% of the final value is given by
(a) RC
(b) 0.9RC
(c) 2.3RC
(d) 2.2RC
20. The rise time of the output of a low-pass RC circuit is given by
(a) tr = 2.2RC
(b) tr = 0.35/f2
(c) tr = 2.2t
(d) all the above
21. An RC low-pass circuit has R = 1.5 k and C = 0.2 F. The rise time
of the output waveform when excited by a step input is
(a) 0.3 ms
(b) 0.66 ms
(c) 0.75 ms
(d) 7.5 ms
22. The bandwidth of a low-pass RC circuit is 1 kHz. What is the rise time
of the output for a step input?
(a) 0.35 ms
(b) 1 ms
(c) 0.35 s
(d) none of these
23. The rise time of the output of a low-pass circuit excited by a step input
is 0.01 s. What is its bandwidth?
(a) 35 Hz
(b) 3.5 Hz
(c) 350 Hz
(d) 1 kHz
24. When a pulse is transmitted through a low-pass circuit, its shape is
preserved if the 3-dB frequency is
(a) approximately equal to the reciprocal of the pulse width
(b) approximately equal to the pulse width
(c) equal to half of the pulse width
(d) equal to double the pulse width
25. For a 0.5 s pulse to be reproduced with minimum distortion, the rise
time of the low-pass circuit must be
(a) 0.35 s
(b) 0.175 s
(c) 1 s
(d) none of these
26. To pass a 0.5 s pulse reasonably well requires a low-pass circuit with
an upper cut-off frequency of
(a) 0.5 MHz
(b) 1 MHz
(c) 2 MHz
(d) none of these
27. When an RC integrating circuit is excited by a symmetrical square
wave, for x = T/4RC, V2 =

28. For a ramp input vi = at, the output of a low-pass RC circuit is vo =

(a) a (t – RC) + a RCe–t/RC
(b) a (t + RC) + a RCe–t/RC
(c) a (t – RC) – a RCe–t/RC
(d) a (t – RC) + a RCet/RC
29. If two stages with rise times tr1 and tr2 respectively are connected in
cascade, the resultant rise time tr is given by:

30. A step signal is applied to a cascade of two circuits with rise times tr1
= 1 s and tr2 = 2 s. The rise time of the output is
(a) 2 s
(b) 0.5 s
 (c) 2.348 s
(d) 3.124 s
31. If an exponential of rise time 0.5 s is passed through a low-pass
circuit with rise time 2 s, the rise time of the output will be
(a) 1 s
(b) 2.5 s
(c) 2.164 s
(d) 2.768 s
32. The transmission error of a low-pass RC circuit for a ramp input is
given by

33. A ramp signal with a ramp time of 2 ms is transmitted through a low-

pass RC circuit with a time constant of 1 s. The transmission error is
(a) 0.5 %
(b) 2 %
(c) 1 %
(d) none of these
34. The low-pass RC circuit acts as an integrator if the time constant RC of
the circuit is
(a) very large
(b) very small
(c) zero
(d) equal to T
35. For good integration it is necessary that
(a) RC = T
(b) RC > 15T
(c) RC << T
(d) RC > T
36. For an RC low-pass circuit, if RC = 15 T, the phase shift between input
and output is
(a) 83.4°
(b) 89.4°
 (c) 90°
(d) 180°
37. The output of an RC integrating circuit is vo =

38. If the time constant of an RC low-pass circuit is very large in

comparison with the time required for the input signal to make an
appreciable change, then the circuit is called a/an
(a) differentiator
(b) integrator
(c) oscillator
(d) large amplifier
39. The capacitive coupling network is a
(a) high-pass filter
(b) low-pass filter
(c) combination of low-pass and high-pass filters
(d) none of these
40. For a high-pass circuit, the magnitude of the gain is |A| =

41. An RC high-pass circuit has R = 1 k and C = 1 s. Its upper cut-off

frequency is
(a) 15.9 Hz
(b) 1000 Hz
(c) 24.7 Hz
(d) none of these
42. The output of the RC high-pass circuit at t = tp for a pulse input is
given by vo =
(a) Vetp/RC
(b) Ve–tp/RC
 (c) Ve–(t–tp)/RC
(d) Ve–RC/tp
43. The lower cut-off frequency of a high-pass circuit is equal to
(a) zero
(b) 1/2pRC
(c) 2pRC
(d) RC
44. The upper cut-off frequency of a high-pass circuit is equal to
(a) 1/2pRC
(b) zero
(c) 
(d) 2pRC
45. The voltage across a capacitor can change instantaneously provided
(a) no current flows through it
(b) a constant current flows through it
(c) an infinite current flows through it
(d) none of these
46. For most applications, the steady-state is assumed to be reached at
(a) t = 10t
(b) t = 5t
(c) t = 
(d) t = t
47. The process of converting pulses into pips by means of a circuit of
short time constant is called
(a) pipping
(b) pulsing
(c) peaking
(d) none of these
48. The dc or average level of the output of a high-pass circuit is
(a) zero
(b) infinite
(c) same as that of the input
(d) none of these
49. The capacitor in the high-pass RC circuit is called the
(a) blocking capacitor
 (b) series capacitor
(c) input capacitor
(d) coupling capacitor
50. The area under the output waveform of a high-pass circuit over one
cycle for a periodic input is
(a) zero
(b) infinite
(c) of finite value
(d) the same as that of the input
51. The percentage tilt in the output of an RC high-pass circuit excited by
a square wave is given by P =

52. A symmetrical square wave of 1 kHz is applied to a high-pass circuit

with R = 5 k and C = 1 F. The percentage tilt of the output is
(a) 10 %
(b) 1 %
(c) 0.1 %
(d) 5 %
53. The response of an RC high-pass circuit for a ramp input for RC << Ts
is vo =
(a) a/RC
(b) sRC/a
(c) aRC
(d) none of these
54. The output of an RC differentiating circuit is vo =

55. The high-pass circuit acts as a differentiator if the time constant of the
circuit is
(a) very small
 (b) very large
(c) infinite
(d) equal to T
56. For a high-pass circuit to act as a differentiator, wRC must be less than
or equal to
(a) 0.1
(b) 0.01
(c) 0.001
(d) 1
57. For a high-pass circuit, if wRC = 0.01, the phase shift between input
and output is
(a) 84.3°
(b) 89.4°
(c) 90°
(d) 180°
58. For perfect differentiation, the phase shift between the input and output
must be
(a) 0°
(b) 90°
(c) 180°
(d) infinite
59. If the time constant of an RC high-pass circuit is very large in
comparison with the time required for the input signal to make an
appreciable change, then the circuit is called a
(a) differentiator
(b) integrator
(c) oscillator
(d) small amplifier
60. Integrators are mostly preferred over differentiators because as
frequency increases, the gain of an integrator
(a) increases
(b) decreases
(c) remains constant
(d) none of these
61. Bandwidth of an integrator is the bandwidth of a
differentiator.
(a) equal to
(b) greater than
(c) less than
(d) none of these
62. An integrator is to noise voltages than a differentiator.
(a) less sensitive
(b) more sensitive
(c) insensitive
(d) none of these
63. It is easier to stabilize than with respect to
spurious oscillations.
(a) a differentiator, an integrator
(b) an integrator, a differentiator
(c) an oscillator, an integrator
(d) a differentiator, an oscillator
64. Attenuators are resistive networks which are used to
(a) reduce the amplitude of the signal
(b) increase the amplitude of the signal
(c) maintain the amplitude of the signal constant
(d) none of these
65. Attenuators are compensated so that the attenuation
(a) is independent of frequency
(b) increases with frequency
(c) decreases with frequency
(d) none of these
66. An attenuator has R1 = 2 M, R2 = 3 M. Its attenuation factor is
(a) 0.4
(b) 0.6
(c) 1.5
(d) 0.666
67. The condition for perfect compensation of an attenuator is
(a) R1C1 > R2C2
(b) R1C1 = R2C2
 (c) R1C1 < R2C2
(d) R1/C1 = R2/C2
68. An attenuator is said to be over compensated if
(a) R1C1 > R2C2
(b) R1C1 = R2C2
(c) R1C1 < R2C2
(d) R1/C1 = R2/C2
69. An attenuator is said to be under compensated if
(a) R1C1 > R2C2
(b) R1C1 = R2C2
(c) R1C1 < R2C2
(d) R1/C1 = R2/C2
70. In a compensated attenuator R1 = 1 M, C1 = 50 pF, R2 = 2 M, C2
= 40 pF. The attenuator is
(a) under compensated
(b) over compensated
(c) perfectly compensated
(d) none of these
71. In an attenuator, the initial output voltage is determined by
(a) capacitors
(b) resistors
(c) both by capacitors and resistors
(d) none of these
72. A 15 V step is applied to an attenuator with R1 = 1 M, C1 = 25 pF,
R2 = 2 M, C2 = 50 pF. Its initial output voltage vo(0+) is
(a) 10 V
(b) 5 V
(c) 15 V
(d) none of these
73. In an attenuator, the final output voltage is determined by
(a) capacitors
(b) resistors
 (c) both by capacitors and resistors
(d) none of these
74. A 15 V step is applied to an attenuator with R1 = 1 M, C1 = 25 pF,
R2 = 2 M, C2 = 50 pF. Its final output voltage vo() is
(a) 10 V
(b) 5 V
(c) 15 V
(d) none of these
75. The output of an RL circuit will be the same as that of an RC circuit
if

76. An RLC circuit which produces as nearly undamped oscillations as

possible is called
(a) an oscillatory circuit
(b) a ringing circuit
(c) an undamped circuit
(d) none of these
77. To obtain a pulse from a step voltage, the RLC circuit should operate in
the neighbourhood of
(a) critical damping
(b) overdamping
(c) undamping
(d) none of these
78. A circuit with Q = 16 will ring for
(a) 5 cycles
(b) 8 cycles
(c) 16 cycles
(d) 32 cycles
79. The quality factor Q of a circuit, which is to ring for N number of
cycles before the amplitude reduces to 1/e of its initial value is given
by Q =
(a) pN
 (b) p/N
(c) N/p
(d) 1/pN

PROBLEMS
1.1 An ideal 2 s pulse is fed to an amplifier. Calculate and plot the
output waveform when the upper 3-dB frequency is (a) 5 MHz, and
(b) 0.05 MHz.
1.2 A symmetrical square wave whose peak-to-peak amplitude is 1 V and
whose average value is zero is applied to an RC integrating circuit.
The time constant of the circuit equals the period of the square wave.
Find the peak-to-peak value of the output waveform.
1.3 A square wave whose peak-to-peak amplitude is 4 V extends 2 V
with respect to ground. The duration of the positive section is 0.1 s and
that of the negative section is 0.3 s. If this waveform is impressed
upon an RC integrating network whose time constant is 0.3 s, what are
the steady-state maximum and minimum values of the output
waveform?
1.4 The periodic waveform shown in Figure P1.4 is applied to an RC
integrating network whose time constant is 10 s. Sketch the output
waveform. Calculate the maximum and minimum values of the output
voltages with respect to ground under steady state. Also calculate and
plot the output for the first two cycles of the input.
 Figure P1.4 Input waveform.

1.5 The square wave shown in Figure P1.5 is fed to an RC integrating

circuit. Compute and plot the output waveforms if (a) RC is large, say,
RC = 2T and (b) RC is small, say, RC = T/2.

Figure P1.5 Input waveform.

1.6 Assuming the capacitor to be initially uncharged, determine the

output response of the low-pass RC circuit with time constant 0.05 ms
to the input waveform shown in Figure P1.6.

Figure P1.6 Input waveform.

1.7 A 20 Hz symmetrical square wave whose peak-to-peak amplitude is 1

V is impressed upon a high-pass RC circuit whose lower 3-dB
 frequency is 10 Hz. Calculate and sketch the output waveform for the
first two cycles. What is the peak-to-peak output amplitude under
steady-state conditions.
1.8 A square wave whose peak-to-peak amplitude is 4 V extends 2 V
with respect to ground. The duration of the positive section is 0.3 s and
that of the negative section is 0.1 s. If this waveform is impressed on
an RC differentiating circuit whose time constant is 0.3 s, find the
steady-state maximum and minimum values of the output waveform.
1.9 The square wave shown in Figure P1.5 is fed to an RC coupling
network. Compute and plot the output waveform if (a) RC is very
large, say, RC = 10T and (b) RC is very small say RC = T/10.
1.10 Determine the steady-state response of a high-pass RC circuit with
time constant 2 ms to a square wave input shown in Figure P1.10.

Figure P1.10 Input waveform.

1.11 A 1 kHz square wave output from an amplifier has rise time tr = 250
ns and tilt = 10%, determine the upper and lower 3-dB frequencies.
1.12 The pulse from a high voltage generator rises linearly for 0.1 s and
then remains constant for 2 s. The rate of rise of the pulse is
measured with an RC differentiating circuit whose time constant is 500
 ps. If the positive output voltage from the differentiator has maximum
value of 50 V, what is the peak voltage of the generator?
1.13 The limited ramp shown in Figure P1.13 is applied to an RC
differentiator. Draw the output waveforms for the following cases: (a)
T = 0.1RC, (b) T = RC, and (c) T = 10RC.

Figure P1.13 Input waveform.

1.14 Compute and draw to scale the output waveform for (a) C1 = 100
pF, (b) C1 = 150 pF and (c) C1 = 50 pF for the circuit shown in Figure
P1.14. The input is an 18 V step.

Figure P1.14 Circuit diagram.

1.15 An oscilloscope test probe is indicated in Figure P1.15. Assume that

the cable capacitance is 150 pF. What is (a) the attenuation of the
probe, (b) the value of C for best response, and (c) the input
impedance of the compensated probe?
 Figure P1.15 Circuit diagram.

1.16 A 100  pulse generator produces 500 s pulses with negligible rise
time and 10 V positive amplitude into an open circuit. If the bottom of
the pulse train is zero and the duty cycle is 50%, determine the pulse
shape, i.e. amplitude, rise time and fall time after it has passed through
the circuits shown in Figure P1.16.

Figure P1.16 Circuit diagram.

1.17 For the circuit shown in Figure P1.17 the input is a 20 V step.
Calculate and plot to scale the output voltage.
 Figure P1.17 Circuit diagram.

1.18 For the circuit and the input waveform shown in Figure P1.18, draw
roughly the output waveform vo. Make reasonable approximations and
estimate the rise time of the waveforms, the magnitude of the
overshoot and the time constant of the decay to the final value.

Figure P1.18 Circuit diagram.

 Chapter 2
Nonlinear Wave Shaping

In the previous chapter we discussed about linear wave shaping. We saw

how a change of wave shape was brought about when a non-sinusoidal
signal is transmitted through a linear network like RC low-pass and high-
pass circuit. In this chapter, we discuss some aspects of nonlinear wave
shaping like clipping and clamping. The circuits for which the outputs are
non-sinusoidal for sinusoidal inputs are called nonlinear wave shaping
circuits, for example clipping circuits and clamping circuits.
Clipping means cutting and removing a part. A clipping circuit is a circuit
which removes the undesired part of the waveform and transmits only the
desired part of the signal which is above or below some particular reference
level, i.e. it is used to select for transmission that part of an arbitrary
waveform which lies above or below some particular reference. Clipping
circuits are also called voltage (or current) limiters, amplitude selectors or
slicers.
Nonlinear wave shaping circuits may be classified as clipping circuits and
clamping circuits. Clipping circuits may be single level clippers or two level
clippers.
Single level clippers may be series diode clippers with and without
reference or shunt diode clippers with and without reference. Clipping
circuits may use diodes or transistors.
 Clamping circuits may be negative clampers (positive peak clampers)
with and without reference or positive clampers (negative peak clampers)
with and without reference.

2.1 CLIPPING CIRCUITS

In general, there are three basic configurations of clipping circuits.

1. A series combination of a diode, a resistor and a reference voltage.

2. A network consisting of many diodes, resistors and reference voltages.
3. Two emitter coupled transistors operating as a differential amplifier.

2.1.1 Diode Clippers

Figure 2.1(a) shows the v–i characteristic of a practical diode. Figures
2.1(b), (c), (d), and (e) show the v–i characteristics of an idealized diode
approximated by a curve which is piece-wise linear and continuous. The
break point occurs at Vg, where Vg  0.2 V for Ge and
Vg  0.6 V for Si. Usually Vg is very small compared to the reference
voltage VR and can be neglected.
 Figure 2.1 v–i characteristics of a diode.

2.1.2 Shunt Clippers

Clipping above reference level
Using the ideal diode characteristic of Figure 2.2(a), the clipping circuit
shown in Figure 2.2(b), has the transmission characteristic shown in Figure
2.2(c). The transmission characteristic which is a plot of the output voltage
vo as a function of the input voltage vi also exhibits piece-wise linear
discontinuity. The break point occurs at the reference voltage VR. To the
left of the break point i.e. for vi < VR the diode is reverse biased (OFF) and
the equivalent circuit shown in Figure 2.2(d) results. In this region the
signal vi may be transmitted directly to the output, since there is no load
across the output to cause a drop across the series resistor R. To the right of
the break point i.e. for vi > VR the diode is forward biased (ON) and the
equivalent circuit shown in Figure 2.2(e) results and increments in the
inputs are totally attenuated and the output is fixed at VR.
Figure 2.2(c) shows a sinusoidal input signal of amplitude large enough so
that the signal makes excursions past the break point. The corresponding
output exhibits a suppression of the positive peak of the signal. The output
will appear as if the positive peak had been clipped off or sliced off.
Clipping below reference level
If this clipping circuit of Figure 2.2(b), is modified by reversing the diode
as shown in Figure 2.3(a), the corresponding piece-wise linear transfer
characteristic and the output for a sinusoidal input will be as shown in
Figure 2.3(b). In this circuit, the portion of the waveform more positive than
VR is transmitted without any attenuation but the portion of the waveform
less positive than VR is totally suppressed. For vi < VR, the diode conducts
and acts as a short circuit and the equivalent circuit shown in Figure 2.3(c)
results and the output is fixed at VR. For vi > VR, the diode is reverse
biased and acts as an open circuit and the equivalent circuit shown in Figure
2.3(d) results and the output is the same as the input.
Figure 2.2 (a) v–i characteristic of an ideal diode, (b) diode clipping circuit, which removes that part
of the waveform that is more positive than VR, (c) the piece-wise linear transmission
characteristic of the circuit, a sinusoidal input and the clipped output, (d) equivalent circuit for
vi < VR, and
(e) equivalent circuit for vi > VR.
Figure 2.3 (a) A diode clipping circuit, which transmits that part of the sine wave that is more
positive than VR, (b) the piece-wise linear transmission characteristic, a sinusoidal input and
the clipped output, (c) equivalent circuit for vi < VR, and (d) equivalent circuit for vi > VR.

In Figures 2.1(b) and 2.2(a), we assumed that Rr =  and Rf = 0. If this

condition does not apply, the transmission characteristic must be modified.
The portions of those curves which are indicated as having unity slope must
instead be considered as having a slope of Rr/(Rr + R), and those having
zero slope as having a slope of Rf/(Rf + R). In the transmission region of a
diode clipping circuit, it is required that Rr >> R, i.e. Rr = kR, where k is a
large number, and in the attenuation region, it is required that R >> Rf. From
these equations we can deduce that , i.e. the external resistance
R is to be selected as the geometric mean of Rf and Rr. The ratio Rr/Rf
serves as a figure of merit for the diodes used in these applications. A zener
diode may also be used in combination with a p-n junction diode to obtain
single-ended clipping, i.e. one-level clipping.

2.1.3 Series Clippers

Clipping above the reference voltage VR

Figure 2.4(a) shows a series clipper circuit using a p-n junction diode. VR is
the reference voltage source. The diode is assumed to be ideal (Rf = 0, Rr =
, Vg = 0) so that it acts as a short circuit when it is ON and as a open
circuit when it is OFF. Since the diode is in the series path connecting the
input and the output it is called a series clipper. The vo versus vi
characteristic called the transfer characteristic is shown in Figure 2.4(b).
The output for a sinusoidal input is shown in Figure 2.4(c).
Figure 2.4 (a) Diode series clipper circuit diagram, (b) transfer characteristic, (c) output waveform
for a sinusoidal input, (d) equivalent circuit for vi < VR, and (e) equivalent circuit for vi > VR.

The circuit works as follows:

For vi < VR, the diode D is forward biased because its anode is at a higher
potential than its cathode. It conducts and acts as a short circuit and the
equivalent circuit shown in Figure 2.4(d) results. The difference voltage
between the input vi and the reference voltage VR i.e. (VR – vi) is dropped
across R. Therefore vo = vi and the slope of the transfer characteristic for vi
< VR is 1. Since the input signal is transmitted to the output without any
change, this region is called the transmission region.
For vi > VR, the diode is reverse biased because its cathode is at a higher
potential than its anode, it does not conduct and acts as an open circuit and
the equivalent circuit shown in Figure 2.4(e) results. No current flows
through R and so no voltage drop across it. So the output voltage vo = VR
and the slope of the transfer characteristic is zero. Since the input signal
above VR is clipped OFF for vi > VR, this region is called the clipping
region. The equations
vo = vi for vi < VR
and............................................vo = VR for vi > VR

are called the transfer characteristic equations.

Clipping below the reference voltage VR

Figure 2.5(a) shows a series clipper circuit using a p-n junction diode and a
reference voltage source VR. The diode is assumed to be ideal (Rf = 0, Rr =
, Vg = 0) so that it acts as a short circuit when it is ON and as a open
circuit when it is OFF. Since the diode is in the series path connecting the
input and the output it is called a series clipper. The transfer characteristic is
shown in Figure 2.5(b). The output for a sinusoidal input is shown in Figure
2.5(c).
Figure 2.5 (a) Diode series clipper circuit diagram, (b) transfer characteristics, (c) output for a
sinusoidal input, (d) equivalent circuit for vi < VR, and (e) equivalent circuit for vi > VR.

The circuit works as follows:

For vi < VR, D is reverse biased because its anode is at a lower potential
than its cathode. The diode does not conduct and acts as an open circuit and
the equivalent circuit shown in Figure 2.5(d) results. No current flows
through R and hence no voltage drop across R and hence vo = VR. So the
slope of the transfer characteristic is zero for vi < VR. Since the input is
clipped off for vi < VR, this region is called the clipping region.
For vi > VR, the diode is forward biased because its anode is at a higher
potential than its cathode. The diode conducts and acts as a short circuit and
the equivalent circuit shown in Figure 2.5(e) results. Current flows through
R and the difference voltage between the input and the output voltages vi –
VR drops across R and the output vo = vi. The slope of the transfer
characteristic for vi > VR is unity. Since the input is transmitted to the
output for vi > VR, this region is called the transmission region.
The equations
vo = VR for vi < VR
and............................................vo = vi for vi > VR

are called the transfer characteristic equations.

Some single-ended diode clipping circuits, their transfer characteristics and
the output waveforms for sinusoidal inputs are shown below (Figure 2.6).
Some single-ended clipping circuits
 Figure 2.6 Examples of single-ended clipping circuits.

In the clipping circuits, the diode may appear as a series element or as a

shunt element. The use of the diode as a series element has the disadvantage
that when the diode is OFF and it is intended that there be no transmission,
fast signals or high frequency waveforms may be transmitted to the output
through the diode capacitance. The use of the diode as a shunt element has
the disadvantage that when the diode is open and it is intended that there be
transmission, the diode capacitance together with all other capacitances in
shunt with the output terminals will round off the sharp edges of the input
waveforms and attenuate the high frequency signals.

2.1.4 Clipping at Two Independent Levels

In Section 2.1.1, we discussed diode clippers, in which a single diode is
used to perform single-ended limiting at one independent level. In this
section we discuss diode clippers, which use pairs of diodes to perform
double-ended limiting at two independent levels. A parallel, a series, or a
series-parallel arrangement may be used. A parallel arrangement is shown
in Figure 2.7. Figure 2.8 shows the transfer characteristic and the output for
a sinusoidal input. The input-output characteristic has two breakpoints, one
at vo = vi = VR1 and the second at vo = vi = –VR2 and has the following
characteristics.

Figure 2.7 A diode clipper which limits at two independent levels.

Figure 2.8 The piece-wise linear transfer curve, the input sinusoidal waveform
and the corresponding output for the clipper of Figure 2.7.

The two level diode clipper shown in Figure 2.8 works as follows.
For vi > VR1, D1 is ON and D2 is OFF and the equivalent circuit shown in
Figure 2.9(a) results. So the output vo = VR1 and the slope of the transfer
characteristic is zero.

Figure 2.9 (a) Equivalent circuit for vi > VR1 and (b) equivalent circuit for vi < – VR2.

For vi < – VR2, D1 is OFF and D2 is ON and the equivalent circuit shown
in Figure 2.9(b) results. So the output vo = – VR2 and the slope of the
transfer characteristic is zero.
For –VR2 < vi < VR1, D1 is OFF and D2 is OFF and the equivalent circuit
shown in Figure 2.10 results. So the output vo = vi and the slope of the
transfer characteristic is one.

Figure 2.10 Equivalent circuit for –VR2 < vi < VR1.

The circuit of Figure 2.7 is called a slicer because the output contains a slice
of the input between two reference levels VR1 and VR2. Looking at the
input and output waveforms, we observe that this circuit may be used to
convert a sine wave into a square wave, if VR1 = VR2, and if the amplitude
of the input signal is very large compared with the difference in the
reference levels, the output will be a symmetrical square wave. Two zener
diodes in series opposing may also be used to form a double-ended clipper.
If the diodes have identical characteristics, then, a symmetrical limiter is
obtained. Some double-ended clippers, their transfer characteristics and the
outputs for sine wave inputs are shown in Figure 2.11.
Some double-ended clipping circuits
 Figure 2.11 Examples of double-ended clippers.

2.1.5 Series and Shunt Noise Clippers

Practically actual signals will be mostly associated with unwanted noise
signals. The presence of noise signals may adversely affect sensitive
circuits. So the noise signals must be eliminated to make the actual signal
free from distortions and fluctuations.
Noise signals can be eliminated by employing noise clippers. These clippers
use two or more diodes depending upon whether the noise is quite small or
considerably large. Noise clippers are of two types: series noise clippers and
shunt noise clippers.
Series noise clipper
Figure 2.12 shows a series noise clipper. This type of clipper circuits are
used when the amplitude of the noise voltage is not greater than Vg the
forward voltage drop of the diode and the signal voltage has an amplitude
larger than Vg . When the input signal along with noise shown in Figure
2.13(a) is applied at the input, the diode D1 will conduct when the
amplitude exceeds + Vg , the diode D2 will conduct when the amplitude
falls below – Vg and no diode will conduct when the amplitude is between
+ Vg and – Vg . Therefore, the noise within the limits of + Vg and – Vg is
clipped and the signal above Vg during positive cycle and the signal below
– Vg during negative cycle will appear at the output.

Figure 2.12 Series noise clipper.

The output voltage waveform is shown in Figure 2.13(b). The effective

amplitude of the output voltage is  (vi max – Vg).

Figure 2.13 (a) Input signal with superimposed noise and (b) output signal (with noise clipped).

Shunt noise clipper

A shunt noise clipper shown in Figure 2.14 is used when the noise
associated with the input signal at the peaks is to be eliminated. When the
input signal with noise shown in Figure 2.15(a) is applied at the input, for –
Vg < vi < Vg , there is no conduction as both the diodes get reverse biased
and are OFF. Hence output voltage will follow the input voltage, vo = vi.

Figure 2.14 Shunt noise clipper.

When vi > Vg , the diode D1 is ON and the diode D2 is OFF. Hence the
output voltage vo = Vg and it remains at Vg until the signal amplitude falls
below Vg . Thus the noise riding the signal voltage positive peaks is
eliminated.
When vi < –Vg , the diode D1 is OFF and the diode D2 is ON. Hence the
output voltage vo = –Vg and it remains at –Vg until the signal amplitude
rises above –Vg . Thus the noise riding the signal voltage negative peak is
eliminated. The output waveform is as shown in Figure 2.15(b).

Figure 2.15 (a) Signal with superimposed noise and (b) output signal free from noise.

2.1.6 Compensation for Variation of Temperature

The forward voltage at which a semiconductor diode breaks and starts
conducting depends on its junction temperature. The break point decreases
by 2 mV/°C rise in temperature. In an ideal diode, the break point occurs at
zero voltage. Since the practical clipper circuits use semiconductor diodes,
the exact point on the input signal waveform at which clipping occurs also
depends on temperature.
Several techniques are adopted in practice to compensate for the effect of
temperature changes. A practical diode may be visualized as an ideal diode
in series with a voltage source Vg as shown in Figure 2.16(a). A series
clipper using a practical diode is shown in Figure 2.16(b).

Figure 2.16 (a) A practical diode and (b) a series clipper.

The following are the techniques adopted for temperature compensation.

1. A diode D2 whose voltage source Vg compensates for Vg of diode D1 is
connected in series with D1 as shown in Figure 2.17. A voltage source V
in series with a resistance R is connected in parallel with D2 in order to
keep D2 conducting all the time for transmission of signal to the output.
 Figure 2.17 Compensated series clipper.

2. Another circuit which provides for temperature compensation is shown in

Figure 2.18(a). This arrangement avoids the use of V. In this arrangement,
the battery VR not only acts as the reference voltage but it also keeps the
diode D2 conducting if vi < VR.

vo = VR – Vg2......if vi < VR

vo = vi – Vg1........if vi > VR

3. Another alternative temperature compensated clipping circuit is shown

in Figure 2.18(b).

When vi < VR, D1 is OFF, D2 is ON,......vo = VR – Vg2

When vi > VR, D1 is ON, D2 is OFF,......vo = vi – Vg1

In this arrangement, the clipping level VR is quite independent of Vg and

hence is not affected by changes of temperature.
 Figure 2.18 (a) Compensated series clipper which avoids the use of V and
(b) in which clipping level is independent of Vg.

2.1.7 Transistor Clippers

A nonlinear device is required for clipping purposes. A diode exhibits a
nonlinearity, which occurs when it goes from OFF to ON. On the other
hand, the transistor has two pronounced nonlinearities, which may be used
for clipping purposes. One occurs when the transistor crosses from the cut-
in region into the active region and the second occurs when the transistor
crosses from the active region into the saturation region. Therefore, if the
peak-to-peak value of the input waveform is such that it can carry the
transistor across the boundary between the cut-in and active regions, or
across the boundary between the active and saturation regions, a portion of
the input waveform will be clipped. Normally, it is required that the portion
of the input waveform, which keeps the transistor in the active region shall
appear at the output without distortion. In that case, it is required that the
input current rather than the input voltage be the waveform of the signal of
interest. The reason for this requirement is that over a large signal excursion
in the active region, the transistor output current responds nominally
linearly to the input current but is related in a quite nonlinear manner to the
input voltage. So, in transistor clippers a current drive needs to be used.
A transistor clipper is shown in Figure 2.19. The resistor R which represents
either the signal source impedance or a resistor deliberately introduced must
be large compared with the input resistance of the transistor in the active
region. Under these circumstances, the input base current will very nearly
have the waveform of the input voltage, because the base current is given
by
iB = (vi – Vg)/R

where Vg is the base-to-emitter cut-in voltage. Vg  0.1 V for Ge and Vg 

0.5 V for Si.

Figure 2.19 A transistor clipper.

If a ramp input signal vi which starts at a voltage below cut-off and

carries the transistor into saturation is applied, the base voltage, the base
current, and the collector current waveforms of the transistor clipper will be
as shown in Figure 2.20.
Figure 2.20 Waveforms of the transistor clipper of Figure 2.19: (a) voltage VBE which results when
a
ramp input drives the transistor from cut-off into saturation, and (b) the base and collector currents.

The waveforms which result when a sinusoidal voltage vi carries the

transistor from cut-off to saturation are shown in Figure 2.21. The base
circuit is biased so that cut-in occurs when vBE reaches the voltage V.
Figure 2.21 Waveforms for the transistor clipper of Figure 2.19: (a) input voltage vi and the base- to-
emitter
voltage vBE, (b) the base current iB, (c) the collector current iC and (d) the output voltage vo.

2.1.8 Emitter-Coupled Clipper

An emitter-coupled clipper is shown in Figure 2.22. It is a two-level clipper
using transistors. The base of Q2 is fixed at a voltage VBB2, and the input
is applied to B1. If initially the input is negative, Q1 is OFF and only Q2
carries the current. Assume that VBB2 has been adjusted so that Q2
operates in its active region. Let us assume that the current I in the emitter
resistance is constant. This is valid if |VBE2| is small compared to |VBB2 +
VEE|. When vi is below the cut-off point of Q1, all the current I flows
through Q2. As vi increases, Q1 will eventually come out of cut-off, both
the transistors will be carrying currents but the current in Q2 decreases
while the current in Q1 increases, the sum of the currents in the two
transistors remaining constant and equal to I. The input signal appears at the
output, amplified but not inverted. As vi continues to increase, the common
emitter will follow the base of Q1. Since the base of Q2 is fixed, a point
will be reached when the rising emitter voltage cuts off Q2. Thus, the input
signal is amplified but twice limited, once by the cut-off of Q1 and once by
the onset of cut-off in Q2. The total range vo, over which the output can
follow the input is IRE and is constant and therefore adjustable through an
adjustment of I. The absolute voltage of the portion of the input waveform
selected for transmission may be selected through an adjustment of a
biasing voltage on which vi is superimposed or through an adjustment of
VBB2. The total range of input voltage vi between the clipping limits is
vo/A, where A is the gain of the amplifier stage. Figure 2.23 shows the
transfer characteristic of an emitter-coupled clipper.
 Figure 2.22 An emitter-coupled clipper.

EXAMPLE 2.1 A square wave has to be generated by passing a sine wave

through a clipper. The square wave has to have an upper level of 40 V and a
lower level of – 20 V. The period of the square wave is to be 5 ms. Draw the
necessary clipper circuit and output waveforms.

Solution: The part of the sine wave above + 40 V and below – 20 V is to be

clipped off to convert a sine wave into a square wave. The required clipper
circuit and the input and output waveforms are shown in Figures 2.24 (a)
and (b) respectively.
The transfer characteristic equations are as follows:
 Figure 2.23 The transfer characteristic of the emitter-coupled clipper.

Figure 2.24 Example 2.1: (a) circuit diagram and (b) output waveform.

EXAMPLE 2.2 Draw the transfer characteristic for the clipping circuit
shown in Figure 2.25(a). Rf = 50 .
 Figure 2.25 Example 2.2: (a) circuit diagram and (b) transfer characteristic.

Solution: Since Vg is not given, assume that Vg = 0.

For vi < 20 V, D1 is OFF and the equivalent circuit shown in Figure
2.26(a) results and vo remains constant at 20 V. So the transfer
characteristic is a straight line with zero slope and 20 V amplitude. For vi >
20 V, D1 is ON. So it can be replaced by its forward resistance Rf = 50 
and the equivalent circuit shown in Figure 2.26(b) results.

So the transfer characteristic is a straight line with a slope of 0.99 [(49.7 –

20)/(50 – 20) = 0.99] for vi > 20 V. The transfer characteristic is shown in
Figure 2.25(b).

Figure 2.26 Example 2.2: (a) equivalent circuit for vi  20 V and (b) equivalent circuit for vi > 20V.

EXAMPLE 2.3 Draw the transfer characteristic for the clipper circuit
shown in Figure 2.27(a). Assume ideal diodes.
 Figure 2.27 Example 2.3: (a) circuit diagram and (b) transfer characteristic.

Solution: When vi  0 V, D1 is OFF, D2 is ON and the equivalent circuit

shown in Figure 2.28 (a) results. In Figure 2.28(a)

So the transfer characteristic is a straight line with zero slope for vi  30

V.
When vi > 30 V, D1 is ON, D2 is ON and the equivalent circuit shown in
Figure 2.28(b) results. The output is the same as the input, i.e. vo = vi.
So the transfer characteristic is a straight line with a slope of unity for vi >
30 V. The transfer characteristic is shown in Figure 2.27(b).
Figure 2.28 Example 2.3: (a) equivalent circuit for vi  30 V and (b) equivalent circuit for vi > 30 V.

EXAMPLE 2.4 Draw the transfer characteristic for the clipper circuit
shown in Figure 2.29(a). Find the value of input voltage at which the output
will be zero. Find also at what values of input voltage D2 conducts.

Figure 2.29 Example 2.4: (a) circuit diagram and (b) transfer characteristic.

Solution: When vi = 0 V, D1 is ON and D2 is OFF. The equivalent circuit

shown in Figure 2.30(a) results.
 So when D1 is ON and D2 is OFF, the transfer characteristic is a straight
line with a slope of 5/10 = 0.5.
When vi > 10 V, D1 is OFF and D2 is OFF, the equivalent circuit shown
in Figure 2.30(b) results, and vo = 10 V.

Figure 2.30 Example 2.4: (a) equivalent circuit for vi = 0 V and (b) equivalent circuit for vi > 10 V.

For D2 to be ON, VA must be  – 20 V

When D1 and D2 are both ON, the equivalent circuit is as shown in
Figure 2.31.
 Figure 2.31 Example 2.4: equivalent circuit for vi < – 50 V.

EXAMPLE 2.5 Draw the transfer characteristics for the clipper circuit
shown in Figure 2.32(a). Assume ideal diodes.

Figure 2.32 Example 2.5: (a) circuit diagram and (b) transfer characteristic.

Solution: When vi  0 V, D1 is ON, D2 is OFF and the equivalent circuit

shown in Figure 2.33(a) results and vo = 0 V. So the transfer characteristic
is a straight line with zero slope and of zero amplitude for vi  0 V. When
vi > 0 V, D1 is ON, D2 is ON and vo = vi. This continues till vi = 30 V.
Therefore for 0 < vi < 30 V, D1 is ON, D2 is ON, the equivalent circuit
shown in Figure 2.33(b) results and vo = vi. So the transfer characteristic is
a straight line with a slope of unity for 0 < vi < 30 V.
Figure 2.33 Example 2.5: (a) equivalent circuit for vi < 0 V and (b) equivalent circuit for 0 < vi < 30
V.

When vi > 30 V, D1 is OFF and D2 is ON and the equivalent circuit shown

in Figure 2.34 results.

Figure 2.34 Example 2.5: equivalent circuit for vi > 30 V.

So, for vi > 30 V, D1 is OFF, D2 is ON and vo = 20 V. So the transfer

characteristic is a straight line with zero slope and 20 V amplitude for vi >
30 V. vo falls from 30 V to 20 V at vi = 30 V. The complete transfer
characteristic is shown in Figure 2.32(b).

EXAMPLE 2.6 Draw the transfer characteristic for the circuit shown in
Figure 2.35. Also draw the output waveform for a sinusoidal input of
amplitude 20 V.

Solution: The transfer characteristic for the circuit of Figure 2.35 may be
drawn based on the following:

Figure 2.35 Example 2.6: circuit diagram.

For vi < 0 V, D1 is ON, D2 is OFF and the equivalent circuit shown in

Figure 2.36(a) results. So the output vo = vi/2.

Figure 2.36 Example 2.6: (a) equivalent circuit for vi < 0 V and (b) equivalent circuit for vi > 0 V.

For vi > 0 V, D1 is OFF, D2 is ON, and the equivalent circuit shown in

Figure 2.36(b) results. So the output vo = vi/2.
So for all values of vi, vo = vi/2.
The transfer characteristic and the output waveform for a sinusoidal input
are as shown in Figures 2.37(a) and (b) respectively.
 Figure 2.37 (a) Transfer characteristic and (b) output voltage for
the circuit of Figure 2.35 for a sinusoidal input.

EXAMPLE 2.7 For the circuit shown in Figure 2.38, plot vo versus vi
indicating all intercepts, slopes and voltage levels. Also sketch vo, if vi = 20
sin wt. Indicate all voltage levels.

Figure 2.38 Example 2.7: circuit diagram.

Solution: Assume ideal diodes in the circuit shown in Figure 2.38.

For vi < 0 V, i.e. when vi is negative D1 is OFF, D2 is OFF and the
equivalent circuit shown in Figure 2.39(a) results. No current flows
anywhere in the circuit and hence vo = 0 V.
Figure 2.39 Example 2.7: (a) equivalent circuit for vi < 0 V and (b) equivalent circuit for 0 < vi < 20
V.

For vi > 0 V, D1 is ON and D2 is OFF and the equivalent circuit shown in

Figure 2.39(b) results. Current flows through D1, 10 k and 10 k
resistors to ground and the output voltage rises as the input rises.

When vi > 20 V, VA rises above 10 V and D2 starts conducting and the

equivalent circuit shown in Figure 2.40 results and so vo is fixed at 10 V.
The transfer characteristic and the output waveform are shown in Figure
2.41.

Figure 2.40 Example 2.7: equivalent circuit for vi > 20 V.

 Figure 2.41 Example 2.7: transfer characteristic and output waveform.

EXAMPLE 2.8 Sketch the voltage across the diode of Figure 2.42(b) for
the input shown in Figure 2.42(a). For the diode used, Vg = 0.6 V and Rf =
100 .

Figure 2.42 Example 2.8: (a) input waveform, (b) circuit diagram, and (c) output waveform.

Solution: For the circuit shown in Figure 2.42(b), when the input level is –
10 V, the diode D is reverse biased and the equivalent circuit shown in
Figure 2.43(a) results and so the output vo = –30 V. When the input vi goes
to + 60 V, the capacitor cannot charge as its time constant is very large
compared to the duration of the pulse.

RC = 500   2.5 F = 1250 s

Pulse width of the input = 100 s

Figure 2.43 Example 2.8: (a) equivalent circuit when vi = – 10 V and (b) equivalent circuit when vi =
60 V.

The diode D conducts and the equivalent circuit shown in Figure 2.43(b)
results and the output vo attains the value VA. Since R >> Rf, the entire
current I flows through Rf only.

The output waveform is shown in Figure 2.42(c).

EXAMPLE 2.9 The clipper shown in Figure 2.44(b) is used with the input
waveform shown in Figure 2.44(a). Find the output waveform assuming
that the back resistance is infinite.
 Figure 2.44 Example 2.9: (a) input waveform, (b) circuit diagram,
(c) ideal output waveform, and (d) practical output waveform.

Solution: For the input waveform shown in Figure 2.44(a), if the diode
were perfect and the capacitances neglected, the output waveform of the
circuit shown in Figure 2.44(b) would be as shown in Figure 2.44(c).
Assume that a steady-state condition has been reached in which the input
is –5 V and the output = 0 V. Now, let the input rise abruptly by 10 V (i.e.
from –5 V to +5 V). If the source impedance is negligible, an impulsive
current results and the initial output voltage rise is determined entirely by
the capacitors.

Therefore, the voltage across the diode is now 3 V and in the direction to
make the diode conduct. The output vo will rise to its final voltage of 5 V
with a time constant t1 = (C1 + C2)Rf, where Rf is the forward resistance of
the diode.
Similarly, when the input voltage drops by 10 V, the output voltage will
drop abruptly by 2 V. The cathode of the diode is now at +3 V, and the
anode is at –5 V, the diode will not conduct and the decay of the output
signal to zero will take place with a time constant, t2 = (C1 + C2)R.
If C1 > C2, then the output waveform would not have rounded rising or
falling sides, instead there would be a spike overshoot at the front and rear
edges. The output waveform when capacitances are considered is shown in
Figure 2.44(d).

EXAMPLE 2.10 The input voltage vi to the two-level clipper shown in

Figure 2.45(a) varies linearly from 0 to 150 V. Sketch the output voltage vo
to the same time scale as the input voltage. Assume ideal diodes.

Figure 2.45 Example 2.10: (a) circuit diagram and (b) the output waveform for a ramp input.

Solution: In the circuit shown in Figure 2.45(a), when input vi = 0 V, D1 is

OFF and D2 is ON, and the equivalent circuit shown in Figure 2.46(a)
results.
Figure 2.46 Example 2.10: (a) equivalent circuit for vi = 0 V and (b) equivalent circuit for vi ≥ 50 V.

Writing KVL around the loop shown in Figure 2.46(a), we have

Since D2 is ON, VA = VB = 50 V.

Diode D1 does not conduct until the input vi attains 50 V. As soon as vi

attains 50 V, D1 conducts and since D2 is already ON equivalent circuit
shown in Figure 2.46(b) results and the rise in input is transmitted to the
points A and B, until point A attains 100 V. When the input rises above 100
V, D2 will be OFF and the equivalent circuit shown in Figure 2.47 results
and the output will be held at 100 V. The transfer characteristic and the
output drawn to the same time scale as the input are shown in Figure
2.45(b).
 Figure 2.47 Example 2.10: equivalent circuit for vi > 100 V.

EXAMPLE 2.11 The input voltage vi to the two-level clipper shown in

Figure 2.48(a) varies linearly from 0 to 150 V. Sketch the output voltage vo
to the same time scale as the input voltage.

Figure 2.48 Example 2.11: (a) circuit diagram and (b) the output waveform for a ramp input.

Solution: In the circuit shown in Figure 2.48(a), when vi = 0 V, D1 is OFF

and D2 is OFF and the equivalent circuit shown in Figure 2.49(a) results.
Therefore, the output vo = 25 V. As the input rises, this continues till D2
conducts at VA = 25 V. Thus,

for 0 < vi < 25 V, vo = 25 V

As the input rises above 25 V, D2 conducts but D1 will remain OFF and
the equivalent circuit shown in Figure 2.49(b) results and the output rises.
This continues till VA = 100 V. When VA = 100 V, VB will also be equal
to 100 V.
Figure 2.49 Example 2.11: (a) equivalent circuit for vi = 0 and (b) equivalent circuit for 25 V < vi <
137.5 V.

When VA = 100 V, D1 conducts. Since D2 is already conducting the

equivalent circuit shown in Figure 2.50 results. Therefore, VA and hence
VB and vo are fixed at 100 V as the input rises from 137.5 V to 150 V.
Thus,

for 137.5 V < vi < 150 V, vo = 100 V

The transfer characteristic and the output drawn to the same time scale as
the input are shown in Figure 2.48(b).
 Figure 2.50 Example 2.11: equivalent circuit for vi ≥ 137.5 V.

EXAMPLE 2.12 For the clipping circuit shown in Figure 2.51 make a plot
of vo versus vi for the range of vi from 0 to 50 V. Indicate all slopes and
voltage levels. Also, indicate for each region, the diodes which conduct.

Figure 2.51 Example 2.12: clipping circuit.

Solution: The input voltage vi increases linearly from 0 to 50 V. When

input vi = 0 V, D3 is OFF, D2 is OFF and D1 is ON and the equivalent
circuit shown in Figure 2.52(a) results. Therefore, a current i1 flows in the
inner loop shown in Figure 2.52(a).
 This continues till D3 conducts at vi = 3 V.

 For.............................................0 < vi < 3 V, vo remains at 3 V.

When the input vi attains 3 V, D3 conducts. D1 is already ON and the

equivalent circuit shown in Figure 2.52(b) results.

Figure 2.52 Example 2.12: (a) equivalent circuit for 0 < vi < 3 V and (b) equivalent circuit for 3V <
vi < 9V.

As the input rises above 3 V, VA and hence vo also rises. When VA

attains 6 V, D1 will be OFF. D2 is already OFF and the equivalent circuit
shown in Figure 2.53(a) results. So, the current i2 in the outer loop will be

When vi > 9 V, D1 is OFF, D2 is OFF and D3 is ON.

 As vi rises, vo also rises till VB = 20 V, at which point D2 starts

conducting and the equivalent circuit shown in Figure 2.53(b) results.
Figure 2.53 Example 2.12: (a) equivalent circuit for 9V < vi < 30 V and (b) equivalent circuit for vi >
30 V.

3
When VB = 20 V, the current i2 in the 5 k resistor is 20/(5  10 ) = 4
mA. This current flows from the supply through the 2.5 k resistor.
–3 3
............................When vo = 20 V, vi = 20 + 4  10  2.5  10 = 30
V

i.e. for 9 V < vi < 30 V, D1 is OFF, D2 is OFF and D3 is ON and the output
rises with a slope of

When VA attains 20 V, D2 conducts.

When vi > 30 V, D1 is OFF, D2 is ON and D3 is ON. So VA and hence vo

rises as vi rises.

The equivalent circuit for vi > 30 V is shown in Figure 2.53(b).

When vi = 50 V, KCL equation at node A is

 The transfer characteristic is as shown in Figure 2.54.

Figure 2.54 Example 2.12: transfer characteristic of the clipping circuit.

EXAMPLE 2.13 Design a clipping circuit with ideal components, which

can give the waveform shown in Figure 2.55 for a sinusoidal input.

Figure 2.55 Example 2.13: output waveform.

 Figure 2.56 Example 2.13: circuit diagram and (b) output waveform.

EXAMPLE 2.14 It is required to suppress the noise in the waveform

shown in Figure 2.57 below. Sketch the clipper circuit used for this purpose
and explain the action of the circuit.
 Figure 2.57 Example 2.14: waveform.

Solution: The required circuit diagram and its transfer characteristic are
shown in Figures 2.58(a) and (b) respectively. The circuit is a two-level
biased series clipper. Input noise is clipped at the levels of V1 and – V2. The
input transmission occurs above V1 and below –V2. When the input is
positive and more than (V1 + Vg), diode D1 conducts and D2 does not.
Therefore, the voltage above V1 will appear at the output and the noise
below it is eliminated.
When the input is more negative than – (V2 + Vg), the diode D2 conducts
and D1 does not. The voltage below –V2 appears at the output. The noise
above –V2 will be eliminated.

Figure 2.58 Example 2.14: (a) designed circuit and (b) the transfer characteristic.

EXAMPLE 2.15 VS a pulse of 12 V and duration 5 s as shown in Figure

2.59(a) is applied to the circuit shown in Figure 2.59(b). Assume that the
initial voltage on C is zero. Determine v0(t) and sketch it. The diode is
ideal, R1 = 8 k and R = 30 k.
 Figure 2.59 Example 2.15: (a) input pulse and (b) circuit diagram.

Solution: For t < 0, VS is at its lower level. So the voltage across the
capacitor is zero. At t = 0, VS jumps to 12 V, and since the voltage across
the capacitor cannot change instantaneously, it acts as a short circuit only at
+
t = 0 . Diode also acts as a short when it is ON under ideal conditions, and
the equivalent circuit shown in Figure 2.60(a) results.

–5/6.316
At t = 5 s, vo = 9.47(1 – e ) = 5.18 V.
For t > 5 s, VS = 0, the diode is reverse biased and acts as an open
circuit. So the capacitor C discharges through R as shown in Figure 2.60(b).
The output waveform is as shown in Figure 2.60(c).
The output for t > 5 s is
 –(t–5)/RC
vo = 5.18e
–(t–5)/30  103  1000  10–12
= 5.18e
–(t–5)/30
= 5.18e

Figure 2.60 Example 2.15: (a) equivalent circuit when VS = 12 V,

(b) discharge of C, and (c) output waveform.

EXAMPLE 2.16 For the circuit shown in Figure 2.61(a), vi is a sinusoidal

voltage of 60 volts. Assuming ideal diodes, sketch one cycle of output
voltage. Determine the maximum diode currents.

Figure 2.61 Example 2.16: (a) circuit diagram and (b) output waveform.
Solution: Referring to Figure 2.61(a),
for vi < 15 V, D1 is ON, D2 is OFF the equivalent circuit shown in Figure
2.62(a) results and vo = 15 V

for vi > 35 V, D1 is OFF, D2 is ON the equivalent circuit shown in Figure

2.62(b) results and vo = 35 V

for 15 V < vi < 35 V, D1 is OFF, D2 is OFF the equivalent circuit shown

in Figure 2.63 results and vo = vi

So the output waveform is as shown in Figure 2.61(b).

D1 is ON when vi < 15 V. The lowest value of vi is – 60 V

Figure 2.62 Example 2.16: (a) equivalent circuit for vi < 15 V and (b) equivalent circuit for vi > 35
V.
 Figure 2.63 Example 2.16: equivalent circuit for 15 V < vi < 35 V.

EXAMPLE 2.17 The circuit shown in Figure 2.64(a) is used to “square” a

1 kHz input sine wave whose peak is 40 V. It is desired that the output
voltage waveform be flat for 90% of time. Find the values of VR1 and VR2.
Assume ideal diodes. At what value of input will the waveform be clipped?

Figure 2.64 Example 2.17: (a) circuit diagram and (b) output waveform.

EXAMPLE 2.18 For the diode clipping circuit in Figure 2.65(a), assume
VR = 10 V, vi = 25 sin wt, Rf = 50 , Rr =  and Vg = 0. Neglect all
capacitances. Draw to scale the input and output waveforms and label the
maximum and minimum values if (a) R = 25 k, (b) R = 5 k, and (c) R =
250 .
 Figure 2.65 Example 2.18: (a) circuit diagram and (b) output waveform.

Solution: Referring to Figure 2.65(a):

When vi < VR, D is OFF and the equivalent circuit shown in Figure
2.66(a) results and vo = vi
When vi > VR, D is ON and the equivalent circuit shown in Figure
2.66(b) results and vo > VR considering Rf
 Figure 2.66 Example 2.18: (a) equivalent circuit for vi < VR and (b) equivalent circuit for vi > VR.

EXAMPLE 2.19 Draw the circuit of a shunt diode positive peak clipper.
Assume Rf = 50 , Vg = 0.6 V, Rr = 2 M, R = 20 k, and VR = +15 V.
Sketch the transfer characteristic when the input voltage varies between –
20 V and +20 V. Indicate the slopes, voltage levels Vo(max) and Vo(min),
and the region where the diode conducts. Also sketch the input/output
waveforms, if a sine wave of 20 V peak is applied as the input. If a load
resistance of 30 k is connected across the output terminals, sketch the
transfer characteristic and the output wave for a 20 V peak sine wave input.

Figure 2.67 Example 2.19: (a) circuit diagram and (b) equivalent circuit when D is ON.

Solution: The circuit diagram of the required shunt clipper is shown in

Figure 2.67(a).
(i) When the load resistance RL is not connected across the output
terminals:

When..........................vi  (VR + Vg), D is OFF and vo = vi

i.e. for vi  (15 + 0.6) = 15.6 V, the diode is OFF and vo = vi

When vi > (VR + Vg) = 15.6 V, D is ON and the equivalent circuit shown
in Figure 2.67(b) results. Then

The transfer characteristic is plotted in Figure 2.68(a). The output

waveform is plotted in Figure 2.68(b).

Figure 2.68 Example 2.19: (a) transfer characteristic and (b) output waveform.
 (ii) When the load resistance RL = 30 k is connected across the output
terminals:
In the absence of the load resistance RL, the slopes in the conducting and
non-conducting regions are given by

respectively.
If RL is connected across the output terminals, it comes in parallel with Rf
or Rr. Hence Rf and Rr are to be replaced by and , where
 The transfer characteristic and the output waveform when RL is present
are shown in Figures 2.69(a) and (b) respectively.

Figure 2.69 Example 2.19: (a) transfer characteristic and (b) output waveform in the presence of RL.

2.1.9 Comparators
A comparator circuit is one, which may be used to mark the instant when an
arbitrary waveform attains some particular reference level. The nonlinear
circuits, which can be used to perform the operation of clipping may also be
used to perform the operation of comparison. In fact, the clipping circuits
become elements of a comparator system and are usually simply referred to
as comparators. The distinction between comparator circuits and the
clipping circuits is that, in a comparator there is no interest in reproducing
any part of the signal waveform, whereas in a clipping circuit, part of the
signal waveform is needed to be reproduced without any distortion.
Figure 2.70 shows the circuit diagram of a diode comparator. As long as
the input voltage vi is less than the reference voltage VR, the diode D is ON
and the output is fixed at VR. When vi > VR, the diode is OFF and hence vo
= vi. The break occurs at vi = VR at time t = t1. So, this circuit can be used
to mark the instant at which the input voltage reaches a particular reference
level VR.

Figure 2.70 Diode comparator.

Comparators may be non-regenerative or regenerative. Clipping circuits

fall into the category of non-regenerative comparators. In regenerative
comparators, positive feedback is employed to obtain an infinite forward
gain (unity loop gain). The Schmitt trigger and the blocking oscillator are
examples of regenerative comparators. The Schmitt trigger comparator
generates approximately a step input. The blocking oscillator comparator
generates a pulse rather than a step output waveform. Most applications of
comparators make use of the step or pulse natures of the input. Operational
amplifiers and tunnel diodes may also be used as comparators.
Applications of voltage comparators
Voltage comparators may be used:

1. In accurate time measurements

 2. In pulse time modulation
3. As timing markers generated from a sine wave.
4. In phase meters
5. In amplitude distribution analyzers
6. To obtain square wave from a sine wave
7. In analog-to-digital converters.

2.2 CLAMPING CIRCUITS

Clamping circuits are circuits, which are used to clamp or fix the extremity
of a periodic waveform to some constant reference level VR. Under steady-
state conditions, these circuits restrain the extremity of the waveform from
going beyond VR. Clamping circuits may be one-way clamps or two-way
clamps. When only one diode is used and a voltage change in only one
direction is restrained, the circuits are called one-way clamps. When two
diodes are used and the voltage change in both the directions is restrained,
the circuits are called two-way clamps.
2.2.1 The Clamping Operation
When a signal is transmitted through a capacitive coupling network (RC
high-pass circuit), it looses its dc component, and a clamping circuit may be
used to introduce a dc component by fixing the positive or negative
extremity of that waveform to some reference level. For this reason, the
clamping circuit is often referred to as dc restorer or dc reinserter. In fact, it
should be called a dc inserter, because the dc component introduced may be
different from the dc component lost during transmission. The clamping
circuit only changes the dc level of the input signal. It does not affect its
shape.
Classification of clamping circuits
Basically clamping circuits are of two types: (1) positive-voltage clamping
circuits and (2) negative-voltage clamping circuits.
In positive clamping, the negative extremity of the waveform is fixed at
the reference level and the entire waveform appears above the reference
level, i.e. the output waveform is positively clamped with reference to the
reference level. In negative clamping, the positive extremity of the
waveform is fixed at the reference level and the entire waveform appears
below the reference, i.e. the output waveform is negatively clamped with
respect to the reference level. The capacitors are essential in clamping
circuits. The difference between the clipping and clamping circuits is that
while the clipper clipps off an unwanted portion of the input waveform, the
clamper simply clamps the maximum positive or negative peak of the
waveform to a desired level. There will be no distortion of waveform.
2.2.2 Negative Clamper
Figure 3.1(a) shows the circuit diagram of a basic negative clamper. It is
also termed a positive peak clamper since the circuit clamps the positive
peak of a signal to zero level. Assume that the signal source has negligible
output impedance and that the diode is ideal, Rf = 0  and Vg = 0 V in that,
it exhibits an arbitrarily sharp break at 0 V, and that its input signal shown
in Figure 2.71(b) is a sinusoid which begins at t = 0. Let the capacitor C be
uncharged at t = 0.
 Figure 2.71 (a) A negative clamping circuit, (b) a sinusoidal input, and (c) a steady-state clamped
output.

During the first quarter cycle, the input signal rises from zero to the
maximum value. The diode conducts during this time and since we have
assumed an ideal diode, the voltage across it is zero. The capacitor C is
charged through the series combination of the signal source and the diode
and the voltage across C rises sinusoidally. At the end of the first quarter
cycle, the voltage across the capacitor, vC = Vm.
When, after the first quarter cycle, the peak has been passed and the input
signal begins to fall, the voltage vC across the capacitor is no longer able to
follow the input, because there is no path for the capacitor to discharge.
Hence, the voltage across the capacitor remains constant at vC = Vm, and
the charged capacitor acts as a voltage source of V volts and after the first
quarter cycle, the output is given by vo = vi – Vm. During the succeeding
cycles, the positive extremity of the signal will be clamped or restored to
zero and the output waveform shown in Figure 2.71(c) results.
Therefore,

Suppose that after the steady-state condition has been reached, the
amplitude of the input signal is increased, then the diode will again conduct
for at most one quarter cycle and the dc voltage across the capacitor would
rise to the new peak value, and the positive excursions of the signal would
be again restored to zero.
Suppose the amplitude of the input signal is decreased after the steady-
state condition has been reached. There is no path for the capacitor to
discharge. To permit the voltage across the capacitor to decrease, it is
necessary to shunt a resistor across C, or equivalently to shunt a resistor
across D. In the latter case, the capacitor will discharge through the series
combination of the resistor R across the diode and the resistance of the
source, and in a few cycles the positive extremity would be again clamped
at zero as shown in Figure 2.72(b). A circuit with such a resistor R is shown
in Figure 2.72(a).

Figure 2.72 (a) Clamping circuit with a resistor R across the diode D and (b) output during transient
period.

2.2.3 Positive Clamper

Figure 2.73(a) shows a positive clamper. This is also termed as negative
peak clamper since this circuit clamps the negative peaks of a signal to zero
level. The negative peak clamper, i.e. the positive clamper introduces a
positive dc.

Figure 2.73 (a) A positive clamping circuit, (b) a sinusoidal input, and (c) a steady-state clamped
output.

Let the input voltage be vi = Vm sin wt as shown in Figure 2.73(b). When

vi goes negative, the diode gets forward biased and conducts and in a few
cycles the capacitor gets charged to Vm with the polarity shown in Figure
2.73(a). Under steady-state conditions, the capacitor acts as a constant
voltage source and the output is
 vo = vi – (– Vm) = vi + Vm

Based on the above relation between vo and vi, the output voltage
waveform is plotted. As seen in Figure 2.73(c) the negative peaks of the
input signal are clamped to zero level. Peak-to-peak value of output voltage
= peak-to-peak value of input voltage = 2Vm. There is no distortion of
waveform. To accommodate for variations in amplitude of input, the diode
D is shunted with a resistor as shown in Figure 2.74(a). When the amplitude
of the input waveform is reduced, the output will adjust to its new value as
shown in Figure 2.74(b).

Figure 2.74 (a) Clamping circuit with a resistor R across D and (b) output during transient period.

2.2.4 Biased Clamping

If a voltage source of VR volts is connected in series with the diode of a
clamping circuit, the input waveform will be clamped with reference to VR.
Depending on the position of the diode, the input waveform may be
positively clamped with reference to VR, or negatively clamped with
reference to VR.
EXAMPLE 2.20 A 100 V peak square wave with a period of 20 ms shown
in Figure 2.75(a) is to be positively clamped at 25 V. Draw the circuit
diagram necessary for this purpose. Draw the output waveform.
Solution: The circuit diagram required to clamp the input voltage waveform
positively with respect to +25 V is shown in Figure 2.75(b).
 Figure 2.75 Example 2.20: (a) input waveform, (b) circuit diagram, and (c) the output waveform.

The diode D conducts when the input swing goes to –100 V and the
capacitor C charges to –125 V in a few cycles. Under steady-state
conditions

Therefore, the output swings between +225 V and +25 V as shown in

Figure 2.75(c).

EXAMPLE 2.21 Sketch the output waveform that you would expect from
the circuit shown in Figure 2.76(b), when the input is a 20V square wave
shown in Figure 2.76(a).

Figure 2.76 Example 2.21: (a) input waveform, (b) circuit diagram, and (c) the output waveform.

Solution: The output waveform in the circuit of Figure 2.76(b) will be

positively clamped with reference to –10 V as shown in Figure 2.76(c). The
diode D conducts when the input swing goes to –20 V and the capacitor
charges to –10 V in a few cycles and the steady-state output vo is given by

EXAMPLE 2.22 A 100 V peak square wave with a period of 20 ms shown

in Figure 2.77(a) is to be negatively clamped at 25 V. Draw the circuit
diagram necessary for this purpose. Draw the output waveform.

Solution: The circuit diagram required to clamp the input waveform

negatively with respect to +25 V is shown in Figure 2.77(b).

Figure 2.77 Example 2.22: (a) input waveform, (b) circuit diagram, and (c) the output waveform.

The diode D conducts when the input swing goes to +100 V, and the
capacitor C charges to +75 V in a few cycles.
Under steady-state conditions
 Therefore, the output swings between +25 V and –175 V as shown in
Figure 2.77(c).

EXAMPLE 2.23 Sketch the output waveform that you would expect from
the circuit shown in Figure 2.78(b), when the input is a 20 V square wave
shown in Figure 2.78(a).

Figure 2.78 Example 2.23: (a) input waveform, (b) circuit diagram, and (c) the output waveform.

Solution: The output waveform will be negatively clamped with respect to

–10 V as shown in Figure 2.78(c). The capacitor charges to +30 V in a few
cycles and the steady-state output vo is given by

Therefore, the output swings between –10 V and –50 V as shown in

Figure 2.78(c).

2.2.5 Clamping Circuit Taking Source and Diode Resistances Into

Account
In the discussion of the clamping circuit of Figure 2.71, we neglected the
output resistance of the source as well as the diode forward resistance.
Many times these resistances cannot be neglected. Figure 2.79 shows a
more realistic clamping circuit taking into consideration the output
resistance of the source RS, which may be negligible or may range up to
many thousands of ohms depending on the source, and the diode forward
resistance Rf which may range from tens to hundreds of ohms. Assume that
the diode break point Vg occurs at zero voltage.

Figure 2.79 Clamping circuit considering the source resistance and the diode forward resistance.

The precision of operation of the circuit depends on the condition that R

>> Rf, and Rr >> R. When the input is positive, the diode is ON and the
equivalent circuit shown in Figure 2.80(a) results. When the input is
negative, the diode is OFF and the equivalent circuit shown in Figure
2.80(b) results.

Figure 2.80 (a) Equivalent circuit when the diode is conducting and
(b) the equivalent circuit when the diode is not conducting.
The transient waveform
When a signal is suddenly applied to the circuit shown in Figure 2.79 the
capacitor charges (transient period) and gradually the steady-state condition
is reached in which the positive peaks will be clamped to zero. The
equivalent circuits shown in Figures 2.80(a) and 2.80(b) may be used to
calculate the transient response.

EXAMPLE 2.24 In the circuit of Figure 2.79, RS = Rf = 50 , R = 20 k,

and C = 2 F. A symmetrical square wave signal of amplitude 20 V and
frequency 5 kHz is applied at t = 0. Draw the first three cycles of the output
waveform.

Solution: Assume that the capacitor C is initially uncharged. At t = 0, the

input jumps to +20 V, the diode D conducts, and the equivalent circuit of
Figure 2.80(a) results.
Since the voltage across the capacitor cannot change instantaneously, the
output will jump suddenly to 20  = 10 V. See Figure 2.81.
 Figure 2.81 Example 2.24: output waveform.

In the interval 0 < t < T/2, the capacitor C charges slowly with a time
constant t = (RS + Rf)C = (50  + 50 )  2 F = 200 s. Since the
period, T = 1/(5 kHz) = 200 s, so, at t = T/2 = 100 s, i.e. at the end of the
half cycle, the output will fall to
(–T/2)/t –100/200 –0.5
vo = 10e = 10e = 10e =6V

At this time, the voltage across Rf is 6 V. The voltage across RS is also 6

V, and so the voltage across the capacitor vC is 8 V(=20 – 6 – 6).
At t = T/2, the input drops back to zero, and the diode is cut off and the
equivalent circuit of Figure 2.80(b) results. In this circuit vC = 8 V and vS =
0. So, the output voltage is
 The output now again starts to decay towards zero. However, the time
constant now is RC = 20 k  2 F = 40,000 s, or 400 times larger than
T/2 = 100 s. Therefore, the decay is negligible and so the output is shown
as a straight line during that interval.
Since in the interval T/2 < t < T, the voltage across the capacitor has not
+
changed, then at t = T , the output returns to +6 V, because the voltage
across Rf is equal to

Again, in the interval T < t < 3T/2, the output decays towards zero and the
decay in this interval is a continuation of the portion in the interval 0 < t <
T/2. If all of the decays indicated were moved together so that they just
joined, they would form one continuous exponential decay from 10 V
towards zero.
–1/2
At t = 3T/2,.........vo = 6e = 3.6 V

The remaining calculations are repetitions of those above and the results
are shown in Figure 2.81. Observe that, cycle-by-cycle, the output
waveform approaches the steady-state case, where the positive excursion of
the waveform is clamped approximately to zero.
Relation between tilts in forward and reverse directions
The steady-state output waveform for a square wave input. Consider that
the square wave input shown in Figure 2.82(a) is applied to the clamping
circuit shown in Figure 2.79. The general form of the output waveform
would be as shown in Figure 2.82(b), extending in both positive and
negative directions and is determined by the voltages V1, V1, V2, and
V2. These voltages may be calculated as discussed below.

Figure 2.82 (a) A square wave input signal of peak-to-peak amplitude V, (b) the general
form of the steady-state output of a clamping circuit with the input as in (a).

In the interval 0 < t < T1, the input is at its higher level; so the diode is
ON and the capacitor charges with a time constant (RS + Rf)C, and the
output decays towards zero with the same time constant. Hence,
 –
Considering the conditions at t = T1. At t = T1 , vS = V, vo = V1, the
diode D is ON, and the equivalent circuit of Figure 2.80(a) results. The
voltage across the capacitor is given by
From equations (i), (ii), (v) and (viii), the values V1, V1, V2 and V2 can
be computed and the output waveform determined.
If the source impedance is taken into account, the output voltage jumps
are smaller than the abrupt discontinuity V in the input. Only if RS = 0, are
the jumps in input and output voltages equal. Thus, when RS = 0,

V1 – V2 = V1 – V2 = V

Observe that the response is independent of the absolute levels V and

V of the input signal and is determined only by the amplitude V. It is
possible, for example, for V to be negative or even for both V and
V to be negative.
The average level of the input plays no role in determining the steady-
state output waveform.
Under steady-state conditions, there is a tilt in the output waveform in
both positive and negative directions. The relation between the tilts can be
obtained by subtracting Eq. (viii) from Eq. (v), i.e.

Since RS is usually much smaller than R, then, the tilt in the forward
direction f is almost always less than the tilt r in the reverse direction.
Only when RS << Rf, are the two tilts almost equal.
2.2.6 Clamping Circuit Theorem
Under steady-state conditions, for any input waveform, the shape of the
output waveform of a clamping circuit is fixed and also the area in the
forward direction (when the diode conducts) and the area in the reverse
direction (when the diode does not conduct) are related.

The clamping circuit theorem states that, for any input waveform under
steady-state conditions, the ratio of the area Af under the output voltage
curve in the forward direction to that in the reverse direction Ar is equal
to the ratio Rf/R.

This theorem applies quite generally independent of the input waveform

and the magnitude of the source resistance. The proof is as follows:
Consider the clamping circuit of Figure 2.79, the equivalent circuits in
Figures 2.80(a) and 2.80(b), and the input and output waveforms of Figures
2.82(a) and 2.82(b) respectively.
In the interval 0 < t < T1, the input is at its upper level, the diode is ON,
and the equivalent circuit of Figure 2.80(a) results. If vf(t) is the output
waveform in the forward direction, then the capacitor charging current is

Therefore, the charge gained by the capacitor during the forward interval is
In the interval T1 < t < T1 + T2, the input is at its lower level, the diode is
OFF, and the equivalent circuit of Figure 2.80(b) results. If vr(t) is the
output voltage in the reverse direction, then the current which discharges
the capacitor is

Therefore, the charge lost by the capacitor during the reverse interval is

Under steady-state conditions, the net charge acquired by the capacitor over
one cycle must be equal to zero. Therefore, the charge gained in the interval
0 < t < T1, will be equal to the charge lost in the interval T1 < t < T1 + T2,
i.e. Qg = Ql.

EXAMPLE 2.25 An unsymmetrical square wave with T1 = 1 ms and T2 =

1 s has an amplitude of 20 V. This signal is applied to the clamping circuit
of Figure 2.79 in which Rf = 100 , R = 100 k and RS = 0. Assume that
the capacitor C is arbitrarily large, so that the output is a square wave
without tilt. (a) Find where the zero-level location on the waveform is
located. (b) If the waveform is inverted so that T1 = 1 s and T2 = 1 ms,
find the location of the zero-level.

Solution: (a) The output waveform and zero-level are shown in Figure
2.83(a).
 Since RS = 0, the peak-to-peak value of the output is the same as that of
the input, i.e. 20 V, and the tilts in the forward and reverse directions are
equal, i.e.

f = r

Since C is arbitrarily large, there is no tilt in the output waveform, i.e.

f = r = 0

which means that the output has a flat top and a flat bottom.

Af = 1000 V1 and Ar = 20 – V1

As per the clamping circuit theorem,

–5
Solving it, V1 = 2  10 V.
This example illustrates that clamping of the broad base line of the
waveform is quite precise, since only a few millionths of the input
waveform is above the zero level.
(b) When the input is inverted, the output waveform is as shown in Figure
2.83(b).
 Figure 2.83 Example 2.25: (a) and (b) output waveforms.

From the clamping circuit theorem,

The zero-level is now not near the positive peak, but is half-way down the
waveform and the circuit performs very poorly as a clamp. This shows that
it is not possible to clamp the narrow peaks precisely.

2.2.7 Practical Clamping Circuit

Perfect flatness of the positive and negative peaks of a square wave can be
obtained only if the capacitor C is arbitrarily large. Practically, in clamping
circuits the capacitor C is such that (Rf + RS)C << T1, and (R + RS)C >>
T2. So, a square wave after clamping appears as shown in Figure 2.84. This
is because during the interval T2, when (R + RS)C >> T2, the capacitor
discharges very slowly and hence there will be a small tilt in the output. In
the interval T1, when (Rf + RS)C << T1, the capacitor recharges very fast
and hence there will be a small spike of magnitude f, at the beginning, and
for the remaining interval T1, the output will be zero. The overshoot f is
usually smaller than the tilt r.

Figure 2.84 The output of a practical clamping circuit for a square wave input.

For the case shown in Figure 2.84, the voltage values are

Even if we assume that the capacitor C is arbitrarily large, unless the

source resistance RS is zero, the part of the input signal which occurs when
the diode is conducting appears at the output multiplied by Rf/(Rf + RS),
and the signal which occurs when the diode is not conducting, appears at
the output multiplied by R/(R + RS). Usually R/(R + RS) is much closer to
unity than Rf/(Rf + RS). Such selective attenuation flattens that part of the
signal, which drives the diode into conduction. This distortion is more
easily observed in the case of a signal with a sharp peak such as a ramp. It is
not apparent in the case of a square wave because it has flat top and flat
bottom. Quite independent of the distortion, the clamping circuit theorem
Af/Ar = Rf/R is valid. See Figure 2.85.

Figure 2.85 Clamping of a ramp signal: (a) input waveform and (b) output waveform.

In the case of biased clamping, i.e. when a reference voltage source VR is

connected in series with the diode to clamp the signal positively, or
negatively with reference to VR, for perfect circuit operation, the positive
excursion of the signal with reference to its average value must be larger
than VR. If the diode breakdown voltage Vg is not negligible, the clamping
circuit theorem for biased clamping is
where T1 is the interval over which the diode is forward biased and R >>
Rf.

2.2.8 Effect of Diode Characteristics on Clamping Voltage

We studied earlier that, when a signal is applied to a clamping circuit, the
circuit clamps the input signal to a definite voltage level and there is no
change of waveform. For an ideal diode, Vg = 0 and Rf = 0. However, for a
practical diode this does not hold good. The forward resistance of the diode
is of the order of a few tens of ohms and Vg = 0.2 V for germanium and 0.6
V for silicon. So a practical diode is represented by an ideal diode in series
with a battery Vg and a resistor Rf. The volt-ampere characteristic of the
diode influences the clamping voltage.
For the clamping circuit shown in Figure 2.86(a) the input signal vs is a
square wave shown in Figure 2.86(b) with peak-to-peak amplitude of V
volts. Assume that the capacitor C is arbitrarily large so that the output
waveform vo across the diode is similarly a square wave. The source
resistance is assumed to be zero to simplify the calculations.

Figure 2.86 (a) A negative clamping circuit and (b) input signal.

During the interval when the input signal is at its positive extremity V,
the diode clamps the output at some clamping voltage Vcl, and the
corresponding diode current is
Vc1/hVT
Icl = Ioe

Io is the reverse saturation current and h = 1 for Ge diode and h = 2 for Si

diode for relatively low levels of diode current. h = 1 for both Ge and Si for
higher levels of diode current. Also VT is the volt-equivalent of
temperature, and its value may be taken as 26 mV.
This current charges the capacitor C so that the voltage across the
capacitor VA = V – Vcl
During the negative half cycle of the input signal, the diode gets reverse
biased and hence does not conduct. The capacitor discharges through
resistor R.

The clamping voltage may be obtained from equation (i). Equation (ii)
indicates how the clamping voltage varies with the amplitude of the input
signal.
From equation (ii) for Ge with V = 10 volts, h = 1, if the input voltage
changes by 1 volt, i.e. dV = 1 volt, we get
dVcl = VT/10 = 2.6 mV

Equation (ii) also indicates that the dependence of the clamping voltage
Vcl on V reduces as the amplitude V of the input signal increases. This is
due to the fact that the diode clamps higher on its volt–ampere characteristic
for an increased value of V. This is obvious, since for a fixed change of
current, a smaller voltage change is needed, higher up on the V–I
characteristic.
The clamping circuit is modified as shown in Figure 2.87 to take
advantage of the above fact and improving the stability of the clamping
level of the biased diode.

Figure 2.87 Clamping circuit modified to reduce the dependence of Vcl on V.

In the modified circuit, the resistor R is connected to an auxiliary voltage

source Vyy. This supplies a current Vyy/R which flows through the diode
even when there is no input signal. Figure 2.87 shows a clamping circuit in
which the diode is biased to operate higher on its V–I characteristic.
 The diode current Icl, in the presence of a square wave input signal of
peak-to-peak amplitude V is given as

This shows that with Vyy = 50 volts, the value of dVcl is only about one-
tenth of that obtained with Vyy = 0 V(0.24 mV and 2.6 mV)
If the diode is represented by a piece-wise linear model, then the
clamping circuit theorem when applied to the biased diode of circuit 2.87
must be generalized as

where T is the period of the input square wave, T1 is the interval over which
the diode conducts, and Vg is the diode break-point voltage.

2.2.9 Synchronized Clamping

The dc restorers discussed above are examples of clamping circuits in
which the time during which the clamping is effective is controlled by the
signal itself. Useful features result when the time of clamping is not
determined directly by the signal but is determined rather by an auxiliary
voltage called a control signal which occurs synchronously with the signal.
Such type of clamping is called synchronous clamping.
 It is not possible to use synchronized clamping with a signal of arbitrary
waveform. Synchronous clamping may be used whenever the signal has
periodically occurring intervals during which the input waveform is
quiescent. Where synchronized clamping is feasible, it may be used to
provide dc restoration even when the positive and negative excursions of
the signal fluctuate from cycle to cycle.
A synchronous clamping circuit is shown in Figure 2.88(b). The signal is
transmitted from input to output through the capacitor Cs. The two diode
circuit which is bridged between signal lead and ground serves the function
of the switch S in Figure 2.88(a). Two control signal pulse trains v1 and v2
are required. These waveforms are identical in all respects except that one is
the inverse of the other. The dc levels of the waveforms are of no
consequence.

Figure 2.88 Synchronized clamping circuit.

This circuit may be analyzed in much the same manner as the dc restorer
circuit because the two circuits have many features in common. Such an
analysis reveals that in the steady-state during the interval Tc, the diodes are
brought to conduction and that the voltage at point A is the same as at point
B. As in the dc restorer, the diodes conduct briefly to supply to the
capacitors C, the charge lost through the resistors R during the non
conducting interval Tn. During Tn both the diodes are back biased, and the
output signal lead is entirely free to flow the input signal. Suppose that at
the end of an interval Tn, the voltage at A is not equal to VR. Then, when
the diodes are brought to the point of conduction, if it should happen that
VA > VR, the diode D1 will conduct, discharging capacitor Cs into
capacitor C until VA = VR. If VA < VR, diode D2 will conduct until VA =
VR.
For proper operation of the circuit it is required that C > Cs and that RC >
Tn. There is however an upper limit on R which results from the fact that
during the interval Tn, the capacitor must be able to discharge through R the
charge it may have acquired from Cs during the interval Tc. When Cs
discharges, it does so through a diode forward resistance Rf and through the
output impedance Rs of one of the generators that furnishes the control
signal. Hence it is also required that Cs (Rf + Rs) << Ts. The required
minimum amplitude Vp of the clamping pulse is determined by the
condition that neither diode be brought into conduction during the interval
Tn by the signal. This condition leads to the restriction that Vp > Vs, where
Vs is the peak signal excursion above or below the average value of the
signal. If the clamping pulse amplitudes are not equal, the circuit will not
clamp to VR but to a somewhat different voltage.
EXAMPLE 2.26 A symmetrical 10 kHz square wave whose peak-to-peak
excursions are 10 V with respect to ground is impressed on the clamping
circuit of Figure 2.79. Here R = 10 k, C = 1 F, the diode has Rr = , Rf
= 0, Vg = 0 and the source impedance RS is zero. (a) Sketch the output
waveform. (b) If the diode forward resistance is 1 k, sketch the output
waveform. Calculate the maximum and minimum values with respect to
ground. (c) Repeat part (b) if the source impedance is 1 k.

Solution: (a) The input and the output waveforms are shown in Figures
2.89(i) and 2.89(ii) respectively.

Figure 2.89 Example 2.26(a): (i) input waveform and (ii) output waveform.

and the amplitude of discontinuity in output = amplitude of discontinuity in

input.
 The output waveform is as shown in Figure 2.90.

Figure 2.90 Example 2.26(b): output waveform.

Since RS  0, f  r, and the amplitude of discontinuity in output 

the amplitude of discontinuity in input.
 –T/2(Rf+RS)C –0.0510–3/(1+1)103110–6
V1 = V1e = V1e =
–0.05/2
V1e = 0.975 V1
–T/2(R+RS)C –0.0510–3/(10+1)103110–6
V2 = V2e = V2e =
–0.05/11
V2e = 0.995 V2

EXAMPLE 2.27 In the restorer circuit shown in Figure 2.79, Rf = 0.1 k,
Rr = , Vg = 0 and R = 100 k. The waveform is a square with V = 30
volts, T1 = 50 s and T2 = 1000 s.
(a) Assume RS = 0, and that C is arbitrarily large. Calculate and sketch
the steady-state output voltage vo. (b) Repeat (a) if RS = 0.1 k. (c) Repeat
(b) if C = 0.05 F and (d) repeat (c) if Vg = 0.7 V.
Solution: (a) C is arbitrarily large. So, the output waveform has flat top and
flat bottom, i.e. there is no tilt in the output. RS = 0, therefore, the amplitude
of discontinuity in input is equal to the amplitude of discontinuity in output.
The input and output waveforms are as shown in Figures 2.91(i) and
2.91(ii) respectively.
From the clamping circuit theorem,

So, the output waveform is the same as shown in Figure 2.91, with V1 =
0.296 V and |V2| = 29.6 V.
 Figure 2.91 Example 2.27(a): (i) input waveform and (ii) output waveform.

(c) C = 0.05 F. Since the capacitor is finite, the output is exponential at
the top and the bottom as shown in Figure 2.92(i).

(d) The capacitor C is finite and Vg = 0.7 V, so the output is exponential

at the top and at the bottom as shown in Figure 2.92(ii).
 Figure 2.92 Example 2.27(c): (i) output waveform. Example 2.27(d): (ii) output waveform.

EXAMPLE 2.28 An attempt needs to be made to restore the maximum

value of the periodic waveform shown in Figure 2.93(a) to a value of +10 V.
The diode used has Vg = 0, Rf = 20  and Rr = . Assume zero source
impedance. The coupling capacitor has a value of 0.05 F. Because of the
load, the effective resistance across the diode when it is not conducting is
20 k. (a) Indicate the circuit to be used. (b) Make a careful sketch of the
output waveform. (c) Indicate two important areas on your sketch and state
the ratio of these two areas.

Solution: The circuit required to clamp the output waveform to +10 V is

shown in Figure 2.93(b). The ideal output waveform is shown by the dotted
lines and the practical waveform is shown by thick lines in Figure 2.93(c).
The important areas in the output waveform are indicated in Figure 2.93(c).
The positive area is above the +10 V line and the negative area is below the
zero axis.

From the clamping circuit theorem,

where Af is the area above the 10 V line.

Now, during the positive swing
–T1/RfC –1010–6/200.0510–6 –10
V1 = V1e = V1  e = V1  e 0

where V1 is the voltage level above 10 V. Therefore, with reference to

zero level V1 = 10 V.
Hence, at t = T1, when the input falls by 30 V, the output also falls by 30
V from 10 V to –20 V.
 Figure 2.93 Example 2.28: (a) input waveform, (b) circuit diagram required, and (c) the output
waveform.

EXAMPLE 2.29 A square wave of peak-to-peak value 20 V with T1 = 1

ms and T2 = 10 ms is applied to the restorer circuit shown in Figure 2.79.
The circuit has RS = 0, R = 1 k, C = 0.1 F, Rf = 10 , Rr = , and Vg =
0.
(a) Compute the steady-state output waveform vo. (b) Repeat (a) if the
diode terminals are reversed. (c) Repeat (a) if R = 1 M.

Solution: (a) Since the time constants for charging (Rf C) and discharging
(RC) are very small, the capacitor charges and discharges very fast and the
output waveform is as shown in Figure 2.94.

Figure 2.94 Example 2.29(a) and (b): output waveform.

(b) If the diode terminals in Figure 2.79 are reversed, the output needs to
be positively clamped, but because of very small time constants the
capacitors charge and discharge very fast and the same output waveform as
shown in Figure 2.94 results.
 Figure 2.95 Example 2.29(c): output waveform.

2.2.10 Design of a Clamping Circuit

EXAMPLE 2.30 Design a diode clamper circuit to clamp the positive

peaks of the input signal at zero level. The frequency of input voltage is 750
Hz.
Solution: Since the positive peaks of the input signal are to be clamped at
zero level, we require an unbiased negative clamping circuit as shown in
Figure 2.96.
Assume that the diode has Rf = 100  and Rr = 200 k and let RC = 20
T.

Figure 2.96 Example 2.30: circuit diagram.

EXAMPLE 2.31 Design a diode clamper to restore the bottom peaks

(negative peaks) of the input signal to zero level. Use a silicon diode with
Rf = 50  and Rr = 400 k. The frequency of input voltage is 5 kHz.

Solution: The negative peaks are to be clamped to zero level. So it is an

unbiased positive clamping circuit as shown in Figure 2.97. Let RC = 20T.
 Figure 2.97 Example 2.31: circuit diagram.

EXAMPLE 2.32 Design a diode clamper to restore the positive peaks of 1

kHz input signal to a voltage level equal to 5 V. Assume the voltage drop
across diode as 0.7 V.

Figure 2.98 Example 2.32: circuit diagram.

EXAMPLE 2.33 Design a diode clamper to restore a dc level of + 5 V to
an input signal of peak-to-peak value 15 V. Assume the drop across the
diode as 0.7 V.

Solution: The circuit required is shown in Figure 2.99(a). In order to restore

a +5 V d.c. level to the input signal, the output signal has to appear as
shown in Figure 2.99(b). The output peak-to-peak is the same as that of the
input peak-to-peak, i.e. 15 V.
The positive peaks of the output will be clamped at 12.5 V and the
negative peaks at –2.5 V.

Figure 2.99 Example 2.33: (a) circuit diagram and (b) output waveform.
EXAMPLE 2.34 Calculate the steady-state output voltage level and plot
the waveform when an input signal with a peak-to-peak value of 15 V is
applied to a clamping circuit. The input base level is a zero level. The
frequency of the input signal is 5 kHz, C = 0.1 F, R = 20 k, Rf = 1 k,
Rr = 500 k. Assume T1 = T2.

Solution: The circuit diagram, and the input and output waveforms are as
shown in Figure 2.100.

Figure 2.100 Example 2.34: (a) circuit diagram, (b) input waveform, and (c) the output waveform.

The charging time constant of the capacitor is given by

The discharging time constant of the capacitor is

EXAMPLE 2.35 A clamping circuit and the input applied to it are shown
in Figures 2.101(a) and (b) respectively. Calculate and plot to scale the
steady-state output. Rf = 100 , RS = 100 , T1 = 100 s, and T2 = 1000
s.

Solution: The output waveform is as shown in Figure 2.101(c).

In the interval 0 < t < T1, the capacitor charges and the charging time
constant is
–6
tf = [(Rf || R) + RS]C  (Rf + RS)C = (100 + 100)  0.2  10 = 40 s
 In the interval T1 < t < T1 + T2 the capacitor discharges and the discharge
time constant is
3 –6
tr = [(R || Rr) + RS]C  (R + RS)C = (200  10 + 100)  0.2  10 =
40.02 ms

From Figure 2.101(c),

–T1/tf –10010–6/4010–6
V1 = V1e = V1e = 0.082 V1
–T2/tr –100010–6/40.0210–3
V2 = V2e = V2e = 0.975 V2

Figure 2.101 Example 2.35: (a) circuit diagram, (b) input waveform, and (c) output waveform.
EXAMPLE 2.36 The input waveform shown in Figure 2.102(a) is applied
to the clamping circuit with RS = Rf = 100 , Rr = , R = 10 k, C = 1 F,
and Vg = 0. Draw the output waveform and label all voltages.

Solution: When the diode is ON, the capacitor charges through RS and Rf
as shown in Figure 2.102(c) with a time constant
–6
tf = (Rf + RS)C = (100 + 100)  1  10 = 200 s
 Figure 2.102 Example 2.36: (a) input waveform, (b) circuit diagram, (c) equivalent circuit
when D is ON, (d) equivalent circuit when D is OFF, and (e) output waveform.

When the diode is OFF, the capacitor discharges through R and RS as

shown in Figure 2.102(d) with a time constant
–6
tr = (R + RS)C = (10,000 + 100)  1  10 = 10.1 ms

The output waveform is shown in Figure 2.102(e).

At t = 0.1 ms, the input voltage shoots up to 10 V. Since the voltage
across the capacitor cannot change instantaneously, it remains at 0 V at t =
0.1 ms.

Since RS = Rf, voltage across RS is also = 3.032 V

 Voltage across capacitor = 10 – 3.032 – 3.032 = 3.936 V

At t = 0.2 ms, the input voltage drops instantaneously from 10 V to – 4 V
Since the voltage across the capacitor cannot change abruptly it remains
at 3.936 V. The diode now becomes reverse biased and hence it is OFF and
the circuit of Figure 2.102(d) results.
 SHORT QUESTIONS AND ANSWERS
1. What do you mean by clipping?
A. Clipping means cutting and removing a part. It is the process of
cutting and removing a part of the input waveform.
2. What are clipping circuits?
A. Clipping circuits are circuits used to select for transmission that part
of an arbitrary waveform which lies above or below some particular
reference level.
3. What are the other names of clipping circuits?
A. The other names of clipping circuits are: voltage (or current)
limiters, amplitude selectors or slicers.
4. What are the three configurations of clipping circuits?
A. The three configurations of clipping circuits are as follows:
(a) A series combination of a diode, a resistor and a power supply
(b) A network consisting of a number of diodes, resistors and power
supplies
(c) Two emitter coupled transistors operating as an overdriven
differential amplifier
5. Which devices are required for clipping purposes? Name the
commonly used ones.
 A. Nonlinear devices are required for clipping purposes. Diodes and
transistors are commonly used.
6. Why should the resistance in the clipping circuit be chosen as the
geometric mean of the diode forward and reverse resistances?
A. The resistance in the clipping circuit is to be chosen as the
geometric mean of the diode forward and reverse resistances because
in the transmission region of a diode clipping circuit, it is required that
Rr >>R, i.e. Rr = KR, where K is a large number, and in the attenuation
region, it is required that R >> Rf, i.e. R = KRf

7. What is the disadvantage of having a diode as a series element in a

clipper?
A. The disadvantage of having a diode as a series element in a clipper
is that, when the diode is off and it is intended that there be no
transmission, fast signals or high frequency waveforms may be
transmitted to the output through the diode capacitance.
8. What is the disadvantage of having a diode as a shunt element in a
clipper?
A. The disadvantage of having a diode as a shunt element in a clipper
is that when the diode is open and it is intended that there be
transmission, the diode capacitance together with all other
capacitances in shunt with the output terminals will round off the sharp
edges of the input waveforms and attenuate the high frequency signals.
9. How many nonlinearities exist for a diode, and when do those
nonlinearities occur?
A. For a diode, only one nonlinearity exists. It occurs when the diode
goes from OFF to ON.
10. How many nonlinearities are there for a transistor, and when do those
nonlinearities occur?
A. A transistor has two pronounced nonlinearities. One of them occurs
when the transistor goes from cut-in region into the active region and
the second one occurs when the transistor goes from the active region
into the saturation region.
11. What do you mean by single ended clipping?
A. Single ended clipping, also called one level clipping, is one in
 which only one part of the waveform which is above or below some
reference level is clipped off.
12. What do you mean by double ended clipping?
A. Double ended clipping, also called two level clipping, is one in
which parts of the waveform above one reference level and also below
another reference level are clipped off.
13. What for clipping circuits are used?
A. Clipping circuits may be used to convert sine waves into square
waves. They may also be used to remove unwanted noise signals.
14. What is the figure of merit for diodes used in clipping circuits?
A. The ratio Rr / Rf is a figure of merit for diodes used in clipping
circuits.
15. What do you mean by a comparator?
A. A comparator is one which may be used to mark the instant when
an arbitrary waveform attains a particular reference level.
16. Distinguish between comparators and clipping circuits.
A. The distinction between clipping circuits and comparator circuits is
that, in comparator circuit there is no interest in reproducing any part
of the signal waveform, but in a clipping circuit, part of the signal
wave form is to be reproduced.
17. What are the applications of voltage comparators?
A. The applications of voltage comparators are the following. They
may be used
1. In accurate time measurements
2. In pulse time modulation
3. As timing markers generated from a sine wave
4. In phase meters
5. In amplitude distribution analyzers
6. To obtain square wave from a sine wave
7. In analog-to-digital converters
18. What do you mean by a regenerative comparator? Give an example.
A. A regenerative comparator is one in which positive feedback is
employed to obtain an infinite forward gain (unity loop gain). The
Schmitt trigger, and the blocking oscillator are examples of
regenerative comparators.
19. What do you mean by a non-regenerative comparator? Give an
example.
A. A non-regenerative comparator is one in which positive feedback is
not employed. A clipping circuit is an example of non-regenerative
comparator.
20. What does the Schmitt trigger comparator generate?
A. The Schmitt trigger comparator generates approximately a step
input.
21. What does the blocking oscillator comparator generate?
A. The blocking oscillator comparator generates a pulse.
22. What do you mean by clamping? What for clamping circuits are used?
A. Clamping means fixing. Clamping circuits are used to clamp or fix
the extremity of a periodic waveform to some constant reference level
VR thereby to introduce a dc level.
23. What are the other names of a clamping circuit?
A. The other names of clamping circuits are (a) dc restorer and (b) dc
reinserter.
24. What do you mean by a one-way clamp?
A. A one-way clamp is a clamping circuit which uses only one diode
and which restrains the voltage change in only one direction?
25. What do you mean by a two-way clamp?
A. A two-way clamp is a clamping circuit which uses two diodes and
which restrains the voltage change in both the directions.
26. Why is the clamping circuit also called a dc inserter?
A. The clamping circuit is also called a dc inserter because it
introduces a dc component.
27. What do you mean by (a) positive clamping and (b) negative
clamping?
A. Positive clamping means the negative extremity of the waveform is
fixed at the reference level and the entire waveform appears above the
reference level.
Negative clamping means the positive extremity of the waveform is
fixed at the reference level and the entire waveform appears below the
reference level.
28. In positive clamping, which extremity of the waveform is fixed at the
reference level?
A. In positive clamping, the negative extremity of the waveform is
fixed at the reference level.
29. In negative clamping, which extremity of the waveform is fixed at the
reference level?
A. In negative clamping, the positive extremity of the waveform is
fixed at the reference level.
30. Write the relation between the tilts in the forward and reverse
directions of the output of a clamping circuit excited by a square wave.
A. The relation between the tilts in the forward and reverse directions
of the output of a clamping circuit excited by a square wave input is

31. State clamping circuit theorem.

A. The clamping circuit theorem states that for any input waveform
under steady-state conditions, the ratio of the area Af under the output
voltage curve in the forward direction to that in the reverse direction
Ar is equal to the ratio Rf / R, i.e.

32. State the clamping circuit theorem considering the source resistance.
A. The clamping circuit theorem considering the source resistance is

33. In a clamping circuit, when can the tilts in the forward and reverse
directions be equal?
A. In a clamping circuit, the tilts in the forward and reverse directions
can be equal if Rs = 0.
34. The precision of operation of the clamping circuit depends on which
condition?
A. The precision of operation of the clamping circuit depends on the
condition that R >>Rf and Rr >>R.
35. What do you mean by biased clamping?
A. A biased clamping is one in which a reference voltage source is
connected in series with the diode. So, clamping is not at zero level but
at some level.
36. What do you mean by a practical clamping circuit?
A. A practical clamping circuit is one in which
Rs  0, Rf  0, Vg  0, Rr   and C is not arbitrarily large.
37. What is the difference between clipping and clamping?
A. Clipping means cutting and removing a part of the waveform. So,
the output of the clipping circuit will be different from the input.
Clamping means fixing the maximum positive or negative peak of the
waveform to a desired level. So, the output of the clamping circuit will
be the same as the input.

REVIEW QUESTIONS
1. With the help of a neat circuit diagram and waveforms, explain the
working of a transistor clipper.
2. With the help of a neat circuit diagram, explain the working of a two-
level diode clipper.
3. With the help of a neat circuit diagram, explain the working of an
emitter-coupled clipper.
4. Explain how a sine wave may be converted into a square wave using a
clipping circuit.
5. With the help of a circuit diagram, explain the working of a simple
diode comparator. Draw the output waveform for a ramp input.
6. Explain how a sine wave may converted into a square wave using
zener diodes.
7. With the help of a neat circuit diagram and waveforms, explain the
working of a negative clamping circuit.
8. With the help of a neat circuit diagram and waveforms, explain the
working of a positive clamping circuit.
9. Explain the principle of clamping. Discuss the effects of source
impedance, load resistance and cut-in voltage.
10. Write the procedure for designing a clamping circuit.
11. Explain the principle of clamping. What is the need for a shunting
resistor R in parallel with the diode in the basic clamping circuit?
12. Derive the relation between the tilts in the forward and reverse
directions of the output of a clamping circuit excited by a square-wave
input.
13. State and prove the clamping circuit theorem.
14. What is synchronized clamping? Explain.

FILL IN THE BLANKS

1. is the process of cutting and removing a part of the
waveform.
2. circuits are used to select for transmission that part of an
arbitrary waveform which lies above or below some particular
reference voltage level.
3. Clipping circuits are also called or limiters,
selectors, or .
4. Clipping circuits do not require elements.
5. In the simple clipping circuits, the external resistance R is selected to
be the of the diode forward and reverse resistances, i.e. R
= .
6. The use of the diode as a series element has the disadvantage that
.
7. The use of the diode as a shunt element has the disadvantage that
.
8. A transistor has nonlinearities which can be used for
clipping purposes.
9. A diode has nonlinearity which can be used for clipping
purposes.
10. Single ended clipping is also called clipping.
11. Double ended clipping is also called clipping.
12. In a diode, the nonlinearity occurs when it goes from to
.
13. In a transistor, the nonlinearities occur when (a) the device goes from
_________ region to region and (b) the device goes from
 region to region.
14. The emitter-coupled clipper is a clipper. It is an emitter-
coupled amplifier.
15. A clipping circuit may be used to convert a sine wave into a
____________ wave.
16. A circuit is one, which may be used to mark the instant
when an arbitrary waveform attains some particular reference level.
17. Comparators may be comparators or
comparators.
18. circuits may be used as comparators.
19. Clipping circuits are comparators.
20. The Schmitt trigger is a comparator.
21. Regenerative comparators employ feedback.
22. In a clipper, when the diode is OFF, the output follows the
input.
23. In a clipper, when the diode is ON, the output follows the
input.
24. Clipping circuits differ from comparators in that .
25. An example of a non-regenerative comparator is a .
26. An example of a regenerative comparator is a .
27. The Schmitt trigger comparator generator generates approximately
.
28. The blocking oscillator comparator generates .
29. are used to fix the positive or negative extremity of a
periodic waveform at some constant reference level.
30. Under steady-state conditions, the clamping circuits restrain the
of a waveform going beyond VR.
31. Clamping circuits may be clamps or clamps.
32. When only one diode is used and the voltage change in only one
direction is restrained, the circuits are called clamps.
33. When two diodes are used and the voltage change in both directions is
restrained, the circuits are called clamps.
34. The circuit is often referred to as dc restorer or dc
reinserter.
35. A clamping circuit should be actually called a .
36. Clamping circuits may be clamping circuits or
clamping circuits.
37. In clamping, the negative extremity of the waveform is
fixed at the reference level and the entire waveform appears above the
reference.
38. In clamping, the positive extremity of the waveform is
fixed at the reference level and the entire waveform appears below the
reference.
39. In circuits, the average level of the input plays no role in
determining the steady-state output waveform.
40. The difference between the clippers and the clampers is that
.
41. The clamping circuit theorem states that .
42. The precision of operation of the circuit depends on the conditions
and .
43. The response of a clamping circuit is independent of of
the input signal and is determined only by the .
44. Only when , the tilts in the forward and reverse directions
are equal.
45. A clamping circuit is one in which Rf and RS are not
negligible and C is not arbitrarily large.
46. In clamping, a reference voltage source is connected in
series with the diode.
47. The tilt in the direction is almost always less than the tilt
in the direction.
48. The clamping circuit theorem for biased clamping is .
49. In the design of a clamping circuit, the value of R is to be selected such
that R = .
50. It is not possible to clamp the peak of pulses precisely.

OBJECTIVE TYPE QUESTIONS

1. Clipping circuits are used to
(a) attenuate the signals
(b) amplify the signals
 (c) remove a part of the signals
(d) none of the these
2. The circuits which are used to select for transmission a part of the
wave form are called
(a) clipping circuits
(b) clamping circuits
(c) linear wave shaping circuits
(d) none of these
3. Clipping circuits are also referred to as
(a) slicers
(b) amplitude selectors
(c) voltage (Current) limiters
(d) all of these
4. In a when the diode is ON, the output follows the input
(a) series diode clipper
(b) shunt diode clipper
(c) comparator
(d) none of these
5. In clipping circuits, the capacitors are
(a) unavoidable
(b) desirable
(c) essential
(d) none of these
6. The external resistance R in a series or shunt clipper is given by

7. The diode used in a clipping circuit has Rf = 25  and Rr = 1 M. The

external resistance R =
(a) 50 k
(b) 5 k
(c) 1/25 M
(d) 25 M
8. A diode has Rf = 10  and Rr = 100 k. Its figure of merit is
(a) 10  103
 (b) 10
(c) 10  105
(d) none of these
9. A diode shunt clipper is required to clip off the input which is exactly
above 4.6 V. The diode has Vg = 0.6 V. The value of VR must be
(a) 4 V
(b) 4.6 V
(c) 5.2 V
(d) none of these
10. A waveform which is above 6 V and below – 4 V is to be clipped off
properly. The diode has Vg = 0.6 V. The reference voltage sources to
be used are
(a) 5.4 V and – 3.4 V
(b) 6.6 V and – 4.6 V
(c) 6 V and – 4 V
(d) none of these
11. A metal semi-conductor diode is also called
(a) p-n diode
(b) hot-carrier diode
(c) cold-carrier diode
(d) zener diode
12. A has a very sharp break in its volt–ampere
characteristics, has very low capacitance and negligible storage time
and is mostly used in clipping circuits as comparator
(a) p-n diode
(b) hot-carrier diode
(c) cold-carrier diode
(d) zener diode
13. In a , when the diode is OFF, the output follows the input.
(a) series diode clipper
(b) shunt diode clipper
(c) comparator
(d) none of these
14. A transistor has
(a) no nonlinearity
 (b) one nonlinearity
(c) two nonlinearities
(d) none of these
15. When the emitters of two identical transistors are coupled, we get
(a) single ended clipper
(b) double ended clipper
(c) coupled clipper
(d) none of these
16. The circuit which is used to mark the instant when an arbitrary
waveform attains some reference level is called
(a) marker
(b) comparator
(c) attenuator
(d) none of these
17. Regenerative comparators employ
(a) negative feedback
(b) positive feedback
(c) no feedback
(d) none of these
18. Non-regenerative comparators are
(a) clipping circuits
(b) blocking oscillator
(c) Schmitt trigger
(d) none of these
19. Regenerative comparators are
(a) clipping circuits
(b) clamping circuits
(c) Schmitt trigger
(d) none of these
20. Clamping circuits are used to
(a) fix the extremity of the waveform at some level
(b) remove the middle portion of the waveform
(c) compare voltages
(d) reduce the amplitude of the signal
21. A circuit which restores or reinserts the lost dc component is called
(a) clipping circuit
 (b) clamping circuit
(c) linear wave shaping circuit
(d) none of these
22. A circuit which clamps the positive peak of a signal to zero level is
called
(a) positive clamping circuit
(b) negative clamping circuit
(c) positive peak clamping circuit
(d) negative peak clamping circuit
23. A circuit which clamps the negative peak of a signal to zero is called
(a) positive clamping circuit
(b) negative clamping circuit
(c) positive peak clamping circuit
(d) negative peak clamping circuit
24. In positive clamping, the entire input waveform appears
(a) above reference level
(b) below reference level
(c) symmetrically w.r.t. reference level
(d) none of these
25. In negative clamping, the entire input waveform appears
(a) above reference level
(b) below reference level
(c) symmetrically w.r.t. reference level
(d) none of these
26. A circuit which clamps the positive peak of a 10 V sine wave to 4 V
level is called
(a) 10/4 clamping circuit
(b) biased negative clamping circuit
(c) biased positive clamping circuit
(d) none of these
27. A circuit which clamps the negative peak of a 10 V sinusoidal signal to
+ 3 V level is called
(a) biased negative clamping circuit
(b) biased positive clamping circuit
(c) unbiased negative clamping circuit
(d) none of these
28. In clamping circuits, the capacitors are
(a) unavoidable
(b) desirable
(c) essential
(d) none of these
29. A clamping circuit should be called a
(a) dc restorer
(b) dc reinserter
(c) dc inserter
(d) dc eliminator
30. The clamping circuit theorem states that

31. Under steady-state conditions, the ratio of the area under the output
voltage curve in the forward direction to that in the reverse direction is
equal to 1/3. The ratio of Rf / Rr is
(a) 1/3
(b) 3
(c) 10
(d) cannot be known
32. Under steady-state conditions, the ratio of the area under the output
voltage curve in the forward direction to that in the reverse direction is
¼. Rf = 100 , R is
(a) 100 
(b) 400 
(c) 250 
(d) cannot be known
33. In a clamping circuit, the tilts in the forward and reverse direction are
related by:
 PROBLEMS
2.1 Draw a circuit to transmit that part of a sine wave, which is below + 6
V.
2.2 Draw a circuit to transmit that part of a sine wave, which is above – 5
V.
2.3 Draw a circuit to transmit that part of a sine wave, which lies between
+ 4 V and + 8 V.
2.4 Draw a circuit to transmit that part of a sine wave, which lies between
– 4 V and – 7 V.
2.5 Draw a circuit, to transmit that part of a sine wave which lies between
– 3 V and + 6 V.
2.6 Draw the transfer characteristic for the circuit shown in Figure P2.6.
Also draw the output waveform for a sinusoidal input of amplitude 25
V.

Figure P2.6 Circuit diagram.

2.7 For the circuit shown in Figure P2.7, plot vo versus vi indicating all
intercepts, slopes and voltages levels, if vi varies linearly from 0 to 50
V.
 Figure P2.7 Circuit diagram.

2.8 The clipper shown in Figure P2.8(b) is used with the input waveform
shown in Figure P2.8(a). Find the output waveform assuming that the
reverse resistance of the diode is infinite.

Figure P2.8 (a) Input waveform and (b) circuit diagram.

2.9 The input voltage vi to the two-level clipper shown in Figure P2.9
varies linearly from 0 to 150 V. Sketch the output voltage vo to the
same time scale as the input voltage. Assume ideal diodes.

Figure P2.9 Two-level clipper.

2.10 The input voltage vi to the two-level clipper shown in Figure P2.10
varies linearly from 0 to 200 V. Sketch the output voltage vo to the
same time scale as the input voltage.

Figure P2.10 Two-level clipper.

2.11 For the clipping circuit shown in Figure P2.11, make a plot of vo
versus vi for the range of vi from 0 to 100 V. Indicate all slopes and
voltage levels. Indicate for each region, the diodes which conduct.

Figure P2.11 Circuit diagram.

2.12 A 100 V peak square wave with an average value of 0 V and a

period of 20 ms is to be negatively clamped at 25 V. Draw the circuit
diagram necessary for this purpose. Also, draw the input and output
waveforms.
2.13 Sketch the output waveform you would expect from the circuit
shown in Figure P2.13, when the input is (a) a sine wave of vi = 40 sin
 wt and (b) a square wave of 40 V peak-to-peak.

Figure P2.13 Circuit diagram.

2.14 A 200 V peak square wave with an average value of 0 V and a

period of 30 ms is to be negatively clamped at 50 V. Draw the circuit
diagram necessary for this purpose. Draw the input and output
waveforms.
2.15 Sketch the output waveform you would expect from the circuit
shown in Figure P2.15 when the input is (a) a sine wave of vi = 30 sin
wt and (b) a square wave of  30 V peak-to-peak.

Figure P2.15 Circuit diagram.

2.16 In the circuit of Figure P2.16, RS = 100 , Rf = 50 , R = 100 k

and C = 2 F. A symmetrical square wave signal of amplitude 20 V
and frequency 5 kHz is applied at t = 0. Draw the first three cycles of
the output waveform.
 Figure P2.16 Circuit diagram.

2.17 An unsymmetrical square wave with T1 = 1 ms and T2 = 100 s has

an amplitude of 20 V. This signal is applied to the clamping circuit of
Figure P2.16 in which Rf = 50 , R = 50 k and RS = 0. Assume that
the capacitor C is arbitrarily large so that the output is a square wave
without tilt. (a) Find the location of zero-level on the waveform. (b) If
the waveform is inverted so that T1 = 100 s and T2 = 1 ms, find the
location of the zero-level.
2.18 A symmetrical 10 kHz square wave whose peak excursions are  20
V with respect to ground is impressed on the clamping circuit of
Figure P2.16. If R = 10 k, C = 2 F, the diode has Rr = , Rf = 0,
Vg = 0 and the source impedance RS is zero, (a) sketch the output
waveform, and (b) if the diode forward resistance is 1 k, sketch the
output waveform. Calculate the maximum and minimum values with
respect to ground. (c) Repeat part (b) if the source impedance is 1 k.
2.19 In the restorer circuit shown in Figure P2.16, Rf = 200 , Rr = , Vg
= 0, and R = 200 k. The waveform is a square with V = 30 V, T1 =
100 s, and T2 = 1000 s. (a) Assume RS = 0  and C is arbitrarily
large. Calculate and sketch the steady-state output voltage vo. (b)
 Repeat (a) if RS = 200 . (c) Repeat (b) if C = 0.1 F, (d) Repeat (c)
if Vg = 0.5 V.

2.20 An attempt needs to be made to restore the maximum in Figure

P2.20 to a value of +15 V. The diode used has Vg = 0, Rf = 10  and
Rr = . Assume zero source impedance. This coupling capacitor has a
value of 0.1 F. Because of the load, the effective resistance across
the diode when it is not conducting is 20 k. (a) Indicate the circuit to
be used. (b) Make a careful sketch of the output waveform. (c)
Indicate two important areas on your sketch and state the ratio of these
two areas.

Figure P2.20 Input waveform.

2.21 A square wave of peak-to-peak value 10 V with T1 = 2 ms and T2 =

20 ms is applied to the restorer circuit shown in Figure P3.5. The
circuit has RS = 0 , Rr = , R = 0.5 k, C = 0.1 F, Rf = 10  and
Vg = 0. (a) Compute the steady-state output waveform vo. (b) Repeat
(a) if R = 1 MW.
 Chapter 3
Switching Characteristics
of Devices

Electronic devices such as junction diodes, thermionic diodes, transistors,

and vaccum tubes all have extreme regions of operation in which they
nominally do not conduct even when large voltages are applied, and there
are regions in which they conduct heavily even when relatively small
voltages are applied. In the first of these regions, the device is described as
being OFF, OPEN, or nonconducting. In the other extreme region the
device is described as being ON, CLOSED or conducting. When the device
is driven from one extreme condition to the other, it operates much like a
switch.

3.1 JUNCTION DIODE—SWITCHING TIMES

Diode forward recovery time
When a diode is driven from the reverse-biased condition to the forward-
biased condition or in the opposite direction, the diode response is
accompanied by a transient, and an interval of time elapses before the diode
recovers to its steady-state. The nature of the forward recovery transient
depends on the magnitude of the current being driven through the diode and
the rise time of the driving signal.
Consider the voltage which develops across the diode when the input is a
current source supplying a step current IF as shown in Figure 3.1(a). If the
current amplitude is comparable to or larger than the diode rated current,
and if the rise time of the current step is small enough, then the waveform
of the voltage which appears across the diode is shown in Figure 3.1(b).
The overshoot results from the fact that initially the diode acts not as a p-n
junction diffusion device but as a resistor. In the steady-state condition, the
current which flows through the diode is a diffusion current which results
from the gradient in the density of minority carriers. If the current is large
enough, then there will also be an ohmic drop across the diode. The ohmic
drop is initially very large, for immediately after the application of the
current, the holes, say, will not have time to diffuse very far into the n-side
in order to build up a minority carrier density. Therefore except near the
junction, there will be no minority charge to establish a density gradient,
and the current flow through the mechanism of diffusion will not be
possible. Indeed, an electric field will be required to achieve current flow by
exerting force on the majority carriers. This electric field gives rise to the
ohmic drop. With the passage of time, however, the ohmic drop will
decrease as more and more minority carriers become available from the
junction, and current by diffusion takes over.

Figure 3.1 (a) Input step current to a diode, (b) diode voltage when the
current is large, and (c) diode voltage when the current is small.
 The magnitude of the overshoot will increase as the magnitude of the
input current increases. At large current amplitudes, the diode behaves as a
combination of a resistor and an inductor. At low currents the diode is
representable by a parallel resistor–capacitor combination. At intermediate
currents, the diode behaves as a resistor, inductor, and capacitor circuit and
oscillations may be produced.
The forward recovery time tfr, for a specified rise time of the input
current is the time difference between the 10% point of the diode voltage
and the time when this voltage reaches and remains within 10% of its final
value. The forward recovery time does not usually constitute a serious
problem.
Diode reverse recovery time
When an external voltage is impressed across a junction in the direction that
reverse biases it, very little current called the reverse saturation current
flows. This current is because of the minority carriers.
The density of minority carriers in the neighbourhood of the junction in
the steady-state is shown in Figure 3.2(a). Here the levels pn0 and np0 are
the thermal equilibrium values of the minority carrier densities on the two
sides of the junction in the absence of an externally impressed voltage.
When a reverse voltage is applied, the density of minority carriers is shown
by the solid lines marked pn and np. Away from the junction, the minority
carrier density remains unaltered, but as these carriers approach the junction
they are rapidly swept across and the density of minority carriers diminishes
to zero at the junction. The reverse saturation current which flows is small
because the density of thermally generated minority carriers is very small.
 Figure 3.2 Minority-carrier density distribution as a function of the distance x from a junction;
(a) a reverse-biased junction and (b) a forward-biased junction.

When the external voltage forward biases the junction, the steady-state
density of minority carriers is as shown in Figure 3.2(b). The injected or
excess hole density is (pn – pn0) and the excess electron density is (np –
np0).
In a diode circuit which has been carrying current in the forward
direction, if the external voltage is suddenly reversed, the diode current will
not immediately fall to its steady-state reverse value. The current cannot
attain its steady-state value until the minority carrier distribution changes
the form in Figure 3.2(b) to the distribution shown in Figure 3.2(a). Until
such time as the injected or excess minority carrier density pn – pn0 (or np
– np0) drops nominally to zero, the diode will continue to conduct easily
and the current will be determined by the external resistance in the diode
circuit.
Storage and transition times
The sequence of events which occurs when a conducting diode is reverse
biased is shown in Figure 3.3. The input voltage shown in Figure 3.3(b) is
applied to a diode circuit shown in Figure 3.3(a). Up to t = t1, vi = VF. The
resistance RL is assumed large so that the drop across RL is large compared
with the drop across the diode.

At the time t = t1, the input voltage reverses abruptly to the value vi = –
VR, the current reverses, until the time t = t2. At t = t2, as

shown in Figure 3.3(c), the injected minority carrier density at the junction
drops to zero, that is, the minority carrier density reaches its equilibrium
state. If the diode ohmic resistance is Rd, then at time t1, the diode voltage
falls slightly by [(IF + IR)Rd] but does not reverse as shown in Figure
3.3(e). At t = t2 when the excess minority carriers in the immediate
neighbourhood of the junction have been swept back across the junction,
the diode voltage begins to reverse as shown in Figure 3.3(e) and the
magnitude of the diode current begins to decrease as shown in Figure
3.3(d). The interval from t1 to t2 for the minority charge to become zero is
called the storage time ts. The time which elapses between t2 and the time
when the diode has nominally recovered is called the transition time tt. The
recovery interval will be completed when the minority carriers which are at
some distance from the junction have diffused to the junction, crossed it and
then, in addition, the junction transition capacitance across the reverse-
biased junction has charged through RL to the voltage –VR as shown in
Figure 3.3(e).
 Figure 3.3 The waveform in (b) is applied to the diode circuit in (a),
(c) the excess carrier density at the junction, (d) the diode current, and (e) the diode voltage.

3.2 PIECE-WISE LINEAR DIODE

CHARACTERISTICS
A large-signal approximation which often leads to a sufficiently accurate
engineering solution is the piece-wise linear representation.
The piece-wise linear approximation for a semiconductor diode
characteristic is shown in Figure 3.4. The breakdown is at Vg, which is
called the offset or threshold voltage. The diode behaves like an open-
circuit if v < Vg. The characteristic shows a constant incremental resistance
r = dv/di if v > Vg. Here r is called the forward resistance. The static
resistance R = V/I is not constant and is not useful.

Figure 3.4 The piece-wise linear characteristic of a diode.

The numerical values of Vg and Rf to be used depend upon the type of

diode and the contemplated voltage and current swings. Typically:
For current swings from cut-off to 10 mA

For current swings up to 50 mA

For avalanche diodes, Vg = VZ, and Rf is the dynamic resistance in the

breakdown region.

3.3 BREAKDOWN IN P-N JUNCTION DIODES

When the p-n junction diode is reverse biased, reverse saturation current I0
flows due to minority carriers. There is a gradual increase in reverse current
with increasing bias due to the ohmic leakage currents around the surface of
the junction. When the reverse bias voltage approaches the breakdown
voltage VBO, there is a sudden increase in reverse current due to
breakdown. Once breakdown occurs, the diode no longer blocks current,
and the diode current can now be controlled only by the resistance of the
external circuit.
Avalanche breakdown
Thermally generated minority carriers cross the depletion region and
acquire sufficient kinetic energy from the applied potential to produce new
carriers by removing valance electrons from other bonds. These new
carriers will in turn collide with other atoms and thus increase the number
of electrons and holes available for conduction. Because of the cumulative
increase in carrier density after each collision, the process is known as
avalanche breakdown.
Zener breakdown
Even if the initially available carriers do not gain enough energy to disrupt
bonds, it is possible to initiate breakdown through a direct rupture of the
bonds because of the existence of a strong electric field. Under these
circumstances the breakdown is referred to as zener breakdown.
Zener breakdown occurs at voltages below 6 V. The operating voltages in
avalanche breakdown are from several volts to several hundred volts with
power rating up to 50 W. The breakdown in a p-n junction diode is shown
in Figure 3.5.
 Figure 3.5 Breakdown in p-n junction diode.

True zener diode action displays a negative temperature coefficient, i.e.

the breakdown voltage decreases with increase in temperature. True
avalanche diode action exhibits a positive temperature coefficient, i.e. the
breakdown voltage increases with increase in temperature.
The breakdown voltage for a particular diode can be controlled during
manufacture by altering the doping levels in the junction. The breakdown
voltage for silicon diodes can be made to occur at a voltage as low as 5 V
17 3
with 10 impurity atoms/cm or as high as 1000 V when doped to a level
4 3
of only 10 impurity atoms/cm .

3.4 TRANSISTOR AS A SWITCH

A transistor can be used as a switch. It has three regions of operation. When
both emitter-base and collector-base junctions are reverse biased, the
transistor operates in the cut-off region and it acts as an open switch. When
the emitter base junction is forward biased and the collector base junction is
reverse biased, it operates in the active region and acts as an amplifier.
When both the emitter-base and collector-base junctions are forward biased,
it operates in the saturation region and acts as a closed switch. When the
transistor is switched from cut-off to saturation and from saturation to cut-
off with negligible active region, the transistor is operated as a switch.
When the transistor is in saturation, junction voltages are very small but the
operating currents are large. When the transistor is in cut-off, the currents
are zero (except small leakage current) but the junction voltages are large.
In Figure 3.6 the transistor Q can be used to connect and disconnect the
load RL from the source VCC. When Q is saturated it is like a closed switch
from collector to emitter and when Q is cut-off it is like an open switch
from collector to emitter.

Referring to the output characteristics shown in Figure 3.6(b), the region

below the IB = 0 curve is the cut-off region. The intersection of the load
line with IB = 0 curve is the cut-off point. At this point, the base current is
zero and the collector current is negligible. The emitter diode comes out of
forward bias and the normal transistor action is lost, i.e. VCE(cut-off) 
VCC. The transistor appears like an open switch.
 Figure 3.6 (a) Transistor used as a switch and (b) output characteristics with load line (dc).

The intersection of the load line with the IB = IB(sat) curve is called the
saturation point. At this point, the base current is IB(sat) and the collector
current is maximum. At saturation, the collector diode comes out of cut-off
and again the normal transistor action is lost, i.e. IC(sat) = VCC/RL. IB(sat)
represents the minimum base current required to bring the transistor into
saturation. For 0 < IB < IB(sat), the transistor operates in the active region.
If the base current is greater than IB(sat), the collector current
approximately equals VCC/RC and the transistor appears like a closed
switch.

3.5 TRANSISTOR SWITCHING TIMES

When the transistor acts as a switch, it is either in cut-off or in saturation.
To consider the behaviour of the transistor as it makes transition from one
state to the other, consider the circuit shown in Figure 3.7(a) driven by the
pulse waveform shown in Figure 3.7(b). The pulse waveform makes
transitions between the voltage levels V2 and V1. At V2 the transistor is at
cut-off and at V1 the transistor is in saturation. The input waveform vi is
applied between the base and the emitter through a resistor RB.

Figure 3.7 (a) Transistor as a switch, (b) input waveform, and

(c) the response of collector current versus time.

The response of the collector current iC to the input waveform, together

with its time relationship to that waveform is shown in Figure 3.7(c). The
collector current does not immediately respond to the input signal. Instead
there is a delay, and the time that elapses during this delay, together with the
time required for the current to rise to 10% of its maximum (saturation)
value (ICS = VCC/RC) is called the delay time td. The current waveform
has a nonzero rise time tr, which is the rise time required for the current to
rise from 10% to 90% of ICS. The total turn-on time tON is the sum of the
delay time and the rise time, i.e. tON = td + tr. When the input signal
returns to its initial state, the collector current again fails to respond
immediately. The interval which elapses between the transition of the input
waveform and the time when IC has dropped to 90% of ICS is called the
storage time ts. The storage interval is followed by the fall time tf, which is
the time required for IC to fall from 90% to 10% of ICS. The turn-off time
tOFF is defined as the sum of the storage and fall times, i.e. tOFF = ts + tf.
We shall now consider the physical reasons for the existence of each of
these times.
The delay time
There are three factors that contribute to the delay time. First there is a
delay which results from the fact that, when the driving signal is applied to
the transistor input, a non-zero time is required to charge up the junction
capacitance so that the transistor may be brought from cut-off to the active
region. Second, even when the transistor has been brought to the point
where minority carriers have begun to cross the emitter junction into the
base, a nonzero time is required before these carriers can cross the base
region to the collector junction and be recorded as collector current. Finally,
a nonzero time is required before the collector current can rise to 10% of its
maximum value.
Rise time and fall time
The rise time and fall time are due to the fact that, if a base current step is
used to saturate the transistor or to return it from saturation into cut-off, the
collector current must traverse the active region. The collector current
increases or decreases along an exponential curve.
Storage time
The failure of the transistor to respond to the trailing edge of the driving
pulse for the time interval ts, results from the fact that a transistor in
saturation has a saturation charge of excess minority carriers stored in the
base. The transistor cannot respond until the saturation excess charge has
been removed.

3.6 BREAKDOWN VOLTAGES OF A

TRANSISTOR
In a transistor switch, the voltage change which occurs at the collector with
switching is nominally equal to the collector supply voltage VCC. Since this
voltage will be used to operate other circuits and devices, then for the sake
of reliability of operation, VCC should be made as large as possible. The
maximum allowable voltage depends not only on the characteristics of the
transistor but also on the associated transistor base circuitry.
The maximum reverse biasing voltage which may be applied before
breakdown between the collector and base terminals of the transistor, under
the condition that the emitter lead be open-circuited is represented by the
symbol BVCBO. This breakdown voltage is a characteristic of the transistor
alone. Breakdown occurs because of the avalanche multiplication of the
current ICO that crosses the collector junction. As a result of this
multiplication the current becomes MICO, in which M is the factor by
which the original current ICO is multiplied by the avalanche effect. At a
high enough voltage, namely BVCBO, the multiplication factor M becomes
nominally infinite and the region of breakdown is then attained. Here the
current rises abruptly and large changes in current accompany small
changes in applied voltage.
The avalanche multiplication factor M depends on the voltage VCB
between the collector and the base, i.e.

The parameter n lies in the range 2 to 10 and controls the sharpness of the
onset of breakdown. When n is large, M continues at nearly unity until VCB
approaches very close to BVCBO at which point M soars upwards abruptly.
When n is small, the onset of breakdown is gradual.
In Figure 3.8(a) the CB characteristics have been extended into the
breakdown region. The curve for IE = 0 is a plot, as a function of VCB of
the product of the reverse collector current ICO and the avalanche
multiplication factor M. The abrupt growth in IC as BVCBO is approached,
is shown along with the slower increase in IC over the active region that
results from the small but not negligible avalanche multiplication.
 Figure 3.8 (a) CB characteristics extended into the breakdown region and
(b) idealized CE characteristics extended into the breakdown region.

If a current IE is caused to flow through the emitter junction, then

neglecting the avalanche effect, a fraction aIE reaches the collector
junction, where a is the common base current gain. Taking multiplication
into account, IC has the magnitude M a IE. Consequently it appears that in
the presence of avalanche multiplication, the transistor behaves as though
its common base current gain were a* where a* = Ma.
The CE configuration
Since hFE = a/(1 – a), in the presence of avalanche multiplication, the CE
*
current gain is h FE

Now a is a positive number with a maximum magnitude less than unity

but Ma may equal unity in magnitude at which point hFE becomes infinite.
Accordingly, any base current no matter how small, will give rise to an
arbitrarily large collector current whenever Ma = 1. It means breakdown has
occurred. Therefore, whenever the base current is kept fixed, breakdown
occurs at the voltage VCB which satisfies the equation
The breakdown voltage with base not open-circuited
Assume that the base is returned to the emitter through a resistor RB as
shown in Figure 3.9(a). We accept that the breakdown voltage BVCEO lies
between BVCER and BVCBO. To estimate BVCEO some assumptions are
made concerning the emitter-base junction diode. The semiconductor
junction diode exhibits a threshold voltage Vg in the forward direction. That
is, until the forward voltage attains about 0.2 V in Ge or 0.6 V in Si, the
forward current is very small. We shall assume that until the threshold has
been reached, the collector current will flow entirely to the base and hence
through RB. We also assume that once the threshold voltage is exceeded,
nearly all the additional collector current will flow through the emitter
junction and the corresponding breakdown voltage is BVCBO. Therefore,
when the collector-to-emitter voltage is larger than BVCBO and the
threshold voltage of the emitter junction is reached, breakdown will occur.
On this, we accept breakdown when the collector current MICO satisfies the
relation,

Figure 3.9 (a) Plot extended into the breakdown region of collector current against VCE for various
connections to the base. The sustaining voltage is BVCEO and (b) common collector transistor
circuit.

This equation is valid if the current in RB is very large compared with the
currents in collector and emitter. If RB = 0, i.e. if the base is short-circuited
to emitter,

BVCER = BVCBO = BVCES

If rBB is present, then base spreading resistance must also be taken into
account along with RB, i.e. (RB + rBB) is to be considered. Accordingly,
even when RB = 0, BVCES is lower in magnitude than BVCBO.
After breakdown has occurred, the collector and the emitter currents will
become very large compared with the base current. Therefore, at large
currents, the presence of RB makes no difference and the voltage across the
transistor will drop from BVCER to BVCEO.
The breakdown voltage may also be increased by returning the resistor
RB to a voltage VBB as shown in Figure 3.9(b) which provides some back
bias for the emitter junction. In this case the condition which determines the
onset of breakdown is

MICBO(RB + rBB) = Vg + VBB

and the breakdown voltage, now represented by the symbol BVCEX is

approximately given by

3.7 THE TRANSISTOR SWITCH IN

SATURATION
When a transistor switch is driven from saturation to cut-off, one of the
factors which has an important effect on the speed of response is the time
required to charge the capacitance which appears in shunt across the output
terminals of the transistor. This capacitance must charge through the load
resistance RL, and for this reason, in fast switching circuits, RL must be
kept small. In saturation, the transistor current is nominally VCC/RL, and
since RL is small, it may be necessary to keep VCC correspondingly small
in order to stay within the limitations imposed by the transistor on the
maximum current and dissipation. The total voltage swing at the transistor
switch is VCC – VCE(sat). The largest possible output swing is desirable in
order to reduce the sensitivity of the switching circuit to noise, supply
voltage fluctuations, transistor ageing, and replacement.
For the transistor switch of Figure 3.10(a), it is difficult to read VCE(sat)
from Figure 3.10(b). By changing scale, Figure 3.10(b) can be drawn as
shown in Figure 3.10(c). In these characteristics, the 0 to – 0.5 V region of
Figure 3.10(b) has been expanded and the same load line is drawn. At IB =
– 0.15 mA, the transistor is in saturation and |VCE| = 175 mV. At IB = –
0.35 mA, |VCE| has dropped to 100 mV. For a transistor operating in the
saturation region, a quantity of interest is the ratio VCE(sat)/IC. This
parameter is called the common emitter saturation resistance, RCE(sat).
 Figure 3.10 (a) Transistor circuit as a switch, (b) CE characteristics using Ge diode, and
(c) expanded saturation region CE characteristics of the transistor.

The saturation voltage VCE(sat) depends not only on the operating point
but also on the semiconductor material (Ge or Si) and on the type of
transistor construction. Alloy-junction transistors and epitaxial transistors
give the lowest values for VCE(sat), whereas the grown junction transistors
yield the highest. Germanium transistors have lower values for VCE(sat)
than those for silicon. An alloy-junction Ge transistor may allow, with
adequate base currents, values for VCE(sat) as low as tens of millivolts at
collector currents which are some tens of milliamperes. Similarly, epitaxial
silicon transistors may yield saturation voltage as low as 0.2 V with
collector currents as high as an ampere. On the other hand, the grown
junction Ge transistors have saturation voltages which are several tenths of
a volt and silicon transistors of this type may have saturation voltages as
high as several volts.
The dc current gain: (hFE or b)

In the saturation region, hFE is a useful parameter and is specified by the

manufacturer. Once we know, IC(= VCC/RL) and hFE, the amount of base
current IB = IC/hFE needed to saturate the transistor can be found.

3.8 TEMPERATURE SENSITIVITY OF

SATURATION PARAMETERS
At constant base and collector currents, the forward base-to-emitter voltage
|VBE| has a typical temperature sensitivity in the range –1.5 to –2 mV/°C.
This applies both to Ge and Si transistors. A plot for Ge of VBE versus the
ambient temperature is shown in Figure 3.11(a). A similar characteristic for
silicon has approximately the same slope.
In saturation, the transistor consists of two forward-biased junctions
back-to-back, series opposing. It is consequently to be anticipated that the
temperature induced voltage change in one junction will be cancelled in
some measure by the change in the other junction. Such is the case for
VBE(sat) as well, as shown in Figure 3.11(b).
The temperature dependence of hFE is shown in Figure 3.11(c). At small
and moderate currents, hFE increases substantially with temperature. At
high currents, hFE may well become rather insensitive to temperature.

Figure 3.11 Variation of (a) VBE(sat), (b) VCE(sat), and (c) hFE with temperature.
3.9 DESIGN OF TRANSISTOR SWITCH
Any transistor amplifier that has the property of inversion, can be used as an
inverter. The transistor that acts as a switch is driven between cut-off and
saturation. A transistor inverter is shown in Figure 3.12.

Figure 3.12 Transistor as a switch.

For low input vi = V(0), the transistor is kept at cut-off, so the output is
VCC or V(1). For high input, i.e. for vi = V(1), the transistor is driven into
saturation. So the output vo = VCE(sat) = V(0). Thus the circuit acts as a
switch. To improve the transient response of the inverter, the capacitor C is
used across the resistor R1. This helps in removing minority carrier charges
in the base when the signal changes between logic states.
Design1
required for the transistor, i.e. 0 V for Si transistor and – 0.1 V for Ge
transistor. The value of R1 is determined on the condition that for the lowest
expected temperature, the transistor will remain in saturation because hFE
decreases with decreasing temperature. When input vi = V(1), the transistor
is in saturation.

EXAMPLE 3.1 Calculate the output levels of the circuit shown in Figure
3.13 for inputs of 0 V and – 8 V and verify that the circuit is an inverter.
What is the minimum value of hFE required. Neglect junction saturation
voltages and assume an ideal diode.
 Figure 3.13 Example 3.1: circuit diagram.

EXAMPLE 3.2 For a common emitter circuit, VCC = 15 V, RC = 1.5 k

and IB = 0.3 mA. (a) Determine the value of hFE(min) for saturation to
occur. (b) If RC is changed to 500 , will the transistor be saturated?

EXAMPLE 3.3 Sketch the typical transistor common-emitter

characteristics. Identify the various regions of the characteristics and show
how VCE(sat) differs with different load resistances.
 RL is inversely proportional to the collector current IC(sat). If RL
increases, IC(sat) decreases. Hence VCE(sat) differs with different values of
RL.
 Figure 3.14 Example 3.3: (a) circuit diagram and (b) output characteristics.

EXAMPLE 3.4 A common-emitter circuit (Figure 3.15) has VCC = 20 V

and a collector resistor which can be either 20 k or 2 k. Calculate the
minimum level of base current to achieve saturation in each case.

Figure 3.15 Example 3.4: circuit diagram.

EXAMPLE 3.5 For a CE transistor circuit with VCC = 15 V, RC = 1.5 k,

calculate the transistor power dissipation (a) at cutoff and (b) at saturation.
 Figure 3.16 Example 3.5: circuit diagram.

SHORT QUESTIONS AND ANSWERS

1. Name the devices that can be used as switches.
A. The electronic devices that are commonly used as switches are (i)
p-n junction diode and (ii) a transistor.
2. How does a diode act as a switch?
A. When the diode is forward biased and conducting, it acts as a short-
circuit and when it is reverse biased and not conducting, it acts as a
open circuit. Hence, the diode acts as a switch.
3. What do you mean by (a) dynamic resistance and (b) static resistance
of a diode?
A. (a) The dynamic or incremental resistance of a diode is r = v/i,
i.e. it is a ratio of the change in voltage across it to the change in
current through it.
 (b) The static resistance of a diode is R = V/I, i.e. it is the ratio of the
voltage across it to the current passing through it.
4. In steady-state condition, which current flows through the diode and
what causes it?
A. In the steady-state condition, the diffusion current flows through the
diode and the gradient in the density of minority carriers causes it.
5. At large current amplitudes, how does the diode behave?
A. At large current amplitudes, the diode behaves as a combination of
a resistor and an inductor.
6. At small current amplitudes, how does the diode behave?
A. At small current amplitudes, the diode behaves as a combination of
a resistor and a capacitor in parallel.
7. At intermediate currents, how does the diode behave?
A. At intermediate currents, the diode behaves as a series combination
of a resistor, an inductor and a capacitor.
8. Define (a) storage time of a diode and (b) transition time of a diode.
A. (a) The storage time ts of a diode is defined as the interval between
the time of reversal of input voltage and the time at which the minority
charge becomes zero.
(b) The transition time tt is the time interval between the time at which
the minority charge has become zero to the time when the diode has
nominally recovered.
9. Define (a) diode forward recovery time and (b) diode reverse recovery
time.
A. (a) The diode forward recovery time tfr for a specified rise time of
the input current is the time difference between the 10% point of the
diode voltage and the time when this voltage reaches and remains
within 10% of its final value.
(b) The sum of the storage time and the transition time is called diode
reverse recovery time, i.e. this is the interval between the time of
application of negative voltage and the time at which the reverse
biased junction has charged to the applied voltage –VR.
10. Explain (a) avalanche breakdown and (b) zener breakdown.
A. (a) In avalanche breakdown, thermally generated minority carriers
cross the depletion region and acquire sufficient kinetic energy from
 the applied potential to produce new carriers by removing valance
electrons from other bonds. These new carriers will in turn collide with
other atoms and thus increase the number of electrons and holes
available for conduction. So there will be a cumulative increase in
carrier density after each collision.
(b) In zener breakdown, the breakdown is initiated by the direct
rupture of the bonds because of the existence of a strong electric field.
11. What are the operating voltages in (a) avalanche breakdown (b) zener
breakdown?
A. (a) The operating voltages in avalanche breakdown are from several
volts to several hundred volts with power rating up to 50 W.
(b) The operating voltages for zener breakdown are below 6 V.
12. On what does the breakdown voltage for a particular diode depend?
A. The breakdown voltage for a particular diode depends on the
doping level.
13. How do you justify that the transistor acts as a switch?
A. When the transistor is in saturation, both the emitter-base and
collector-base junctions are forward biased and it acts as a short
circuit. It is equivalent to a closed switch. When the transistor is in cut-
off, both the emitter-base and collector-base junctions are reverse
biased and it acts as an open circuit. It is equivalent to an open switch.
So we can say that the transistor acts as a switch, if it is driven from
saturation to cut-off and from cut-off to saturation with negligible
active region.
14. What are the three regions of operation of a transistor?
A. The three regions of operation of a transistor are — the cut-off
region, the active region, and the saturation region.
15. How are the junctions of a transistor biased for cut-off region
operation?
A. For cut-off region operation of a transistor, both the emitter-base
and collector-base junctions must be reverse biased.
16. How are the junctions of a transistor biased for active region
operation?
A. For active region operation of a transistor, the emitter-base junction
must be forward biased and the collector-base junction must be reverse
biased.
17. How are the junctions of a transistor biased for saturation region
operation?
A. For saturation region operation of a transistor, both the emitter-base
and collector-base junctions must be forward biased.
18. When does a transistor act as (a) a closed switch and (b) an open
switch?
A. A transistor acts as a closed switch when it is in saturation and acts
as an open switch when it is in cut-off.
19. What do you mean by delay time of a transistor? What factors
contribute to it?
A. The delay time of a transistor is the time required for the collector
current to raise to 10% of its final value after the application of the
positive input voltage pulse. The factors which contribute to the delay
time are as follows:
First, when the driving signal is applied to the transistor input, a non-
zero time is required to charge up the junction capacitance so that the
transistor may be brought from cut-off to the active region. Second,
even when the transistor has been brought to the point where minority
carriers have begun to cross the emitter junction into the base, a non-
zero time is required before these carriers can cross the base region to
the collector junction and be recorded as collector current. Third, a
non-zero time is required before the collector current can raise to 10%
of its maximum value.
20. Define (a) rise time, (b) storage time, and (c) fall time.
A. (a) The rise time tr is defined as the time required for the collector
current waveform to rise from 10% to 90% of its maximum value
(ICS).
(b) The storage ts is the time interval which elapses between the
negative transition of the input waveform and the time when IC has
dropped to 90% of ICS.
(c) The fall time tf is the time required for IC to fall from 90% to 10%
of ICS.
21. What is the reason for the existence of the rise and fall times?
A. The reason for the existence of rise and fall times of IC is the fact
 that if a base current step is used to saturate the transistor or to return it
from saturation into cut-off, the collector current must traverse the
active region. The collector current increases or decreases along an
exponential curve.
22. Which factor contributes for the existence of the rise and fall times?
A. The factor which contributes to the existence of the storage time ts
is that a transistor in saturation has a saturation charge of excess
minority carriers stored in base and the transistor can not respond until
the saturation excess charge has been removed.
23. What do you mean by turn ON time of a transistor?
A. The turn ON time of a transistor, tON is the sum of the delay time
td and rise time tr, i.e. tON = td + tr. i.e. it is the time interval between
the time of occurrence of the leading edge of a positive voltage pulse
applied and the time at which the collector current has raised to 90% of
its final maximum value (ICS).
24. What do you mean by turn-off time of a transistor?
A. The turn-off time of a transistor, tOFF is the sum of the storage time
ts and the fall time tf. i.e. tOFF = ts + tf, i.e. it is the time interval
which elapses between the transition of the input waveform and the
time at which the collector current IC has dropped to 10% of its
maximum value.
25. On what does the saturation voltage VCE (sat) of a transistor depend?
A. The saturation voltage VCE (sat) of a transistor depends (a) on the
operating point, (b) on the semiconductor material used, and (c) on the
type of transistor construction.
26. Define the common emitter saturation resistance RCE (sat).
A. The common emitter saturation resistance RCE (sat) is defined as
the ratio of VCE (sat) to IC.
27. What do you mean by BVCBO?
A. BVCBO is the collector-to-base breakdown voltage with open
circuited emitter. It is the maximum reverse biasing voltage which may
be applied before breakdown between the collector and base terminals
 of the transistor under the condition that the emitter lead be open
circuited.
28. What do you mean by BVCEO?
A. BVCEO is the collector-to-emitter breakdown voltage, with open
circuited base. It is the maximum reverse biasing voltage which may
be applied before breakdown between the collector and emitter
terminals of the transistor under the condition that the base lead is open
circuited.
29. What do you mean by BVCER?
A. BVCER is the collector-to-emitter breakdown voltage, with base
returned to emitter through a resistance RB. It is the maximum reverse
biasing voltage which may be applied before breakdown between the
collector and emitter terminals of the transistor under the condition that
the base is returned to the emitter through a resistance RB.

REVIEW QUESTIONS
1. Write notes on (a) diode switching times and (b) transistor switching
times.
2. A rectangular pulse of voltage is applied to the base of a transistor
driving it from cut-off to saturation. Discuss the changes in output
potential. Explain the various times involved in the switching process.

FILL IN THE BLANKS

1. The static resistance of a diode is the ratio of ________ to ________.
2. The dynamic resistance of a diode is the ratio of ________ to
________.
3. When a diode is reverse biased it acts as an __________ switch, and
when it is forward biased it acts as a __________ switch.
4. In the steady-state condition, the current which flows through the
diode is a __________ current.
 5. The __________ current results from the gradient of the minority
carriers.
6. At large current amplitudes, the diode behaves as a combination of a
________ and _____.
7. At intermediate currents, the diode behaves as a ____________,
________ and a ________.
8. At low currents, the diode is represented by a parallel combination of a
_______ and _______.
9. The forward recovery time tfr is the time difference between the
_________ and the time when this voltage reaches and remains within
_________.
10. The __________ recovery time of a diode does not usually constitute a
problem.
11. The time required for the stored minority charge to become zero after
the application of the reverse voltage is called the __________.
12. The time which elapses between the instant when the stored minority
charge becomes zero and the time when the diode has nominally
recovered is called the __________.
13. A large-signal approximation which often leads to a sufficient accurate
engineering solution is the __________ representation.
14. Once breakdown occurs, the diode current can be controlled only by
the resistance of the __________.
15. The breakdown due to thermally generated carriers is called the
__________ breakdown.
16. The breakdown due to existence of strong electric fields is called the
__________ breakdown.
17. __________ breakdown occurs at voltages below 6 V.
18. The operating voltages in __________ breakdown are from several
volts to several hundred volts.
19. The breakdown voltage of a zener diode __________ with temperature
whereas the breakdown voltage of an avalanche diode __________
with temperature.
20. The breakdown voltage for a particular diode depends on the
__________ levels in the junction.
21. When a transistor is in saturation, junction voltages are __________
but the operating currents are __________.
22. When a transistor is in cut-off, the junction voltages are __________
but the currents are __________.
23. For Ge, Vg = __________. For Si, Vg = __________. For avalanche
diodes Vg = __________.
24. The time required for the current to rise to 10% of its saturation value
after the application of the input is called the __________.
25. The time required for the current to rise from 10% to 90% of the
saturation value is called the __________.
26. The sum of the delay time and the rise time of a transistor is called the
__________ time.
27. The interval which elapses between the transition of the input
waveform and the time when IC has dropped to 90% of saturation
current is called the __________.
28. The time required for IC to fall from 90% to 10% of its saturation level
is called the __________.
29. The sum of the storage time and the fall time of a transistor is called
the __________ time.
30. A transistor can operate in three regions: __________, __________,
and __________.
31. The hFE of a transistor __________ with temperature.
32. In the cut-off region of a transistor, both the emitter junction and
collector junction are __________ and the transistor acts as an
__________.
33. In the saturation region, both the emitter junction and the collector
junction are __________ and the transistor acts as a __________.
34. In the active region, the emitter junction is __________ and the
collector junction is __________ and the transistor acts as an
__________.
35. The saturation voltage VCE (sat) of a transistor depends not only on
the ________ but also on the ________ and on the type of _________.
36. BVCBO is a characteristic of the __________ alone.
37. BVCEO = ____________ BVCBO.
38. __________ lies between BVCER and BVCBO.
39. In fast switching circuits _____________ must be kept small.
40. In switching circuits, the largest possible output voltage swing is
desirable in order to reduce the sensitivity of the switching circuit to
______, ___________, ________, and __________.
41. ________ transistors and _________ transistors give the lowest values
for VCE (sat), whereas the _________ transistors yield the highest.
42. Germanium transistors have _________ values for VCE (sat) than
those for silicon.
43. At small and moderate currents, hFE _________ substantially with
temperature. At high currents, hFE may become _________ to
temperature changes.

OBJECTIVE TYPE QUESTIONS

1. A transistor acts as an open switch when it is in
(a) cut-off region
(b) active region
(c) saturation region
(d) none of these
2. A transistor acts as a closed switch when it is in
(a) cut-off region
(b) active region
(c) saturation region
(d) none of these
3. For a transistor to be in saturation
(a) both the junctions must be forward biased
(b) both the junctions must be reverse biased
(c) one junction must be forward biased and the other must be reverse
biased
(d) none of these
4. For a transistor to be in cut-off region, both the junctions of the
transistor must be
(a) forward biased
 (b) reverse biased
(c) un biased
(d) none of these
5. For the transistor to be in the active region,
(a) both junctions must be forward biased
(b) both junctions must be reverse biased
(c) emitter-base junction must be reverse biased and collector-base
junction must be forward biased.
(d) emitter-base junction must be forward biased and collector-base
junction must be reverse biased.
6. A transistor acts as an amplifier when it is in
(a) saturation region
(b) cut-off region
(c) active region
(d) none of these
7. The breakdown which occurs through a direct rupture of the bonds
because of the existence of the strong electric field is referred to as
(a) zener breakdown
(b) avalanche breakdown
(c) zener multiplication
(d) avalanche multiplication
8. The thermally generated electrons and holes acquire sufficient energy
from the applied potential to produce new carriers by removing
valance electrons form their bonds. These new carriers, in turn,
produce additional carriers again through the process of disrupting
bonds. This cumulative process is referred to as
(a) zener breakdown
(b) avalanche breakdown
(c) zener multiplication
(d) avalanche multiplication
9. In the steady-state condition, the current which flows through the
diode is a
(a) diffusion current
(b) drift current
(c) reverse current
(d) none of these
10. The reverse saturation current doubles for every ________ rise in
temperature
(a) 100° C
(b) 10° C
(c) 1° C
(d) 25° C
11. Zener breakdown occurs below
(a) 6 V
(b) 4 V
(c) 2 V
(d) none of these
12. The capacitance which appears across a reverse biased junction of a
diode is called
(a) diffusion capacitance
(b) transition capacitance
(c) drift capacitance
(d) none of these
13. Diodes which are designed with adequate power dissipation
capabilities to operate in the breakdown region may be employed as
(a) voltage reference
(b) current reference
(c) power reference
(d) none of these
 Chapter 4
Multivibrators

Multi means many; vibrator means oscillator. A circuit which can oscillate
at a number of frequencies is called a multivibrator. Basically there are
three types of multivibrators:

1. Bistable multivibrator
2. Monostable multivibrator
3. Astable multivibrator

Each of these multivibrators has two states. As the names indicate, a

bistable multivibrator has got two stable states, a monostable multivibrator
has got only one stable state (the other state being quasi stable) and the
astable multivibrator has got no stable state (both the states being quasi
stable). The stable state of a multivibrator is the state in which the device
can stay permanently. Only when a proper external triggering signal is
applied, it will change its state. Quasi stable state means temporarily stable
state. The device cannot stay permanently in this state. After a
predetermined time, the device will automatically come out of the quasi
stable state.
In this chapter we will discuss multivibrators with two-stage regenerative
amplifiers. They have two cross-coupled inverters, i.e. the output of the first
stage is coupled to the input of the second stage and the output of the
second stage is coupled to the input of the first stage. In bistable circuits
both the coupling elements are resistors (i.e. both are dc couplings). In
monostable circuits, one coupling element is a capacitor (ac coupling) and
the other coupling element is a resistor (dc coupling) In astable
multivibrators both the coupling elements are capacitors (i.e. both are ac
couplings).
 A bistable multivibrator requires a triggering signal to change from one
stable state to another. It requires another triggering signal for the reverse
transition. A monostable multivibrator requires a triggering signal to change
from the stable state to the quasi stable state but no triggering signal is
required for the reverse transition, i.e. to bring it from the quasi stable state
to the stable state. The astable multivibrator does not require any triggering
signal at all. It keeps changing from one quasi stable state to another quasi
stable state on its own the moment it is connected to the supply.
A bistable multivibrator is the basic memory element. It is used to
perform many digital operations such as counting and storing of binary
data. It also finds extensive applications in the generation and processing of
pulse type waveforms. The monostable multivibrator finds extensive
applications in pulse circuits. Mostly it is used as a gating circuit or a delay
circuit. The astable circuit is used as a master oscillator to generate square
waves. It is often a basic source of fast waveforms. It is a free running
oscillator. It is called a square wave generator. It is also termed a relaxation
oscillator.

4.1 BISTABLE MULTIVIBRATOR

A bistable multivibrator is a multivibrator which can exist indefinitely in
either of its two stable states and which can be induced to make an abrupt
transition from one state to the other by means of external excitation. In a
bistable multivibrator both the coupling elements are resistors (dc
coupling). The bistable multivibrator is also called a multi, Eccles–Jordan
circuit (after its inventors), trigger circuit, scale-of-two toggle circuit, flip-
flop, and binary.
There are two types of bistable multivibrators:

1. Collector coupled bistable multivibrator

2. Emitter coupled bistable multivibrator

There are two types of collector-coupled bistable multivibrators:

1. Fixed-bias bistable multivibrator

 2. Self-bias bistable multivibrator

4.2 A FIXED-BIAS BISTABLE

MULTIVIBRATOR
Figure 4.1 shows the circuit diagram of a fixed-bias bistable multivibrator
using transistors (inverters). Note that the output of each amplifier is direct
coupled to the input of the other amplifier. In one of the stable states,
transistor Q1 is ON (i.e. in saturation) and Q2 is OFF (i.e. in cut-off), and in
the other stable state Q1 is OFF and Q2 is ON. Even though the circuit is
symmetrical, it is not possible for the circuit to remain in a stable state with
both the transistors conducting (i.e. both operating in the active region)
simultaneously and carrying equal currents. The reason is that if we assume
that both the transistors are biased equally and are carrying equal currents I1
and I2 and suppose there is a minute fluctuation in the current I1—let us say
it increases by a small amount—then the voltage at the collector of Q1
decreases. This will result in a decrease in voltage at the base of Q2. So Q2
conducts less and I2 decreases and hence the potential at the collector of Q2
increases. This results in an increase in the base potential of Q1. So, Q1
conducts still more and I1 is further increased and the potential at the
collector of Q1 is further reduced, and so on. So, the current I1 keeps on
increasing and the current I2 keeps on decreasing till Q1 goes into
saturation and Q2 goes into cut-off. This action takes place because of the
regenerative feedback incorporated into the circuit and will occur only if the
loop gain is greater than one.
 A stable state of a binary is one in which the voltages and currents satisfy
the Kirchhoff’s laws and are consistent with the device characteristics and
in which, in addition, the condition of the loop gain being less than unity is
satisfied.
The condition with respect to loop gain will certainly be satisfied, if
either of the two devices is below cut-off or if either device is in saturation.
But normally the circuit is designed such that in a stable state one transistor
is in saturation and the other one is in cut-off, because if one transistor is
biased to be in cut-off and the other one to be in active region, as the
temperature changes or the devices age and the device parameters vary, the
quiescent point changes and the quiescent output voltage may also change
appreciably. Sometimes the drift may be so much that the device operating
in the active region may go into cut-off, and with both the devices in cut-off
the circuit will be useless.

Figure 4.1 Circuit diagram of a fixed-bias bistable multivibrator.

Selection of components in the fixed-bias bistable multivibrator

In the fixed-bias binary shown in Figure 4.1, nearly the full supply voltage
VCC will appear across the transistor that is OFF. Since this supply voltage
VCC is to be reasonably smaller than the collector breakdown voltage
BVCE, VCC is restricted to a maximum of a few tens of volts. Under
saturation conditions the collector current IC is maximum. Hence RC must
be chosen so that this value of IC ( VCC/RC) does not exceed the
maximum permissible limit. The values of R1, R2 and VBB must be
selected such that in one stable state the base current is large enough to
drive the transistor into saturation whereas in the second stable state the
emitter junction must be below cut-off. The signal at a collector called the
output swing VW is the change in collector voltage resulting from a
transistor going from one state to the other, i.e. VW = VC1 – VC2. If the
loading caused by R1 can be neglected, then the collector voltage of the
OFF transistor is VCC. Since the collector saturation voltage is few tenths
of a volt, then the swing VW  VCC, independently of RC. The component
values, the supply voltages and the values of ICBO, hFE, VBE(sat), and
VCE(sat) are sufficient for the analysis of transistor binary circuits.
Loading
The bistable multivibrator may be used to drive other circuits and hence at
one or both the collectors there are shunting loads, which are not shown in
Figure 4.1. These loads reduce the magnitude of the collector voltage VC1
of the OFF transistor. This will result in reduction of the output voltage
swing. A reduced VC1 will decrease IB2 and it is possible that Q2 may not
be driven into saturation. Hence the flip-flop circuit components must be
chosen such that under the heaviest load, which the binary drives, one
transistor remains in saturation while the other is in cut-off.
Since the resistor R1 also loads the OFF transistor, to reduce loading, the
value of R1 should be as large as possible compared to the value of RC. But
to ensure a loop gain in excess of unity during the transition between the
states, R1 should be selected such that R1 < hFERC.
For some applications, the loading varies with the operation being
performed. In such cases, the extent to which a transistor is driven into
saturation is variable. A constant output swing VW = V, and a constant base
saturation current IB2 can be obtained by clamping the collectors to an
auxiliary voltage V < VCC through the diodes D1 and D2 as indicated in
Figure 4.2. As Q1 cuts OFF, its collector voltage rises and when it reaches
V, the “collector catching diode” D1 conducts and clamps the output to V.

Figure 4.2 A fixed-bias binary with collector catching diodes added.

Transistor as an ON-OFF switch
In digital circuits transistors operate either in the cut-off region or in the
saturation region. Specially designed transistors called switching transistors
with negligible active region are used. In the cut-off region the transistor
does not conduct and acts as a open switch. In the saturation region the
transistor conducts heavily and acts as a closed switch.
In a binary which uses two cross-coupled transistors, each of the
transistors is alternately cut-off and driven into saturation. Because of
regenerative feedback provided both the transistors cannot be ON or both
cannot be OFF simultaneously. When one transistor is ON, the other is OFF
and vice versa.
Standard specifications

The above values hold good for n-p-n transistors. For p-n-p transistors the
above values with opposite sign are to be taken.
Test for saturation
To test whether a transistor is really in saturation or not evaluate the
collector current iC and the base current iB independently.
If iB > iB (min), where iB (min) = iC/hFE (min) the transistor is really in
saturation.
If iB  iB (min), the transistor is not in saturation.
Test for cut-off
To test whether a transistor is really cut-off or not, find its base-to-emitter
voltage. If VBE is negative for an n-p-n transistor or positive for a p-n-p
transistor, the transistor is really cut-off.
EXAMPLE 4.1 The fixed-bias binary shown in Figure 4.3 uses n-p-n
silicon transistors with VCE(sat) = 0.5 V, VBE(sat) = 1 V, ICBO = 10 nA at
25°C and zero base-to-emitter voltage at cut-off. The circuit parameters are
VCC = VBB = 6 V, RC = 1.2 k, R1 = 4.7 k, R2 = 27 k. Find (a)
hFE(min) and stable state voltages and currents. (b) If the reverse saturation
current doubles for every 10°C rise in temperature, what is the maximum
temperature at which the circuit can operate properly with one device
remaining OFF?

Figure 4.3 Example 4.1: circuit diagram.

Solution: Let Q1 be OFF and Q2 be ON in one of the two stable states. The
current distribution is as indicated in Figure 4.3.
 The base potential of Q1 is

VB1 = VC2 – I2R1 = 0.5 – 0.205  4.7 = – 0.4635 V

Since a negative voltage is appearing at the base of the n-p-n transistor

Q1, it is ensured that Q1 is really OFF.

VC1 = VCC – I3RC = 6 – 0.847  1.2 = 4.983 V

So, the stable state voltages and currents are:

To calculate ICBO, the reverse saturation current, the effective resistance

seen looking into the base, i.e. RB needs to be calculated (see Figure 4.4).
 The transistor Q2 is ON and hence it acts as a short circuit.

The maximum temperature at which the circuit can operate properly with
one device remaining OFF is

T = 25 + 10  n = 25 + 10  3.531 = 60.31°C

Figure 4.4 Example 4.1: (a) circuit to calculate RB and (b) circuit to calculate ICBO(max).

EXAMPLE 4.2 The fixed-bias bistable multivibrator uses n-p-n transistors

with hFE = 20. The circuit parameters are VCC = 12 V, VBB = 3 V, RC = 1
k, R1 = 5 k, R2 = 10 k, VCE(sat) = 0.4 V, and VBE(sat) = 0.8 V. (a)
Find the stable state voltages and currents. (b) What is the maximum load
the multivibrator can drive, still maintaining one transistor in saturation and
the other in cut-off? (c) What is the maximum reverse saturation current
ICBO tolerated so that neither of the transistor is at cut-off? (d) If the initial
value of ICBO is 10 A at room temperature, what is the maximum
temperature at which one device remains OFF?

 The actual base current of Q2 is

IB2(actual) = I3 – I4 = 1.867 mA – 0.38 mA = 1.487 mA

Since IB2(actual) > IB2(min), the transistor Q2 is really in saturation

–3 3
VB1 = VC2 – I2R1 = VCE2(sat) – I2R1 = 0.4 – (0.227  10 )  (5  10 )
= – 0.735 V
 Since VBE1 is negative for an n-p-n transistor, the transistor Q1 is really
in cut-off, so its collector and base currents are zero.

(b) Let the maximum load be RL. The equivalent circuit with the load at
the collector of Q1 is shown in Figure 4.5.

Figure 4.5 Example 4.2: circuit to calculate the maximum load.

For Q2 to be just in saturation, its base current can decrease at most to

IB2(min). Taking the worst case:
 (c) Collector-base bias of OFF transistor has reverse leakage current due
to minority carriers. As the temperature increases, minority carriers
multiply and the leakage current increases.
We have calculated that VB1 of OFF transistor Q1 is –0.735 V.
To calculate the effective resistance looking into the base, all active
sources need to be shorted as shown in Figure 4.6(a). Thus,

When ICBO increases, it offsets the negative bias of Q1 and the limiting
value is when RBICBO(max) – VB1 = 0 as shown in Figure 4.6(b).
Figure 4.6 Example 4.2: (a) equivalent circuit to calculate RB and (b) equivalent circuit to calculate
ICBO.

EXAMPLE 4.3 For the fixed-bias binary shown in Figure 4.7, hFE(min) =
40, VCC = 18 V, VBB = 6 V, V = 6 V, RC = 1.5 k, R1 = 5 k, R2 = 25 k.
Neglect the drop across the forward biased junctions. (a) Verify that one
transistor is in cut-off and the other is in saturation. (b) What is the
maximum load the bistable multivibrator can drive? (c) If ICBO = 5 A at
20°C and doubles for every 10°C rise in temperature, find the maximum
temperature at which one device will still remain in cut-off condition and
the other in saturation.
 Figure 4.7 Example 4.3: circuit diagram.

Solution: For the bistable multivibrator shown in Figure 4.7, assume that
Q2 is ON and Q1 is OFF in one of its stable states. Neglecting junction
voltages, D1 is ON and D2 is OFF. Since Q1 is OFF, IC1 = 0 mA and IB1 =
0 mA. Since Q2 is ON and the forward bias junction voltages are neglected,
 Since the base-to-emitter voltage of n-p-n transistor Q1 is negative, Q1 is
really in cut-off. Since the diode D1 is ON and V = 6 V, the collector of Q1
is at 6 V, i.e. VC1 = 6 V.
 Since IB2(actual) = 0.96 mA is greater than IB2(min) = 0.295 mA, Q2 is
really ON. So, the stable state with Q2 ON and Q1 OFF is confirmed.
The stable state voltages and currents are:

(b) To find the maximum load that the multivibrator can drive, refer to
Figure 4.8. When the bistable multivibrator drives an external load, the
collector potential cannot change as it is clamped to 6 V. The currents I3, I4,
and I5 are fixed. Only the diode current can change. The load current IL
may in the worst case be equal to the diode current ID.

Figure 4.8 Example 4.3: equivalent circuit with the maximum load.

(c) To find the maximum temperature at which one device will remain at
cut-off and the other in saturation, refer to Figures 4.6(a) and 4.6(b).
EXAMPLE 4.4 The fixed-bias binary shown in Figure 4.9 uses p-n-p
silicon transistors with worst case values of hFE = 25, VCE(sat) = – 0.5 V,
VBE(sat) = – 1 V, ICBO = – 10 A at 25°C and zero base-to-emitter
voltage at cut-off. The circuit parameters are VCC = – 12 V, VBB = 6 V, RC
= 2 k, R1 = 10 k, R2 = 20 k, and C = 100 pF. (a) Find the stable state
voltages and currents. (b) If the reverse saturation current doubles for every
10°C rise in temperature, what is the maximum temperature at which one
device will remain OFF? (c) What is the maximum load the binary can
drive and still have one transistor in saturation and the other in cut-off. (d)
What is the maximum frequency at which the circuit can operate?

Solution: (a) Referring to Figure 4.9, let Q1 be OFF and Q2 be ON in one

of the two stable states. The current distribution is as indicated in Figure
4.9.
 Figure 4.9 Example 4.4: circuit diagram.

Since Q1 is OFF, IC1 = 0 mA and IB1 = 0 mA.

Since Q2 is ON, VB2 = – 1 V and VC2 = – 0.5 V.

Since | IB2(actual) | > | IB2(min) |, the transistor Q2 is really in

saturation.
 Since VB1 is positive, the p-n-p transistor Q1 is really cut-off.
This proves that Q2 is ON and Q1 is OFF in one of the stable states.
The stable state voltages and currents are:

(b) Collector base bias of OFF transistor has reverse leakage current due
to minority carriers. As temperature increases, minority carriers multiply
and leakage current increases.
We have calculated that VB1 of OFF transistor Q1 = 1.667 V.
To calculate the effective resistance looking into the base, all active
sources are shorted as shown in Figure 4.10(a).
When ICBO increases, it offsets the positive bias of Q1 and the limiting
value is when RBICBO (max) – VB1 = 0 as shown in Figure 4.10(b).

Figure 4.10 Example 4.4: (a) circuit to calculate RB and (b) circuit to calculate ICBO(max).
 Any further increase in temperature and hence in ICBO makes Q1 ON.
ICBO at room temperature of 25°C is – 10 A and doubles for every 10°C
rise in temperature.

The maximum temperature at which the device can work properly is

25 + 10  n = 25 + 10  4.64 = 71.4°C
(c) Let the maximum load be RL. The equivalent circuit with the load at
the collector of Q1 is as shown in Figure 4.11.

Figure 4.11 Example 4.4: circuit to calculate the maximum load.

For Q2 to be just in saturation, its base current can decrease at most to

IB2(min). Taking the worst case of IB2(min) = – 0.221 mA
EXAMPLE 4.5 Silicon transistors with hFE(min) equal to 20 are available.
If VCC = VBB = 10 V, design the bistable multivibrator.

Solution: Since two supply voltages are specified, the bistable multivibrator
is of fixed-bias type. For n-p-n transistors, VCC is positive and VBB
negative. The circuit to be designed is shown in Figure 4.1.
In this circuit, let Q2 be ON and Q1 be OFF in one of the two stable
states.

 IC1 = 0 mA and IB1 = 0 mA; and VC2 = VCE2(sat) = 0 V, and VB2 =

VBE2(sat) = 0 V

Neglect the loading effect of R1 at the collector of Q2 (i.e. neglect I2

compared to I1). Let the saturation current of the ON transistor be IC(sat) =
5 mA.
 Figure 4.12 Example 4.5: circuit diagram.

Let IB2(actual) = 1.5  IB2(min) = 1.5  0.25 = 0.375 mA

 Solving, R1 = 21.423 k and R2 = 192.8 k (The higher values of the
solution should be taken.) The designed circuit is shown in Figure 4.12.

EXAMPLE 4.6 Design a bistable multivibrator to meet the following

specifications, VCC = VBB = 12 V, IC(sat) = 6 mA, hFE(min) = 25.
Maximum trigger frequency = 25 kHz.

Solution: Since two supply voltages are specified, the circuit to be designed
is a fixed bias bistable multivibrator as shown in Figure 4.13.

Figure 4.13 Example 4.6: circuit diagram.

Let Q2 be ON and Q1 be OFF in one of the two stable states. Let

VCE(sat) = 0.4 V, VBE(sat) = 0.8 V, ICBO = 0 A and IB(actual) =
1.5IB(min).
Neglecting the loading effect of R1 and R2 at the collector of Q2
4.3 A SELF-BIASED TRANSISTOR BINARY
A fixed-biased bistable multivibrator requires two power supplies—one
positive and one negative. The need for the negative power supply may be
eliminated by using a common emitter resistor RE. The binary using the
common emitter resistor RE to provide self-bias is called the self-biased
binary. A self-biased binary is shown in Figure 4.14. The procedure for
calculating the stable state voltages and currents is in principle the same as
that employed for a fixed-bias flip-flop.
 Figure 4.14 Example 4.7: a self-biased binary.

EXAMPLE 4.7 A self-biased bistable multivibrator using n-p-n transistors

having VCE(sat) = 0.4 V, VBE(sat) = 0.8 V, RC = 4.7 k, R1 = 30 k, R2 =
15 k, RE = 0.39 k, hFE = 25, VCC = 20 V, and zero base-to-emitter
voltage for cut-off is shown in Figure 4.14. Find (a) the stable state voltages
and currents, (b) the maximum load that the binary can drive and still have
one transistor in saturation while the other is below cut-off, and (c) the
maximum value of ICBO required to reach the condition that neither device
is OFF.

Solution: Assume that Q1 is cut-off and Q2 is in saturation. The

connections between the base of Q1 and the collector of Q2 are indicated in
Figure 4.15(a), and the connections between the base of Q2 and the
collector of Q1 are indicated in Figure 4.15(b). In order to calculate the
voltages and currents in the circuit, it is required first to calculate the value
of VEN from the common emitter to the ground N. Since VEN = (IC2 +
IB2)RE, the saturation currents IC2 and IB2 are to be determined. The
currents IC2 and IB2 can be determined from the equivalent circuit when
Q2 is ON as shown in Figure 4.15(c). In this diagram, the collector circuit
of Q2 in Figure 4.15(a) is replaced by its Thevenin’s equivalent voltage, i.e.

Figure 4.15(a) Example 4.7: equivalent circuit at the collector of Q2.

 Figure 4.15(b) Example 4.7: equivalent circuit at the base of Q2.

Figure 4.15(c) Example 4.7: equivalent circuit when Q2 of Figure 4.14 is in saturation.

and its Thevenin’s equivalent resistance

 Since IB2(actual)(= 0.225 mA) > IB2(min)(= 0.1517 mA), the transistor
Q2 is really in saturation. The voltages in the circuit are now found as
 The output swing, VW = VCN1 – VCN2 = 15.548 – 1.967 = 13.581 V.

(b) Referring to Figure 4.16(a), RL(max) can be calculated as given

below:
 (c) The maximum ICBO the bistable multivibrator can withstand so that
one device is still OFF can be found by finding the equivalent resistance
looking into the base as shown in Figure 4.16(b).

Figure 4.16 Example 4.7: (a) equivalent circuit to find RL(max),

(b) circuit to calculate RB, and (c) equivalent circuit to find ICBO.
EXAMPLE 4.8 Calculate the stable state voltages and currents for the self-
biased binary shown in Figure 4.17 using p-n-p germanium transistors. Find
the minimum value of hFE which will keep the ON transistor in saturation.
If the commutating capacitor C1 = 100 pF, determine the maximum
frequency of operation.

Figure 4.17 Example 4.8: circuit diagram.

Solution: Let Q2 be ON and Q1 be OFF in one of the stable states. The

connections between the base of Q1 and the collector of Q2 are indicated in
Figure 4.18(a), and the connections between the base of Q2 and the
collector of Q1 are indicated in Figure 4.18(b). In order to calculate the
voltages and currents in the circuit, it is required first to calculate the value
of VEN from the common emitter to the ground N. Since VEN = (IC2 +
IB2)RE, the saturation currents IC2 and IB2 are to be determined. The
currents IC2 and IB2 can be determined from the equivalent circuit when
Q2 is ON, shown in Figure 4.18(c). In this diagram, the collector circuit of
Q2, in Figure 4.18(a), is replaced by its Thevenin’s equivalent voltage.
Figure 4.18 Example 4.8: (a) equivalent circuit at collector of Q2, (b) equivalent circuit
at base of Q2, and (c) equivalent circuit when Q2 of Figure 4.17 is in saturation.
 Hence the equivalent circuit when Q2 is ON is as shown in Figure
4.18(c). Let VCE(sat) = –0.1 V and VBE(sat) = – 0.3 V.
The KVL equation to the base circuit is

– VB2T + VBE2(sat) + IB2(RB2T + RE) + IC2RE = 0

 A positive value of VBE only of about 0.1 V is required to cut off a p-n-p
transistor. Hence Q1 is certainly OFF.

EXAMPLE 4.9 The self-biased bistable multivibrator uses silicon

transistors with hFE(min) = 20. The junction voltages and ICBO may be
neglected. Design the circuit subject to the condition VCC = 18 V, R1 = R2,
IC(max) = 10 mA. The base current of ON transistor is twice the minimum
base current, and VBE of the OFF transistor is equal to – 1 V.

Solution: The circuit is as shown in Figure 4.19. Let Q2 be ON and Q1 be

OFF in one of the stable states. Let IC2(sat) = 10 mA.

Figure 4.19 Example 4.9: (a) circuit diagram and (b) the Thevenin’s equivalent at the base of Q2.
EXAMPLE 4.10 Junction transistors of n-p-n type with hFE(min) = 50,
and a battery supply of 6 V are available. Calculate the component values
required to realize a self-biased bistable multivibrator. Neglect junction
voltages.
Solution: The circuit diagram to be designed is as shown in Figure 4.20(a).
Let Q2 be ON, Q1 be OFF in one of the stable states. Let us neglect the
junction voltages and let
 Figure 4.20 Example 4.10: (a) circuit diagram and (b) circuit diagram to find IB2 (actual).

EXAMPLE 4.11 Design a self-biased symmetrical binary with the

following specifications: VCC = 10 V, RC = 1 k, VBE(sat) = 0.3 V, bON =
20, operating frequency up to 80 kHz, impedances of the triggering sources
= 250 .

Solution: The circuit to be designed is shown in Figure 4.14. VBE(sat) =

0.3 V implies that Ge transistors are used.
4.4 COMMUTATING CAPACITORS
We know that the bistable multivibrator has got two stable states and that it
can remain in either of its two stable states indefinitely. It can change state
only when a triggering signal such as a pulse from some external source is
applied. When a triggering signal is applied, conduction has to transfer from
one device to another. The transition time is defined as the interval during
which conduction transfers from one transistor to another. The reason for
this transition time is—even though the input signal at the base of a
transistor may be transferred to the collector with zero rise time, the signal
at the collector of the transistor cannot be transferred to the base of the other
transistor instantaneously. This is because the input capacitance Ci present
at the base of the transistor makes the R1–R2 attenuator act as an
uncompensated attenuator and so it will have a finite rise time, tr =
(R1||R2)Ci. The transition time may be reduced by compensating this
attenuator by introducing a small capacitor in parallel with the coupling
resistors R1 and R1 of the binary as shown in Figure 4.21. Since these
capacitors are introduced to increase the speed of operation of the device,
they are called speed-up capacitors. They are also called transpose or
commutating capacitors. So, commutating capacitors are small capacitors
connected in parallel with the coupling resistors in order to increase the
speed of operation. The commutating capacitors hasten the removal of
charge stored at the base of the ON transistor due to minority carriers. If the
commutating capacitors are arbitrarily large, the R1–R2 network acts as an
overcompensated attenuator and the signal at the collector will be
transmitted to the base of the other transistor very rapidly, but large values
of capacitors have some disadvantages.
 In the flip-flop shown in Figure 4.21, if for example Q1 is OFF and Q2 is
ON, the voltages across C1 and C1 are not alike because, when Q2 is ON
and Q1 is OFF, the voltage across C1 is VCE2(sat) – VB1(off) which is very

small  0.3 – (–1) = 1.3 V, and the voltage across C1 is equal to VCC –
VBE2(sat)  12 – 0.7 = 11.3 V. When the circuit is triggered so that Q2 is
OFF and Q1 is ON, then the voltage across C1 must be 11.3 V and that
across C1 must be 1.3 V. The flip-flop would not have settled in its new
state until the interchange of voltages had been completed.

Figure 4.21 A fixed-bias binary with commutating capacitors.

A transistor having been induced to change the state by a triggering

signal, a certain minimum time must elapse before a succeeding signal is
able to reliably induce the reverse transition. The smallest allowable
interval between triggers is called the resolving time of the flip-flop, and its
reciprocal is the maximum frequency at which the binary will respond.
The complete transfer of conduction from one device to another involves
two phases. The first of these is the transition time during which conduction
transfers from one device to another. For this transfer of conduction to take
place, the voltages across the input and output capacitances of the transistor
have to change. The voltages across the commutating capacitors C1 and
C1 need not change during this transfer of conduction. After this transfer
of conduction, the capacitors are allowed to interchange their voltages. This
additional time required for the purpose of completing the recharging of
capacitors after the transfer of conduction is called the settling time. Of
course, no clear-cut distinction can be made between the transition time and
the settling time. The sum of the transition time and the settling time is
called the resolution time. If the commutating capacitors are too small, the
transition time is increased but the settling time will be small and if the
commutating capacitors are too large, the transition time is reduced but the
settling time will be large. So, a compromise is called for.
The maximum frequency of operation fmax is given by

Methods of improving resolution

The resolution of a binary can be improved by taking the following steps:

1. By reducing all stray capacitances. Reductions in the values of stray

capacitances reduce their charging time, resulting in a reduction in the
time taken by the transistors to go to the opposite state.
2. By reducing the resistors R1, R2, and RC. Reductions in the values of
R1 and R2 result in a reduction in the charging time of the
commutating capacitors with a consequent improvement in transition
speed. Reducing resistors also reduces the recovery time.
 3. By not allowing the transistors to go into saturation. When the
transistors do not saturate, the storage time will be reduced resulting in
fast change from ON to OFF.

4.5 A NON-SATURATING BINARY

The binary discussed earlier is a saturated binary. When the transistors are
driven into saturation, because of the storage time delay, the speed of
operation is reduced. The speed of operation can be increased by not
allowing the transistors to go into saturation. Such a binary in which the
transistors always operate in the active region only, is called a non-
saturating binary.
Figure 4.22 shows the circuit diagram of a non-saturating binary. This is
obtained by adding two zener diodes and two p-n junction diodes to the
collector-coupled binary shown in Figure 4.21. These diodes ensure that the
collector base junctions are reverse biased and hence the transistor is always
operating in the active region. Both the zener diodes D3 and D4 are always
biased in the breakdown direction and each has a voltage VZ < VCC across
it. The voltage across the diode D1 or D2 is very small in the forward
direction. When Q2 is ON, its emitter junction is forward biased with VBE2
 0 V. So, the left side of D2 is at VZ and the right side is at VCE(sat).
Therefore, D2 is ON and acts as a short circuit. Hence VC2 = VZ, making
the collector junction reverse biased, and the transistor Q2 operates in the
active region.
 Figure 4.22 A non-saturated binary.

This negative voltage keeps Q1 cut-off. With Q1 cut-off, VCE1 is HIGH

and so the diode D1 is back biased. The output swing is approximately
equal to VCC – VZ.
The non-saturating binary is preferred over the saturated binary only
when an extremely high speed of operation is required because of the
following drawbacks:

1. The non-saturating circuits are more complicated than the saturated

circuits.
2. The non-saturating circuits consume more power than the saturated
circuits.
3. The voltage swing is less stable with temperature, ageing and
component replacement than in the case of saturated binary.

4.6 TRIGGERING THE BINARY

We know that a bistable multivibrator has got two stable states and that it
can remain in any one of the states indefinitely. The process of applying an
external signal to induce a transition from one state to the other is called
triggering. The triggering signal, which is usually employed is either a
pulse of short duration or a step voltage. There are two methods of
triggering—unsymmetrical triggering and symmetrical triggering.
Unsymmetrical triggering is one in which the triggering signal is effective
in inducing a transition in only one direction. In this, a second triggering
signal from a separate source must be introduced in a different manner to
achieve reverse transition. Symmetrical triggering is one in which each
successive triggering signal induces a transition regardless of the state in
which the binary happens to be, i.e. unsymmetrical triggering requires two
separate sources whereas symmetrical triggering requires only one source.
Unsymmetrical triggering finds extensive applications in logic circuitry (in
registers, coding, etc.). It can be used as a generator of a gate whose width
equals the interval between the triggers. Symmetrical triggering is used in
binary counting circuits and other applications.
The sensitivity of the binary to a pulse of such polarity as to turn OFF the
conducting device will appreciably exceed the sensitivity to a pulse of
opposite polarity. The triggering signal may be applied at the output of a
stage or at the input of a stage. In transistor circuits the triggering signal
may be applied at the collector of the transistor, or at the base.
An excellent method for triggering a binary unsymmetrically on the
leading edge of a pulse is to apply the pulse from a high impedance source
to the output of the non-conducting device. For p-n-p transistors, a positive
pulse needs to be applied.
The triggering signal may be applied through a resistor and a capacitor or
through a unilateral device such as a diode. Figure 4.23 shows a method of
triggering unsymmetrically through a resistor and a capacitor. If p-n-p
transistors are employed, the polarity of the triggering signal should be
reversed.

Figure 4.23 Unsymmetrical triggering through a resistor and a capacitor

(a) at the collectors and (b) at the bases.
4.7 TRIGGERING UNSYMMETRICALLY
THROUGH
A UNILATERAL DEVICE (DIODE)
Figure 4.24 shows unsymmetrical triggering through a unilateral device
when the signals are applied at the collectors. Suppose in one stable state
Q1 is ON and Q2 is OFF. When Q1 is ON, the diode D at the collector of
Q1 is back biased by the drop across RC because its anode is at VCE(sat)
and cathode is at VCC. So the diode will not transmit a positive pulse and
even the negative pulse cannot be transmitted unless it has an amplitude
larger than this voltage drop which anyway cannot affect the state of Q2. So
no change of state can take place by the application of a pulse at the
collector of Q1 when Q1 is ON. When Q2 is OFF, both anode and cathode
of the diode at its collector are at VCC and so the drop across D is zero. The
diode will still fail to transmit a positive-going trigger, but will transmit a
negative pulse or step to the input (base) of Q1 (which is ON) which will
result in a change of state. So when Q1 is ON and Q2 is OFF, only a
negative pulse applied at ‘R’ can change the state. The resistor R must be
large enough not to load down the trigger source. On the other hand, R must
be small enough so that any charge which accumulates on C during the
interval when D conducts will have time to decay during the time between
pulses. If the triggering rate is high, then it may be necessary to replace R
with a diode.
Figure 4.25 shows unsymmetrical triggering through a diode when
triggering signals are applied at the bases of the transistors. Here the
negative pulse is applied through D to the base of the ON stage. R is
returned to ground rather than to the supply voltage.

Figure 4.24 Unsymmetrical triggering at collectors.

Figure 4.25 Unsymmetrical triggering at bases.

If the trigger amplitude available is small, it may be necessary to amplify

the signal before applying it to the flip-flop. In this case a diode need not be
used because the amplifier can provide the unilateral action previously
supplied by the diode.
4.8 TRIGGERING SYMMETRICALLY
THROUGH A UNILATERAL DEVICE
Figure 4.26(a) shows an arrangement for symmetrical triggering through
diodes at the collectors of the transistors. If Q2 is ON and Q1 is OFF in one
of the stable states, the collector of Q2 is at VCE(sat) and the collector of
Q1 is at VCC. Therefore, D2 is reverse biased by VCC and D1 is at zero
bias. Hence a negative input signal will be transmitted through D1 to the
collector of Q1 and thus to the base of the ON stage Q2 via the R1C1
combination connecting the output of Q1 to the input of Q2. This negative
pulse at the base of Q2 which is ON, turns it to OFF state thus causing a
transition. After the transition is completed, D1 will be reverse biased and
D2 will be at zero bias. So the next negative pulse will pass through D2
instead of through D1. Hence these diodes are called steering diodes. The
binary will change state at each successive negative input pulse or step but
will not respond to the triggers of opposite polarity. The diode D3 serves the
purpose of R in unsymmetrical triggering. If p-n-p transistors are used, then
the diodes must be reversed and a positive triggering signal would be
required.
 Figure 4.26 Symmetrical triggering through diodes (a) at the collectors and (b) at the bases.

Figure 4.26(b) shows the arrangement of symmetrical triggering through

the diodes at the bases of the transistors.
Triggering may also be done symmetrically without the use of the
auxiliary diodes. The presence of commutating capacitors facilitates this,
but for this, the commutating capacitors must be large, and large values of
commutating capacitors lengthen the settling time of the binary. Therefore
this method of triggering without the auxiliary steering diodes is not
employed where the shortest possible resolution time is required.
Figure 4.27 shows the arrangement for triggering a self-biased bistable
multivibrator without steering diodes. Here a positive step is applied at the
common emitters of the flip-flop.

Figure 4.27 Symmetrical triggering of a self-biased binary.

4.9 A DIRECT-CONNECTED BINARY

Figure 4.28 shows a direct-connected binary. No coupling elements are used
and the collector of each transistor is connected to the base of the other
transistor directly by a wire. In one stable state, transistor Q1 is in saturation
and Q2 is conducting slightly, and in the other stable state, Q2 is in
saturation and Q1 is conducting slightly.
 Figure 4.28 A direct-connected binary.

Initially if we assume that Q1 is ON, since its emitter is grounded and

since its base and collector are connected to VCC through a resistor RC,
then

and hence Q1 is driven heavily into saturation. So for a Ge transistor, VCE1

= 0.05 V and VBE1 = 0.3 V. Because of the direct connection between the
collector of Q1 and the base of Q2, VBE2 = VCE1 = 0.05 V, a small
positive value. So Q2 is not OFF and it will be conducting slightly. The
output swing = VCE2 – VCE1 = VBE1 – VCE1 = 0.3 – 0.05 = 0.25 V. Even
though it has some advantages, there are many serious disadvantages too,
and so this circuit is not used these days. It was available in IC form as
DCTL earlier.
The advantages of direct connected binary are:
 1. Its extreme simplicity
2. Only one supply voltage of low value about 1.5 V is required.
3. Low power dissipation
4. Transistors with low breakdown voltages may be used.
5. The direct connected binary may be easily constructed as an IC
because of the few elements involved.

The disadvantages of direct connected binary are:

1. As temperature increases, the reverse saturation current ICBO may

increase sufficiently to bring Q1 into active region and may even take
Q2 out of saturation.
2. Since Q2 is driven heavily into saturation, the storage time delay will
be large and the switching speed will be low.
3. The output voltages are equal to their saturation base and collector
voltages, and these parameters may vary appreciably from transistor to
transistor.
4. The voltage swing is only a fraction of a volt and hence the binary is
susceptible to spurious voltages.
5. Since an OFF collector is tied directly to an ON base, it is difficult to
trigger the binary by the usual method of applying a pulse to the OFF
transistor. To supply sufficient current to take the ON transistor out of
saturation, an amplifier trigger circuit is usually required.

4.10 THE EMITTER-COUPLED BINARY

(THE SCHMITT TRIGGER CIRCUIT)
Figure 4.29 shows the circuit diagram of an emitter-coupled bistable
multivibrator using n-p-n transistors. Quite commonly it is called Schmitt
trigger after the inventor of its vacuum-tube version. It differs from the
basic collector-coupled binary in that the coupling from the output of the
second stage to the input of the first stage is missing and the feedback is
obtained now through a common emitter resistor RE.
It is a bistable circuit and the existence of only two stable states results
form the fact that positive feedback is incorporated into the circuit, and
from the further fact that the loop gain of the circuit is greater than unity.
There are several ways to adjust the loop gain. One way of adjusting the
loop gain is by varying RC1. Suppose RC1 is selected such that the loop
gain is less than unity. When RC1 is small, regeneration is not possible.
For the circuit of Figure 4.29, under quiescent conditions Q1 is OFF and
Q2 is ON because it gets the required base drive from VCC through RC1
and R1. So the output voltage

vo = VCC – IC2RC2 (where IC2 is the current in RC2 when Q1 is OFF)

is at its lower level. With Q2 conducting, there will be a voltage drop across
RE = (IC2 + IB2)RE, and this will elevate the emitter of Q1. As the input v
is increased from zero, the circuit will not respond until Q1 reaches the cut-
in point (at v = V1). Until then the output remains at its lower level. With
Q1 conducting (for v > V1) the circuit will amplify because Q2 is already
conducting and since the gain vo/v is positive, the output will rise in
response to the rise in input. As v continues to rise, C1 and hence B2
continue to fall and E2 continues to rise. Therefore a value of v will be
reached at which Q2 is turned OFF. At this point vo = VCC and the output
remains constant at this value of VCC, even if the input is further increased.
A plot of vo versus v is shown in Figure 4.30(a) for loop gain < 1.

Figure 4.29 An emitter-coupled binary.

Suppose the loop gain is increased by increasing the resistance RC1. Such
a change will have negligible effect on the cut-in point V1 of Q1. However
in the region of amplification (i.e. for v > V1) the amplifier gain vo/v
will increase and so the slope of the rising portion of the plot in Figure
4.30(a) will be steeper. This increase in slope with increase in loop gain
continues until at a loop gain of unity where the circuit has just become
regenerative the slope will become infinite. And finally when the loop gain
becomes greater than unity, the slope becomes negative and the plot of vo
versus v assumes the S shape shown in Figure 4.30(b).
 Figure 4.30 Response of emitter-coupled binary for (a) loop gain  1 and (b) loop gain > 1.

The behaviour of the circuit may be described by using this S curve. As v

rises from zero voltage, vo will remain at its lower level (= VCC – IC2
RC2) until v reaches V1. (This value of v = V1 at which the transistor Q1
just enters into conduction is called the upper triggering point, UTP.) As v
exceeds V1 the output will make an abrupt transition to its higher level (=
VCC). For v > V1, Q1 is ON and Q2 is OFF. Similarly if v is initially greater
than V1, then as v is decreased, the output will remain at its upper level until
v attains a definite level V2 at which point the circuit makes an abrupt
transition to its lower level. For v < V2, Q1 is OFF and Q2 is ON. (This
value of v = V2 at which the transistor Q2 resumes conduction is called the
lower triggering point, LTP.) This circuit exhibits hysteresis, that is, to
effect a transition in one direction we must first pass beyond the voltage at
which the reverse transition took place.
A vertical line drawn at v = V which lies between V2 and V1 intersects the
S curve at three points a, b and c. The upper and lower points a and c are
points of stable equilibrium. The S curve is a plot of values which satisfy
Kirchhoff’s laws and which are consistent with the transistor characteristics.
At v = V, the circuit will be at a or c, depending on the direction of
approach of v towards V. When v = V in the range between V2 and V1, the
Schmitt circuit is in one of its two possible stable states and hence is a
bistable circuit.
Applications of Schmitt trigger circuit
Schmitt trigger is also a bistable multivibrator. Hence it can be used in
applications where a normal binary is used. However for applications where
the circuit is to be triggered back- and-forth between stable states, the
normal binary is preferred because of its symmetry. Since the base of Q1 is
not involved in regenerative switching, the Schmitt trigger is preferred for
applications in which the advantage of this free terminal can be taken. The
resistance RC2 in the output circuit of Q2 is not required for the operation
of the binary. Hence this resistance may be selected over a wide range to
obtain different output signal amplitudes.
 A most important application of the Schmitt trigger is its use as an
amplitude comparator to mark the instant at which an arbitrary waveform
attains a particular reference level. As input v rises to V1 or falls to V2, the
circuit makes a fast regenerative transfer to its other state.
Another important application of the Schmitt trigger is as a squaring
circuit. It can convert a sine wave into a square wave. In fact, any slowly
varying input waveform can be converted into a square wave with faster
leading and trailing edges as shown in Figure 4.31, if the input has large
enough excursions to carry the input beyond the limits of the hysteresis
range, VH = V1 – V2.

Figure 4.31 Response of the emitter-coupled binary to an arbitrary input waveform.

In another important application, the Schmitt trigger circuit is triggered

between its two stable states by alternate positive and negative pulses. If the
input is biased at a voltage V between V2 and V1 and if a positive pulse of
amplitude greater than V1 – V is coupled to the input, then Q1 will conduct
and Q2 will be OFF. If now a negative pulse of amplitude larger than V –
V2 is coupled to the input, the circuit will be triggered back to the state
where Q1 is OFF and Q2 is ON.
Hysteresis
If the amplitude of the periodic input signal is large compared with the
hysteresis range VH, then the hysteresis of the Schmitt trigger is not a
matter of concern. In some applications, a large hysteresis range will not
allow the circuit to function properly.
Hysteresis may be eliminated by adjusting the loop gain of the circuit to
unity. Such an adjustment may be made in a number of ways:

(1) The loop gain may be increased or decreased by increasing or

decreasing the resistance RC1.
(2) The loop gain may be increased or decreased by adding a resistance
RE1 in series with the emitter of Q1, or by adding a resistance RE2 in
series with the emitter of Q2 and then decreasing or increasing RE1 and
RE2. Since RC1 and RE1 are in series with Q1, these resistors will have
no effect on the circuit when Q1 is OFF. Therefore, these resistors will
not change V1 but may be used to move V2 closer to or coincident with
V1. Similarly, RE2 will affect V1 but not V2.
(3) The loop gain may also be varied by varying the ratio R1/(R1 + R2).
Such an adjustment will change both V1 and V2.
(4) The loop gain may be increased by increasing the value of RS.
 If RE1 or RE2 is larger than the value required to give zero hysteresis,
then the gain will be less than unity and the circuit will not change state. So,
usually RE1 or RE2 is chosen so that a small amount of hysteresis remains
in order to ensure that the loop gain is greater than unity.
V1 is independent of RS but V2 depends on RS and increases with an
increase in the value of RS. So for a large value of RS it is possible for V2 to
be equal to V1. Hysteresis is thus eliminated and the gain is unity. If RS
exceeds this critical value, the loop gain falls below unity and the circuit
cannot be triggered. If RS is too small, the speed of operation of the circuit
is reduced.
Derivation of expression for UTP
The upper triggering point UTP is defined as the input voltage V1 at which
the transistor Q1 just enters into conduction. To calculate V1, we have to
first find the current in Q2 when Q1 just enters into conduction. For this we
have to find the Thevenin’s equivalent voltage V and the Thevenin’s
equivalent resistance RB at the base of Q2, where

It is possible for Q2 to be in its active region or to be in saturation.

Assuming that Q2 is in its active region

IC2 = hFEIB2.......... IE2 = IC2 + IB2 = (hFE + 1)IB2

In the circuit shown in Figure 4.32, to calculate V1, we replace VCC,

RC1, R1 and R2 of Figure 4.29 by V and RB at the base of Q2.
 Figure 4.32 The equivalent circuit of Figure 4.29 with Q1 just at cut-in.

Writing KVL around the base loop of Q2,

Since Vg1 is the voltage from base to emitter at cut-in where the loop
gain just exceeds unity, it differs from VBE2 in the active region by only 0.1
V for either Ge or Si.

............................................................V1 = V – 0.1

This indicates that V1 may be made almost independent of hFE, of the

emitter resistance RE, of the temperature and of whether or not a silicon or
germanium transistor is used. Hence the discriminator level V1 is stable
with transistor replacement, ageing, temperature changes, provided that
(hFE + 1)RE >> RB and that V >> 0.1. Since V depends on VCC, RC1,
R1 and R2, where stability is required it is necessary that a stable supply
and stable resistors are selected.
Derivation of expression for LTP
The lower triggering point LTP is defined as the input voltage V2 at which
the transistor Q2 resumes conduction. V2 can be calculated from the circuit
shown in Figure 4.33 which is obtained by replacing VCC, RC1, R1 and R2
of Figure 4.29 by Thevenin’s equivalent voltage VTh and Thevenin’s
equivalent resistance R at the collector of Q1, where
 Figure 4.33 The equivalent circuit of Figure 4.29 when Q2 just resumes conduction.

The voltage ratio from the collector of Q1 to the base of Q2 is a = R2/(R1

+ R2). In Figure 4.33, the input signal to Q1 is decreasing, and when it
reaches V2 then Q2 comes out of cut-off.
Writing KVL around the base circuit of Q2,
Therefore from Figure 4.33,

Since VBE1 is higher for silicon than germanium, the LTP V2 is a few
tenths of a volt higher for a Schmitt trigger using silicon transistors than for
one using germanium transistors.

EXAMPLE 4.12 Consider the emitter-coupled bistable multivibrator of

Figure 4.29 with hFE = 20, VCC = 10 V, RS = 1 k, RE = 4 k, RC1 = 6
k, RC2 = 1 k, R1 = 2 k, R2 = 8 k. (a) Calculate the UTP and the LTP,
and plot the output wave when the input is 10 sin wt. (b) Find the angles at
which the circuit flips. (c) Find RE1 to eliminate hysteresis. (d) Find RE2 to
eliminate hysteresis.

Solution: (a) Referring to Figure 4.29, an approximate value of UTP is

given by

V1 = V – 0.1
The input and output waveforms are shown in Figure 4.34.
 Figure 4.34 Example 4.12: (a) input waveform and (b) output waveform.

(c) A resistor RE1 in series with the emitter of Q1 will affect V2 but not
V1. Hence V1 = 4.704 V. From Figure 4.35 with RE1 in series with E1, we
see that IC1 which was determined by the base circuit of Q2 is unaffected
by RE1. Hence the value of VEN2 at which Q2 returns to conduction is the
same as before, in order for the currents to remain unchanged by the amount
of the voltage drop across RE1. Hence, this resistance must be chosen so
that (IC1 + IB1)RE1 is equal to the value of VH before the addition of RE1.
 The comparator level is now 5.704 V for either increasing or decreasing
voltages.

Figure 4.35 Calculation of RE1 to eliminate hysteresis.

(d) From Figure 4.36, we see that if we place a resistor RE2 in series with
the emitter of Q2 it can have no effect on V2 because Q2 is OFF. Hence V2
remains at 3.3 V. However RE2 will affect VEN1 and hence V1. From the
base circuit of Q2,
 Figure 4.36 Calculation of RE2 to eliminate hysteresis.

EXAMPLE 4.13 A Schmitt trigger with Ge transistors having hFE = 40 is

shown in Figure 4.37. The circuit parameters are VCC = 22 V, RS = 2 k,
RC1 = 10 k, RC2 = 2 k, R1 = 25 k, R2 = 100 k and RE = 30 k.
Find (a) UTP(V1), (b) LTP(V2), (c) RE1 to eliminate hysteresis, and (d)
RE2 to eliminate hysteresis.

Figure 4.37 Example 4.13: circuit diagram.

 Figure 4.38 Example 4.13: circuit of Figure 4.37 with Q1 just at cut-in.

Applying KVL at the base circuit of Q2,

 Figure 4.39 Example 4.13: circuit of Figure 4.37 with Q2 just at cut-off.

(c) Calculation of RE1 to eliminate hysteresis

EXAMPLE 4.14 Design a Schmitt trigger circuit to have VCC = 12 V, UTP
= 6 V, LTP = 3 V, using two silicon n-p-n transistors with hFE(min) = 60.

Solution: The circuit to be designed is as shown in Figure 4.40. Let IC2 = 2

mA and I2 = IC2/10.
 Figure 4.40 Example 4.14: circuit to be designed.

Calculation of RE:
EXAMPLE 4.15 Design a Schmitt trigger circuit for the following
specifications: UTP = 8 V, LTP = 5 V, VCC = 15 V, IC(sat) = 2 mA,
hFE(min) = 25.

Solution: The circuit to be designed is as shown in Figure 4.29. The circuit

components to be evaluated are RE, RS, RC1, R1, R2, and RC2

Calculation of RE:

UTP is the value of input voltage at which Q1 just enters into conduction.
Q2 is already conducting and is in the active region. Assuming silicon
transistors Vg = 0.5 V.

Calculation of RS:

The source resistance RS must be selected such that RS << hFERE

(When Q1 is conducting, the drop across RS must be very small
compared to VE)

RS << 25  3.75 (= 93.75) k

Choose RS = 1 k (arbitrary value)

Calculation of RC1:
Calculation of R1:

R1 should be 3 to 5 times larger than RC1

4.11 MONOSTABLE MULTIVIBRATOR
As the name indicates, a monostable multivibrator has got only one
permanent stable state, the other state being quasi stable. Under quiescent
conditions, the monostable multivibrator will be in its stable state only. A
triggering signal is required to induce a transition from the stable state to
the quasi stable state. Once triggered properly the circuit may remain in its
quasi stable state for a time which is very long compared with the time of
transition between the states, and after that it will return to its original state.
No external triggering signal is required to induce this reverse transition. In
a monostable multivibrator one coupling element is a resistor and another
coupling element is a capacitor.
When triggered, since the circuit returns to its original state by itself after
a time T, it is known as a one-shot, a single-step, or a univibrator. Since it
generates a rectangular waveform which can be used to gate other circuits,
it is also called a gating circuit. Furthermore, since it generates a fast
transition at a predetermined time T after the input trigger, it is also referred
to as a delay circuit. The monostable multivibrator may be a collector-
coupled one, or an emitter-coupled one.

4.12 THE COLLECTOR COUPLED

MONOSTABLE MULTIVIBRATOR
Figure 4.41 shows the circuit diagram of a collector-to-base coupled
(simply called collector-coupled) monostable multivibrator using n-p-n
transistors. The collector of Q2 is coupled to the base of Q1 by a resistor R1
(dc coupling) and the collector of Q1 is coupled to the base of Q2 by a
capacitor C (ac coupling). C1 is the commutating capacitor introduced to
increase the speed of operation. The base of Q1 is connected to –VBB
through a resistor R2, to ensure that Q1 is cut off under quiescent
conditions. The base of Q2 is connected to VCC through R to ensure that
Q2 is ON under quiescent conditions. In fact, R may be returned to even a
small positive voltage but connecting it to VCC is advantageous.
 Figure 4.41 Circuit diagram of a collector-coupled monostable multivibrator.

The circuit parameters are selected such that under quiescent conditions,
the monostable multivibrator finds itself in its permanent stable state with
Q2 ON (i.e. in saturation) and Q1 OFF (i.e. in cut-off). The multivibrator
may be induced to make a transition out of its stable state by the application
of a negative trigger at the base of Q2 or at the collector of Q1. Since the
triggering signal is applied to only one device and not to both the devices
simultaneously, unsymmetrical triggering is employed.
When a negative signal is applied at the base of Q2 at t = 0, due to
regenerative action Q2 goes to OFF state and Q1 goes to ON state. When
Q1 is ON, a current I1 flows through its RC and hence its collector voltage
drops suddenly by I1RC. This drop will be instantaneously transmitted
+
through the coupling capacitor C to the base of Q2. So at t = 0 , the base
voltage of Q2 is VBE(sat) – I1RC.
The circuit cannot remain in this state for a long time (it stays in this state
only for a finite time T) because when Q1 conducts, the coupling capacitor
C charges from VCC through the conducting transistor Q1 and hence the
potential at the base of Q2 rises exponentially with a time constant (R +
Ro)C  RC, where Ro is the conducting transistor output impedance
including the resistance RC. When it passes the cut-in voltage Vg of Q2 (at
a time t = T), a regenerative action takes place turning Q1 OFF and
eventually returning the multivibrator to its initial stable state.
The transition from the stable state to the quasi-stable state takes place at
t = 0, and the reverse transition from the quasi-stable state to the stable state
takes place at t = T. The time T for which the circuit is in its quasi-stable
state is also referred to as the delay time, and also as the gate width, pulse
width, or pulse duration. The delay time may be varied by varying the time
constant t(= RC).
Expression for the gate width T of a monostable multivibrator
neglecting the reverse saturation current ICBO

Figure 4.42(a) shows the waveform at the base of transistor Q2 of the

monostable multivibrator shown in Figure 4.41.
 Figure 4.42(a) Voltage variation at the base of Q2 during the quasi-stable state (neglecting ICBO).

For t < 0, Q2 is ON and so vB2 = VBE(sat). At t = 0, a negative signal

applied brings Q2 to OFF state and Q1 into saturation. A current I1 flows
through RC of Q1 and hence vC1 drops abruptly by I1RC volts and so vB2
also drops by I1RC instantaneously. So at t = 0, vB2 = VBE(sat) – I1RC.
For t > 0, the capacitor charges with a time constant RC, and hence the base
voltage of Q2 rises exponentially towards VCC with the same time constant.
At t = T, when this base voltage rises to the cut-in voltage level Vg of the
transistor, Q2 goes to ON state, and Q1 to OFF state and the pulse ends.
In the interval 0 < t < T, the base voltage of Q2, i.e. vB2 is given by
–t/t
vB2 = VCC – (VCC – {VBE(sat) – I1RC})e
– +
But I1RC = VCC – VCE(sat) (because at t = 0 , vC1 = VCC and at t = 0 ,
vC1 = VCE(sat))
 Normally for a transistor, at room temperature, the cut-in voltage is the
average of the saturation junction voltages for either Ge or Si transistors,
i.e.

The larger the VCC is, compared to the saturation junction voltages, the
more accurate the result is.
The gate width can be made very stable (almost independent of transistor
characteristics, supply voltages, and resistance values) if Q1 is driven into
saturation during the quasi-stable state.
Expression for the gate width of a monostable multivibrator
considering the reverse saturation current ICBO

In the derivation of the expression for gate width T above, we neglected the
effect of the reverse saturation current ICBO on the gate width T. In fact, as
the temperature increases, the reverse saturation current increases and the
gate width decreases.
In the quasi-stable state when Q2 is OFF, ICBO flows out of its base
through R to the supply VCC. Hence the base of Q2 will be not at VCC but
at VCC + ICBOR, if C is disconnected from the junction of the base of Q2
with the resistor R. It therefore appears that the capacitor C in effect charges
through R from a source VCC + ICBOR. See Figure 4.42(b).

Figure 4.42(b) Voltage variation at the base of Q2 during the quasi-stable state (considering ICBO).

So, the expression for the voltage at the base of Q2 is given by

Neglecting the junction voltages and the cut-in voltage of the transistor,
 Since ICBO increases with temperature, we can conclude that the delay
time T decreases as temperature increases.
Waveforms of the collector-coupled monostable multivibrator
The waveforms at the collectors and bases of both the transistors Q1 and Q2
of the monostable multivibrator of Figure 4.41 are shown in Figure 4.44.
The triggering signal is applied at t = 0, and the reverse transition occurs
at t = T.
The stable state. For t < 0, the monostable circuit is in its stable state with
Q2 ON and Q1 OFF. Since Q2 is ON, the base voltage of Q2 is vB2 =
VBE2(sat) and the collector voltage of Q2 is vC2 = VCE2(sat). Since Q1 is
OFF, there is no current in RC of Q1 and its base voltage must be negative.
Hence the voltage at the collector of Q1 is,

vC1 = VCC

and the voltage at the base of Q1 using the superposition theorem is

The quasi-stable state. A negative triggering signal applied at t = 0 brings

Q2 to OFF state and Q1 to ON state. A current I1 flows in RC of Q1. So,
the collector voltage of Q1 drops suddenly by I1RC volts. Since the voltage
across the coupling capacitor C cannot change instantaneously, the voltage
at the base of Q2 also drops by I1RC, where I1RC = VCC – VCE2(sat).
Since Q1 is ON,

In the interval 0 < t < T, the voltages vC1, vB1 and vC2 remain constant
at their values at t = 0, but the voltage at the base of Q2, i.e. vB2 rises
exponentially towards VCC with a time constant, t = RC, until at t = T, vB2
reaches the cut-in voltage Vg of the transistor.
Waveforms for t > T. At t = T+, reverse transition takes place. Q2 conducts
and Q1 is cut-off. The collector voltage of Q2 and the base voltage of Q1
return to their voltage levels for t < 0. The voltage vC1 now rises abruptly
since Q1 is OFF. This increase in voltage is transmitted to the base of Q2
and drives Q2 heavily into saturation. Hence an overshoot develops in vB2
at t = T+, which decays as the capacitor recharges because of the base
current. The magnitude of the base current may be calculated as follows.
Replace the input circuit of Q2 by the base spreading resistance rBB in
series with the voltage VBE(sat) as shown in Figure 4.43. Let IB be the
base current at t = T+. The current in R may be neglected compared to IB.
From Figure 4.43,
VBE = IBrBB + VBE(sat) and VC = VCC – IBRC – VBE

Figure 4.43 Equivalent circuit for calculating the overshoot at base B2 of Q2.

The jumps in voltages at B2 and C1 are, respectively, given by

d = VBE – Vg = IBrBB + VBE(sat) – Vg and d = VCC – VCE(sat)
– IBRC
Since C1 and B2 are connected by a capacitor C and since the voltage
across the capacitor cannot change instantaneously, these two discontinuous
voltage changes d and d must be equal.
Equating them,
Figure 4.44 Waveforms at the collectors and bases of the collector-coupled monostable multivibrator.
(a) at the base of Q2, (b) at the collector of Q1, (c) at the collector of Q2, and (d) at the base
of Q1
Monostable multivibrator as a voltage-to-time converter (as a pulse
width modulator)
Figure 4.45(a) shows the circuit diagram of a monostable multivibrator as a
voltage-to-time converter. By varying the auxiliary supply voltage V, the
pulse width can be changed. It can be seen that the resistor R is connected to
the auxiliary voltage source V instead of to VCC.
The waveform of the voltage vB2 at the base of Q2 is shown in Figure
4.45(b).

Figure 4.45 Monostable multivibrator.

 Thus the pulse width is a function of auxiliary voltage V. For this reason
the monostable multivibrator shown in Figure 4.45(a) is termed a voltage-
to-time converter. It is also called a pulse width modulator.
EXAMPLE 4.16 The monostable multivibrator shown in Figure 4.46 uses
n-p-n silicon transistors with hFE = 30 and rBB = 200 . The component
values are: C = 1000 pF, R1 = 20 k, R2 = 20 k, R = 20 k, RC = 2 k.
The supply voltages are: VCC = 12 V and –VBB = –3 V, VBE(sat) = 0.7 V
and VCE(sat) = 0.3 V. (a) Compute and plot the voltage waveforms. (b)
Calculate the width of the gating signal.

Figure 4.46 Example 4.16: current distribution when Q2 is ON.

Solution: (a) In the circuit diagram of Figure 4.46, we will assume that Q2
is in saturation and Q1 is cut-off in the stable state and then justify this
assumption. Since IC2  I2,
 Since the actual base current (IB2 = 0.565 mA) is greater than the
minimum base current, [IB2(min) = 0.192 mA] Q2 is really in saturation.

This negative voltage at the base of Q1 ensures that Q1 is really cut off.
When a triggering signal is applied at t = 0, the multivibrator goes to its
quasi-stable state with Q2 OFF and Q1 ON.
We will first assume that Q1 is in saturation and then justify this
assumption. Assuming that Q1 is in saturation and Q2 is cut-off, the current
distribution is as shown in Figure 4.47.
 Figure 4.47 Example 4.16: current distribution when Q1 is ON.

Since actual IB1 > IB1(min), the transistor Q1 is really in saturation

during the quasi-stable state.
EXAMPLE 4.17 A collector-coupled one shot has the waveform shown in
Figure 4.48 at the collector of the normally OFF transistor Q1. The base
spreading resistance of the n-p-n transistors used is 200 . Draw to scale
the waveform at the base of the normally ON transistor Q2 and evaluate
RC.

Figure 4.48 Example 4.17: waveform.

Solution: In the circuit of the monostable multivibrator shown in Figure
4.41, Q1 is normally OFF. So the given waveform is vC1 (at the collector of
Q1). From Figure 4.48 it is obvious that VCC = 3V, VCE (sat) = 0.1 V and
the overshoot d = 0.6 V – 0.1 V = 0.5 V.
Since VCE (sat) = 0.1 V, the transistor used must be of germanium type.
So VBE (sat) = 0.3 V and Vg = 0.1 V. The required waveform is shown in
Figure 4.49.

Figure 4.49 Example 4.17: monostable multivibrator circuit when Q1 is OFF.

Calculation of RC:

EXAMPLE 4.18 Design a collector-coupled one-shot with a gate width of

3 ms, using n-p-n transistors.
Solution: Referring to the collector-coupled monostable multivibrator of
Figure 4.41, let us neglect ICBO, VBE(sat) and VCE(sat). Let hFE = 20.
Let IB(actual) = 1.5  IB(min) for the transistor in saturation and let VBE
= –1 V for the OFF transistor.
Also let, R1 = R2, VCC = 6 V and IC(sat) = 2 mA
We have to calculate the values of RC, R, VBB, R1, R2 and C. In the
stable state, Q2 is ON and Q1 is OFF.

Calculation of R1 and R2:

In the quasi-stable state, Q1 is ON and Q2 is OFF. Assuming that in the
quasi-stable state Q1 is equally driven into saturation, (Figure 4.47)
Design of triggering circuit
The RC combination is a differentiating circuit. Let the pulse width of
the triggering signal be tp = 1 s.
Let the time constant of the circuit RC be one-tenth of the pulse
width, i.e.

Let R be 10 k.

The diode permits only the negative-going trigger pulse. The circuit
diagram designed is shown in Figure 4.50.
 Figure 4.50 Example 4.17: designed circuit.

EXAMPLE 4.19 Calculate the component values of a monostable

multivibrator developing an output pulse of 500 s duration. Assume
hFE(min) = 25, IC(sat) = 5 mA, VCC = 10 V, and VBB = – 4 V.

Solution: The circuit to be designed is shown in Figure 4.41. In stable state,

Q2 is ON and Q1 is OFF. Let VCE(sat) = 0.4 V and VBE(sat) = 0.8 V.
 In quasi-stable state, Q1 is ON and Q2 is OFF. Assuming that Q1 is
equally driven into saturation
 The designed circuit is as shown in Figure 4.50.

EXAMPLE 4.20 Design a collector-coupled one-shot multivibrator circuit

using n-p-n transistors. Neglect ICBO and the junction voltages of the
transistor in saturation. Let hFE(min) = 20. In the stable state the OFF
transistor has VBE = – 1 V. The ON transistor has base current IB which is
50% in excess of the IB(min) value. VCC = 8 V, IC(sat) = 2 mA, delay time
= 2500 s. Choose R1 = R2.

Solution: The circuit to be designed is shown in Figure 4.41.

Calculation of RC:

Under quiescent conditions, Q2 is ON and Q1 is OFF.

Calculation of R1 = R2:

Assuming that Q1 is equally driven into saturation in quasi-stable state

4.13 THE EMITTER-COUPLED
MONOSTABLE MULTIVIBRATOR
Figure 4.51 shows the circuit diagram of an emitter-coupled monostable
multivibrator. It differs from the collector-coupled one-shot in that the
collector of Q2 is not coupled to the base of Q1 and instead the feedback
has been provided through a common emitter resistance RE. Also, there is
no need for a negative power supply. Since the signal at C2 is not directly
involved in the regenerative loop, this collector makes an ideal point from
which to obtain an output voltage waveform. Since the base of Q1 is not
connected to any other point in the circuit, it makes a good point at which to
inject a triggering signal. Hence the trigger source cannot load the circuit.
The gate width of a one-shot can be controlled through I1. In the case of
collector-coupled one-shot it is not possible to stabilize I1, but in an emitter-
coupled one-shot, the presence of the emitter resistance RE serves to
stabilize I1. The current I1 may be adjusted through the bias voltage V, and
T varies linearly with V. Hence an emitter-coupled configuration makes an
excellent gate wave generator whose width is easily and linearly
controllable by means of an electrical signal.

Figure 4.51 An emitter-coupled monostable multivibrator.

The waveforms of the emitter-coupled monostable multivibrator are

shown in Figure 4.52.
Figure 4.52 Waveforms of emitter-coupled monostable multivibrator.
 In the stable state, Q2 is ON because it gets the required base drive from
VCC through R and develops a potential VEN across the resistor RE. The
biasing resistors R1 and R2 are selected such that VB1 is smaller than VEN
to ensure that Q1 is OFF. This is the stable state. When a positive going
triggering pulse is applied at the base of Q1, the circuit goes into the quasi-
stable state because VB1 > VEN2. When Q1 goes ON its collector potential
drops, consequently a negative step is applied to the base of Q2 turning Q2
OFF. Due to conduction of Q1, a voltage drop VEN1 is developed across
RE. In the quasi-stable state, VB1 > VEN1 and Q1 is ON and Q2 is OFF.
However when Q1 is ON, the capacitor C charges from VCC through R.
When the potential VBN2 reaches the value of VEN1 + Vg, the transistor
Q2 conducts and due to regenerative feedback Q2 goes into saturation and
Q1 into cut-off and the pulse ends.

Expression for gate width

4.14 TRIGGERING THE MONOSTABLE
MULTIVIBRATOR
A monostable multivibrator needs to be triggered by a suitable signal in
order to switch it from the stable state to the quasi stable state. However
after remaining in the quasi stable state for a time T = 0.693 RC, it
automatically switches back to the original stable state, without any
triggering signal applied. Thus unlike a bistable multivibrator, a monostable
multivibrator requires only one triggering signal. Hence only
unsymmetrical triggering techniques are adopted for monostable
multivibrators. Generally speaking, all the triggering methods which are
applicable to the binary are also applicable to the monostable multivibrator.
The collector-coupled monostable multivibrator is normally triggered by
applying a negative pulse at the collector of the OFF transistor (n-p-n) Q1
through an RC differentiator circuit which converts it into positive and
negative spikes as shown in Figure 4.50. The positive spike is blocked by
the diode and the negative spike is transmitted through it and the capacitor
C to the base of the ON transistor Q2. So Q2 goes to the OFF state and Q1
to the ON state. This method has two advantages: one is as we know; the
multivibrator is more sensitive to a pulse of such a polarity which brings the
ON device to the OFF state. The second is, at the instant of the transition,
the collector of Q1 drops, the diode no longer conducts, and the
multivibrator does not respond to the triggering signal till the quasi-stable
state is completed. The emitter-coupled monostable multivibrator may be
triggered by applying a positive pulse of sufficient amplitude at the base of
Q1 to bring the OFF transistor Q1 to the ON state as shown in Figure 4.51.

4.15 ASTABLE MULTIVIBRATOR

As the name indicates an astable multivibrator is a multivibrator with no
permanent stable state. Both of its states are quasi stable only. It cannot
remain in any one of its states indefinitely and keeps on oscillating between
its two quasi stable states the moment it is connected to the supply. It
remains in each of its two quasi stable states for only a short designed
interval of time and then goes to the other quasi stable state. No triggering
signal is required. Both the coupling elements are capacitors (ac coupling)
and hence both the states are quasi stable. It is a free running multivibrator.
It generates square waves. It is used as a master oscillator.
There are two types of astable multivibrators:

1. Collector-coupled astable multivibrator

2. Emitter-coupled astable multivibrator

4.16 THE COLLECTOR-COUPLED ASTABLE

MULTIVIBRATOR
Figure 4.53 shows the circuit diagram of a collector-coupled astable
multivibrator using n-p-n transistors. The collectors of both the transistors
Q1 and Q2 are connected to the bases of the other transistors through the
coupling capacitors C1 and C2. Since both are ac couplings, neither
transistor can remain permanently at cut-off. Instead, the circuit has two
quasi-stable states, and it makes periodic transitions between these states.
Hence it is used as a master oscillator. No triggering signal is required for
this multivibrator. The component values are selected such that, the moment
it is connected to the supply, due to supply transients one transistor will go
into saturation and the other into cut-off, and also due to capacitive
couplings it keeps on oscillating between its two quasi stable states.

Figure 4.53 A collector-coupled astable multivibrator.

The waveforms at the bases and collectors for the astable multivibrator
are shown in Figure 4.54. Let us say at t = 0, Q2 goes to ON state and Q1 to
OFF state. So, for t < 0, Q2 was OFF and Q1 was ON. Hence for t < 0, vB2
is negative, vC2 = VCC, vB1 = VBE(sat) and vC1 = VCE(sat). The capacitor
C2 charges from VCC through R2 and vB2 rises exponentially towards
VCC. At t = 0, vB2 reaches the cut-in voltage Vg and Q2 conducts. As Q2
conducts, its collector voltage vC2 drops by I2RC = VCC – VCE(sat). This
drop in vC2 is transmitted to the base of Q1 through the coupling capacitor
C2 and hence vB1 also falls by I2RC. Q1 goes to OFF state. So, vB1 =
VBE(sat) – I2RC, and its collector voltage vC1 rises towards VCC. This rise
in vC1 is coupled through the coupling capacitor C2 to the base of Q2,
causing an overshoot d in vB2 and the abrupt rise by the same amount d in
vC1 as shown in Figure 4.51(c). Now since Q2 is ON, C1 charges from
VCC through R1, and hence vB1 rises exponentially. At t = T1, when vB1
rises to Vg, Q1 conducts and due to regenerative action Q1 goes into
saturation and Q2 to cut-off. Now, for t > T1, the coupling capacitor C2
charges from VCC through R2 and at t = T1 + T2, when vB2 rises to the cut-
in voltage Vg , Q2 conducts and due to regenerative feedback Q2 goes to
ON state and Q1 to OFF state. The cycle of events repeats and the circuit
keeps on oscillating between its two quasi-stable states. Hence the output is
a square wave. It is called a square wave generator or square wave oscillator
or relaxation oscillator. It is a free running oscillator.
Expression for the frequency of oscillation of an astable multivibrator
Consider the waveform at the base of Q1 shown in Figure 4.54(d). At t = 0,
Figure 4.54 Waveforms at the bases and collectors of a collector-coupled astable multivibrator.
The frequency of oscillation may be varied over the range from cycles to
mega cycles by varying RC. It is also possible to vary the frequency
electrically by connecting R1 and R2 to an auxiliary voltage source V (the
collector supply remains +VCC) and then varying this voltage V.
The astable multivibrator as a voltage-to-frequency converter
Figure 4.55 shows the circuit diagram of an astable multivibrator used as a
voltage-to-frequency converter. The frequency can be varied by varying the
magnitude of the auxiliary voltage source V. Now the supply voltage is
VCC only, but the voltage level to which the coupling capacitors C1 and C2
try to charge is not VCC but V.
For 0 < t < T1, Q1 is OFF and Q2 is ON. From the base waveform shown
in Figure 4.56(a) the voltage at the base of Q1 is given by

Figure 4.55 The astable multivibrator as a voltage-to-frequency converter.

Figure 4.56 (a) Waveform at the base of Q1 and (b) waveform at
the base of Q2 for the circuit of Figure 4.55.
This shows that by varying V, the frequency f can be varied and hence this
circuit acts as a voltage-to-frequency converter.
The astable multivibrator with vertical edges
The collector-coupled astable multivibrator shown in Figure 4.53 produces
the output waveforms at the collectors of Q1 and Q2 with rounded edges as
shown in Figure 4.54. An astable multivibrator which can generate collector
waveforms with vertical edges can be obtained by the addition of two
diodes and two resistors as shown in Figure 4.57. If Q2 is driven OFF, its
collector voltage rises immediately to VCC so that D2 is reverse biased and
Q1 goes into saturation. The saturation base current of Q1 passes through
C1 and R3, rather than through RC. Since IB no longer passes through
RC, the collector waveform now has vertical edges as desired.
 Figure 4.57 The astable multivibrator with vertical edges.

The astable multivibrator which does not block

For the astable multivibrator shown in Figure 4.53 if the supply voltage is
increased slowly from zero to its full value VCC, both the transistors may
go into saturation simultaneously and remain in that state. This blocked
condition does not occur if the voltage is applied suddenly. A circuit which
cannot block is shown in Figure 4.58.

Figure 4.58 The astable multivibrator which does not block.

The gated astable multivibrator

Figure 4.59 shows the circuit diagram of a gated astable multivibrator. This
is obtained by adding a transistor Q3 in series with the emitter of Q1 or Q2
of the collector-coupled astable multivibrator. This gated astable
multivibrator can start or stop oscillating at definite times.

Figure 4.59 The gated astable multivibrator.

The input vi to Q3 can assume one of two values. One level is chosen
such that Q3 is OFF. With Q3 OFF, Q1 will be OFF, and Q2 will be ON and
the circuit is quiescent, i.e. it does not oscillate. The second binary level is
chosen such that Q3 is driven into saturation. Hence, at any instant (say t =
0) that this voltage is applied, Q1 goes ON and Q2 is driven OFF. The
circuit operates as an astable multivibrator with waveforms which are
essentially those in Figure 4.54 starting at t = 0.

EXAMPLE 4.21 Find the period of output and the frequency of oscillation
of an astable multivibrator with R1 = R2 = 25 k and C1 = C2 = 0.2 F.
EXAMPLE 4.22 For the astable multivibrator shown in Figure 4.53 if R1 =
20 k, R2 = 10 k, C1 = 0.02 F and C2 = 0.015 F, find the frequency
of oscillation and duty cycle of the output waveform.

EXAMPLE 4.23 Find the ratio VCC/V, if a voltage-to-frequency converter

generates oscillations of frequency twice of that when V = VCC.

Solution: The frequency of oscillation of the output voltage of a voltage-to-

frequency converter is given as
EXAMPLE 4.24 Design an astable multivibrator to generate a square wave
of 1 kHz.

Solution: Referring to Figure 4.53, let us use n-p-n transistors with hFE =
25. Let IC(sat) = 5 mA and VCC = 12 V and let us assume that a
symmetrical square wave (T1 = T2 = T/2) is to be generated. Also, let us
neglect the junction voltages.
For a symmetrical square wave R1 = R2 = R and C1 = C2 = C.
Calculation of R2:

When Q2 is in saturation:

Let IB2 = 1.5  IB2(min) = 1.5  0.2 = 0.3 mA.

Since Q2 gets its base drive from VCC through R2

The designed circuit is as shown in Figure 4.60.

 Figure 4.60 Examples 4.24 and 4.25: designed circuit.

EXAMPLE 4.25 Silicon n-p-n transistors with hFE(min) = 40 are

available. Design an astable multivibrator to generate a square wave of 1
kHz frequency with a duty cycle of 25%.

Solution: The astable multivibrator to be designed is shown in Figure 4.60.

Since the amplitude of the square wave to be generated is not given let us
assume it to be 12 V. Let IC(sat) = 10 mA, and VCC = 12 V.

Let us assume that the transistors are driven equally into saturation when
they are conducting.
The design values are

RC = 1.17 k R1 = R2 = R = 18.8 k C1 = 0.0192 F, C2 = 0.057 F

The designed circuit is as shown in Figure 4.60.

EXAMPLE 4.26 Design a free running multivibrator to generate a square
wave of amplitude 10 V and frequency 1 kHz with 70% duty cycle.
Solution: Since the duty cycle is not 50%, the multivibrator is generating an
unsymmetrical square wave. The output waveform is shown in Figure 4.61.
The circuit to be designed is as shown in Figure 4.60.
 Figure 4.61 Example 4.26: output waveform.

Given amplitude of square wave V = 10 V. Therefore choose VCC = V =

10 volts.
Consider n-p-n transistors with hFE = 25, VBE(sat) = 0.7 V, VCE(sat) =
0.3 V, and IC (sat) = 5 mA
Let R1 = R2 = R (this ensures that the transistors are driven equally into
saturation when they are conducting).
 The design values are as follows:
RC = 1.94 k, R1 = R2 = R = 31 k, C1 = 32.58 nF, C2 = 13.96 nF
The designed circuit is shown in Figure 4.60.
EXAMPLE 4.27 A symmetrical collector-coupled astable multivibrator has
the following parameters: VCC = 10V, RC = 500 , R = 5 k and C = 50
pF. For the silicon transistors used hFE = 25 and rbb = 200 . Calculate
and plot to scale the waveforms at the base and collector of both transistors.
For silicon transistors VBE(sat) = 0.7 V, VCE(sat) = 0.3 V and Vg = 0.5 V.
Solution: The waveforms at the base and collector of Q1 and Q2 are as
shown in Figure 4.54. We have to calculate d.
Given VCC = 10 V, VBE (sat) = 0.7 V, VCE(sat) = 0.3V, hFE = 25, rbb
= 200 , RC1 = RC2 = RC = 500 , R1 = R2 = R = 5 k and C1 = C2 = C
= 50 pF.

These expressions have been derived in section 4.11.

Substituting the given values, we get
 Knowing d, the required waveforms are easily plotted as shown in Figure
4.54.
EXAMPLE 4.28 Draw a transistor astable multivibrator circuit which
generates output square wave with vertical edges.
VCC = 10 V, RC = 2 k, R1 = R2 = 20 k, R3 = 2 k. Calculate the
quasi-stable state currents in the circuit when Q1 is ON and Q2 is OFF.
Assume VCE(sat) = 0.3 V and VBE(sat) = 0.7 V, hFE (min) = 30.
Determine the output waveform time intervals and frequency if the timing
capacitors are equal to 0.01 F.
Solution: The circuit of a transistor astable multi which generates a square
wave with vertical edges is shown in Figure 4.62(a).
When Q1 is ON and Q2 is OFF in one of the two quasi-stable states, the
currents iC1 and iB1 are as indicated in Figures 4.62(b) and 4.62(c).

Figure 4.62 Example 4.28.

4.17 THE EMITTER-COUPLED ASTABLE
MULTIVIBRATOR
An emitter-coupled astable multivibrator may be obtained by using three
power supplies or a single power supply.
Figure 4.63 shows the circuit diagram of a free-running emitter coupled
multivibrator using n-p-n transistors. Figure 4.64 shows its waveforms.
Three power supplies are indicated for the sake of simplifying the analysis.
A more practical circuit using a single supply is indicated in Figure 4.65.
Let us assume that the circuit operates in such a manner that Q1 switches
between cut-off and saturation and Q2 switches between cut-off and its
active region.

Figure 4.63 The astable emitter-coupled multivibrator.

Calculations at t = t1–
–
Since Q1 is ON and Q2 is OFF just before the transition at t = t1 , we have

During the interval preceding t = t1, the capacitor C charges from a fixed
voltage VBB – Vs through the resistor RE2. All circuit voltages remain
constant except vEN2, which falls asymptotically towards zero. The
transistor Q2 will begin to conduct when vEN2 falls to
–
vEN2(t1 ) = vBN2 – Vs + VCE(sat) – Vg
+
Calculations at t = t1
When Q2 conducts, vEN2 and vEN1 rise. As vEN1 rises, Q1 comes out of
saturation and vCN1 (= vBN2) also increases, causing a further increase in
the current in Q2. Because of this regenerative action, Q1 is driven OFF and
Q2 is driven into its active region where its base-to-emitter voltage is
VBE2, its base current is IB2 and its collector current is IC2. From Figure
+
4.64, we see that after transition, at t = t1 .
+
vCN2(t1 ) = VCC2 – IC2RC2
+ +
vCN1(t1 ) = vBN1(t1 ) = VCC1 – IB2RC1
+ + +
vEN2(t1 ) = vBN2(t1 ) – vBE2(t1 ) = VCC1 – IB2RC1 –
vBE2
 Figure 4.64 Waveforms of the emitter-coupled astable multivibrator.

At t1 there is an abrupt change VD in vEN2.

 Because of the capacitive coupling between emitters there must also be
the same discontinuity VD in vEN1. Hence,

Neglecting junction voltages and IB2RC1 compared with VCC1

+ +
vEN1(t1 ) = vEN2(t1 ) = VCC1
The period
The interval T1 when Q2 conducts and Q1 is OFF ends at t = t2. The
transistor Q1 will turn ON when the base-to-emitter voltage reaches the cut-
in value Vg or when VEN1 reaches the voltage
–
vEN1(t2 ) = VBB – Vg

Since the base voltage of Q1 is fixed, then to carry the transistor from the
cut-in point to saturation the emitter must drop. However this drop d is
small, since d = Vs – Vg = 0.2 V.
Because the emitters are capacitively coupled there will be an identical
jump d in vEN2.
After t = t2, in the interval T2, conditions are the same as they were for t
< t1. Therefore, the cycle of events described above is repeated and the
circuit behaves as an astable multivibrator.
+
From Figure 4.64(a), we see that the voltage vEN1 starts at V1 at t = t1
–
and falls to VBB – Vg at t = t2 . Since this decay is exponential with a time
constant RE1C and approaches zero asymptotically,
Assuming that the supply voltages are large compared with the junction
voltages and assuming also that IB2RE1 << VCC1, we find

Subject to the same approximations, T2 is given by

If VCC1 and VBB are arranged to be proportional to one another, then the
frequency is independent of the supply voltages.
When Q1 is OFF, its collector-to-ground voltage is approximately VCC1
and equals the base-to-ground voltage of Q2. Since it is desired that Q2 be
in its active region, then VBN2 should be less than VCN2 or VCC1 <
VCC2. Since Q1 is to be driven into saturation, then its base voltage may be
almost as large as its collector supply voltage. However, to avoid driving
Q1 too deeply into saturation it is better to arrange that VBB < VCC1. A
circuit which uses a single supply and which satisfies the requirements that
VBB be proportional to VCC1 and that VBB < VCC1 < VCC2 is shown in
Figure 4.65. Since C is a bypass capacitor intended to maintain VBB
constant, it is not involved in the operation of the circuit. We assume that
R1 and R2 are small enough so that the voltage VBB at the junction of R1
and R2 remains normally constant during the entire cycle of operations of
the multivibrator. Using Thevenin’s theorem we see that the circuit of
Figure 4.65 is of the same form as that of Figure 4.63 with VCC2 = VCC
and with

Figure 4.65 The emitter-coupled multivibrator.

The advantages and disadvantages of the emitter-coupled astable

multivibrator over the collector-coupled astable multivibrator are given
below:
Advantages

1. It is inherently self-starting.
 2. The collector of Q2 where the output is taken may be loaded heavily
even capacitively.
3. The output is free of recovery transients.
4. Because it has an isolated input at the base of Q1, synchronization is
convenient.
5. Frequency adjustment is convenient because only one capacitor is
used.

Disadvantages

1. This circuit is more difficult to adjust for proper operating conditions.

2. This circuit cannot be operated with T1 and T2 widely different.
3. This circuit uses more components than does the collector-coupled
circuit.

SHORT QUESTIONS AND ANSWERS

1. What do you mean by a multivibrator? How many states does it have?
A. Multi means many. Vibrator means oscillator. A multivibrator is a
circuit which can operate at a number of frequencies. It has two states.
2. How many types of multivibrators are there? Name them.
A. There are three types of multivibrators. They are: (a) Bistable
multivibrator (b) Monostable multivibrator and (c) Astable
multivibrator.
3. What do you mean by a bistable circuit?
A. A bistable circuit means a circuit which has got two stable states.
4. Describe a bistable multivibrator.
A. A bistable multivibrator is a multivibrator with two stable states. It
can remain permanently in either one of its two stable states. It can be
induced to make a transition from one stable state to another by
application of a triggering signal. Symmetrical or unsymmetrical
triggering can be employed to induce transition. In this both the
coupling elements are resistors.
5. What are the other names of a bistable multivibrator?
 A. The other names of a bistable multivibrator are: Eccles–Jordan
circuit, multi, trigger circuit, scale-of-two toggle circuit, flip-flop and
binary.
6. What do you mean by dc coupling?
A. The dc coupling means resistive coupling.
7. What do you mean by ac coupling?
A. The ac coupling means capacitive coupling.
8. What are the applications of a bistable multivibrator?
A. The applications of a bistable multivibrator are as follows. It is the
basic memory element. It is used to perform many digital operations
such as counting and storing of binary information. It is also used in
the generation and processing of pulse type waveforms.
9. What do you mean by stable state of a binary?
A. A stable state of a binary means the state in which the circuit can
remain permanently. A stable state of a binary is one in which the
currents and voltages satisfy Kirchhoff’s laws and are consistent with
the device characteristics and in which, in addition, the condition of
loop gain being less than unity is satisfied.
10. What do you mean by a quasi-stable state?
A. A quasi-stable state means a temporarily stable state. The circuit
remains in the quasi-stable state only for a specified time and
afterwards it comes back to the other state.
11. What do you mean by the term ‘loop gain’?
A. The loop gain is the gain associated with the path making that loop
when a signal is transmitted through it.
12. When is the loop gain less than one and when is the loop gain greater
than one for a bistable multivibrator?
A. For a bistable multivibrator, the loop gain is greater than one during
transition between the states and loop gain is less than one in the stable
state.
13. What do you mean by output swing?
A. The output swing means the change in collector voltage resulting
from a transition from one state to the other.
14. What is the basis for selection of various components of a bistable
multivibrator?
A. In a bistable multivibrator
(a) VCC is selected such that VCC < BVCEO
(b) RC is selected such that Ic(sat) is less than the maximum permitted
collector current.
(c) R1 is selected such that it is very large but R1 < hFE RC.
(d) VBB, R1, and R2 are selected such that, in one stable state the base
current is large enough to drive the transistor into saturation whereas
in the second stable state the emitter junction must be below cut-off.
15. What do you mean by loading of a binary? What are its effects on the
performance of a binary?
A. Connecting external circuits at the collectors of the binary and
drawing currents from them is called loading the binary. The effect of
loading is that the output voltage swing gets reduced and if the loading
is heavy, the transistor may not be driven into saturation and the binary
malfunctions.
16. How can you obtain a constant output swing in a binary?
A. A constant output swing can be obtained in a binary by clamping
the collector to an auxiliary voltage V < VCC through the collector
catching diodes D1 and D2.
17. What do you mean by collector catching diodes?
A. The diodes which connect the collectors of the transistors of the
binary to an auxiliary voltage source V < VCC to maintain a constant
output swing are called collector catching diodes.
18. What is the advantage of a self-biased binary over fixed-biased
binary?
A. The advantage of self-biased binary over fixed-biased binary is only
one power supply is sufficient.
19. What are commutating capacitors? Why are they required?
A. Commutating capacitors are small capacitors connected in parallel
with the coupling resistors. They are required to increase the speed of
operation.
20. What are the other names of commutating capacitors?
A. The other names of commutating capacitors are: speed-up
capacitors and transpose capacitors.
21. What do you mean by transition time? How can it be reduced?
A. The time taken for the transfer of conduction from one device to
another is called transition time. Transition time can be reduced by
connecting small capacitors in parallel with the coupling resistors.
22. Why transition time occurs?
A. Transition time occurs because, even though the input signal at the
base of a transistor may be transferred to the collector with zero rise
time, the signal at the collector of the transistor cannot be transferred to
the base of the other transistor instantaneously as the input capacitance
Ci present at the base of the transistor makes the R1 – R2 attenuator act
as an uncompensated attenuator and so it will have a finite rise time tr.
23. Write the expression for the maximum frequency of operation fmax of
a fixed-bias binary with a commutating capacitor C1.

24. What do you mean by (a) resolving time, (b) settling time, and (c)
resolution time?
A. (a) Resolving time means the smallest allowable interval between
triggers.
(b) Settling time means the additional time required for the purpose
of recharging commutating capacitors after the transfer of
conduction from one device to another.
(c) Resolution time means the sum of the transition time and the
settling time.
25. What are the methods of improving the resolution of a binary?
A. The methods of improving the resolution of a binary are: (a)
reducing all stray capacitances, (b) Reducing the resistors R1, R2 and
RC, (c) not allowing the transistors to go into saturation.
26. What is a non-saturated binary? What are its advantages and
disadvantages compared to saturated binary?
A. A bistable multivibrator in which the transistors always operate in
the active region only (the transistors are not allowed to go into
saturation) is called a non-saturated binary. The advantage of non-
saturated binary is high speed of operation. The draw backs are as
follows:
(a) It is more complicated than saturated binary.
(b) It consumes more power than saturated binary.
(c) Its voltage swing is less stable with temperature, ageing and
component replacement than in the case of saturated binary.
27. What do you mean by triggering?
A. Triggering is the process of applying an external signal to induce a
transition from one state to the other.
28. How many methods of triggering are there? Name them. Distinguish
between them.
A. Basically there are two types of triggering: (a) unsymmetrical
triggering and (b) symmetrical triggering.
In unsymmetrical triggering, the triggering signal is effective in
inducing a transition in only one direction. A second triggering signal
from a separate source must be introduced in a different manner to
achieve reverse transition whereas in symmetrical triggering each
successive triggering signal induces a transition regardless of the state
in which the binary happens to be, i.e. unsymmetrical triggering
requires two separate sources, whereas symmetrical triggering requires
only one source.
29. Which signals are commonly used for triggering?
A. The signals which are commonly used for triggering are either a
pulse of short duration or a step voltage.
30. What do you mean by unsymmetrical triggering? Where is it used?
A. Unsymmetrical triggering is one in which the triggering signal is
effective in inducing a transition in only one direction. In this, a second
triggering signal from a separate source must be introduced in a
different manner to achieve reverse transition. Unsymmetrical
 triggering finds extensive applications in logic circuitry (in registers,
coding, etc.). It is also used to trigger a monostable multivibrator.
31. What do you mean by symmetrical triggering? Where is it used?
A. Symmetrical triggering is one in which each successive triggering
signal induces a transition regardless of the state in which the binary
happens to be, i.e. symmetrical triggering requires only one source.
Symmetrical triggering is used in binary counting circuits and other
applications.
32. What is the best method of triggering a binary unsymmetrically?
A. The best method of triggering a binary unsymmetrically on the
leading edge of a pulse is to apply the pulse from a high impedance
source to the output of the non conducting device.
33. What are the advantages and disadvantages of a direct-connected
binary?
A. The advantages of direct-connected binary are as follows:
(a) Its extreme simplicity
(b) Only one power supply voltage of low value of about 1.5 V is
required.
(c) Low power dissipation
(d) Transistors with low breakdown voltages may be easily constructed
as an IC because of the few elements involved.
The disadvantages of direct-connected binary are as follows:
(a) The voltage swing is only a fraction of a volt and hence the binary
is susceptible to spurious voltages.
(b) The output voltages are equal to their saturation base and collector
voltages and these parameters may vary appreciably from transistor
to transistor.
(c) Since Q2 is driven heavily into saturation, the storage time delay
will be large and the switching speed will be low.
(d) As temperature increases, ICBO may increase sufficiently to bring
Q1 into active region and may even take Q2 out of saturation.
(e) Triggering is difficult.
34. What is a Schmitt trigger?
 A. A Schmitt trigger is an emitter-coupled binary.
35. What are the applications of a Schmitt trigger?
A. A Schmitt trigger is mainly used as an amplitude comparator and as
a squaring circuit.
36. How does a Schmitt trigger differ from the basic collector-coupled
binary?
A. The Schmitt trigger differs from the basic collector-coupled binary
in that the coupling from the output of the second stage to the input of
the first stage is missing and the feedback is obtained now through a
common emitter resistance RE.
37. Explain how a Schmitt trigger converts a sine wave into a square
wave.
A. If a sine wave of amplitude larger than the UTP is fed to a Schmitt
trigger, whenever the input rises to V1, the output jumps to V1 and
remains at its upper level V1 till the input falls to V2. The output
remains at its lower level V2 till the input rises to V1. So a square wave
is obtained.
38. Define the terms: upper triggering point (UTP) and lower triggering
point (LTP).
A. (a) The upper triggering point UTP is defined as the input voltage at
which the transistor Q1 just enters into conduction.
(b) The lower triggering point LTP is defined as the input voltage at
which the transistor Q2 just resumes conduction.
39. Write an expression for UTP (V1).
A. UTP (V1) = V – VBE2 + Vg1 = V – 0.1, where V = VCC
R2/(R2 + RC + R1)
40. Write the expression for LTP (V2).

41. When does a Schmitt trigger exhibit hysteresis?

 A. A Schmitt trigger exhibits hysteresis when loop gain is greater than
one.
42. How can hysteresis be eliminated in a Schmitt trigger?
A. Hysteresis can be eliminated in a Schmitt trigger by adjusting the
loop gain of the circuit to unity. The loop gain can be varied by
adjusting RC1, or RE1 or RE2, or R1/(R1 + R2), or Rs.
43. How can you vary UTP and LTP of a Schmitt trigger?
A. UTP of a Schmitt trigger can be varied by varying RE2 or R1/(R1 +
R2).
LTP of a Schmitt trigger can be varied by varying Rs, RC1, RE1, or
R1/(R1 + R2).
44. Describe a monostable multivibrator.
A. A monostable multivibrator is a multivibrator with one stable state
and one quasi-stable state. Under quiescent conditions, it remains in its
stable state only. When a triggering signal is applied, it goes from the
stable state to the quasi-stable state, remains in the quasi-stable state
for a predetermined short interval of time and then comes back to the
stable state automatically. So a triggering signal is required to induce
transition from the stable state to the quasi-stable state but no
triggering signal is required to induce transition from the quasi-stable
state to the stable-state. Only unsymmetrical triggering can be
employed. In this one coupling element is a resistor and the other one
is a capacitor.
45. What are the other names of a monostable multivibrator?
A. The other names of a monostable multivibrator are: one shot, a
single step circuit, univibrator, gating circuit, and delay circuit.
46. Why is monostable multivibrator also called a delay circuit?
A. Since the monostable multivibrator generates a fast transition at
predetermined time T after the input trigger, it is called a delay circuit.
47. Why is monostable multivibrator also called a gating circuit?
A. Since the monostable multivibrator generates a rectangular
waveform which can be used to gate other circuits, it is also called a
gating circuit.
48. What are the applications of a monostable multivibrator?
A. The main applications of a monostable multivibrator are as follows:
(a) As a gating circuit
(b) As a delay circuit
49. What is the expression for the gate width of a monostable
multivibrator with and without considering the reverse saturation
current?
A. The expression for the gate width of a monostable multivibrator is
as follows:

50. What type of triggering is used in a monostable multivibrator?

A. Unsymmetrical triggering is used in monostable multivibrator.
51. Describe an astable multivibrator.
A. An astable multivibrator is a multivibrator with two quasi-stable
states. It does not have any stable state. It does not require any
triggering. The moment it is connected to the power supply, it keeps on
oscillating between its two quasi-stable states and generates a square
wave. It is used as a master oscillator. In this both the coupling
elements are capacitors.
52. Write the expression for the period of oscillation of an astable
multivibrator when it is used as a (a) square wave generator and (b)
voltage to frequency converter.
A. The expression for the period of oscillation of an astable
multivibrator when used as a
(a) Square generator is T = 1.386 RC
(b) Voltage to frequency converter is T = RC ln [1 + (VCC/V)].
53. What do you mean by blocked condition in an astabe multivibrator?
A. Blocked condition in an astable multivibrator means the astable
multivibrator gets blocked and does not start at all when both of its
transistors go into saturation simultaneously.
54. When is the blocked condition likely to occur in an astable
multivibrator?
A. The blocked condition is likely to occur in an astable multivibrator
if the supply voltage is increased slowly from zero to full value VCC,
but the blocked condition does not occur if the voltage is applied
suddenly.

REVIEW QUESTIONS
1. With the help of a neat circuit diagram, explain the working of a fixed-
bias binary.
2. Write notes on commutating capacitors.
3. With the help of a neat diagram explain the working of a non-saturated
binary. What are its drawbacks?
4. What are the advantages and drawbacks of direct connected binary?
5. With the help of neat diagrams discuss the different methods of
triggering a binary.
6. What is a Schmitt trigger? With the help of a neat circuit diagram and
waveforms, explain the working of a Schmitt trigger.
7. Derive expressions for the UTP and LTP of a Schmitt trigger.
8. Explain how hysteresis can be eliminated in a Schmitt trigger.
9. With the help of a neat circuit diagram and waveforms, explain the
working of a collector-coupled monostable multivibrator.
10. Derive an expression for the gate width of a monostable multivibrator.
11. Derive an expression for the gate width of a monostable multivibrator
considering the effect of reverse saturation current.
12. With the help of a neat circuit diagram, explain the working of an
emitter-coupled monostable multivibrator.
13. With the help of a neat circuit diagram and waveforms, explain the
working of an astable multivibrator.
14. Derive an expression for the frequency of oscillation of an astable
multivibrator.
15. Show that an astable multivibrator can be used as a voltage-to-
frequency converter.
16. Draw the circuit of the gated astable multivibrator and explain how it
works.
17. Draw the circuit of the astable multivibrator with vertical edges.
18. Draw the circuit of the astable multivibrator which does not block.

FILL IN THE BLANKS

1. A circuit which can oscillate at a number of frequencies is called a
_________.
2. Basically there are ________ types of multivibrators. They are
_________, _________, _________.
3. Resistive coupling is called _________ coupling and capacitive
coupling is called ______ coupling.
4. A _______ multivibrator is the basic memory element.
5. In bistable multivibrators, the coupling elements are _________.
6. In monostable multivibrator the coupling elements are _______.
7. In astable multivibraror, the coupling elements are _________.
8. A ___________ circuit is one which can exist indefinitely in either of
its two stable states and which can be induced to make an abrupt
transition from one state to the other.
9. A bistable multivibrator is also called ___________, ___________,
___________, ___________, or ___________.
10. A ___________ multivibrator is used to perform many digital
operations such as counting and storing of binary information. It is also
used in the generation and processing of pulse type waveforms.
11. A ___________ of a binary is one in which the currents and voltages
satisfy Kirchhoff’s laws and are consistent with the device
characteristics and in which, in addition, the condition of loop gain
being less than unity is satisfied.
12. A ___________ state of a binary is one in which the device can remain
permanently.
13. Loop gain will be ___________ if either of the two devices is below
cut-off or if either device is in saturation.
14. In the stable state, the loop gain is ___________.
15. During transition, the loop gain is ___________.
16. The change in collector voltage resulting from a transition from one
state to the other is called ___________ and is given by ___________.
17. ___________ reduces the output swing.
18. The flip-flop circuit components must be chosen so that under the
maximum load which the binary drives, one transistor remains in
___________ while the other is ___________.
19. A constant output swing and a constant base saturation current can be
obtained by clamping the collectors to an auxiliary voltage V
___________ VCC through the diodes D1 and D2.
20. The diodes used in a bistable multivibrator to maintain a constant
output swing are called ___________ diodes.
21. The interval during which conduction transfers from one transistor to
another is called the ___________.
22. The transition time may be reduced by shunting the coupling resistors
with ___________ called the ___________.
23. Commutating capacitors, also called ___________ or ___________
capacitors are used to increase the speed of operation.
24. The smallest allowable interval between triggers is called the
___________ of the flip-flop.
25. The reciprocal of the resolving time of the flip-flop is the
___________ at which the binary will respond.
26. The additional time required for the purpose of completing the
recharging of capacitors after the transfer of conduction is called the
___________.
27. The sum of the transition time and the settling time is called the
___________.
28. If the commutating capacitors are too small, the ___________ time is
increased and if they are too large the ___________ time is increased.
29. The resolution time of a binary can be improved by (a) _______, (b)
_______, (c) _______.
30. The disadvantages of non-saturated binary are (a) _______, (b)
_______, (c) _______.
31. The application of an external signal to induce a transition from one
state to the other is called ___________.
32. The triggering signal which is usually employed is either a _________
or a ________.
33. If the triggering signal is effective in inducing the transition in only
one direction, the triggering is called ___________.
34. If each successive triggering signal induces the transition regardless of
the state in which the binary happens to be, the triggering is called
___________.
35. ___________ triggering is used when the binary is to be used as a
generator of a gate whose width equals the interval between triggers.
36. ___________ triggering is used in binary counting circuits.
37. An excellent method for triggering a binary ___________ on the
leading edge of a pulse is to apply the pulse from a high impedance
source at the output of the non-conducting device.
38. The ___________ is called an emitter-coupled binary.
39. A Schmitt trigger exhibits hysteresis when loop gain is ___________.
40. ___________ is said to exist if to effect a transition in one direction,
we must first pass beyond the voltage at which the reverse transition
takes place.
41. Hysteresis in a Schmitt trigger may be eliminated by adjusting the loop
gain to ___________.
42. The ___________ is used as an amplitude comparator and as a
squaring circuit.
43. For a Schmitt trigger, _________ is defined as the input voltage at
which Q1 starts conducting.
44. For a Schmitt trigger, ___________ is defined as the input voltage at
which Q2 resumes conduction.
45. A Schmitt trigger can be used to convert a ________ wave into a
_________ wave.
46. Any slowly varying input waveform can be converted into a square
wave by using a ______.
47. A Schmitt trigger is also a __________ multivibrator.
48. A circuit which has got one permanent stable state and one quasi-
stable state is called a ___________.
49. Quasi-stable state means a ___________ stable state.
50. The monostable multivibrator is also called ___________,
___________, ___________, ___________, or ___________,
_____________.
51. Since a monostable multivibrator generates a rectangular waveform
and hence can be used to gate other circuits, it is also called a
___________.
52. Since the monostable multivibrator generates a fast transition at a
predetermined time T after the input trigger, it is also called a
___________.
53. A ___________ multivibrator is used as a delay circuit and as a gating
circuit.
54. ___________ triggering is used in monostable multivibrators.
55. The ___________ multivibrator has two quasi-stable states. It is a free
running circuit.
56. The ___________ multivibrator is used as a master oscillator.
57. The astable multivibrator can be used as a ___________ by connecting
R1 and R2 to an auxiliary supply voltage and varying that voltage.
58. The astable multivibrator is called a ___________ multivibrator. It is
also called a _________ generator.
59. The astable multivibrator is used as a ___________.
60. An ___________ multivibrator can be used as a voltage-to-frequency
convertor.
61. An astable multivibrator is used as a ________ generator.
62. An astable multivibrator can be used as a _________ to ________
convertor.

OBJECTIVE TYPE QUESTIONS

1. Basically how many types of multivibrators are there?
(a) 3
(b) 4
(c) 6
(d) 7
2. _________ are basically regenerative circuits comprising of two cross
coupled active devices.
 (a) Multivibrators
(b) Clippers
(c) Clampers
(d) Oscillators
3. In the stable state, the loop gain is
(a) < 1
(b) = 1
(c) > 1
(d) = 0
4. During transition, the loop gain is
(a) < 1
(b) = 1
(c) > 1
(d) = 
5. Which multivibrator is called a flip-flop?
(a) Bistable
(b) Monostable
(c) Astable
(d) None of these
6. Which multivibrator is used as a memory element?
(a) Bistable
(b) Monostable
(c) Astable
(d) None of these
7. A ________ multivibrator is used for digital operations like counting
and storing of binary information.
(a) monostable
(b) astable
(c) bistable
(d) Schmitt trigger
8. In bistable multivibrators, the coupling elements are
(a) Both capacitors
(b) Both resistors
(c) One capacitor and one resistor
(d) None of these
 9. The condition for a transistor to be indeed in saturation is
(a) IB < IB(min)
(b) IB = IB(min)
(c) IB > IB(min)
(d) none of these
10. IB(min) =
(a) hfe (min)/IC
(b) IC/hfe(min)
(c) hfe (min) IC
(d) none of these
11. Speed up capacitors are also called
(a) variable capacitors
(b) fixed capacitors
(c) transpose capacitors
(d) transfer capacitors
12. The main feature of commutating capacitors is to reduce the
(a) transition time
(b) speed
(c) total time
(d) none of these
13. The capacitors which assist the binary in making abrupt transitions
between states are called
(a) assisting capacitors
(b) variable capacitors
(c) commutating capacitors
(d) fixed capacitors
14. The interval during which conduction transfers from one device to
another is called
(a) resolving time
(b) transition time
(c) transfer time
(d) change over time
15. The time required for the recharging of capacitors after the transfer of
conduction is called the
 (a) settling time
(b) recharge time
(c) charge time
(d) none of these
16. Large commutating capacitors
(a) reduce transition time but increase settling time
(b) increase transition time but reduce settling time
(c) increase both transition and settling times
(d) reduce both transition and settling times
17. Small commutating capacitors
(a) reduce transition time but increase settling time
(b) increase transition time but reduce settling time
(c) increase both transition and settling times
(d) reduce both transition and settling times
18. The smallest allowable interval between triggers is called
(a) resolving time
(b) transition time
(c) trigger time
(d) none of these
19. The reciprocal of the resolving time is the _________ at which the
binary will respond.
(a) maximum frequency
(b) minimum frequency
(c) operating frequency
(d) none of these
20. __________ triggering is used in binary counting circuits.
(a) Unsymmetrical
(b) Symmetrical
(c) Asymmetrical
(d) Random
21. Usually the range of commutating capacitors is
(a) 5 to 10 pF
(b) 1 to 2 pF
(c) 50 to 75 pF
(d) none of these
22. For hysteresis to exist in a Schmitt trigger, the loop gain must be
(a) < 1
(b) > 1
(c) = 1
(d) = 0
23. For elimination of hysteresis in a Schmitt trigger, the loop gain must be
(a) < 1
(b) > 1
(c) = 1
(d) = 
24. A Schmitt trigger has UTP (V1) = 8 V and LTP (V2) = 4 V. The
hysteresis range VH is
(a) 4 V
(b) 2 V
(c) 32 V
(d) 12 V
25. A Schmitt trigger has VCC = 20 V, R2 = 25 k, R1 = 20 k, RC1 = 5
k. Its UTP 
(a) 10.1 V
(b) 9.9 V
(c) 15.2 V
(d) none of these
26. A Schmitt trigger is
(a) a collector-coupled binary
(b) an emitter-coupled binary
(c) not a bistable multivibrator
(d) one type of monostable circuit
27. Which multivibrator is used as an amplitude comparator?
(a) Bistable
(b) Monostable
(c) Astable
(d) Schmitt trigger
28. Schmitt trigger can be used to convert a sine wave into a
(a) pulse
(b) square wave
 (c) triangular wave
(d) none of these
29. In monostable multivibrators, the coupling elements are
(a) both resistors
(b) both capacitors
(c) one capacitor and one resistor
(d) short circuits
30. Monostable multivibrator generates a
(a) pulse waveform
(b) triangular waveform
(c) square wave
(d) none of these
31. The pulse width of a monostable multivibrator is given by
(a) 0.693 RC
(b) 1.386 RC
(c) 2 RC
(d) 5 RC
32. In a monostable multivibrator, as temperature increases delay time
(a) decreases
(b) increases
(c) remains constant
(d) none of these
33. In a monostable multivibrator, R = 20 k, C = 0.1 F. The gate width
T will be equal to
(a) 2 m s
(b) 0.693 m s
(c) 1.386 m s
(d) none of these
34. Which multivibrator can be used as a gating circuit?
(a) Bistable
(b) Monostable
(c) Astable
(d) Schmitt trigger
35. In astable multivibrators the coupling elements are
(a) both resistors
(b) both capacitors
 (c) one capacitor and one resistor
(d) short circuits
36. Which multivibrator is called a free-running circuit?
(a) Bistable
(b) Monostable
(c) Astable
(d) Schmitt trigger
37. Which multivibrator is used as a master oscillator?
(a) Bistable
(b) Monostable
(c) Astable
(d) Schmitt trigger
38. Which multivibrator can be used as a voltage-to-frequency converter?
(a) Bistable
(b) Monostable
(c) Astable
(d) Schmitt trigger
39. The astable multivibrator requires
(a) symmetrical triggering
(b) unsymmetrical triggering
(c) no triggering
(d) any triggering is OK
40. The frequency of oscillation of an astable multivibrator with R = 10
k and C = 0.1 F is
(a) 721.5 Hz
(b) 825.5 Hz
(c) 1 KHz
(d) none of these
41. An astable multivibrator has R1 = 1 k, C1 = 0.1 F, R2 = 2 k, C2 =
0.2 F. The duty cycle of the output waveform is
(a) 0.2
(b) 0.8
(c) 0.6
(d) none of these
42. For a voltage-to-frequency converter to generate oscillations of
frequency half of that when V = VCC, the ratio of VCC/V must be
(a) 3
(b) 0.333
(c) 4
(d) not possible
43. The change in collector voltage resulting from a transition from one
state to the other is called
(a) output voltage swing
(b) input voltage swing
(c) transition swing
(d) change in swing
44. Blocked condition may occur in
(a) a bistable multivibrator
(b) a monostable multivibrator
(c) an astable multivibrator
(d) a Schmitt trigger
45. The __________ circuit has two quasi-stable states.
(a) bistable
(b) monostable
(c) astable
(d) none of these
46. The _________ multivibrator does not require external triggering
signal
(a) bistable
(b) monostable
(c) astable
(d) none of these
47. An emitter-coupled multi constitutes an excellent
(a) voltage-to-time converter
(b) time-to-frequency converter
(c) voltage-to-frequency converter
(d) frequency-to-voltage converter
48. The time period of an astable multi is
(a) 0.693 R1C1
 (b) 0.693 R2C2
(c) 0.693 (R1C1 + R2C2)
(d) 1.386 RC
49. The time period of an astable multi when used as a voltage-to-
frequency converter is

50. Typically VBE(cut-off) for Ge =

(a) –0.1 V
(b) 0.2 V
(c) 0.3 V
(d) none of these

PROBLEMS
4.1 The fixed-bias binary of Figure 4.1 uses n-p-n silicon transistors with
hFE = 25. The circuit parameters are VCC = 10 V, VBB = 2 V, RC = 1
k, R1 = 5 k and R2 = 10 k, VCE(sat) = 0.3 V, and VBE(sat) = 0.7
V. (a) Verify that one transistor is in cut-off and the other in saturation
and find the stable state currents and voltages. (b) What is the
maximum value of ICBO tolerated before the condition is reached
where neither transistor is cut-off? (c) What is the maximum load that
the binary can drive and still have one transistor in saturation and the
other in cut-off?
4.2 The fixed-bias binary of Figure 4.1 uses p-n-p silicon transistors with
the worst-case values of VCE(sat) = – 0.5 V, VBE(sat) = – 1 V, ICBO =
–10 nA at 25°C and zero base- to-emitter voltage at cut-off. The circuit
parameters are VCC = –10 V, VBB = 5 V, RC = 1 k, R1 = 5 k, R2 =
20 k. (a) Find the stable state currents and voltages and hFE(min). (b)
If the reverse saturation current doubles for every 10°C rise in
 temperature, what is the maximum temperature at which one transistor
will remain OFF?
4.3 Germanium transistors with hFE(min) = 25 are used in the fixed-bias
flip-flop with collector catching diodes (Figure 4.7). The circuit
parameters are VCC = 15 V, VBB = 5 V, V = 6 V, RC = 1 k, R1 = 4
k, R2 = 20 k. Neglect the voltage drop across a forward-biased
junction. (a) Verify that if one transistor is in cut-off, the other is in
saturation. Find the stable-state voltages and currents, including the
currents in the two diodes. (b) What is the maximum load that the
binary can drive (the minimum R from collector to ground) and still
maintain the output swing in part (a). (c) If ICBO = 5 A at 20°C and
doubles every 10°C rise in temperature, what is the maximum
temperature at which one transistor will remain in cut-off state?
4.4 Silicon transistors with hFE(min) = 30 are available. If VCC = 12 V
and VBB = 6 V, design a fixed-bias bistable multivibrator.
4.5 Design a fixed-bias bistable multivibrator to provide an output with a
swing of 10 V.
4.6 The self-biased binary of Figure 4.8 uses n-p-n silicon transistors
having the worst- case (maximum) values of VCE(sat) = 0.4 V and
VBE (sat) = 0.8 V and zero base-to-emitter voltage for cut-off. The
circuit parameters are VCC = 18 V, RC = 1 k, R1 = 6 k, R2 = 15 k
and RE = 500 . (a) Find the stable-state voltages and currents, and the
minimum value of hFE required to give the values in part (a). (b) As
the temperature is increased, what is the maximum value to which
ICBO can increase before the condition is reached where neither
transistor is OFF.
4.7 The self-biased flip-flop uses p-n-p germanium transistors with
VCE(sat) = – 0.2 V, VBE(sat) = – 0.6 V and hFE(min) = 20, VCC = –
10 V, RC = 1 k, R1 = 5 k, R2 = 10 k and RE = 500 . (a) Find the
stable state voltages and currents, and the maximum load that the
binary can drive and still have one transistor in saturation while the
 other is below cut-off. (b) Determine the maximum value of ICBO
required to reach the condition that neither device is OFF.
4.8 Junction transistors of n-p-n type with hFE(min) = 30 and a battery
supply of 10 V are available. Calculate the component values required
to realize a collector-coupled bistable multivibrator.
4.9 A self-biased bistable multivibrator uses silicon transistors with
hFE(min) = 25. The junction voltages and ICBO may be neglected.
Take VCC = 20 V, R1 = R2, IC(sat) = 10 mA. If VBE of the OFF
transistor is equal to –1 V and the base current of the ON transistor is
twice the minimum base current, calculate the component values RE,
RC, R1, and R2.
4.10 Consider the Schmitt trigger of Figure 4.29 with germanium
transistors having hFE = 20. The circuit parameters are VCC = 15 V,
RS = 2 k, RC1 = 4 k, RC2 = 1 k, R1 = 3 k, R2 = 10 k, and RE
= 6 k. (a) Calculate V1 and V2. (b) For an input sine wave of 12 sin
wt, find the angles at which the circuit flips.
4.11 Consider the emitter-coupled binary of Figure 4.29 with silicon
transistors having hFE = 40. The circuit parameters are VCC = 20 V,
RS = 2 k, RC1 = 6 k, RC2 = 2 k, R1 = 10 k, R2 = 40 k, and
RE = 8 k. (a) Find V1 and V2. (b) For an input sine wave of 20 sin wt,
find the angles at which the circuit flips.
4.12 Design a Schmitt trigger circuit using silicon transistors with
hfe(min) = 40, VCC = 15 V, UTP = 10 V and LTP = 6 V.
4.13 Design a Schmitt trigger circuit using n-p-n silicon transistors with
hfe(min) = 20, Vg = 0.5 V and IC(sat) = 4 mA for UTP = 12 V, LTP = 8
V, VCC = 18 V.
4.14 A collector-coupled monostable multivibrator using n-p-n silicon
transistors has the following parameters. VCC = 12 V, VBB = 4 V, RC
= 1 k, R1 = R2 = R = 15 k, hFE = 35, rBB = 220  and C = 1000
pF. Neglect ICBO. (a) Show that in the stable state one transistor is ON
and the other is OFF. (b) Calculate and plot to scale the wave shapes at
each base and collector. (c) Find the width of the output pulse.
4.15 Design a collector-coupled one-shot using n-p-n transistors. Neglect
ICBO and the junction voltages. Assume hFE(min) = 20, VBE = –1 V
for the transistor in cut-off and IB = 1.5IB(min) for the transistor in
saturation, VCC = 8 V, IC(sat) = 2 mA, T = 2 ms, and R1 = R2. Find
RC, R, VBB, R1, and C.
4.16 Design a one-shot circuit to produce a pulse with a gate width of 5
ms. Assume the required data.
4.17 Design a collector-coupled astable multivibrator to generate a square
wave of 2.5 kHz.
4.18 Design an astable multivibrator to generate a square wave of 2 kHz
frequency with a duty cycle of 35%.
 Chapter 5
Time-Base Generators

A time-base generator is an electronic circuit which generates an output

voltage or current waveform, a portion of which varies linearly with time.
Ideally the output waveform should be a ramp. Time-base generators may
be voltage time-base generators or current time-base generators. A voltage
time-base generator is one that provides an output voltage waveform, a
portion of which exhibits a linear variation with respect to time. A current
time-base generator is one that provides an output current waveform, a
portion of which exhibits a linear variation with respect to time. There are
many important applications of time-base generators, such as in CROs,
television and radar displays, in precise time measurements, and in time
modulation. The most important application of a time-base generator is in
CROs. To display the variation with respect to time of an arbitrary
waveform on the screen of an oscilloscope it is required to apply to one set
of deflecting plates a voltage which varies linearly with time. Since this
waveform is used to sweep the electron beam horizontally across the screen
it is called the sweep voltage and the time-base generators are called the
sweep circuits.

5.1 GENERAL FEATURES OF A TIME-BASE

SIGNAL
Figure 5.1(a) shows the typical waveform of a time-base voltage. As seen
the voltage starting from some initial value increases linearly with time to a
maximum value after which it returns again to its initial value. The time
during which the output increases is called the sweep time and the time
taken by the signal to return to its initial value is called the restoration time,
the return time, or the flyback time. In most cases the shape of the
waveform during restoration time and the restoration time itself are not of
much consequence. However, in some cases a restoration time which is
very small compared with the sweep time is required. If the restoration time
is almost zero and the next linear voltage is initiated the moment the present
one is terminated then a saw-tooth waveform shown in Figure 5.1(b) is
generated. The waveforms of the type shown in Figures 5.1(a) and (b) are
generally called sweep waveforms even when they are used in applications
not involving the deflection of an electron beam.
In fact, precisely linear sweep signals are difficult to generate by time-
base generators and moreover nominally linear sweep signals may be
distorted when transmitted through a coupling network.

Figure 5.1 (a) General sweep voltage and (b) saw-tooth voltage waveforms.
 The deviation from linearity is expressed in three most important ways:

1. The slope or sweep speed error, es

2. The displacement error, ed
3. The transmission error, et

The slope or sweep-speed error, es

An important requirement of a sweep is that it must increase linearly with

time, i.e. the rate of change of sweep voltage with time be constant. This
deviation from linearity is defined as

The displacement error, ed

Another important criterion of linearity is the maximum difference between

the actual sweep voltage and the linear sweep which passes through the
beginning and end points of the actual sweep. The displacement error ed is
defined as
As shown in Figure 5.2(a), vs is the actual sweep and vs is the linear
sweep.
The transmission error, et

When a ramp signal is transmitted through a high-pass circuit, the output

falls away from the input as shown in Figure 5.2(b). This deviation is
expressed as transmission error et, defined as the difference between the
input and the output divided by the input at the end of the sweep.

where as shown in Figure 5.2(b), Vs is the input and Vs is the output at the
end of the sweep, i.e. at t = Ts.

Figure 5.2 (a) Sweep for displacement error and (b) sweep for transmission error.

If the deviation from linearity is small so that the sweep voltage may be
approximated by the sum of linear and quadratic terms in t, then the above
three errors are related as
which implies that the sweep speed error is the more dominant one and the
displacement error is the least severe one.

5.2 METHODS OF GENERATING A TIME-

BASE WAVEFORM
In time-base circuits, sweep linearity is achieved by one of the following
methods.

1. Exponential charging. In this method a capacitor is charged from a

supply voltage through a resistor to a voltage which is small compared
with the supply voltage.
2. Constant current charging. In this method a capacitor is charged
linearly from a constant current source. Since the charging current is
constant the voltage across the capacitor increases linearly.
3. The Miller circuit. In this method an operational integrator is used to
convert an input step voltage into a ramp waveform.
4. The Phantastron circuit. In this method a pulse input is converted into
a ramp. This is a version of the Miller circuit.
5. The bootstrap circuit. In this method a capacitor is charged linearly by
a constant current which is obtained by maintaining a constant voltage
across a fixed resistor in series with the capacitor.
6. Compensating networks. In this method a compensating circuit is
introduced to improve the linearity of the basic Miller and bootstrap
time-base generators.
7. An inductor circuit. In this method an RLC series circuit is used. Since
an inductor does not allow the current passing through it to change
instantaneously, the current through the capacitor more or less remains
constant and hence a more linear sweep is obtained.
5.3 EXPONENTIAL SWEEP CIRCUIT
Figure 5.3(a) shows an exponential sweep circuit. The switch S is normally
closed and is open at t = 0. So for t > 0, the capacitor charges towards the
supply voltage V with a time constant RC. The voltage across the capacitor
at any instant of time is given by
–t/RC
vo(t) = V(1 – e )

After an interval of time Ts when the sweep amplitude attains the value Vs,
the switch again closes. The resultant sweep waveform is shown in Figure
5.3(b).

Figure 5.3 (a) Charging a capacitor through a resistor from a fixed voltage and
(b) the resultant exponential waveform across the capacitor.

The relation between the three measures of linearity, namely the slope or
sweep speed error es, the displacement error ed, and the transmission error
et for an exponential sweep circuit is derived below.
Slope or sweep speed error, es

We know that for an exponential sweep circuit of Figure 5.3(a),

 –t/RC
vo(t) = V(1 – e )

 Rate of change of output or slope is

For small Ts, neglecting the second and higher order terms

Neglecting the second and higher order terms

So the smaller the sweep amplitude compared to the sweep voltage, the
smaller will be the slope error.
The transmission error, et
From Figure 5.2(b),

The displacement error, ed

From Figure 5.2(a), we can see that the maximum displacement between
the actual sweep and the linear sweep which passes through the beginning
and end points of the actual sweep occurs at t = Ts/2
If a capacitor C is charged by a constant current I, then the voltage across C
is It/C. Hence the rate of change of voltage with time is given by

Sweep speed = I/C

5.4 UNIJUNCTION TRANSISTOR

As the name implies a UJT has only one p-n junction, unlike a BJT which
has two p-n junctions. It has a p-type emitter alloyed to a lightly doped n-
type material as shown in Figure 5.4(a). There are two bases: base B1 and
base B2, base B1 being closer to the emitter than base B2. The p-n junction
is formed between the p-type emitter and n-type silicon slab. Originally this
device was named as double base diode but now it is commercially known
as UJT.
The equivalent circuit of the UJT is shown in Figure 5.4(b). RB1 is the
resistance between base B1 and the emitter, and it is basically a variable
resistance, its value being dependent upon the emitter current iE. RB2 is the
resistance between base B2 and the emitter, and its value is fixed.

Figure 5.4 (a) Construction of UJT, (b) equivalent circuit of UJT, and (c) circuit when iE = 0.

If iE = 0, due to the applied voltage VBB, a current i results as shown in

Figure 5.4(c).
 From the equivalent circuit, it is evident that the diode cannot conduct
unless the emitter voltage

VE = Vg + V1

where Vg is the cut-in voltage of the diode.

This value of emitter voltage which makes the diode conduct is termed
peak voltage and is denoted by VP.

It is obvious that if VE < VP, the UJT is OFF and if VE > VP, the UJT is
ON.
The symbol of UJT is shown in Figure 5.5(a). The input characteristics of
UJT (plot of VE versus iE) are shown in Figure 5.5(b). The main
application of UJT is in switching circuits wherein rapid discharge of
capacitors is very essential. UJT sweep circuit is called a relaxation
oscillator.
 Figure 5.5 (a) Symbol and (b) input characteristics of UJT.

5.5 SWEEP CIRCUIT USING UJT

Many devices are available to serve as the switch S. Figure 5.6(a) shows the
exponential sweep circuit in which the UJT serves the purpose of the
switch. In fact, any current-controlled negative-resistance device may be
used to discharge the sweep capacitor.
The supply voltage VYY and the charging resistor R must be selected
such that the load line intersects the input characteristic in the negative-
resistance region. Assume that the UJT is OFF. The capacitor C charges
from VYY through R. When it is charged to the peak value VP, the UJT
turns ON and the capacitor now discharges through the UJT. When the
capacitor discharges to the valley voltage VV, the UJT turns OFF, and again
the capacitor starts charging and the cycle repeats. The capacitor voltage
appears as shown in Figure 5.6(b). The expression for the sweep time Ts
can be obtained as follows.
Figure 5.6 (a) UJT sweep circuit and (b) output waveform across the capacitor.
For good linearity, Vs = VP – VV must be much smaller than V = VYY –
VV. Since usually VP >> VV and VYY >> VV, we require that VP << VYY.
Also, VYY >> VBB.
When VV is very small,

EXAMPLE 5.1 In the UJT sweep circuit of Figure 5.6(a), VBB = 20 V,

VYY = 50 V, R = 5 k, RB1 = RB2 = 0 , and C = 0.01 F. Using the UJT
characteristics, find (a) the amplitude of sweep signal, (b) the slope and
displacement errors, (c) the duration of the sweep, and (d) the recovery
time.

Solution: (a) When the UJT is OFF, the voltage across the capacitor vs rises
towards VYY = 50 V. From the UJT characteristics we observe that the UJT
fires when vC = 10.6 V, and goes to OFF state when vC = 2.8 V.

EXAMPLE 5.2 Design a relaxation oscillator to have 2 kHz output

frequency, using 2N3980 and a 20 V supply. Calculate the output
amplitude. (Note: The specifications from the data sheet are given as h =
0.68 to 0.82, IP = 2 A, IV = 1 mA and VEB(sat) = 3 V).
 Figure 5.7 Example 5.2: circuit diagram.

EXAMPLE 5.3 The specifications of UJT are given as h = 0.6, VV = 2 V,

RBB = 5 k, IV = 1.5 mA, IP = 8 A, and VBB = 18 V. Calculate the
component values of the UJT sweep circuit to generate an output sweep
frequency of 10 kHz with sweep amplitude of 12 V.

Solution: The circuit to be designed is as shown in Figure 5.7.

 But RB1 should be of the order of a few tens of ohms. Therefore, choose
RB1 = 50 . RB2 should be more than RB1 and it must be of the order of
several hundred ohms. Therefore, choose RB2 = 250 .
 The component values are

RB2 = 250 ,.......RB1 = 50 ,.......R = 100 k,.......C = 0.685 nF

EXAMPLE 5.4 (a) Design a UJT sweep circuit. The sweep amplitude is to
be 10 V. The sweep duration is 1 ms and the sweep speed error is 10%. Find
RB1, RB2, VBB, VYY, R, and C. (b) To get the required sweep duration of
100 s, which component (either R or C) should be varied and what should
be its value?
 RB2 should be more than RB1 and must be of the order of several
hundred ohms. Let RB2 = 300 
 (b) The sweep duration is reduced from 1000 s to 100 s. The time
duration is reduced by 10 times. This can be achieved by reducing either R
or C to 1/10th of its value. However, it is advisable to reduce C rather than
R. By reducing the value of C, the charging current can be reduced. The
increase in charging current is undesirable

EXAMPLE 5.5 Design a sweep circuit with RB1 = RB2 = 0 . The sweep
amplitude is to be 10 V. The sweep duration is 1 ms and the sweep speed
error is to be 10%. Specify reasonable values for VBB, VYY, R, and C. The
circuit to be designed is as shown in Figure 5.7.
5.6 SWEEP CIRCUIT USING A TRANSISTOR
SWITCH
Figure 5.8(a) shows the circuit diagram of a sweep circuit using a transistor
switch. The input gating waveform vi may be the output of a monostable
circuit in which case we get a triggered sweep circuit or it might be the
output of an astable circuit in which case we get a free-running sweep
circuit. The input and output waveforms are shown in Figure 5.8(b).
In the quiescent state, i.e. for t < 0, the input is clamped near ground and
hence the transistor gets enough base drive from VYY through R and
therefore goes into saturation. Hence the output voltage is at its lowest
magnitude ( VCE(sat) = VV). At t = 0, the input goes to its lower level
and remains at that level for t = Ts. So for 0 < t < Ts, the transistor remains
cut-off, the capacitor charges through R towards VYY with a time constant
RC. At t = Ts, the output is at its peak value. At the end of sweep time Ts,
the capacitor discharges and its final value is VV.

Figure 5.8 (a) A transistor sweep circuit and (b) its input and output waveforms.

5.7 A TRANSISTOR CONSTANT-CURRENT

SWEEP
For a transistor in the common base configuration, except for very small
values of collector-to-base voltage, the collector current is very nearly
constant when the emitter current is held constant. This characteristic may
be used to generate a quite linear sweep by causing a constant current to
flow through a capacitor connected in the collector circuit.
Figure 5.9(a) shows the circuit diagram of a transistor constant-current
sweep circuit. In Figure 5.9(a), if VEB is the emitter-to-base voltage, the
emitter current is

The switch S is opened at t = 0. Assuming that VEB remains constant for

t > 0, the collector current will be a constant whose nominal value is

IC = hfbIE  – aIE

So the capacitor charges linearly with time and a sweep is obtained.

The equivalent circuit from which to determine the sweep voltage vs is
shown in Figure 5.9(b).

Figure 5.9 (a) A constant-current sweep circuit and (b) its small-signal model.

When...........................................vi = VEE – Vg = Vi

On applying KVL to the input mesh and KCL to the output node of Figure
5.9(b), we have
 vi = iE(RE + hib) + hrbvs = Vi

At t = 0, vs = 0, the solution to these equations is given by

5.8 MILLER AND BOOTSTRAP TIME-BASE

GENERATORS—
BASIC PRINCIPLES
The linearity of the time-base waveforms may be improved by using
circuits involving feedback. Figure 5.10(a) shows the basic exponential
sweep circuit in which S opens to form the sweep. A linear sweep cannot be
obtained from this circuit because as the capacitor charges, the charging
current decreases and hence the rate at which the capacitor charges, i.e. the
slope of the output waveform decreases. A perfectly linear output can be
obtained if the initial charging current i = V/R is maintained constant. This
can be done by introducing an auxiliary variable generator v whose
generated voltage v is always equal to and opposite to the voltage across the
capacitor as shown in Figure 5.10(b). Two methods of simulating the
fictitious generator are discussed below.

Figure 5.10 (a) The current decreases exponentially with time and (b) the current remains constant.

In the circuit of Figure 5.10(b) suppose the point Z is grounded as in

Figure 5.11(a). A linear sweep will appear between the point Y and ground
and will increase in the negative direction. Let us now replace the fictitious
(imaginary) generator by an amplifier with output terminals YZ and input
terminals XZ as shown in Figure 5.11(b). Since we have assumed that the
generated voltage is always equal and opposite to the voltage across the
capacitor, the voltage between X and Z is equal to zero. Hence the point X
acts as a virtual ground. Now for the amplifier, the input is zero volts and
the output is a finite negative value. This can be achieved by using an
operational integrator with a gain of infinity. This is normally referred to as
the Miller integrator circuit or the Miller sweep.

Figure 5.11 (a) Figure 5.10(b) with Z grounded and (b) Miller integrator circuit.

Suppose that the point Y in Figure 5.10(b) is grounded and the output is
taken at Z. A linear sweep will appear between Z and ground and will
increase in the positive direction. Let us now replace the fictitious generator
by an amplifier with input terminals XY and output terminals ZY as shown
in Figure 5.12. Since we have assumed that the generated voltage v at any
instant is equal to the voltage across the capacitor vC, then vo must be equal
to vi, and the amplifier voltage gain must be equal to unity. The circuit of
Figure 5.12 is referred to as the Bootstrap sweep circuit.
 Figure 5.12 Bootstrap sweep circuit.

The Miller sweep

The Miller integrating circuit of Figure 5.11(b) is redrawn in Figure 5.13(a).
A switch S at the closing of which the sweep starts is included. The basic
amplifier has been replaced at the input side by its input resistance and on
the output side by its Thevenin’s equivalent. Ro is the output resistance of
the amplifier and A its open circuit voltage gain. Figure 5.13(b) is obtained
by replacing V, R and Ri on the input side by a voltage source V in series
with a resistance R where

Neglecting the output resistance in the circuit of Figure 5.13(b), if the

switch is closed at t = 0 and if the initial voltage across the capacitor is zero,
+ –
then vo (t = 0 ) = 0, because at t = 0 , vi = 0 and since the voltage across
the capacitor cannot change instantaneously.
+
At t = 0 ,.......vi – Avi = 0.......or.......vi = Avi = vo = 0

This indicates that the sweep starts from zero.

 At t = , the capacitor acts as an open-circuit for dc. So no current flows
and therefore

vi = V.......and.......vo = AV

Figure 5.13 (a) A Miller integrator with switch S, input resistance Ri and Thevenin’s equivalent
on the output side and (b) Figure 5.13(a) with input replaced by Thevenin’s equivalent.

This indicates that the output is exponential and the sweep is negative-
going since A is a negative number.
 If Ro is taken into account, the final value attained by vo remains as
before, AV = – |A|V. The initial value however is slightly different.
+
To find vo at t = 0 , writing the KVL around the mesh in Figure 5.13(b),
assuming zero voltage across the capacitor, we have

+
Therefore, if Ro is taken into account, vo(t = 0 ) is a small positive value
and still it will be a negative-going sweep with the same terminal value.
Thus the negative-going ramp is preceded by a small positive jump. Usually
this jump is small compared to the excursion AV. Hence, improvement in
linearity because of the increase in total excursion is negligible.
The bootstrap sweep
Figure 5.14 shows the bootstrap circuit of Figure 5.12. The switch S at the
opening of which the sweep starts is in parallel with the capacitor C. Here,
Ri is the input resistance, A is the open-circuit voltage gain, and Ro is the
output resistance of the amplifier.

Figure 5.14 Bootstrap circuit of Figure 5.12 with switch S which opens at t = 0,
input resistance Ri, and Thevenin’s equivalent of the amplifier on the output side.

–
At t = 0 , the switch was closed and so vi = 0. Since the voltage across
+
the capacitor cannot change instantaneously, at t = 0 also, vi = 0 and hence
Avi = 0, and the circuit shown in Figure 5.15 results.

–
The output has the same value at t = 0 and hence there is no jump in the
output voltage at t = 0.

Figure 5.15 Equivalent circuit of Figure 5.14 at t = 0.

 At t = , the capacitor acts as an open-circuit and the equivalent circuit
shown in Figure 5.16 results.

Figure 5.16 Equivalent circuit of Figure 5.14 at t = .

Writing KVL in the circuit of Figure 5.16,

This shows that the slope error is [1 – A + (R/Ri)] times the slope error that
would result if the capacitor is charged directly from V through a resistor.
Comparing the expressions for the slope error of Miller and bootstrap
circuits, we can see that it is more important to keep R/Ri small in the
bootstrap circuit than in the Miller circuit. Therefore, the Miller integrator
has some advantage over the bootstrap circuit in that in the Miller circuit a
higher input impedance is less important.

5.9 THE TRANSISTOR MILLER TIME-BASE

GENERATOR
Figure 5.17 shows the circuit diagram of a transistor Miller time-base
generator. It consists of a three-stage amplifier. To have better linearity, it is
essential that a high input impedance amplifier be used for the Miller
integrator circuit. Hence the first stage of the amplifier of Figure 5.17 is an
emitter follower. The second stage is a common-emitter amplifier and it
provides the necessary voltage amplification. The third stage (output stage)
is also an emitter follower for two reasons. First, because of its low output
impedance Ro it can drive a load such as the horizontal amplifier. Second,
because of its high input impedance it does not load the collector circuit of
the second stage and hence the gain of the second stage can be very high.
The capacitor C placed between the base of Q1 and the emitter of Q3 is the
timing capacitor. The sweep speed is changed from range to range by
switching R and C and may be varied continuously by varying VBB.
 Figure 5.17 A transistorized Miller time-base generator.

Under quiescent condition, the output of the Schmitt gate is at its lower
level. So transistor Q4 is ON. The emitter current of Q4 flows through R1
and hence the emitter is at a negative potential. Therefore the diode D
conducts. The current through R flows through the diode D and the
transistor Q4. The capacitor C is bypassed and hence is prevented from
charging. When a triggering signal is applied, the output of the Schmitt gate
goes to its higher level. So the base voltage of Q4 rises and hence the
transistor Q4 goes OFF. A current flows now from 10 V source through R1.
The positive voltage at the emitter of Q4 now makes the diode D reverse
biased. At this time the upper terminal of C is connected to the collector of
Q4 which is in cut-off. The capacitor gets charged from VBB and hence a
run down sweep output is obtained at the emitter of Q3. At the end of the
sweep, the capacitor C discharges rapidly through D and Q4.
 Considering the effect of the capacitance C1, the slope or sweep speed
error is given by

5.10 THE TRANSISTOR BOOTSTRAP TIME-

BASE GENERATOR
Figure 5.18 shows a transistor bootstrap time-base generator. The input to
transistor Q1 is the gating waveform from a monostable multivibrator (it
could be a repetitive waveform like a square wave). Figure 5.19(a) shows
the base voltage of Q1. Figure 5.19(b) shows the collector current
waveform of Q1 and Figure 5.19(c) shows the output voltage waveform at
the emitter of Q2.

Figure 5.18 A voltage time-base generator.

Quiescent conditions
Under quiescent conditions, i.e. before the application of the gating
waveform at t = 0, Q1 is in saturation because it gets enough base drive
from VCC through RB. So the voltage across the capacitor which is also the
voltage at the collector of Q1 and the base of Q2 is VCE (sat). Since Q2 is
conducting and acting as an emitter follower, the voltage at the emitter of
Q2 which is also the output voltage is less than this base voltage by VBE2,
i.e.

vo = VCE(sat) – VBE2

is a small negative voltage (a few tenths of a volt negative). If we neglect

this small voltage as well as the small drop across the diode D, then the
voltage across C1 as well as across R is VCC. Hence the current iR through
R is VCC/R. Since the quiescent output voltage at the emitter of Q2 is close
to zero, the emitter current of Q2 is VEE/RE. Hence the base current of Q2
is iB2  VEE/ hFE RE.

.........................................................iR = iC1 + iB2

Since the base current of Q2, i.e. iB2 is very small compared with the
collector current iC1 of Q1,

For Q1 to be really in saturation under quiescent condition, its base

current (iB1 = VCC/RB) must be at least equal to iC1/hFE, i.e. VCC/hFER,
so that
Formation of sweep
When the negative-going gating waveform is applied at t = 0, the transistor
Q1 is driven OFF. The current iC1 now flows into the capacitor C and so
the voltage across the capacitor rises according to the equation

Assuming unity gain for the emitter follower,

Since the voltage across C1 is constant and equal to VCC, when the sweep
starts, the diode is reverse biased and the current through R is supplied by
the capacitor C1.
 Figure 5.19 Voltage time-base generator of Figure 5.18: (a) the base voltage of Q1,
(b) the collector current of Q1, and (c) the output voltage at the emitter of Q2.

The equation, vo = VCCt/RC is valid only if the gate duration Tg is small

enough so that the calculated value of vo does not exceed VCC. From
Figure 5.18 it can be seen that when vo approaches VCC, the voltage VCE
of Q2 approaches zero and the transistor Q2 goes into saturation. Then it no
longer acts as an emitter follower. Hence vo (also vC) remains constant at
VCC. The current VCC/R through C1 and R now flows from base to emitter
of Q2.
 If the output vo reaches the voltage VCC in a time Ts < Tg, then

whereas if the sweep amplitude Vs is less than VCC, then the maximum
ramp voltage is given by

Retrace interval
At t = Tg, when the gate terminates, the transistor Q1 goes into conduction
and a current iB1 = VCC/RB flows into the base of Q1. Hence a current iC1
= hFEiB1 flows into the collector of Q1. This current remains constant till
the transistor goes into saturation. Since Q1 is ON the capacitor C
discharges through Q1. Because of emitter follower action, when vC falls,
vo also falls by the same amount and so the voltage across R remains
constant at VCC. The constant current iR = VCC/R also flows through Q1.
Applying KVL at the collector of Q1 and neglecting iB2,

Since the discharging current of C, i.e. iA is constant, the voltage across C

and hence the output voltage falls linearly to its initial value.
If the retrace time is Tr, then the charge lost by the capacitor = iATr.
where Vs is the sweep amplitude. That is,

After C is discharged, the collector current is now supplied completely

through R and becomes established at the value VCC/R.
The retrace time can be reduced by choosing a small value of RB.
However if RB is reduced greatly, then the collector current may

increase to the point where the transistor dissipation may be excessive.

The recovery process
During the entire interval T = Tg + Tr , the capacitor C1 discharges at a
constant rate because the current i = VCC/R through it has remained
constant. So it would have lost a charge Hence at the time T when

the voltage across C and at the base of Q2 returns to its value for t < 0, the
voltage across C1 is smaller than it was at the beginning of the sweep. The
diode D starts conducting at t = T, and the end of C1, which is connected to
D, returns to its initial voltage, i.e. VCC. Therefore, the other terminal of C1
which is connected to the emitter of Q2 is at a more positive potential than
it was at t = 0 and so Q2 goes to cut-off. So the capacitor C1 charges
through the resistor RE with a current, iE = VEE/RE.

The maximum recovery time T1 for C1 can be calculated as follows.

 This shows that T1 is independent of C1 and varies inversely with VEE.
T1 can be reduced by increasing VEE. However this modification will
increase the quiescent current in Q2 and hence its dissipation.

EXAMPLE 5.6 The transistor bootstrap circuit shown in Figure 5.18 has
the following parameters, VCC = 10 V, VEE = – 10 V, RB = 30 k, R = 10
k, RE = 5 k, C = 0.002 F, C1 = 0.25 F and CB may be taken as
arbitrarily large. The input gate has an amplitude of 1 V and a width of 50
s. The transistor parameters are hFE = hfe = 60, hie = 2 k, 1/hoe = 10
–4
k, hre = 10 , ICBO = 0, and the forward biased junction voltages are
negligible. The diode is ideal. (a) Plot the gate voltage, collector current
iC1, and the output voltage vo. Evaluate (b) the sweep speed and the
amplitude of the sweep at its maximum value, and the sweep time (c) the
time it takes to discharge C at the end of the sweep, (d) the peak voltage
change across C1 and the time required to replace the lost charge, and (e)
the slope error.
 The time it takes to discharge C at the end of the sweep, i.e.,
The retrace time Tr is

(d) Let the peak voltage change across C1 be VC1, then the charge lost
by C1 during (Tg + Tr) must be equal to the charge gained by C1 during the
recovery time T1.
 (a) Using the above data, the waveforms can be sketched as shown in
Figure 5.20.
 Figure 5.20 Example 5.6: waveforms.

EXAMPLE 5.7 In the transistor bootstrap circuit of Figure 5.18, VCC = 25

V, VEE = –15 V, R = 10 k, RE =15 k, RB = 150 k, C = 0.05 F, and
C1 = 100 F. The gating waveform has a duration, Tg = 300 s. The
–4
transistor parameters are hie = 1.1 k, hre = 2.5  10 k, hfe = 50, hoe
= 1/40 k.
(a) Draw the waveforms of iC1 and vo, labeling all current and voltage
levels. (b) What is the slope error of the sweep? (c) What is the sweep speed
and the maximum value of the sweep voltage? (d) What is the retrace time
Tr for C to discharge completely? (e) Calculate the recovery time T1 for C1
to recharge completely.
 The waveforms are shown in Figure 5.21.

Figure 5.21 Example 5.7: waveforms.

EXAMPLE 5.8 The circuit shown in Figure 5.22 is a variation of the

bootstrap which avoids the need for a voltage source neither side of which
is grounded. Show that precise linearity results if the amplifier gain is A = 1
+ (R2/R1).

Solution: The output voltage will be linear if the input voltage is linear. For
the input voltage to be linear, the current flowing through the capacitor
should be constant, i.e. iC should be constant.
Applying KVL at the input node,

Since Vi varies with time linearly, for iC to be constant, the coefficient of

Vi must be zero, i.e.

Figure 5.22 Example 5.8: circuit diagram.

EXAMPLE 5.9 The circuit of Figure 5.18 has the following parameters:
VCC = 18 V, VEE = – 9 V, RE = 8 k, R = 5 k and Tg = 750 s. The
–4
transistor h parameters are hfe = 50, hie = 1.1 k, hre = 2.5  10 , and
hoe = 1/40 k. An 18 V sweep in 500 s is desired. (a) Find a reasonable
value for RB. (b) Calculate C. (c) Calculate es assuming C1 arbitrarily
large. (d) Choose C1 so that es is increased by no more than 10 per cent
over its value in part (c). (e) Calculate the retrace time Tr for C to discharge
completely at the end of the gating waveform. (f) Calculate the recovery
time T1 for C1 to recharge completely.

Solution: Referring to Figure 5.18: (a) For the transistor Q1 to be in

saturation under quiescent conditions,

Hence a reasonable value for RB is 100 k.

(b) Since sweep time Ts (= 500 s) < Tg (= 750 s), the output vo
reaches the value VCC in Ts seconds, i.e.

(c) To find es, we must first calculate the input impedance Ri and the
voltage gain A = AV of the emitter follower.
EXAMPLE 5.10 For the bootstrap sweep generator shown in Figure
5.23(a), find the slope error, sweep amplitude, retrace time, and recovery
time. Plot to scale the output and the input on the same time scale. Assume
–4
hfe = 50, hre = 2  10 , hoe = 1/35 k, hie = 1 k. Junction voltages are
neglected. The input is a 1 kHz symmetrical square wave.

Solution: Referring to Figures 5.23(a) and (b):

Input frequency, f = 1 kHz
 Figure 5.23 (a) Example 5.10: circuit diagram and (b) input/output waveforms.

For an emitter follower, the current gain is given as

 3 –6
Sweep time constant, RC = 10  10  0.07  10 = 0.7 ms
The output waveform is shown in Figure 5.23(b).

EXAMPLE 5.11 A bootstrap sweep generator is shown in Figure 5.24.

Transistors Q1 and Q2 are of silicon with hfe(min) = 30, VCE(sat) = 0.4 V
and VBE(sat) = 0.8 V. Assume a voltage drop of 0.5 V across the forward-
biased diode D. Calculate all the quiescent state voltages and currents. If a
periodic gating signal with a frequency of 1 kHz and Tg = 0.5 ms is applied,
determine the sweep time, sweep amplitude and sweep frequency.

Solution: (a) Under quiescent conditions, transistor Q1 is in saturation and

transistor Q2 operates in its active region.

Figure 5.24 Example 5.11: circuit diagram.

IB2 = IE2 – IC2 = 1.72 – 1.664 = 0.0554 mA

IC1 = IR – IB2 = 1.14 – 0.0554 = 1.0846 mA

 IE1 = IC1 + IB1 = 1.0846 + 0.1147 = 1.1993 mA

VCE2 = VCC – Vo = 18 – (– 0.4) = 18.4 V

Hence the quiescent state voltages and currents are:

VE1 = 0 V, VB1 = 0.8 V, VC1 = 0.4 V, IC1 = 1.0846 mA, IB1 = 0.1147 mA,
IE1 = 1.1993 mA

VE2 = – 0.4 V, VB2 = 0.4 V, VC2 = 18 V, IC2 = 1.664 mA, IB2 = 0.0554
mA, IE2 = 1.72 mA

VCE2 = 18.4 V, IR = 1.14 mA

EXAMPLE 5.12 Design a transistor bootstrap ramp generator to provide

an output amplitude of 12 V over a time period of 2 ms. The input signal is
a negative-going pulse with an amplitude of 5 V, a pulse width of 2 ms and
the time interval between pulses is 0.5 ms. The load resistance is 2 k and
the ramp is to be linear within 1%. The supply is to be  15 V. Take
hfe(min) = 80.

Solution: Referring to Figure 5.18, we have to determine the component

values RB, R, C, and C1
 The designed circuit is as shown in Figure 5.18.

The design values are R = 941 , C = 2.65 F, RB = 50.88 k, C1 =

26.56 F

EXAMPLE 5.13 Find the component values of a bootstrap sweep

generator, given VCC = 18 V, IC(sat) = 2 mA, and hfe(min) = 30.

Solution: The circuit to be designed is shown in Figure 5.18. We have to

determine the values of the components R, C, RB, RE, and C1

Calculation of R:
The current through the resistor R is given by
The designed circuit is shown in Figure 5.25. The design values are

R = 8.6 k, C = 1.163 F, RB = 174.74 k, RE = 5.8 k, C1 = 11.63 F

EXAMPLE 5.14 A transistor bootstrap ramp generator is to produce a 15
V, 5 ms output to a 2 k load resistor. The ramp is to be linear within 2%.
Design a suitable circuit using VCC = 22 V, –VEE = – 22 V and transistor
with hfe(min) = 25. The input pulse has an amplitude of – 5 V, pulse width
= 5 ms and space width = 2.5 ms.

Solution: The circuit to be designed is as shown in Figure 5.24.

Figure 5.25 Example 5.13: designed circuit.

5.11 CURRENT TIME-BASE GENERATORS
We have mentioned earlier that a linear current time-base generator is one
that provides an output current waveform a portion of which exhibits a
linear variation with respect to time. This linearly varying current waveform
can be generated by applying a linearly varying voltage waveform
generated by a voltage time-base generator, across a resistor. Alternatively,
a linearly varying current waveform can be generated by applying a
constant voltage across an inductor. Linearly varying currents are required
for magnetic deflection applications.

5.12 A SIMPLE CURRENT SWEEP

Figure 5.26(a) shows a simple transistor current sweep circuit. Here the
transistor is used as a switch and the inductor L in series with the transistor
is bridged across the supply voltage. Rd represents the sum of the diode
forward resistance and the damping resistance. The gating waveform shown
in Figure 5.26(b) applied to the base of the transistor is in two levels. These
levels are selected such that when the input is at the lower level the
transistor is cut-off and when it is at the upper level the transistor is in
saturation. For t < 0, the input to the base is at its lower level (negative). So
the transistor is cut-off. Hence no currents flow in the transistor and iL = 0
and vCE = VCC. At t = 0, the gate signal goes to its upper level (positive).
So the transistor conducts and goes into saturation. Hence the collector
voltage falls to vCE(sat) and the entire supply voltage VCC is applied across
the inductor. So the current through the inductor
increases linearly with time. This continues till t = Tg, at which time the
gating signal comes to its lower level and so the transistor will be cut-off.
During the sweep interval Ts (i.e. from t = 0 to t = Tg), the diode D is
reverse biased and hence it does not conduct. At t = Tg, when the transistor
is cut-off and no current flows through it, since the current through the
inductor cannot change instantaneously it flows through the diode and the
diode conducts. Hence there will be a voltage drop of ILRd across the
resistance Rd. So at t = Tg, the potential at the collector terminal rises
abruptly to VCC + ILRd, i.e. there is a voltage spike at the collector at t =
Tg. The duration of the spike depends on the inductance L but the amplitude
of the spike does not. For t > Tg, the inductor current decays exponentially
to zero with a time constant t = L/Rd. So the voltage at the collector also
decays exponentially and settles at VCC under steady-state conditions. The
inductance L normally represents a physical yoke and its resistance RL may
not be negligible. If RCS represents the collector saturation resistance of the
transistor, the current increases in accordance with the equation
 If the current increases linearly to a maximum value IL, the slope error is
given by

The inductor current waveform and the waveform at the collector of the
transistor are shown in Figures 5.26(c) and 5.26(d) respectively. To
maintain linearity, the voltage (RL + RCS)IL across the total circuit
resistance must be kept small compared with the supply voltage VCC.

5.13 LINEARITY CORRECTION THROUGH

ADJUSTMENT
OF DRIVING WAVEFORM
In the circuit of Figure 5.26(c), the current waveform is not perfectly linear.
A nonlinearity exists because as the current in the inductor (yoke) increases,
the voltage drop across the series resistance also increases and hence the
voltage across the inductor decreases, and so the rate of rise of the current
in the inductor decreases as well. If the voltage developed across the
resistor is compensated, then a linear waveform can be obtained.
Figure 5.27 shows a method of compensating the voltage drop across the
series resistor to obtain a linear current waveform. The driving voltage
source has a Thevenin’s resistance Rs and the total circuit resistance is Rs +
RL. If the inductor current is to be perfectly linear, i.e. if iL = kt, then the
voltage source waveform must be
 Figure 5.26 (a) A simple current sweep circuit, (b) the input gating waveform,
(c) the inductor current waveform, and (d) the waveform of the collector voltage.

Figure 5.27 The trapezoidal voltage waveform shown in figure (a) produces a
linear current ramp in the inductor in figure (b).
 This applied waveform consists of a step followed by a ramp. Such a
waveform is called trapezoidal.
So considering the resistance of the yoke, transistor, and the source to
obtain a linear current waveform, a trapezoidal rather than a step signal
should be applied.
If the voltage source vs in series with the resistance Rs is replaced by a
current source is = vs/Rs in parallel with a resistance Rs as shown in Figure
5.28(b), the current source must furnish a current

This is also a step followed by a ramp. Hence the waveform of the current
source must also be trapezoidal.

Figure 5.28 The trapezoidal current waveform in figure (a) produces a

linear current ramp in the inductor of figure (b).

At the end of the sweep, the current will return to zero exponentially with
a time constant t = L/(Rs + RL). Normally Rs >> RL. Therefore, neglecting
RL, t = L/Rs. If Rs is small, the time constant is large and so the current
decays very slowly, but the peak voltage developed across the current
source will be small. If Rs is large, the time constant is small and so the
current decays very fast but the peak voltage developed across the source
will be large. As a compromise, a damping resistor Rd is connected in
parallel to the yoke. If R is the parallel combination of Rs and Rd, then the
time constant is t = L/R.
Figure 5.29 shows a voltage sweep circuit modified by the addition of a
resistor R1 in series with C1 to generate a trapezoidal voltage waveform. If
the switch S is opened at t = 0, the output vo is given by

As long as t/2R2C1 << 1, the waveform vo is trapezoidal consisting of a

step of amplitude VR1/R2 on which is superimposed a ramp of slope
V/R2C1. If the inductor is placed directly across the output terminals of
Figure 5.29, the signal vo will no longer be trapezoidal. Therefore, the
signal generated by the circuit of Figure 5.29 should not be applied directly
to the yoke but rather through an active device, i.e. a transistor.
 Figure 5.29 A circuit for generating a trapezoidal voltage waveform.

Figure 5.30 A transistor current sweep circuit.

5.14 A TRANSISTOR CURRENT TIME-BASE

GENERATOR
Figure 5.30 shows the circuit diagram of a transistor current time-base
generator. Transistor Q1 is a switch which serves the function of S in Figure
5.29. Transistor Q1 gets enough base drive from VCC1 through RB and
hence is in saturation under quiescent conditions. At t = 0, when the gating
signal is applied it turns off Q1 and a trapezoidal voltage waveform appears
at the base of Q2. Transistors Q2 and Q3 are connected as darlington pair to
increase the input impedance so that the trapezoidal waveform source is not
loaded. Such loading would cause nonlinearity in the ramp part of the
trapezoid.
The emitter resistor RE introduces negative current feedback into the
output stage and thereby improves the linearity with which the collector
current responds to the base voltage. For best linearity it is necessary to
make the emitter resistance as large as possible. RE is selected so that the
voltage developed across it will be comparable to the supply voltage VCC2.

EXAMPLE 5.15 (a) In the circuit shown in Figure 5.31(a), L = 200 mH,
and it is required that the current in L increases from zero to 100 mA in 1.0
ms. Find VCC. Assume RL = 0 and VCE(sat) = 0. (b) If Rd, consisting of
the diode resistance alone, is 10 ohms, draw the waveforms of iL and vCE
indicating voltage levels and time constants. (c) If the transistor can
withstand a collector-to-emitter voltage of 60 V, what is the maximum value
of Rd that may be used? What is the recovery time?
 Figure 5.31 Example 5.15: (a) circuit diagram, (b) waveform of iL, and (c) waveform of vCE.

Solution: (a) When the transistor is in saturation, the entire voltage VCC
will appear across the inductor [see Figure 5.31(a)]. If the current reaches a
maximum value IL (max) in time Ts, then
 The waveforms for iL and vCE are shown in Figures 5.31(b) and (c)
respectively.

EXAMPLE 5.16 In the circuit shown in Figure 5.31(a), VCC = 20 V, L =

200 mH, the yoke resistance RL = 20 ohms, RCS = 5 ohms, and Rd = 200
ohms. For a 500 s sweep, draw the waveforms of iL and vCE, indicating
voltage levels and time constants, and calculate the slope error of the sweep.

The current decays as per the equation

–(t–Ts)/(L/(RL+Rd)) –3 –(t–0.510–3)/(20010–
iL = ILe = 48.4  10 ◊e
3/(20+200)

–3
Spike in collector voltage at the end of sweep = ILRd = 48.4  10 
200 = 9.68 V
Therefore, peak collector voltage, VCE(peak) = VCC + ILRd
 = 20 + 9.7 = 29.7 V

Slope error of sweep is given by

The voltage and current waveforms are shown in Figures 5.32(a) and (b)
respectively.

Figure 5.32 Example 5.16: waveforms.

SHORT QUESTIONS AND ANSWERS

1. How many types of time-base generators are there? Name them.
A. There are two types of time-base generators. They are (a) voltage
time-base generators and (b) current time-base generators.
2. What do you mean by (a) a voltage time-base generator, (b) a current
time-base generator, and (c) a linear time-base generator?
 A. (a) A voltage time-base generator is one that provides an output
voltage waveform, a portion of which exhibits a linear variation
with time.
(b) A current time-base generator is one that provides an output
current wave form, a portion of which exhibits a linear variation
with time.
(c) A linear time-base generator is one that provides an output
waveform a portion of which exhibits a linear variation of voltage
or current with time.
3. What are the applications of time-base generators?
A. Some of the important applications of the time base generators are
found in CROs, in television and radar displays, in precise time
measurements, and in time modulation.
4. Why are time-base generators called sweep circuits?
A. Time-base generators are called sweep-circuits because the output
of the time-base generator applied to one set of deflecting plates of a
CRO is used to sweep the electron beam horizontally across the screen.
5. Which is the most important application of a time-base generator?
A. The most important application of a time-base generator is in CROs
where it is used to sweep the electron beam horizontally across the
screen of the scope.
6. What do you mean by sweep waveforms?
A. The waveforms which increase linearly with time are called sweep
waveforms.
7. What do you mean by (a) sweep time and (b) restoration time?
A. (a) Sweep time is the time during which the output increases
linearly.
(b) Restoration time is the time required by the sweep voltage to
return to its initial value.
8. When do we get a saw-tooth or ramp wave form?
A. When the restoration time is zero, we get a saw-tooth or ramp
output waveform.
9. How is the deviation from linearity expressed?
 A. The deviation from linearity is expressed in three ways: (a) the
slope or sweep speed error es, (b) the displacement error ed and (c) the
transmission error et.
10. Define the terms (a) slope error, (b) displacement error, and (c)
transmission error. How are they related for an exponential sweep
circuit?
A. (a) The slope error or sweep speed error es is defined as the ratio of
the difference in slope at the beginning and end of the sweep to the
initial value of slope.
(b) The displacement error ed is defined as the ratio of the maximum
difference between the actual sweep voltage and the linear sweep
to the amplitude of the sweep.
(c) The transmission error et is defined as the ratio of the difference
between the input and the output to the input at the end of the
sweep. es, ed and et are related as es = 2et = 8 ed for an
exponential sweep circuit.
11. Out of the three errors es, ed and et which is more dominant one and
which is least dominant?
A. Out of es, ed and et, the slope error es is the more dominant one and
the displacement error ed is the least severe one.
12. What are the methods of generating a time-base waveform?
A. The methods of generating a time-base waveform are as follows:
1. Exponential charging. In this method, a capacitor is charged from a
supply voltage through a resistor to a voltage which is small
compared with the supply voltage.
2. Constant current charging. In this method, a capacitor is charged
linearly from a constant current source. Since the charging current is
constant the voltage across the capacitor increases linearly.
3. The Miller circuit. In this method, an operational integrator is used
to convert an input step voltage into a ramp waveform.
4. The Phantastron circuit. In this method, a pulse input is converted
into a ramp. This is a version of the Miller circuit.
 5. The bootstrap circuit. In this method, a capacitor is charged linearly
by a constant current which is obtained by maintaining a constant
voltage across a fixed resistor in series with the capacitor.
6. Compensating networks. In this method, a compensating circuit is
introduced to improve the linearity of the basic Miller and bootstrap
time-base generators.
7. An inductor circuit. In this method, an RLC series circuit is used.
Since an inductor does not allow the current passing through it to
change instantaneously, the current through the capacitor more or less
remains constant and hence a more linear sweep is obtained.
13. Write the expressions for es, ed and et for an exponential sweep
circuit.
A. For an exponential sweep circuit es = Ts/RC = Vs/V; et = Ts/2RC;
ed = Ts/8RC.
14. Which devices can be used as a switch in sweep circuits?
A. A UJT can be used as the switch in sweep circuits. In fact any
current controlled negative resistance device can be used as a switch to
discharge the sweep capacitor.
15. Write the expression for sweep time of a UJT sweep circuit.
A. For a UJT sweep circuit Ts = RC ln

16. Which amplifier is required in miller time-base generator?

A. In miller time base generator an inverting amplifier with a gain of
infinity is required.
17. Which amplifier is required in bootstrap time-base generator?
A. In bootstrap time-base generator, a non inverting amplifier with
unity gain is required.
18. What is the advantage of the miller integrator over the bootstrap
circuit?
A. The advantage of the miller integrator over the bootstrap circuit is
that in the miller circuit, higher input impedance is less important.
19. What type of sweep does a miller time-base generator produce?
A. A miller time-base generator produces a negative-going sweep.
20. What type of sweep does a bootstrap time-base generator produce?
A. A bootstrap time-base generator produces a positive-going sweep.
21. What type of currents are required for magnetic deflection
applications?
A. Linearly varying currents are required for magnetic deflection
applications.
22. How can a linearly varying current waveform be generated?
A. A linearly varying current waveform can be generated by applying a
linearly varying voltage waveform generated by a voltage time-base
generator across a resistor. It can also be generated by applying a
constant voltage across an inductor.
23. Write the expression for the slope error of miller and bootstrap time-
base generators.

24. For a bootstrap voltage time-base generator, write the expressions for
output voltage vo, retrace time Tr and recovery time T1.

25. Write the expression for the slope error es of a simple current sweep
circuit.

26. What type of voltage input is required to obtain a linear current

sweep?
A. To obtain a linear current sweep, a trapezoidal rather than a step
voltage input is required.
 REVIEW QUESTIONS
1. With the help of a neat circuit diagram and waveforms, explain the
working of a UJT relaxation oscillator.
2. With the help of a neat circuit diagram and waveforms, explain the
working of a simple transistor current time-base generator.
3. With the help of a neat circuit diagram, explain the working of a
transistor constant current sweep circuit.
4. Explain the basic principles of the Miller and bootstrap time-base
generators.
5. With the help of a neat circuit diagram, explain the working of a
transistor Miller time-base generator.
6. With the help of a neat circuit diagram and waveforms, explain the
working of a transistor bootstrap time-base generator.
7. How are linearly varying current waveforms generated?
8. With the help of a neat circuit diagram, explain the working of a
simple current sweep.
9. How is linearity corrected through adjustment of the driving waveform
for a current time-base generator?
10. With the help of a neat circuit diagram, explain the working of a
transistor current time-base generator.

FILL IN THE BLANKS

1. The time-base generators may be __________ or ____________.
2. A ____________ is one that provides an output waveform a portion of
which exhibits a linear variation of voltage or current with time.
3. A ____________ is one that provides an output current waveform a
portion of which exhibits a linear variation with time.
4. A ____________ is one that provides an output voltage waveform a
portion of which exhibits a linear variation with time.
5. The most important application of a time-base generator is in
__________.
 6. The output of a time-base generator is called the _____ and the time-
base generators are called the ____________.
7. Time-base generators are used in ____________, ____________,
____________, and ____________ etc.
8. The time during which the output increases linearly is called the
____________ and the time required by the sweep voltage to return to
the initial value is called the ____________.
9. When ________ is zero, we get a saw-tooth or ramp output waveform.
10. The waveforms which increase linearly with time are called
_________.
11. The deviation from linearity is expressed in three ways: (a)
____________, (b) ____________, and (c) ____________.
12. The ratio of the difference in slope at beginning and end of the sweep
to the initial value of slope is called the ____________.
13. The ratio of the maximum difference between the actual sweep and the
linear sweep which passes through the beginning and end points of the
actual sweep to the amplitude of the sweep is called the
____________.
14. The ratio of the difference between the input and the output to the
input at the end of the sweep time is called the ____________.
15. If the deviation from linearity is small, then the slope error es, the
displacement error ed, and the transmission error et are related as
____________.
16. If the restoration time of the sweep is zero, we get a ____________.
17. There are _________ methods of generating a sweep.
18. In ______ circuit, an operational integrator is used to convert an input
step voltage into a ramp.
19. In __________ circuit, a pulse input is converted into a ramp.
20. _______ may be used to improve the linearity of Miller and bootstrap
circuits.
21. In a Miller circuit, the gain A of the ____________ amplifier should be
____________.
22. In bootstrap circuit, the gain A of the ____________ amplifier should
be ____________.
23. A Miller time-base generator produces a ____________ going sweep,
whereas a bootstrap time-base generator produces a ____________
going sweep.
24. A linearly varying current waveform can be generated by applying a
constant voltage across ____________.
25. A ____________ oscillator is a circuit which generates non-sinusoidal
oscillations.
26. ___________ currents are required for magnetic deflection
applications.
27. In a simple current time-base generator when the resistance of the coil
and the resistance of the transistor in saturation are considered, a
____________ voltage rather than a ____________ voltage is applied
across the inductor to obtain a linear current.

OBJECTIVE TYPE QUESTIONS

1. A ________ is one that provides an output waveform, a portion of
which exhibits a linear variation of voltage or current with time.
(a) linear time-base generator
(b) nonlinear time-base generator
(c) voltage time-base generator
(d) current time-base generator
2. The most important application of a time-base generator is in
(a) TVs
(b) radar displays
(c) CROs
(d) time measurements
3. To get a saw-tooth or ramp output waveform, the restoration time must
be
(a) zero
(b) infinity
(c) small
(d) large
4. The ratio of difference in slope at the beginning and end of sweep to
the initial value of slope is called
 (a) sweep speed error
(b) displacement error
(c) transmission error
(d) difference error
5. The ratio of the maximum difference between the actual sweep and the
linear sweep which passes through the beginning and end points of the
actual sweep to the amplitude of the sweep is called the
(a) sweep speed error
(b) displacement error
(c) transmission error
(d) difference error
6. The ratio of the difference between the input and the output to the
input at the end of the sweep is called the
(a) sweep speed error
(b) displacement error
(c) transmission error
(d) difference error
7. The slope error, displacement error and transmission error are related
as

8. There are __________ methods of generating a sweep.

(a) two
(b) four
(c) six
(d) seven
9. In a miller circuit, the amplifier gain A should be
(a) infinite
(b) finite
(c) unity
(d) zero
10. In a bootstrap sweep circuit, the amplifier gain A should be
(a) infinite
(b) finite
 (c) unity
(d) zero
11. In an exponential charging circuit, sweep speed is
(a) RC/V
(b) V/RC
(c) VRC
(d) none of these
12. A set of coils is called a
(a) yoke
(b) coil
(c) winding
(d) none of these
13. A circuit which generates non sinusoidal waveforms is called a
(a) relaxation oscillator
(b) square wave generator
(c) non-sinusoidal oscillator
(d) none of these
14. Sweep speed error is given by es =
(a) Ts/RC
(b) RC/Ts
(c) RCTs
(d) none of these
15. Sweep time Ts for a UJT sweep circuit is

16. The expression for slope error in bootstrap sweep circuit is

17. A _________ circuit converts an input step voltage into a ramp.

(a) bootstrap
 (b) Phantastron
(c) Miller
(d) RLC
18. A ________ circuit converts a pulse input into a ramp.
(a) bootstrap
(b) Phantastron
(c) Miller
(d) RLC
19. The _________ networks may be used to improve the linearity of
Miller and bootstrap circuits.
(a) RLC series
(b) RLC parallel
(c) compensating
(d) linear
20. The expression for slope error in miller bootstrap circuit is

21. A bootstrap sweep circuit employs

(a) no feedback
(b) positive feedback
(c) negative feedback
(d) none of these
22. When resistances are considered, to obtain a linear current sweep
______ voltage is to be applied across an inductor.
(a) step
(b) ramp
(c) trapezoidal
(d) rectangular
23. _________ currents are required for magnetic deflection applications.
(a) linearly varying
(b) nonlinearly varying
(c) constant
(d) none of these
 PROBLEMS
5.1 The transistor bootstrap circuit shown in Figure 5.18 has the
following parameters: VCC = 15 V, VEE = 15 V, RB = 40 k, R = 12
k, RE = 5 k. C = 0.0025 F, C1 = 0.25 F and CB that must be
taken as arbitrarily large. The input gate has an amplitude of 1.5 V and
a width of 50 s. The transistor parameters are hFE = hfe = 60, hie = 2
k, 1/hoe = 10 k, hre = 10–4, ICBO = 0, and the forward-biased
junction voltage is negligible. The diode is ideal. (a) Plot the gate
voltage, collector current iC1 and the output voltage vo. (b) Evaluate
the sweep speed and the amplitude of the sweep at its maximum value.
(c) Find the time it takes to discharge C at the end of the sweep, the
peak voltage change across C1, the time required to replace the lost
charge, and the slope error.
5.2 In the transistor bootstrap circuit of Figure 5.18, VCC = 30 V, VEE =
–15 V, RE = 10 k, R = 15 k, RB = 150 k, C = 0.05 F, and C1 =
50 F. The gating waveform has a duration Tg = 250 s. The
transistor parameters are hie = 1.1 k, hre = 2.5  10–4, hfe = 50, hoe
= 1/40 k. (a) Draw the waveforms of iC1 and vo labelling all current
and voltage levels. (b) What is the slope error of the sweep? (c) What is
the sweep speed and the maximum value of the sweep voltage? (d)
What is the retrace time Tr for C to discharge completely? (e) Calculate
the recovery time T1 for C1 to recharge completely.
5.3 The circuit of Figure 5.18 has the following parameters: VCC = 22 V,
VEE = –12 V, RE = 12 k, R = 8 k and Tg = 650 s. The transistor h
parameters are hfe = 50, hie = 1.1 k, hre = 2.5  10–4 and hoe = 1/40
k. A 22 V sweep in 500 s is desired. (a) Find a reasonable value for
RB. (b) Calculate C. (c) Calculate es assuming C1 as arbitrarily large.
(d) Choose C1 so that es is increased by no more than 8 per cent over
its value in part (c). (e) Calculate the retrace time Tr for C to discharge
 completely at the end of the gating waveform. (f) Calculate the
recovery time T1 for C1 to recharge completely.
5.4 Design a transistor boot strap ramp generator to provide an output
amplitude of 10 V over a time period of 2.5 mS. The input signal is a
negative going pulse with an amplitude of 5 V and a pulse width of 2.5
mS and the time interval between pulses is 0.5 mS. The load resistance
is 2 k and the ramp is to be linear within 1.5%. The supply is to be
within 18 V. Take hfe(min) = 60.
5.5 Find the component values of a boot strap sweep generator, given
VCC = 20 V, Ic(sat) = 4 mA and hfe(min) = 25. Take VCE(sat) = 0.3 V,
VBE(sat) = 0.7 V, VEE = –10 V.
5.6 In the circuit shown in Figure 5.26(a), L = 250 mH and it is required
that the current in L increases from zero to 150 mA in 1.0 ms. (a) Find
VCC. Assume RL = 0 and VCE(sat) = 0. (b) If Rd consisting of the
diode resistance alone is 20 , draw the waveforms of iL and vCE
indicating voltage levels and time constants. (c) If the transistor can
withstand a collector-to-emitter voltage of 50 V, what is the maximum
value of Rd that may be used? What is the recovery time?
5.7 In the circuit shown in Figure 5.26(a), VCC = 22 V, L = 250 mH. The
yoke resistance RL = 25 , RCS = 10  and Rd = 250 . (a) For a 500
s sweep, draw the waveforms of iL and vCE, indicating voltage levels
and time constants. (b) Calculate the slope error of the sweep.
 Chapter 6
Synchronization and
Frequency Division

A pulse or digital system may involve several different basic waveform

generators and the system may require that all these generators be operated
synchronously—in step with one another, i.e. each one of them arrives at
some reference point in the cycle at exactly the same time. Two or more
waveform generators are said to operate in synchronism if each one of them
arrives at some reference point in its cycle at the same time.
Synchronization is the process of making two or more waveform generators
arrive at some reference point in the cycle at exactly the same time.
Synchronization may be on a one-to-one basis or with frequency division.
Synchronization is said to be on a one-to-one basis if all the generators
operate at exactly the same frequency and arrive at some reference point in
the cycle exactly at the same time. Synchronization is said to be with
frequency division if the generators operate at different frequencies which
are integral multiples of each other but arrive at some reference point at the
same time. The two processes, i.e. (i) synchronization and (ii)
synchronization with frequency division are basically very nearly alike and
no clear-cut distinction can be drawn between them. Counting circuits are
an example of frequency division.

6.1 PULSE SYNCHRONIZATION OF

RELAXATION DEVICES
Relaxation circuits are circuits in which the timing interval is established
through the gradual charging of a capacitor, the timing interval being
terminated by the sudden discharge (relaxation) of a capacitor. The
multivibrator, the sweep generator, the blocking oscillator which we have
discussed in earlier chapters are examples of relaxation circuits. All these
circuits have in common a timing interval and a relaxation (or recovery)
interval and each exists in an astable or monostable form. The mechanism
of synchronization and frequency division is the same for all these devices.
In the monostable circuits the matter of synchronization is a trivial one.
The monostable circuit normally remains in its quiescent condition and a
single cycle of operation is initiated by the application of a triggering pulse.
The only requirement is that the interval between triggers should be larger
than the timing interval and the recovery period should be combined.
Figure 6.1 shows an arrangement for pulse synchronization of a sweep
generator using UJT. In the absence of an external synch. signal, the
capacitor stops charging when the voltage vC reaches the peak or
breakdown voltage VP of the negative-resistance device. Thereafter, the
capacitor discharges abruptly through the negative resistance device UJT.
When the capacitor voltage vC falls to the valley voltage VV, the UJT goes
OFF and the capacitor begins to recharge. A negative pulse applied at the
base B2 of the UJT will lower VP. In fact, any current-controlled negative-
resistance device such as a silicon-controlled switch, thyristor, etc. can be
used in place of the UJT. In such a case, a positive pulse applied at the gate
or base will lower the breakdown voltage.

Figure 6.1 A sweep generator with synchronization signal.

 Figure 6.2(a) shows the situation which results when synchronizing
pulses are applied. The effect of the synchronization pulse is to lower the
peak or breakdown voltage VP for the duration of the pulse. A pulse train of
regularly-spaced pulses is shown in Figure 6.2(a), starting at an arbitrary
time t = 0. The first several pulses have no influence on the sweep
generator, because the amplitude of the sweep at the occurrence of the pulse
plus the amplitude of the pulse is less than VP. Hence, the sweep generator
runs unsynchronized. Eventually, however, the exact moment at which the
UJT goes ON is determined by the instant of occurrence of a pulse [at time
T in Figure 6.2(a)] as is also each succeeding beginning of the ON interval.
From this point onwards, the sweep generator runs synchronously with the
pulses.
For synchronization to result, the time of occurrence of the pulse should
be such that it can serve to terminate the cycle prematurely. This
requirement means that the interval between pulses Tp, must be less than
the natural period T0 of the generator. Figure 6.2(b) shows the case in
which Tp > T0. Here synchronization of each cycle does not occur. The
pulses do serve to establish that four sweep cycles shall occur during the
course of three pulse periods, but synchronization of this type is normally of
no use. Figure 6.2(c) shows a case in which Tp < T0 as required, but
synchronization does not result because the pulse amplitude is too small. In
fact, even if the requirement Tp < T0 is met, synchronization cannot result
unless the pulse amplitude is at least large enough to bridge the gap between
the quiescent breakdown voltage and the sweep voltage vC.
 Figure 6.2 (a) Tp < T0: synchronization results, (b) Tp > T0: no synchronization results and
(c) Tp < T0 but amplitude of synch pulse is small, hence no synchronization results.

6.2 FREQUENCY DIVISION IN THE SWEEP

CIRCUIT
In Section 6.1 we saw that synchronization (1:1 division) occurs when Tp <
T0 and the amplitude of the pulse is sufficient to terminate each cycle
prematurely. Even if Tp < T0, if the pulse amplitude is too small, then each
cycle may not get terminated. Figure 6.3 shows a case in which the sweep
cycles are terminated only by alternate pulses marked “2”. The pulses
marked “1” would be required to have an amplitude at least equal to V1 if
they were to be effective. The pulses marked “2” are effective because they
occur closer to the time when the cycle would terminate of its own accord.
The sweep generator now acts as a divider, the division factor being 2, since
exactly one sweep cycle occurs for every two synchronizing pulses. If Ts is
the sweep generator period after synchronization, Ts/Tp = 2. Observe that
the amplitude Vs of the sweep after synchronization is less than the
unsynchronized amplitude Vs.
Suppose Tp in Figure 6.3 is progressively decreased, eventually a point
would be reached where even the alternate pulses would be too small in
amplitude to fire the switch device. At this point, if T0 > 3Tp, division by a
factor of 3 would result. If the condition T0 > 3Tp were not met, then again
there would be no synchronization. On the other hand, if the pulse is made
large enough, every (n + 1)st pulse will be in a position to ensure
synchronization before the nth pulse loses control.

Figure 6.3 Frequency division by a factor of 2 in a sweep generator.

The basic principle of synchronization and use for counting purposes of

other relaxation devices is same as the basic principle of synchronization of
the sweep generator.
6.3 OTHER ASTABLE RELAXATION
CIRCUITS
Blocking oscillator
Figure 6.4 shows the circuit diagram indicating the use of an RC-controlled
astable blocking oscillator to obtain frequency division by 4. Positive synch
triggers are introduced through a separate transistor Q2. These positive
triggers applied at the base of Q2, appear as negative triggers at the
common collector, and because of the polarity inversion of the transformer
windings they appear as positive triggers at the base of Q1. The waveform
v1 across the R1C1 combination of Figure 6.4 is shown in Figure 6.5(a).
During the interval tp the capacitor charges and the pulse is generated. At
the end of the pulse (at t = tp), v1 = V1, Q1 goes OFF and the capacitor
discharges through R1, and so the voltage v1 decreases. In the absence of
the synchronizing pulse, a new blocking oscillator pulse will form when v1
falls to the level VBB – Vg. In Figure 6.5(a) the injected triggers are shown
superimposed on the level VBB – Vg. The pulse number 4 occurs at this
time and has sufficient amplitude to cause a premature firing of the
oscillator. The oscillator therefore fires at a moment dictated by the
occurrence of a trigger and is not permitted to terminate its cycle naturally.
 Figure 6.4 Frequency division by an RC-controlled astable blocking oscillator.

Figure 6.5 The waveform v1 across R1C1 of Q1 showing frequency division by 4.

Astable multivibrator
The astable multivibrator shown in Figure 6.6 may be synchronized or used
as a divider by applying either positive or negative triggering pulses to
either transistor or to both the transistors simultaneously. These pulses may
be applied to the collector, base, or emitter. If for example, positive pulses
are applied to B1 or C2 or negative pulses to E1, these triggers may produce
synchronization by establishing the exact instant at which Q1 comes out of
cut-off. If negative pulses are applied to B2 or C1 or positive pulses to E2,
then when Q2 conducts, these pulses will be amplified and inverted and
appear as positive pulses at B1. Hence again the pulses may establish the
instant when Q1 comes out of cut-off. The negative pulses will not be
effective unless they succeed in moving the transistor at least slightly into
the active region. Therefore, such negative pulses must be large enough in
amplitude and be supplied from a low impedance source to divert enough
current from the base to draw the transistor out of saturation.

Figure 6.6 An astable multivibrator.

In Figures 6.7(a) and (b) are shown the waveforms for the case where
positive pulses are applied to one base, say B1. The division ratio is 6. The
cycle would normally have terminated at t = T0, when the base voltage
reached the cut-in level Vg, as shown by the dashed extension of the base
waveform in Figure 6.7(a). The cycle is prematurely terminated at the sixth
pulse since the amplitude of the sixth pulse added to the base waveform B1,
at the time of the sixth pulse, raises the base voltage above Vg. Observe that
while the complete multi period has been synchronized, the individual
portions have not been synchronized. Thus T in Figure 6.7(a) is the same
as it would be without synchronization because the waveform at B2 is
unaltered by the application of the synch pulses.
Figure 6.7 (a) and (b) base waveforms for division by 6 through the application of positive pulses to
one base. (c) and (d) base waveforms for division by 5 through the application of negative
pulses to both bases.
 Figures 6.7(c) and (d) show the base waveforms for the case where
negative pulses are applied to both multi bases simultaneously. Here the
division ratio is 5. Both timing portions of the multi waveform are
synchronized and are necessarily of unequal duration since the division
ratio is an odd number. The positive pulses superimposed on the
exponential portions of the waveforms result from the combination of the
negative pulses applied directly and the inverted and amplified (hence
positive and larger) pulses received from the other transistor.
A special situation of interest is illustrated in Figure 6.8. Here positive
pulses are being applied to B1 through a small capacitor from a low-
impedance source. During the time when Q1 is conducting, the base draws
current at each input pulse. At the end of the pulse the input capacitor
discharges, giving rise to a negative overshoot. Alternatively, we may say
that during the conduction period of Q1, the pulse input time constant is
small and the input pulse is quasi differentiated. The negative overshoot is
amplified and inverted by Q1 and appears at Q2 as a positive overshoot,
which may then serve to mark the end of the cut-off period of Q2. Hence
the net result is that both portions of the multi cycle have been synchronized
without the need for applying pulses to both transistors simultaneously.
Observe that one portion of the cycle is terminated at the leading edge of a
synch. pulse and the second portion is terminated at the trailing edge of
another pulse.
Figure 6.8 Synchronization of both portions of astable multi waveform by applying positive pulses to
one base through a small capacitance from a low impedance source. Illustrating
synchronization at B1 resulting from pulse overshoot due to differentiation of input pulse.

6.4 MONOSTABLE RELAXATION CIRCUITS

AS DIVIDERS
Figure 6.9(a) shows the use of a monostable relaxation device, a
monostable multivibrator for frequency division. The input pulses may be
applied at B1 or C1 depending on the polarity. A coupling diode may be
used to minimize the reaction of the multivibrator on the pulse source. The
waveforms of Figure 6.9(b) show the voltage at B1 and B2. Each fourth
pulse causes a transition of the multivibrator, the remaining pulses
occurring at a time when they are ineffective. Observe that while the total
multivibrator cycle consisting of timing portion and recovery period is
synchronized, the two separate portions are not synchronized.
Figure 6.9 (a) Monostable multivibrator for frequency division, (b) waveform at B2 with no pulse
overshoot and (c) waveform at B2 with pulse overshoot.
 If positive pulses are applied, say, directly at B1 through a small
capacitance from a low impedance source, the pulses are quasi
differentiated during the conduction period of Q1. The negative overshoot is
amplified and inverted by Q1 and appears as positive overshoot at B2, and
it may serve to terminate the cycle prematurely as shown in Figure 6.9(c).
In this case, the two portions of the multivibrator waveform would be
synchronized. Also, the counting ratio will change with increasing
amplitude of pulse input. If the overshoot is large enough, the exponential
will be terminated by the overshoot at pulse 2 or pulse 1 and in which case
the counting ratio will become respectively 3 or 2. Finally, with a large
overshoot, the timing portion will terminate at the trailing edge of pulse 4,
and the circuit will not operate as a multivibrator at all.

6.5 PHASE DELAY AND PHASE JITTERS

The delay between the input pulse to a divider and the output pulse is
referred to as phase delay. It results from the finite rise time of the input
trigger pulse and the finite response time of the relaxation time devices. The
phase delay may vary with time due to variations in device characteristics,
supply voltages, etc.
Occasionally some extraneous signal may be coupled unintentionally into
the divider. Such a signal may have an influence on the exact moment at
which a basic waveform, say, reaches cut-off. In this case the phase delay
may be subject to periodic variations. All these factors which affect the
phase delay give rise to what is termed phase jitter. In large-scale counters
consisting of many stages, the phase jitter is compounded. In many
applications, phase jitter is of no particular consequence but it constitutes an
important difficulty in connection with nanosecond pulses.
A method for achieving division without phase jitter is illustrated in
Figure 6.10. The train of regularly spaced input pulses (I) is applied to the
divider input. The output of the divider consists of the pulses (D). These
latter pulses trigger a gating waveform generator, say, a monostable
multivibrator which provides a gate of duration Tg adequate to encompass
each pulse labeled ‘1’. This waveform is applied to a sampling gate which
opens for a time Tg. The input pulse train is sampled and the output
waveform then consists of each pulse labeled ‘1’. The condition for proper
transmission is Tp < Tg < 2Tp, i.e. it is enough if Tg is longer than the
interval between the pulses Tp and shorter than the interval between the
alternate pulses.

Figure 6.10 Block diagram and waveform for a divider without phase jitter.

6.6 SYNCHRONIZATION OF A SWEEP

CIRCUIT
WITH SYMMETRICAL SIGNALS
In the previous sections we discussed the phenomenon of synchronization
only for the case of pulse-type synchronizing signals. It was assumed that
the synchronizing signal consists of a train of waveforms with leading
edges which rise abruptly. In this section we will consider the case in which
the voltage variation is gradual rather than abrupt. The mechanism of
synchronization for a gradually varying synch signal is very nearly identical
for all types of relaxation oscillators. Let us consider the synchronization of
a ramp generator for illustration.
Sinusoidal synchronization signal
Consider the sweep generator of Figure 6.1, which uses a current-controlled
negative-resistance device, a UJT, as a switch. Let us assume for simplicity
that as a result of the synchronization signal, the breakdown voltage of the
negative-resistance device varies sinusoidally. The polarity and the precise
waveform required of the synchronization signal for such sinusoidal
variation will depend on the particular negative-resistance device being
employed. It is to be noted, however, that the circuit behaviour to be
described does not depend on the sinusoidal nature of the breakdown
voltage variation. The results depend only on the relatively gradual
variation of the breakdown voltage in contrast to the abrupt variation with
pulse-type sync signals.
In Figure 6.11, the dashed voltage level VPO is the breakdown voltage of
the negative-resistance device in the absence of a synch signal and the solid
curve VP is the breakdown voltage in the presence of the synchronization
signal. The sync signal has a period T, and the natural period is T0.
Consider that synchronization has been established with T = T0. Such
synchronization requires that the period of the sweep shall not be changed
in the sync signal. Hence the voltages which mark the limits of the
excursion of the sweep voltage must remain unaltered. The sweep cycle
must therefore continue to terminate at VPO. This result, in turn, means that
the intersection of the sweep voltage with the waveform VP must occur as
shown in Figure 6.11, at the time when VP crosses VPO, at the points
labeled O in the figure. It is possible that the sweep will terminate at the
points marked O in the figure.

Figure 6.11 The timing relationship that must exist between VP and the sweep
voltage in a synchronized sweep when T = T0.

In the case of pulse synchronization, we noted that synchronism could

result only if the synch signal period was equal to or less than the natural
period. This feature resulted from the fact that a pulse could serve reliably
only to terminate a timing cycle prematurely and not to lengthen it. In the
case of synchronization with symmetrical signals, however, synchronization
is possible both when T < T0 and when T > T0. The timing relationship
between the sweep voltage and the breakdown voltage for both the cases is
shown in Figure 6.12(a). The sweep voltage drawn as a solid line has a
natural period T0 > T. The sweep voltage meets the VP curve at a point
below VPO and is consequently prematurely terminated. The sweep voltage
drawn as a dashed line has a natural period T0 < T. This sweep meets
the VP curve at a point above VPO and is consequently lengthened. In each
case the synchronized period Ts equals the period T.

Figure 6.12 (a) Shows the timing of the sweep voltage with respect to VP for a case in which
T < T0 = T0 (dashed line) and (b) pertains to the general case, T  T0.

The general situation may be described by reference to Figure 6.12(b).

When T = T0, the sweep is terminated at point O, leaving the period
unaltered. When T > T0, the sweep terminates at a point such as X—
between O and the positive maximum A. When T < T0, the sweep
terminates at a point such as Y—between O and the negative maximum B.
When the period T is such that the sweep terminates either at the point A or
B, the limits of synchronization have been reached since at A the sweep
period has been lengthened to the maximum extent possible whereas at B
the shortening is at maximum.
6.7 SINE WAVE FREQUENCY DIVISION WITH
A SWEEP CIRCUIT
In Section 6.6, we discussed synchronization of a sweep generator using a
symmetrical (sinusoidal) signal. The operation of a sweep circuit as a
divider is an extension of the process of synchronization. Figure 6.13 shows
the operation of the sweep circuit for frequency division. The solid lines in
the figure show the sweep and synchronizing waveforms for division by a
factor of 4. This case is one in which the natural period T0 is slightly
smaller than 4T. The sync signal changes the sweep period from T0 to Ts,
where Ts = 4T. An increase in amplitude of the sync signal can change the
division (counting) ratio from 4 to 3 as shown by the dashed sweep and
synchronizing waveforms. A general observation that can be made with a
sweep circuit as a counter is that if the sweep terminates on the descending
portion of the VP curve and if as a consequence the period T0 is lengthened
or shortened to Ts, where Ts = nT, then the circuit will operate stably as an
n:1 counter.
Figure 6.13 Frequency division using a sweep circuit. Illustrating the change in frequency division
ratio with synch signal amplitude.

Earlier it was conveniently assumed that the range of synchronization (or

counting) extends from the point where the sweep intersects the VP curve at
a maximum to the point where the intersection is at a minimum of the VP
curve. This normally holds only for small values of sync voltage, but may
not hold when the sync amplitude is comparable to the sweep amplitude. In
Figure 6.13, we can observe that the sweep will never be able to terminate
at a maximum of VP, because to do so, it is required that the sweep must
first cross the previous negative excursion of the VP waveform.
Figure 6.14 illustrates a case (dashed sweep) where the sync amplitude, in
principle, is just large enough to cause 1:1 synchronization. The actual
sweep waveform, however, as shown consists of alternate long and short
sweeps. So, when a sweep is used in connection with a scope, it is advisable
always to use as small a sync signal as possible.

Figure 6.14 Illustrating a possible result of excessive amplitude of the sync signal in a sweep.

Sine wave synchronization may be compared with pulse synchronization

as follows:

1. Even though for small sync signals, synchronization holds over a small
range in the neighbourhood of integral relations between T and T0 for
both pulses and sine waves, pulse synchronization persists for variation
of T0/T in only one direction, whereas sine-wave synchronization
persists for variation of T0/T in either direction.
2. In both cases, the range of synchronization increases with the
increasing sync signal amplitude.
3. With pulses, for large sync signal amplitudes, synchronization holds
for all values of T0/Tp > 1, whereas with sine waves, however, there is
no guarantee that synchronization in a useful fashion occurs for all
values of T0/T > 1.

SHORT QUESTIONS AND ANSWERS

1. What do you mean by synchronization?
A. Synchronization is the process of making two or more waveform
 generators arrive at some reference point in the cycle at exactly the
same time.
2. How many types of synchronization are there? Name them.
A. There are two types of synchronization. They are (a)
synchronization on a one-to-one basis and (b) synchronization with
frequency division.
3. When do you say that two or more waveform generators are
synchronized?
A. Two or more waveform generators are said to be synchronized, if
all of them arrive at some reference point in the cycle at exactly the
same instant of time.
4. What do you mean by synchronization on a one-to-one basis?
A. Synchronization on a one-to-one basis means all the generators
operate at exactly the same frequency and arrive at some reference
point in the cycle at exactly the same instant of time.
5. What do you mean by synchronization with frequency division? Give
an example of synchronization with frequency division.
A. Synchronization with frequency division means, the generators
operate at different frequencies which are integral multiples of each
other but arrive at some reference point at the same time. Counting
circuits are an example of synchronization with frequency division.
6. Distinguish between synchronization and synchronization with
frequency division.
A. The two processes, i.e. (a) synchronization and (b) synchronization
with frequency division are basically very nearly alike and no clear cut
distinction can be drawn between them.
7. What do you mean by a relaxation circuit? Give a few examples of
relaxation circuits.
A. A relaxation circuit is a circuit in which the timing interval is
established through the gradual charging of a capacitor, the timing
interval being terminated by the sudden discharge (relaxation) of a
capacitor. The multivibrators time-base generators, blocking oscillators
etc. are examples of relaxation circuits.
8. Name some negative-resistance devices used as relaxation oscillators.
A. Some negative-resistance devices which are used as relaxation
 oscillators are: the UJT, the p-n-p-n diode, the silicon controlled
switch, the thyristor, etc.
9. What do you mean by phase delay?
A. The delay between the input pulse to a divider and the output pulse
is referred to as phase delay.
10. Why does phase delay occur?
A. The phase delay results from the finite rise time of the input trigger
pulse and the finite response time of the relaxation time devices.
11. Why does the phase delay vary?
A. The phase delay may vary with time due to variations in device
characteristics, supply voltages, etc.
12. What do you mean by phase jitter?
A. The periodic variations in phase delay due to the extraneous signals
is termed phase jitter.
13. Compare sine-wave synchronization with pulse synchronization.
A. Sine-wave synchronization may be compared with pulse
synchronization as follows.
1. Even though for small synch signal, synchronization holds over a
small range in the neighborhood of integral relations between T and T0
for both pulses and sine waves, pulse synchronization persists for
variation of T0/T in only one direction, whereas sine-wave
synchronization persists for variation of T0/T in either direction.
2. In both cases, the range of synchronization increases with increasing
synch signal amplitude.
3. With pulses, for large synch signals amplitudes, synchronization
holds for all values of T0/Tp > 1, whereas with sine waves, however,
there is no guarantee that synchronization in a useful fashion occurs
for all values of To/T > 1.
14. What is the condition to be met for pulse synchronization?
A. The condition to be met for pulse synchronization is that the time of
occurrence of the pulse should be such that it can serve to terminate
the cycle prematurely. This requirement means that the interval
between pulses TP must be less than the natural period T0 of the
generator.
 REVIEW QUESTIONS
1. How does the synch signal affect the frequency of operation of the
sweep generator?
2. What is the condition to be met for pulse synchronization of
monostable circuits?
3. With the help of a neat circuit diagram and waveforms, explain
synchronization of a sweep generator with pulse signals.
4. With the help of neat waveforms, explain frequency division with
respect to a sweep circuit.
5. With the help of a circuit diagram and waveforms, explain frequency
division by an astable blocking oscillator.
6. With the help of a circuit diagram and waveforms, explain frequency
division by an astable multivibrator.
7. Explain the use of a monostable relaxation device as a divider.
8. Explain the synchronization of a sweep circuit with symmetrical
signals.
9. With the help of neat waveforms, explain sine wave frequency division
with a sweep circuit.

FILL IN THE BLANKS

1. Two or more generators are said to be running __________ if all of
them arrive at some reference point in the cycle at exactly the same
instant of time.
2. Synchronization may be on a __________ or may be with
__________.
3. When two generators produce waveforms at different frequencies, it is
essential for proper synchronization that the frequency of one
generator is an __________ of that of the other generator.
4. When generators with equal frequencies run in synchronism, the
synchronization is said to be on a __________.
5. If synchronization is achieved with different frequencies, i.e. one
frequency being n times the other, then it is termed __________.
 6. Counting circuits are an example of synchronization with __________.
7. The circuits in which the timing interval is established through the
gradual charging of a capacitor, the timing interval being terminated by
the sudden discharge of a capacitor, are called __________.
8. The multivibrators, time-base generators, blocking oscillators, etc. are
examples of __________.
9. Synchronization with pulse signals is possible only if __________.
10. In case of synchronization with symmetrical signals, synchronization
is possible for both _______ and __________.
11. In pulse synchronization as well as synchronization with symmetrical
signals, ______ increases with increasing _________ .
12. Between the instant of occurrence of the pulse which prematurely
terminates the cycle and the instant of the change of state of the
oscillator there is a certain time delay. This is termed __________.
13. The several factors which affect the phase delay give rise to
__________.
14. Any _______ controlled negative resistance device can be used as a
relaxation circuit.

OBJECTIVE TYPE QUESTIONS

1. Two or more generators are said to be running _________ provided, all
generators arrive at some reference point in the cycle simultaneously.
(a) synchronously
(b) asynchronously
(c) symmetrically
(d) asymmetrically
2. When two generators produce waveforms at different frequencies, it is
essential for proper synchronization that the frequency of one
generator is an ________ of that of the other generator.
(a) integral multiple
(b) derivative
(c) integral
(d) additive
3. When generators with equal frequencies run in synchronism, the
synchronization is said to be on a
(a) one-to-one basis
(b) equal basis
(c) any-to-one basis
(d) any-to-any basis
4. If synchronization is achieved with different frequencies, i.e. one
frequency being thrice the other, then it is termed
(a) synchronization with frequency multiplication
(b) synchronization with frequency division
(c) multiple synchronization
(d) none of these
5. A divider circuit with a division factor n can be built by making
(a) T0 < nTp
(b) T0 = n Tp
(c) T0 > n Tp
(d) T0  n Tp
6. The time interval between the time of occurrence of the pulse which
prematurely terminates the cycle and the instant of the change of state
of the oscillator is termed as
(a) total phase delay
(b) phase jitters
(c) magnitude delay
(d) none of these
7. The several factors which affect phase delay give rise to
(a) total phase delay
(b) phase jitters
(c) magnitude delay
(d) none of these
 Chapter 7
Sampling Gates

Sampling gates, also called linear gates, transmission gates or selection

circuits, are trans-mission circuits in which the output is an exact
reproduction of the input during a selected time interval and is zero
otherwise. The time interval for transmission is selected by an externally
impressed signal which is called the gating signal and is usually rectangular
in wave shape. Sampling gates may be unidirectional sampling gates or
bidirectional sampling gates. Unidirectional sampling gates are those which
transmit signals of only one polarity, and bidirectional sampling gates are
those which transmit signals of both the polarities.
Sampling gates are different from the logic gates. In logic gates there can
be any number of inputs and the inputs and outputs of the logic gates are
either pulses or voltage levels and the output is not a reproduction of the
input. The output of a sampling gate is an exact reproduction of the input
(whatever may be the shape of the input—be a pulse, square wave, sine
wave or any other waveform) during the selected time interval.

7.1 BASIC OPERATING PRINCIPLES OF

SAMPLING GATES
The basic operating principle of a sampling gate is illustrated in Figures
7.1(a) and (b). In Figure 7.1(a) the switch is normally open, but is in closed
position when the signal is transmitted. In Figure 7.1(b) the switch is
normally closed, but is in open position when the signal is transmitted.
These switches are normally electronic devices—diodes or transistors.
When the device is conducting, it acts as a closed switch and when it is not
conducting it acts as an open switch. Ideally, a closed switch should have
zero resistance and an open switch should have infinite resistance, but
semiconductor devices do not have infinite back resistance and their
forward resistances may lie in the range of several ohms. When such
devices are used as switches, there is no specific advantage of either the
series or the shunt switch position and the choice of the circuit depends
upon the particular application.

Figure 7.1 A sampling gate using (a) a series switch and (b) a shunt switch.

7.2 UNIDIRECTIONAL DIODE GATE

A unidirectional diode gate which transmits only the positive-going input
signals is shown in Figure 7.2. The gate signal, i.e. the signal which
determines the gating or transmission period is a rectangular waveform that
makes abrupt transitions between the two negative levels –V1 and –V2. The
gate signal is also called a control pulse, a selector pulse, or an enabling
pulse. When the gating signal is at its lower level –V2, the diode is heavily
back biased and there will be no output due to the input signal unless the
peak amplitude of the input signal is larger than the magnitude of this back-
biasing voltage. When the gate signal is at its upper level –V1 , a time-
coincident signal input pulse may be transmitted to the output. The effect of
the upper level of the gating signal on the output is illustrated in Figure 7.3.
The input signal is a +10 V pulse. In Figure 7.3(a), when the gate pulse has
–V2 = –20 V and –V1 = –10 V, there is no output pulse at all. In Figure
7.3(b), when –V2 = –20 V and –V1 = –5 V, the output is a +5 V pulse. In
Figure 7.3(c), when –V2 = –20 V and –V1 = 0 V, the output is a +10 V
pulse. In Figure 7.3(d), when –V2 = –20 V and –V1 = 5 V, the output is a 10
V pulse superimposed on a pedestal of +5 V. Actually the waveforms with
vertical edges shown in Figure 7.3 are unrealistic because the R1C1
network constitutes an integrating network for the gate waveform and
therefore the gating signal will have exponentially rising and falling edges
as shown in Figure 7.4. Hence this type of gate is not suitable for
transmitting a portion of a continuous waveform. However if the input is a
pulse of very short duration compared to the gate width, the input may be
transmitted satisfactorily.
 Figure 7.2 A unidirectional diode gate.

Figure 7.3 Illustrating the effect of control voltage (–V1) on gate output.
 The advantages of the unidirectional diode gate are:

1. It is extremely simple.
2. There is very little time delay through the gate.
3. The gate draws no current in its quiescent condition.
4. The gate can be easily extended into a multi-input OR circuit, with an
INHIBITOR or NOT terminal.

Figure 7.4 Distortion of the control waveform.

The disadvantages of the unidirectional diode gate are:

1. There will be interaction between the signal source and the control
voltage source.
2. The gate is of limited use because of the slow rise of the control
voltage at the diode.

7.3 UNIDIRECTIONAL DIODE GATES TO

ACCOMMODATE
MORE THAN ONE INPUT SIGNAL
Figure 7.5 shows a unidirectional diode sampling gate with two input
signals, but the circuit can be extended to larger number of inputs as well.
When the control signal is at its lower level, the gate transmits no inputs.
When the control signal is at its higher level, the gate acts as a capacitively-
coupled OR circuit. Hence, the negative level of the control pulse may be
considered as an inhibitor signal. So the circuit is a multi-input OR circuit
with an inhibition terminal. The drawback of this circuit is that as the
number of inputs increases, the loading on the control signal becomes
excessively heavy. This difficulty may be overcome by using one more
diode as shown in Figure 7.6. In this latter circuit the control output voltage
does not feed into the signal sources.

Figure 7.5 The unidirectional diode gate for more than one input signal.
 Figure 7.6 A two-input gate in which the signal sources do not load the control signal.

Figure 7.7 shows a diode gate which will transmit only when a number of
gate voltages occur simultaneously. A number of control signals vc1, vc2,
… are required. Let all the signals be at levels –V2 and –V1. When any one
of the control signals vc is at –V2, the point A is negative with respect to
ground by an amount and no part of the waveform is transmitted unless the
input signal is larger by this back-bias voltage at point A. When all the
control voltages are at –V1, the back-bias on the diode D0 is removed and
the signal is sampled. This circuit is an AND circuit.

Figure 7.7 A unidirectional gate which delivers an output only at a

coincidence of a number of control voltages.
 In all the gates discussed above, unless the upper level of the gating
waveform is exactly zero, either a portion of the input signal will not get
through the gate or else the transmitted signal will be superimposed on a
pedestal.
A gate whose response is not sensitive to the upper level of the control
voltage is shown in Figure 7.8. Initially in the absence of a gating signal at
the control terminals, diode D1 conducts and the consequent voltage drop
across R keeps the diode D0 back-biased. A positive-going gating signal
brings D1 to OFF state and the signal is sampled for the duration of the
control pulse.

Figure 7.8 A gate whose response is not sensitive to the upper level of the control voltage.

7.4 BIDIRECTIONAL SAMPLING GATES

USING TRANSISTORS
All the gates discussed so far have a limitation that they transmit signals of
only one polarity, i.e. either only positive signals or only negative signals.
Figures 7.9 and 7.10 show bidirectional gates, i.e. gates which can transmit
signals of either polarity, i.e. both positive and negative signals. In Figure
7.9, the signal voltage vs and the control voltage vc are applied through the
summing resistors R1 and R2 to the base of a transistor. The gating voltage
vc is a pulse waveform between the levels V1 and V2 and with a pulse width
tp equal to the desired transmission interval. When the gating signal is at its
lower level V2 , the transistor is well below cut-off. When the gating signal
is at its upper level V1 , the bias brings the transistor into the active region.
So, as long as the gating signal is at its upper level, signals of either polarity
appearing at the base will be sampled and will appear amplified at the
output. Hence the circuit of Figure 7.9 acts as a bidirectional gate.

Figure 7.9 A bidirectional gate using a transistor.

Figure 7.10 shows a bidirectional gate using two transistors which are
emitter coupled. In this, two separate bases are available for the signal and
gating voltages. When the gate signal vc is at its upper level, the transistor
Q1 is ON and the current through RE is large enough to raise the emitter
voltage to the point where Q2 is cut-off. With Q2 cut-off, there is no
response at the output for the input signal. When the control signal vc is at
its lower level, Q1 is cut off and Q2 is free to operate as an amplifier stage.
The signal vs appears at the output amplified. The signal may be applied
directly at the base as well.

Figure 7.10 An emitter-coupled bidirectional sampling gate.

7.5 REDUCTION OF PEDESTAL IN A GATE

CIRCUIT
In the gate circuits of Figures 7.9 and 7.10, initially the voltage level at the
output is VCC. When the gating signal is applied, the transistor draws
current and the output therefore establishes itself at a new quiescent level.
When a signal is applied, the output signal is superimposed on this new
quiescent level. So the output during the gating interval appears as shown in
Figure 7.11 where we see that the sampled portion of the signal is
superimposed on a pedestal.
 Figure 7.11 Pedestal associated with the sampling gates of Figures 7.9 and 7.10.

Figure 7.12 shows a symmetrical arrangement that suppresses the

pedestal to a great extent. Q1 is the gating transistor and Q2 is used to
minimize the pedestal. Gating voltages of opposite polarity are applied to
the transistor bases.

Figure 7.12 A sampling gate with provision to cancel the pedestal.

 During the transmission time tp, when the control signal is at its upper
level, Q1 conducts and Q2 is cut-off. A current flows from VCC through
RC and Q1. During the non-transmission time when the control signal is at
its lower level, Q1 is OFF and Q2 conducts and a current flows from VCC
through RC and Q2. The base voltages – VBB1 and – VBB2 and the gate
signal amplitude have been adjusted so that the two transistor currents are
identical and as a result the quiescent output voltage level will remain
constant.
If the gate waveform has a non-zero rise time, then the arrangement
shown in Figure 7.12 does not completely solve the problem of pedestal.
Assume that the gate pulse is large compared with the active region base-
voltage range, so that each transistor, when it is not conducting is biased far
below cut-off. Then when the gate voltage appears, Q2 will be driven to
cut-off before Q1 starts to conduct, whereas at the end of the gate, Q1 will
be cut-off before Q2 starts to conduct. Hence as a result of the gate signals
themselves, the output will appear as in Figure 7.13(b). The gated signal
voltage will appear superimposed on this waveform. If the gate waveform
rise time is small compared with the gate duration, these spikes may not be
very objectionable.
Figure 7.13 (a) The gating waveform of Figure 7.12 drawn with non-zero rise time and (b) Spikes
which may occur in the output circuit of Figure 7.12 due to the gating waveform with non-
zero rise time.

The circuit of Figure 7.12 used to eliminate pedestal has the following
drawbacks.

1. If the gating waveforms have definite rise and fall times, two sharp
spikes are generated at the output.
2. There is a continuous flow of current through RC and so it has to
dissipate a lot of heat.
3. The circuit is complicated. It requires two bias voltages, i.e. –VBB1
and –VBB2 and two control signal sources which are complements of
each other.

7.6 BIDIRECTIONAL DIODE SAMPLING

GATE
Figure 7.14 shows a bidirectional sampling gate using diodes. The diode
sampling gates have the basic advantage of linearity of operation. Also they
can be adjusted easily to obtain zero pedestal. The gate shown in Figure
7.14 consists essentially of two gates of the type shown in Figure 7.2 with
the modification that C1 is replaced by a resistor. The circuit is redrawn in
the form of a bridge in Figure 7.15. Two symmetrical gating voltages +vc
and –vc are now required. When the control signals are at the levels +Vn
and –Vn respectively as observed from Figure 7.14, the signal at A is –Vn
and the signal at B is +Vn. So both the diodes D1 and D2 are reverse biased
and hence no signal transmission takes place. When the control signals are
at the levels Vc and –Vc, i.e. when the signal at A is +Vc and the signal at B
is –Vc, both the diodes D1 and D2 are ON and then a sample of vs appears
at the output. If the diodes are identical in characteristics because of the
symmetry in the circuit, no pedestal can appear at the output in response to
the control voltages. For simplicity, the impedance of the signal source is
neglected in the discussion below.

Figure 7.14 A bidirectional diode sampling gate.

 Figure 7.15 Bidirectional diode sampling gate of Figure 7.14 redrawn in the form of a bridge
network.

Gain
The gain of the sampling gate defined as the ratio vo/vs during the
transmission interval can be easily calculated from the equivalent circuit of
Figure 7.16 which is derived from that of Figure 7.14 through the
application of Thevenin’s theorem. R1, R3, and a in Figure 7.16 are defined
as
 Figure 7.16 An equivalent circuit for the bidirectional diode gate of Figure 7.15.

Each diode has been replaced by its piece-wise linear model, i.e. a battery
of Vg equal to the offset voltage in series with a resistance Rf equal to the
diode forward resistance.
From the equivalent circuit we can observe that the offset voltages Vg and
Vg and the control voltage components (1 – a)vc and (1 – a)vc try to send
equal currents in opposite directions in RL and hence the net current due to
them is zero. The open-circuit voltage at P with respect to ground is avs
(because all other sources are to be neglected) and the Thevenin’s
equivalent resistance at P with respect to ground is R3/2. The Thevenin’s
equivalent circuit is shown in Figure 7.17. From this circuit, the output
voltage is given by
 Figure 7.17 Thevenin’s equivalent circuit of Figure 7.16.

The control voltage Vc

When the signal voltage attains a maximum value Vs, a minimum control
voltage (Vc)min is required to ensure that the diodes D1 and D2 continue to
conduct. Initially, in the presence of control voltages Vc and –Vc, diodes D1
and D2 conduct equal currents. Hence the load current is zero and the
pedestal is zero. If vs is a positive-going signal, the current in D2 decreases
and hence the difference current flows through RL. As vs continues to
increase, eventually the current in D2 becomes zero, i.e. D2 will be cut-off.
To compute (Vc)min, assume that D2 has just stopped conducting. Then
in the equivalent circuit of Figure 7.16 the voltage across R3 associated
with D2 is zero. Neglecting Vg the output voltage must be equal to the
voltage
 This is the minimum value of control voltage required to ensure signal
transmission over the full range of the input signal by keeping both the
diodes conducting. The value of (Vc)min decreases with increasing RL as
seen from the above expression.
The control voltage Vn

A minimum control voltage (Vn)min is required to keep both the diodes

OFF when no sampling takes place. The value of (Vn)min may be
calculated as follows. When both the diodes are reverse biased, point P in
Figure 7.16 is at ground potential. Hence the voltage across D1 is

aVs – (1 – a)Vn, where Vn is the magnitude of the voltage for the lower
level of vc.

For D1 to be reverse biased, this voltage must be either negative or in

worst case zero. Equating it to zero,
In practice, for safety reasons, larger values of (Vc)min and (Vn)min are
chosen compared to the above minimum values. A larger value of (Vc)min
improves linearity in addition to safety.

7.7 FOUR-DIODE SAMPLING GATE

Some of the disadvantages of the two-diode sampling gate of Figure 7.14
are:

1. Its gain is low.

2. It is sensitive to control voltage imbalance.
3. There is a possibility that (Vn)min may be excessive.
4. There may be appreciable leakage through the diode capacitance.

The four-diode sampling gate shown in Figure 7.18 improves these

features. This is obtained by adding two more diodes to the two-diode
sampling gate of Figure 7.14. Two balanced voltages +V and –V are also
required.
 Figure 7.18 A four-diode gate.

The operation of the four-diode gate is as follows. When the control

voltages are Vc and –Vc respectively, the diodes D3 and D4 are reverse
biased. Because of the voltages +V and –V, the diodes D1 and D2 conduct
and the signal source is coupled to the load through the resistors R2 and the
conducting diodes D1 and D2. Under these circumstances, the control
voltages are disconnected from the gate by the reverse-biased diodes D3
and D4, so an imbalance in control signals cannot result in a pedestal at the
output.
When the control voltages are Vn and –Vn, the diodes D4 and D3 conduct
and the points P2 and P1 are clamped to these voltages. So, the diodes D1
and D2 are reverse biased. Under these circumstances, the output is zero.
Let us now compute the gain A and the required minimum values of V,
Vc, and Vn.
 During transmission, diodes D3 and D4 are OFF and the circuit of Figure
7.18 is identical to the circuit of Figure 7.14 except that the voltages Vc and
–Vc are replaced by +V and –V respectively. Hence the gain of this circuit is
the same as the gain of the gate of Figure 7.14 and is given by

Also, the Vmin of this circuit is the same as the (Vc)min of the gate of
Figure 7.14 and is given by

The voltage (Vc)min is computed as follows. Assuming that Rf << RL, for
a positive going signal of amplitude Vs, the voltage at point P1 is the same
as the output voltage vo given by AVs where A is the circuit gain. If the
diode D3 is to continue to be reverse biased, Vc must be at least equal to the
voltage at P1. Hence,

(Vc)min = AVs

The voltage Vn must be selected not only to keep the transmission diodes
D1 and D2 reverse biased but also to keep the clamp diodes D3 and D4
conducting in the presence of the signal Vs. The voltage at P2 for a positive
signal Vs and hence the minimum value of Vn by applying superposition
theorem is
7.8 FOUR-DIODE GATE (ALTERNATIVE
FORM)
Figure 7.19 shows the alternative form of the four-diode gate shown in
Figure 7.18. In this gate, supply voltages +V and –V are not present but to
avoid pedestal, Vc and –Vc must be balanced. The operation of the circuit is
as follows. When the control voltages are at the levels Vc and –Vc, all the
four diodes are forward biased and so the source is connected to the load
through two parallel paths each consisting of two diodes in series. So signal
transmission takes place. When the control voltages are at the levels Vn and
–Vn, all the four diodes are OFF and so no signal transmission takes place.

Figure 7.19 An alternative form of a four-diode gate.

The required voltages Vc and –Vc depend on the amplitude Vs of the

signal and are determined by the condition that the current be in the forward
direction in each of the diodes D1, D2, D3, and D4. The current in each
diode consists of two components, one due to Vc as indicated in Figure
7.20(a) and the other due to Vs as indicated in Figure 7.20(b). The current
due to Vc is Vc/2RC and is in the forward direction in each diode, but the
current due to Vs is in reverse direction in D3 (between P1 and P4) and in
D2 (between P3 and P2). The larger reverse current is in D3 and equals
Vs/RC + Vs/2RL, and hence this quantity must be less than Vc/2RC. The
minimum value of Vc occurs when

The above derivation assumes that Rf << RC or RL.

Figure 7.20 Diodes in Figure 7.18 are replaced by short circuits:

(a) the currents due to Vc and (b) the currents due to Vs.

A balancing divider may be inserted between D3 and D4 so as to give

zero output for zero input. If the divider is assumed to be set at its mid-
point, if its total resistance is R, and if R and Rf are both << RC or RL, then
 The voltage (Vc)min may become excessive if the resistance R is too
large relative to Rf. Under these circumstances the second equation is to be
used.
If RC and RL are large compared with Rf and R, then the gain will be very
close to unity (i.e. A  1) because the points P3 and P4 in Figure 7.20(b)
are approximately at the same potential.
The diodes in Figure 7.19 are to remain reverse biased when the control
voltages are Vn and –Vn. If the signal has a peak amplitude Vs, then it is
required that at a minimum

(Vn)min = Vs

EXAMPLE 7.1 For the four-diode gate shown in Figure 7.19 with a divider
resistance R used, Vs = 25 V, Rf = 20 , RL = RC = 200 k, and R = 100 .
Find (Vc)min, A, and (Vn)min.

Solution: When a divider resistance is used,

EXAMPLE 7.2 In the circuit of Figure 7.19, consider that RL = RC = 100
k and that R2 = 2 k, Rf = 50 . For Vs = 25 V, compute A, Vmin, and
(Vc)min. Compute (Vn)min for V = Vmin.

7.9 SIX-DIODE SAMPLING GATE

Figure 7.21 shows a six-diode sampling gate. This gate combines the
features of the four-diode gates of Figures 7.18 and 7.19. When the control
signals are at the levels Vn and –Vn, the diodes D6 and D5 conduct and the
points P2 and P1 are clamped to these levels. Hence D4 and D3 are back
biased and no signal transmission takes place. In the six-diode gate, the
control signals need not be balanced. When the control signals are at levels
Vc and –Vc, the diodes D5 and D6 are OFF and the six-diode gate becomes
equivalent to the four-diode gate of Figure 7.19. The only change is that the
control voltages Vc and –Vc of Figures 7.19 are replaced by the fixed
voltages V and –V. The signal transmission takes place. Hence the
minimum value of V, assuming that Rf << RL or RC, is given by

and if a balanced voltage-divider resistance R is used, then Vmin is given by

In the example cited above, (Vc)min for the four-diode gate or Vmin for
the six-diode gate may be as large as 168.75 V for a 25 V signal. In such a
case the advantage of the six-diode gate is that such a large voltage need
appear only as a fixed voltage but not as a control signal.
From Figure 7.21 we see that if the clamping diodes D5 and D6 are to
remain reverse biased for signal amplitude Vs, then Vc must be at least
equal to (Vc)min = Vs. On the other hand, if the points P1 and P2 are
clamped at voltage Vn, then none of the transmission diodes will conduct
until Vs exceeds Vn. Hence the minimum required value of Vn is (Vn)min =
Vs.

.........................................(Vc)min = (Vn)min = Vs

Again if RC and RL >> Rf and R, the gain will be very close to unity, i.e.
A  1.
 Figure 7.21 A six-diode sampling gate.

7.10 APPLICATIONS OF SAMPLING GATES

The sampling gates are used in

1. Multiplexers
2. Sample and hold circuits
3. Digital-to-analog converters
4. Chopper stabilized amplifiers
5. Sampling scopes

7.11 CHOPPER AMPLIFIER

One application of a sampling gate is a chopper amplifier. Suppose it is
required to amplify a small signal (of the order of millivolts) and that the
signal v(t) is one in which dv/dt is very small. An ac amplifier would not be
feasible because the coupling capacitors required would be impractically
large. A dc amplifier would also not serve the purpose because we would
not be able to distinguish a change in output voltage as the result of a
change in input voltage or as a result of the drift in some active device or
component. A chopper amplifier will be useful in this case.
Figure 7.22(a) shows a chopper stabilized amplifier. Figure 7.22(b) shows
a low frequency input signal. The switch S1 is being driven so that it is
alternately open and closed. Then the signal vi at the amplifier input will
appear as in Figure 7.22(c). When S1 is open, vi = v and when S1 is closed
vi = 0. Observe that the waveform vi is a chopped version of the waveform
v. Hence the circuit consisting of R and S1 in the present case is called a
chopper.
If the frequency of operation of the switch is very large compared with
the frequency of the signal vi, the waveform vi may be described as a square
wave of amplitude proportional to v and having an average value that is also
proportional to v, i.e. the waveform vi is a square wave at the switching
frequency, amplitude modulated by the input signal and superimposed on a
signal which is proportional to the input signal v itself. The waveform vA at
the output of the amplifier is shown in Figure 7.22(d). This is a modulated
waveform. Because of this process of modulation the chopper is often
called a modulator. The signal is recovered through the mechanism of the
capacitor C and the switch S2. The switch S2 closes and opens in
synchronism with S1. Thus during the interval T1, the negative extremity of
vA is restored to zero, whereas during T2 the positive extremity is restored
to zero. As a result, except for an increase in amplitude, the signal vo across
S2 assumes again the form of the signal vi. If now this signal vo is passed
through a low-pass filter which rejects the square wave and transmits the
signal frequency, at the filter output we shall have an amplified replica of
the original signal. The combination of the capacitor C, the switch S2 and
the filter constitutes a synchronous demodulator.

Figure 7.22 (a) A chopper-stabilized amplifier, (b) input signal,

(c) chopped signal, and (d) signal-modulated square wave.

7.12 SAMPLING SCOPE

An important application of a sampling gate is in sampling scopes. In the
sampling scope the display consists of a sequence of samples of the input
waveform, each sample taken at a time progressively delayed with respect
to some reference point in the waveform.
 Assume that the waveform to be displayed is a pulse in the train of pulses
in Figure 7.23(c). Further assume that a train of triggers shown in Figure
7.23(b), whose time of occurrence precedes somewhat the pulses in Figure
7.23(c), is available. The triggers are used to trigger a sweep signal and a
stairstep signal. Figure 7.23(a) shows the block diagram of a sampling
scope.

Figure 7.23 (a) Block diagram of the essential elements required for a sampling-scope display,
(b) the triggered signal, (c) the signal to be observed, and (d) the ramp and stairstep signals.

The stairstep and ramp signals are applied to a comparator. The stairstep
serves as the reference voltage, and in each cycle, whenever the ramp
attains the stairstep level, the comparator furnishes a pulse output which is
used as the control signal of the sampling gate. At each such control signal,
the gate furnishes at its output a sample of the signal, the sample having a
duration equal to the width of the control pulse. The gate output at each
control signal is a voltage equal to the signal voltage at the time of
sampling. The points at which the samples are taken have been marked by
dots 1, 2, … on the waveform of Figure 7.23(c). We observe that the
samples are taken at a time, which is progressively delayed by equal
increments.
The sample consists then of a pulse whose duration is equal to the
duration of the sampling gate control and whose amplitude is determined by
the magnitude of the input signal at the sampling time. This voltage is to be
held constant for a time comparable to but smaller than the interval between
samples. The sample is so short in duration that it is not feasible to charge a
capacitor in this small interval. Therefore, before the sample is applied to
the “hold” diode-capacitor combination, it is first passed through an
amplifier stage whose output time constant is rather long. The sample pulse
is thereby widened, i.e. stretched and now will have a much broader peak.
The stairstep generator furnishes the horizontal deflection signal for the
scope. Thus the CRT spot moves horizontally across the screen and at each
new position, the spot is deflected vertically by an amount proportional to
the sample height. The CRT screen consists of a series of dots which trace
out the form of the original signal.
The sampling principle finds application in a scope used to display very
fast periodic waveforms, i.e. waveforms with rise times in the nanosecond
range. Its usefulness lies in the fact that it makes unnecessary the use of
high-gain wide-band amplifiers.

SHORT QUESTIONS AND ANSWERS

1. What do you mean by a sampling gate?
A. A sampling gate is a transmission circuit in which the output is an
exact reproduction of the input waveform during a selected time
interval and is zero otherwise.
2. What are the other names of sampling gates?
A. The other names of sampling gates are: linear gates, transmission
gates, or time selection circuits.
3. Why are sampling gates called linear gates?
A. Sampling gates are called linear gates because the output is exactly
the same as the input during the transmission interval.
4. How many types of sampling gates are there? Name them.
A. Basically there are two types of sampling gates: (a) unidirectional
sampling gates and (b) bidirectional sampling gates.
5. How do sampling gates differ from logic gates?
A. The output of a logic gate is a pulse or a voltage level but the output
of a sampling gate is same as the input during the selected time
interval.
6. What do you mean by (a) a unidirectional sampling gate and (b) a
bidirectional sampling gate?
A. (a) A unidirectional sampling gate is a sampling gate which
transmits signals of only one polarity.
(b) A bidirectional sampling gate is a sampling gate which can
transmit signals of both the polarities.
7. What do you mean by a gating signal?
A. Gating signal is an externally impressed signal to select the time
interval for transmission.
8. What are the other names of a gate signal?
A. The other names of a gate signal are: control pulse, selector pulse,
enabling pulse.
 9. What do you mean by pedestal?
A. Pedestal is the base voltage in the output on which the input signal
is superimposed.
10. What are the advantages of diode sampling gates?
A. The diode sampling gates have the basic advantage of linearity of
operation. Also they can be adjusted easily to obtain zero pedestal.
11. What are the advantages of unidirectional diode gate?
A. The advantages of unidirectional diode gate are: its simplicity, very
little time delay through the gate, no currents in its quiescent condition,
and easy extension into a multi input OR gate.
12. What are the disadvantages of the unidirectional diode gate?
A. The disadvantages of the unidirectional diode gate are: (a)
interaction between the signal source and the control voltage source
and (b) limited use of the gate because of the slow rise of the control
voltage at the diode.
13. What are the drawbacks of two-diode gates?
A. The drawbacks of a two-diode gate are: low gain, sensitivity to
control voltage unbalance, the possibility that (Vn)min may be
excessive and the possibility of leakage through the diode capacitance.
14. What do you mean by gain of a gate?
A. The gain of a sampling gate is defined as the ratio of the output
voltage to the input voltage during the transmission interval.
15. What are the applications of sampling gates?
A. The applications of sampling gates are as follows: They are used in
(a) multiplexers (b) sample and hold circuits, (c) digital to analog
converters, (d) chopper stabilized amplifiers and (e) sampling scopes.
16. What for a chopper amplifier is used?
A. A chopper amplifier is used to amplify small signals of the order of
millivolts with very small value of dv/dt.
17. What does the display consists of in a sampling scope?
A. In the sampling scope, the display consists of a sequence of samples
of the input waveform, each sample taken at a time progressively
delayed with respect to some reference point in the waveform.
18. What is a chopper often called?
A. The chopper is often called a modulator.
 REVIEW QUESTIONS
1. With the help of a neat diagram, explain the working of bidirectional
gates using transistors.
2. With the help of a neat diagram, explain the working of a two-diode
sampling gate. Derive expressions for (a) gain, (b) (Vc)min, and (c)
(Vn)min.
3. With the help of a neat diagram, explain the working of a four-diode
gate.
4. With the help of a neat diagram, explain the working of a six-diode
gate.

FILL IN THE BLANKS

1. A __________ is basically a transmission circuit which allows an input
signal to pass through it during a selected time interval and blocks its
passage outside that time interval.
2. The output of a sampling gate is an __________ of the input signal
during the selected interval and is zero otherwise.
3. A sampling gate is also referred to as a __________ or _______ or
__________.
4. Sampling gates may be __________ gates or __________ gates.
5. The interval of time of transmission of a signal is selected by means of
an externally applied signal termed __________.
6. A sampling gate which can handle the input signal excursion of only
one polarity is termed __________.
7. A sampling gate which can handle the input signal excursions of both
the polarities is termed __________.
8. The gate signal is also referred to as __________, or ________ or an
__________.
9. _______ is an externally impressed signal to select the time interval
for transmission.
10. _______ is the base voltage in the output on which the input signal is
superimposed.
11. The gain of a sampling gate is defined as __________.
12. The diode sampling gates have the basic advantage of __________.
Also they can be adjusted easily to obtain _____________.
13. The sampling gates are used in (a) _________, (b) ___________, (c)
_____________, (d) _______ and (e) ____________.
14. The disadvantages of the two diode gate are __________,
___________, __________ and __________.
15. The advantages of the unidirectional gate are: _________, ________,
___________, and __________.
16. The disadvantages of the unidirectional gate are (a) __________ and
(b) ___________.
17. A chopper amplifier is used to amplify small signals of the order of
___________ with very small value of ___________.
18. The chopper is often called a __________.

OBJECTIVE TYPE QUESTIONS

1. A ________ is basically a transmission circuit which allows an input
signal to pass through it during a selected interval and blocks its
passage outside this interval.
(a) sampling gate
(b) logic gate
(c) basic gate
(d) none of these
2. The output of a _____ is an exact replica of the input signal during the
selected interval and is zero otherwise.
(a) sampling gate
(b) logic gate
(c) basic gate
(d) none of these
3. The interval of transmission time is selected by means of an externally
applied signal termed
(a) impulse signal
(b) step signal
 (c) gating signal
(d) logic signal
4. A sampling gate is also referred to as
(a) transmission gate
(b) logic gate
(c) normal gate
(d) none of these
5. A sampling gate which can handle both positive and negative signals is
called
(a) unidirectional gate
(b) bidirectional gate
(c) logic gate
(d) bipolar gate
6. A sampling gate which can handle signals of only one polarity is called
(a) unidirectional gate
(b) unipolar gate
(c) bipolar gate
(d) one polar gate
7. The _________ is the base voltage in the output on which the input
signal is superimposed.
(a) selector pulse
(b) enabling pulse
(c) pedestal
(d) none of these
8. The advantage of bidirectional gate over unidirectional gate is
(a) linearity of operation
(b) efficiency
(c) non linearity
(d) cost
9. The chopper is often called a
(a) demodulator
(b) modulator
(c) multiplexer
(d) demultiplexer
10. A chopper amplifier is used to amplify signals of the order of
(a) microvolts
(b) millivolts
(c) volts
(d) hundreds of volts
 Chapter 8
Logic Gates

Logic gates are the fundamental building blocks of digital systems. They
are called logic gates because such devices have the ability to make
decisions, in the sense that they produce one output level when some
combinations of input levels are present, and a different output level when
other combinations of input levels are present. There are a number logic
gates and each gate is dedicated to a specific logic operation. The
interconnection of gates to perform a variety of logical operations is called
logic design.
The performance of a logic gate is described by a truth table. A table
which lists all possible combinations of input variables and the
corresponding outputs is called a truth table. It shows how the logic
circuit’s output responds to various combinations of logic levels at the
inputs.
Inputs and outputs of logic gates can occur only in two levels. These two
levels are termed HIGH and LOW, or TRUE and FALSE, or ON and OFF,
or simply 1 and 0.
Logic can be either pulse logic or level logic. In pulse or dynamic logic,
the presence of a pulse represents logic 1 and no pulse represents logic 0.
The dc level logic is a logic in which the voltage levels represent logic 1
and logic 0. Level logic may be positive logic or negative logic. A positive
logic system is the one in which the higher of the two voltage levels
represents logic 1 and the lower of the two voltage levels represents logic 0.
A negative logic system is the one in which the lower of the two voltage
levels represents logic 1 and the higher of the two voltage levels represents
logic 0. In transistor-transistor logic (TTL, the most widely used logic
family), the voltage levels are +5 V and 0 V. In the following discussion in
this chapter, logic 1 corresponds to +5 V and logic 0 to 0 V.
A logic gate is a digital circuit with one or more inputs and only one
output. All input and output signals to the gate can be either low voltage
levels or high voltage levels. These gates are so named because they are
used to implement Boolean algebraic expressions. In Boolean algebra, the
variables of an equation can take only two values 0 and 1. There is no
subtraction, no division and no fractions. Only logical addition and logical
multiplication are there.
In logical addition (OR operation), 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1+
1 = 1.
In logical multiplication (AND operation), 0.0 = 0, 0.1 = 0, 1.0 = 0 and
1.1 = 1.

There are just three BASIC gates. They are (a) AND gate, (b) OR gate
and (c) NOT gate (Inverter).
They are called basic gates or basic building blocks of a digital system
because any digital circuit of any complexity can be built by using only
these three gates.
There are two UNIVERSAL gates. They are (a) NAND gate and (b)
NOR gate. They are called universal gates because any digital circuit of any
complexity can be built by using only NAND gates or only NOR gates.
In addition, there are two derived gates. They are (a) Exclusive-OR (X-
OR) gate and (b) Exclusive-NOR (X-NOR) gate.
Logic gates are electronic circuits because they are made up of a number
of electronic devices and components. They are constructed in a wide
variety of forms. They are usually embedded in large-scale integrated
circuits (LSI) and very large-scale integrated circuits (VLSI) along with a
large number of other devices, and are not easily accessible or identifiable.
Each gate is dedicated to a specific logic operation. Logic gates are also
constructed in small-scale integrated circuits (SSI), where they appear with
a few others of the same type. In these integrated devices, the inputs and
outputs of all the gates are accessible, that is, external connections can be
made to them just like discrete logic gates.

8.1 THE BASIC GATES

8.1.1 The OR Gate
An OR gate can have two or more inputs but only one output. The output of
the OR gate assumes the logic 1 state, even if one of its inputs is in the logic
1 state. Its output assumes the logic 0 state, only when each one of its inputs
is in the logic 0 state. An OR gate may, therefore, be defined as a device (or
circuit) whose output is 1, even if one of its inputs is 1. Hence an OR gate is
also called an any or all gate. It is also called an inclusive OR gate because
it includes the condition ‘both the inputs can be present’.
Figure 8.1 shows the logic symbols and truth tables of two-input and
three-input OR gates. Note that the output is 1 (HIGH) even if one of the
inputs is 1(HIGH).

Figure 8.1 The OR gate.

The symbol for the OR operation is ‘+’. The OR operation is logical

addition. With the input variables to the OR gate represented by A, B, C…,
the Boolean expression for the output X can be written as X = A + B and
read as “X is equal to A or B”, or “X is equal to A plus B” for a two input
gate. X = A + B + C and read as “X is equal to A or B or C”, or “X is equal
to A plus B plus C” for a three-input gate.
The operation of a two-input OR gate can be illustrated using Figure 8.2.
 Figure 8.2 Operation of two-input OR gate.

In Figure 8.2 A and B are mechanical switches connected in parallel and

X is a lamp. It can be observed that the lamp X lights up with (a) A closed
and B open, (b) A open and B closed and (c) both A and B closed. It can
also be observed that when both A and B are open, the lamp does not light
up. Let a binary 0 indicate open switch and a binary 1 indicate closed
switch. Also let binary 0 indicate a dark lamp and binary 1 indicate a bright
lamp. The various combinations of the switch positions and the state of the
lamp are listed below.

This is same as the truth table of a two input OR gate.

Realization of OR gate (DL OR gate and RTL OR gate)
Discrete OR gates may be realized by using diodes or transistors as shown
in Figures 8.3(a) and 8.3(b), respectively. The inputs A and B to the gates
may be either 0 V or + 5 V.
 Figure 8.3 Discrete OR gates.

In the positive logic diode OR gate (Diode Logic OR gate) shown in

Figure 8.3(a) A and B are voltage sources and R is load resistance. The two
inputs A and B can occur in four possible combinations.
(a) When both A and B are low, i.e. when A = 0 V and B = 0 V, both the
diodes D1 and D2 are OFF. No current flows through R, and so, no
voltage drop occurs across R. Hence, the output voltage X = 0 V (logic
0).
(b) When A is high and B is low, i.e. A = + 5 V and B = 0 V, diode D1 is
forward biased and diode D2 is reverse biased. Current flows through
D1 and R and the output voltage X  5 V (logic 1).
(c) When A is low and B is high, i.e. A = 0 V and B = +5 V, diode D1 is
OFF and diode D2 is ON. Current flows through D2 and R and the
output voltage X  5 V (logic 1).
(d) When A is high and B is high, i.e. A = +5 V and B = +5 V both the
diodes D1 and D2 are ON. Current flows through D1, D2 and R and the
output voltage X  + 5 V(logic 1). In practice X = 5 V – diode drop =
5 V – 0.7 V = 4.3 V which is regarded as logic 1.
The truth table for the above two input diode OR gate is shown below.
A negative logic OR gate uses the same configuration as that of Figure
8.3(a) except that all the diodes are reversed.
In the transistor OR gate (RTL OR gate) shown in Figure 8.3(b),
(a) When A = 0 V and B = 0 V, both T1 and T2 are OFF. No current
flows through them. T3 gets enough base drive from the +5 V supply
and so T3 is ON and the output X = VCE (sat) = 0.3 V  0 V (logic 0).
(b) When A = 0 V and B = 5 V, T1 is OFF and T2 is ON. Current flows
through T2, and T3 does not get enough base drive and so T3 is OFF.
No current flows through its collector resistance RC. So there is no
voltage drop across it. The output X = + 5 V (logic 1).
(c) When A = 5 V and B = 0 V, T1 is ON and T2 is OFF. Current flows
through T1, and T3 does not get enough base drive and so T3 is OFF.
No current flows through its collector resistance RC. So no voltage
drop across it. The output X = + 5 V (logic 1).
(d) When A = 5 V and B = 5 V, both T1 and T2 are ON. Current flows
through T1 and T2, and T3 does not get enough base drive and so T3 is
OFF. No current flows through its collector resistance RC. So no
voltage drop across it. The output X = + 5 V (logic 1).
The IC 7432 contains four two-input OR gates.
8.1.2 The AND Gate
An AND gate has two or more inputs but only one output. The output of the
AND gate assumes the logic 1 state, only when each one of its inputs is at
the logic 1 state. Its output assumes the logic 0 state even if one of its inputs
is at the logic 0 state. The AND gate may, therefore, be defined as a device
(or circuit) whose output is 1, if and only if all its inputs are 1. Hence the
AND gate is also called an all or nothing gate.
Figure 8.4 shows the logic symbols and truth tables of two-input and
three-input AND gates. Note that the output is 1 (HIGH) only when each
one of the inputs is 1 (HIGH). The symbol for the AND operation is ‘◊’, or
we use no symbol at all. The AND operation is logical multiplication.

Figure 8.4 The AND gate.

With the input variables to the AND gate represented by A, B, C,…, the
Boolean expression for the output can be written as X = A ◊ B and read as
“X is equal to A and B.” or “X is equal to AB”, or “X is equal to A dot B”,
for a two-input gate.
X = A ◊ B ◊ C, and read as “X is equal to ABC”, or “X is equal to A dot
B dot C” or “X is equal to A and B and C”, for a three-input gate.
The operation of a two-input AND gate can be illustrated using Figure
8.5.
 Figure 8.5 Operation of two-input AND gate.

In Figure 8.5 A and B are mechanical switches connected in series and X

is the lamp. It can be observed that the lamp X lights up only when both the
switches A and B are closed. It can also be observed that the lamp does not
light up with (a) both A and B open, (b) A open and B closed and (c) A
closed and B open. Let binary 0 indicate an open switch and binary 1
indicate a closed switch. Also let binary 0 indicate a dark lamp and binary 1
indicate a bright lamp. The various combinations of the switch positions
and the state of the lamp are listed below.

This is the same as the truth table of a two-input AND gate.

Realization of AND gate (DL AND gate and RTL AND gate)
Discrete AND gates may be realized by using diodes or transistors as shown
in Figures 8.6(a) and 8.6(b), respectively. The inputs A and B to the gates
may be either 0 V or + 5 V. The two inputs A and B can occur in four
possible combinations.
In the positive logic diode AND gate (Diode Logic AND gate) shown in
Figure 8.6(a) A and B are voltage sources and R is load resistance.
(a) When both A and B are low, i.e. A = 0 V and B = 0 V, both the diodes
D1 and D2 are ON. Current flows through R, D1 and D2 and so almost
all the supply voltage is dropped across R. Hence the output voltage X
 0 V (logic 0).
 (b) When A is low and B is high, i.e. A = 0 V and B = 5 V, diode D1 is
ON and diode D2 is OFF. Current flows thorough R and D1 and almost
all the supply voltage is dropped across R. Hence the output voltage X
 0 V (logic 0).
(c) When A is high and B is low, i.e. A = 5 V and B = 0 V, diode D1 is
OFF and diode D2 is ON. Current flows through R and D2 and almost
all the supply voltage is dropped across R. Hence the output voltage X
 0 V (logic 0).
(d) When both A and B are high, i.e. A = 5 V and B = 5 V, both the
diodes D1 and D2 are OFF. No current flows through R, so no voltage
drop across R. Hence the output voltage X  5 V (logic 1).
The truth table for the above diode logic AND gate is shown below.

A negative logic AND gate uses the same configuration as that of Figure
8.6(a) except that all the diodes are reversed.

Figure 8.6 Discrete AND gates.

 In the transistor AND gate (RTL AND gate) shown in Figure 8.6(b),
(a) When A = 0 V and B = 0 V, T1 is OFF and T2 is OFF. No current
passes through them. T3 gets enough base drive from +5V source and
so goes into saturation. Output
X = VCE(sat) = 0.3 V  0 V(logic 0).
(b) When A = 0 V and B = 5 V, both T1 and T2 are OFF. No current
passes through them. T3 gets enough base drive from +5 V source and
so goes into saturation. Output X = VCE(sat) = 0.3 V  0 V (logic 0).
(c) When A = 5 V and B = 0 V, both T1 and T2 are OFF. No current
passes through them. T3 gets enough base drive from +5 V source and
so goes into saturation. Output X = VCE(sat) = 0.3 V  0 V (logic 0).
(d) When A = 5 V and B = 5 V, both T1 and T2 are ON. Current flows
through them. T3 does not get enough base drive and so will be OFF.
Output X  5 V (logic 1).
The truth table for the above two-input Resistor Transistor Logic AND
gate is the same as discussed earlier.
The IC 7408 contains four two-input AND gates, the IC 7411 contains
three three-input AND gates, and the IC 7421 contains two four-input AND
gates.
8.1.3 The NOT Gate (Inverter)
A NOT gate, also called an inverter, has only one input and, of course, only
one output. It is a device (or circuit) whose output is always the
complement of its input. That is, the output of a NOT gate assumes the
logic 1 state when its input is in the logic 0 state and assumes the logic 0
state when its input is in the logic 1 state. The logic symbol and the truth
table of an inverter are shown in Figures 8.7(a) and 8.7(b), respectively.
 Figure 8.7 The inverter.

The symbol for NOT operation is ‘–’ (bar). When the input variable to the
NOT gate is represented by A and the output variable by X, the expression
for the output is X = . This is read as “X is equal to A bar”.
Realization of NOT gate (RTL NOT gate)
A discrete NOT gate may be realized using a transistor as shown in Figure
8.7(c). The input to the gate may be 0 V or + 5 V.
(a) When A = 0 V, transistor T is OFF. No current flows through R, and
hence no voltage drop occurs across R. The output voltage X = + 5
V(logic 1).
(b) When A = + 5 V, T is ON. Current flows through R and hence almost
all the supply voltage is dropped across R. The output voltage X =
VCE(sat) = 0.3 V  0 V (logic 0). The truth table for the NOT gate is
shown below.

The IC 7404 contains six inverters.

Logic circuits of any complexity can be realized using only AND, OR
and NOT gates. Logic circuits which use these three gates only are called
AND/OR/INVERT, i.e. AOI logic circuits. Logic circuits which use AND
gates and OR gates only are called AND/OR, i.e. AO logic circuits.
8.2 THE UNIVERSAL GATES
Though logic circuits of any complexity can be realized by using only the
three basic gates (AND, OR and NOT), there are two universal gates
(NAND and NOR), each one of which can also realize any digital circuit of
any complexity single-handedly. The NAND and NOR gates are also,
therefore, called universal building blocks. Both NAND and NOR gates can
perform all the three basic logic functions (AND, OR and NOT). Therefore,
AOI logic can be converted to NAND logic or NOR logic.
8.2.1 The NAND Gate
NAND means NOT AND, i.e. the AND output is NOTed. So, a NAND gate
is essentially an AND gate and a NOT gate. The output of a NAND gate is
therefore NOT the AND of the inputs. A NAND gate can have two or more
inputs but only one output.
The output of a NAND gate is low, only when all its inputs are high. Its
output is high even if one of its inputs is low.
The logic symbols and truth tables for two input and three-input NAND
gates are shown in Figures 8.8 and 8.9, respectively.

Figure 8.8 A two-input NAND gate.

 Figure 8.9 A three-input NAND gate.

Figure 8.10 Bubbled OR gate.

The OR gate with inverted inputs (Figure 8.10(a)) is called a bubbled OR

gate. So, a NAND gate is equivalent to a bubbled OR gate whose truth table
is shown in Figure 8.10(b). A bubbled OR gate is also called a negative OR
gate. Since its output assumes the HIGH state even if any one of its inputs is
0, the NAND gate is also called an active-LOW OR gate.
Realization of NAND gate (Diode Transistor Logic DTL)
A discrete positive logic two-input NAND gate using diodes and transistors
is shown in Figure 8.11(a). Its operation is as follows.
(a) When A = +5 V and B = +5 V, both the diodes D1 and D2 are OFF.
The transistor T gets enough base drive from +5 V supply through R
and so, T is ON. The output X = VCE (sat) = 0.3 V  0 V (logic 0).
 (b) When A = +5 V and B = 0 V, D1 is OFF, D2 is ON. Current flows
through R and D2. Transistor T does not get enough base drive and is
OFF. The output X = 5 V (logic 1).
(c) When A = 0 V and B = 5 V, D1 is ON and D2 is OFF. Current flows
through R and D1. Transistor T does not get enough base drive and is
OFF. The output X = 5 V (logic 1).
(d) When A = 0 V and B = 0 V, both the diodes D1 and D2 are ON.
Current flows through R, D1 and D2. The transistor T does not get
enough base drive and is OFF. The output X is equal to 5 V (logic 1).
The truth table is shown in Figure 8.11(b).

Figure 8.11 Discrete two-input NAND gate (DTL).

The IC 7400 contains four two-input NAND gates; the IC 7410 contains
three three-input NAND gates; the IC 7420 contains two four-input NAND
gates; and the IC 7430 contains one eight-input NAND gate.
A NAND gate can also be used as an inverter by tying all its input
terminals together and applying the signal to be inverted to the common
terminal (Figure 8.11(c)), or by connecting all its input terminals except
one, to logic 1 and applying the signal to be inverted to the remaining
terminal as shown in Figure 8.11(d). In the latter form, it is said to act as a
controlled inverter.
RTL NAND gate
Figure 8.12(a) shows a positive logic two-input RTL NAND gate (Negative
Logic NOR gate).
 Figure 8.12 RTL NAND gate.

The circuit works as follows.

(a) When A = 0 V and B = 0 V or A = 0 V and B = 5 V or A = 5 V and B
= 0 V both the transistors are OFF. No current flows through R. No
voltage drop across it. So output X = +5 V (logic 1)
(b) When A = +5 V and B = +5 V both transistors T1 and T2 are ON.
Output X = 0.6 V  0 V (logic 0).
The truth table is shown in Figure 8.11(b).
Two-input TTL NAND gate (standard TTL)
In the circuit of the two-input TTL NAND gate shown in Figure 8.13 the
input transistor Q1 is a multiple emitter transistor. Transistor Q2 is called
the phase splitter. Transistor Q3 ‘sits above’ Q4 and, therefore, Q3 and Q4
make a totem pole arrangement. Diodes D1 and D2 protect Q1 from being
damaged by the negative spikes of voltages at the inputs. When negative
spikes appear at the input terminals, the diodes conduct and bypass the
spikes to ground. Diode D ensures that Q3 and Q4 do not conduct
simultaneously. Transistor Q3 acts as an emitter follower.
 Figure 8.13 Two input TTL NAND gate.

When both the inputs A and B are HIGH (+5 V), both the base-emitter
junctions of Q1 are reverse biased. So, no current flows to the emitters of
Q1. However, the collector-base junction of Q1 is forward biased. So, a
current flows through R1 to the base of Q2, and Q2 turns on. Current from
Q2’s emitter flows into the base of Q4. So, Q4 is turned on. The collector
current of Q2 flows through R2 and, so, produces a drop across it thereby
reducing the voltage at the collector of Q2. Therefore, Q3 is OFF. Since Q4
is ON, Vo is at its low level (VCE (sat)). So, the output is a logic 0, When
either A or B or both are LOW, the corresponding base-emitter junction(s)
is (are) forward biased and the collector-base junction of Q1 is reverse
biased. So, the current flows to ground through the emitters of Q1.
Therefore, the base of Q1 is at 0.7 V, which cannot forward bias the base-
emitter junction of Q2. So, Q2 is OFF. With Q2 OFF, Q4 does not get the
required base drive. So, Q4 is also OFF. Transistor Q3 gets enough base
drive because Q2 is OFF, i.e. since no current flows into the collector of Q2,
all the current flows into the base of Q3, and therefore, Q3 is ON. The
output voltage, Vo = VCC – VR2 – VBE3 – VD  3.4 to 3.8 V, which is a
logic HIGH level. So, the circuit acts as a two-input NAND gate. When Q4
is OFF, no current flows through it, but the stray and output capacitances
between the output terminal, i.e. the collector of Q4, and ground get
charged to this voltage of 3.4 to 3.8 V.
8.2.2 The NOR Gate
NOR means NOT OR, i.e. the OR output is NOTed. So, a NOR gate is
essentially an OR gate followed by a NOT gate (i.e. an inverter). A NOR
gate can have two or more inputs but only one output. The output of the
NOR gate assumes the 1 state only when each one of its inputs assume the 0
state, i.e. the output of the NOR gate is high only when all its inputs are
low. Its output is low even if one of its inputs is high.
The logic symbols and truth tables of two-input and three-input NOR
gates are shown in Figures 8.14 and 8.15 respectively.

Figure 8.14 A two-input NOR gate.

Figure 8.15 A three-input NOR gate.

 Figure 8.16 Bubbled AND gate.

The AND gate with inverted inputs (Figure 8.16(a)) is called a bubbled
AND gate. So, a NOR gate is equivalent to a bubbled AND gate whose
truth table is shown in
Figure 8.16(b). A bubbled AND gate is also called a negative AND gate.
Since its output assumes the HIGH state only when all its inputs are in
LOW states, a NOR gate is also called an active-LOW AND gate.
Realization of NOR gate (Diode Transistor Logic DTL)
A discrete positive logic two-input NOR gate using diodes and transistors
(DTL) is shown in Figure 8.17(a). Its operation is as follows.
(a) When A = 0 V and B = 0 V, both the diodes D1 and D2 are OFF. The
transistor T is OFF. No current flows through RC. So, no voltage drop
across RC. Hence output voltage
X = 5 V (logic 1).
 (b) When A = 0 V and B = 5 V, D1 is OFF and D2 is ON. Current flows
through D2 and R. Transistor T is ON. Hence output X = VCE (sat) =
0.3 V  0 V (logic 0).
(c) When A = 5 V and B = 0 V, D1 is ON and D2 is OFF. Current flows
through D1 and R. Transistor T is ON. Hence output X = VCE (sat) =
0.3 V  0 V (logic 0).
(d) When A = 5 V and B = 5 V, both D1 and D2 are ON. Current flows
through D1, D2 and R. Transistor T is ON. Hence output X = VCE (sat)
= 0.3 V  0 V (logic 0).
The truth table is as shown in Figure 8.17(b).

Figure 8.17 Discrete two-input DTL NOR gate.

RTL NOR gate

Figure 8.18 shows a positive logic two-input RTL NOR gate (Negative
Logic NAND gate).
 Figure 8.18 RTL NOR gate.

The circuit works as follows.

(a) When A = 0 V and B = 0 V, both transistors T1 and T2 are OFF. So no
current flows through R and therefore no voltage drop across R. Hence
the output voltage X = +5 V (logic 1).
(b) When A = 0 V and B = +5 V, T1 is OFF and T2 is ON. Hence the
output X = VCE(sat) = 0.3 V  0 V (logic 0).
(c) When A = +5 V and B = 0 V, T1 is ON, and T2 is OFF. Hence the
output X = VCE(sat) = 0.3 V  0 V (logic 0).
(d) When A = +5 V and B = +5 V, both T1 and T2 are ON. Hence the
output X = VCE(sat) = 0.3 V  0 V (logic 0).
The truth table is shown in Figure 8.18 (b).
The IC 7402 contains four two-input NOR gates; the IC 7427 contains
three three-input NOR gates; and the IC 7425 contains two four-input NOR
gates.
A NOR gate can also be used as an inverter, by tying all its input
terminals together and applying the signal to be inverted to the common
terminal (Figure 8.18(c)) or by connecting all its input terminals except one
to logic 0, and applying the signal to be inverted to the remaining terminal
as shown in Figure 8.18(d). In the latter form it is said to act as a controlled
inverter.
8.3 THE DERIVED GATES
In addition to the three basic gates and two universal gates there are two
more logic gates. They are the Exclusive-OR (X-OR) gate and the
Exclusive-NOR (X-NOR) gate.
8.3.1 The Exclusive-OR (X-OR) Gate
An X-OR gate is a two input, one output logic circuit, whose output
assumes a logic 1 state when one and only one of its two inputs assumes a
logic 1 state. Under the conditions when both the inputs assume the logic 0
state, or when both the inputs assume the logic 1 state, the output assumes a
logic 0 state.
Since an X-OR gate produces an output 1 only when the inputs are not
equal, it is called an anti-coincidence gate or inequality detector. The output
of an X-OR gate is the modulo sum of its two inputs. The name Exclusive-
OR is derived from the fact that its output is a 1, only when exclusively one
of its inputs is a 1 (it excludes the condition when both the inputs are 1).

Figure 8.19 Exclusive-OR gate.

Three or more variable X-OR gates do not exist. When more than two
variables are to be X-ORed, a number of two-input X-OR gates will be
used. The X-OR of a number of variables assumes a l state only when an
odd number of input variables assume a 1 state.
An X-OR gate can be used as an inverter by connecting one of the two
input terminals to logic 1 and feeding the input sequence to be inverted to
the other terminal as shown in Figure 8.19(c). If the input bit is a 0, the
output is, 0  1 = 1, and if the input bit is a 1, the output is, 1  1 = 0. In
fact, we can say that an X-OR gate can be used as a controlled inverter, that
is, one of its inputs can be used to decide whether the signal at the other
input will be inverted or not.
The TTL IC 7486 contains four X-OR gates.
8.3.2 The Exclusive-NOR (X-NOR) Gate
An X-NOR gate is a combination of an X-OR gate and a NOT gate. The X-
NOR gate is a two-input, one-output logic circuit, whose output assumes a 1
state only when both the inputs assume a 0 state or when both the inputs
assume a 1 state. The output assumes a 0 state, when one of the inputs
assumes a 0 state and the other a 1 state. It is also called a coincidence gate,
because its output is 1 only when its inputs coincide. It can be used as an
equality detector because it outputs a 1 only when its inputs are equal.
The logic symbol and truth table of a two-input X-NOR gate are shown in
Figures 8.20(a) and 8.20(b), respectively. If the input variables are
represented by A and B and the output variable by X, the expression for the
output of this gate is written as

and read as “X is equal to A ex-nor B”.

Three or more variable X-NOR gates do not exist. When a number of
variables are to be X-NORed, a number of two-input X-NOR gates can be
used. The X-NOR of a number of variables assumes a 1 state, only when an
even number (including zero) of input variables assume a 0 state.
An X-NOR gate can be used as an inverter by connecting one of the two
input terminals to logic 0 and feeding the input sequence to be inverted to
the other terminal as shown in Figure 8.20(c). If the input bit is a 0, the
output is, 0  0 = 1, and if the input bit is a 1, the output is, 1  0 = 0. In
fact, we can say that an X-NOR gate can be used as a controlled inverter,
that is, one of its inputs can be used to decide whether the signal at the other
input will be inverted or not. The X-NOR gate can be used as a comparator
too.
 Figure 8.20 Exclusive-NOR gate.

The X-NOR of two variables A and B is the complement of the X-OR of

those two variables. That is,

But the X-NOR of three variables A, B and C is not equal to the

complement of the X-OR of A, B and C. That is,

However, the X-NOR of a number of variables is equal to the complement

of the X-OR of those variables only when the number of variables involved
is even.
The TTL IC 74LS266, the CMOS IC 74C266 and the high speed CMOS
IC 74HC266 contain four each X-NOR gates.

8.4 INHIBIT CIRCUITS

AND, OR, NAND and NOR gates can be used to control the passage of an
input logic signal through to the output. This is shown in Figure 8.21 where
a logic signal A is applied to one input of each of the above mentioned logic
gates. The other input of each gate is the control input B. The logic level at
this control input will determine whether the input signal is enabled to reach
the output or inhibited from reaching the output.
 Figure 8.21 Enable and inhibit circuits.

We notice that when AND and OR gates are enabled, the output follows
the A input exactly. Conversely, when NAND and NOR gates are enabled,
the output is exactly the inverse of the A input.
We also see that when AND and NOR gates are inhibited, they produce a
constant LOW output. Conversely, the NAND and OR gates produce a
constant HIGH output in the inhibited condition.
There will be many situations in digital circuit design, where the passage
of a logic signal is either enabled or inhibited depending on the conditions
present at one or more control inputs.
EXAMPLE 8.1 Show that NAND and NOR gates are universal gates.
Solution: To show that NAND and NOR gates are universal gates, it is
sufficient to show that the basic gates, i.e. AND, OR and NOT gates can be
realized using only NAND gates or only NOR gates. Figure 8.22 shows the
realization of AND, OR and NOT gates either using only NAND gates or
only NOR gates.
 Figure 8.22 Example 8.1: realization of basic gates using universal gates.

EXAMPLE 8.2 Realize the X-OR function using (a) AOI logic, (b) NAND
logic, and
(c) NOR logic.
Solution: (a) Using AOI logic:
Figure 8.23 Example 8.2: realization of X-OR gate using (a) AOI logic, (b) NAND logic and (c)
NOR logic.
EXAMPLE 8.7 Find the logical equivalent of the following expressions.

EXAMPLE 8.8 Determine which of the following expressions are

equivalent to A  B and which to A  B?
8.5 PULSED OPERATION OF LOGIC GATES
In a majority of applications, the inputs to a gate are not stationary levels,
but are voltages that change frequently between two logic levels and can be
classified as pulse waveforms. We will now look at the operation of all
logic gates discussed till now with pulsed waveforms. All the logic gates
obey the truth table operation, regardless of whether the inputs are constant
levels or pulsed levels. The timing diagrams of various gates for different
inputs are shown in the following examples.
EXAMPLE 8.9 For a two-input AND gate, determine its output waveform
in relation to input waveforms of Figure 8.24(a).

Figure 8.24 Example 8.9.

Solution: The output of the AND gate is High only when each one of its
input is HIGH.
The output waveform X is shown in Figure 8.24(b).
EXAMPLE 8.10 For a two-input OR gate, determine its output waveform
in relation to the inputs A and B shown in Figure 8.25(a).
Solution: The output waveform is shown in Figure 8.25(b).
 Figure 8.25 Example 8.10.

EXAMPLE 8.11 If the waveform shown in Figure 8.26(a) is applied to an

inverter, what is the resulting output waveform?
Solution: The output of an inverter is the complement of its input. The
output waveform is shown in Figure 8.26(b).

Figure 8.26 Example 8.11.

EXAMPLE 8.12 The waveforms A and B shown in Figure 8.27(a) are

applied to a two-input NAND gate. Determine the output waveform.
Solution: The output of a NAND gate is LOW only when all its inputs are
HIGH. The output waveform is shown in Figure 8.27(b).

Figure 8.27 Example 8.12.

EXAMPLE 8.13 The waveforms A and B shown in Figure 8.28(a) are

applied to a two-input NAND gate. Determine the output waveform.
Solution: The output waveform is shown in Figure 8.28(b). In this case, the
two inputs of the NAND gate are never HIGH simultaneously. So, the
output is never LOW. It is always HIGH.
 Figure 8.28 Example 8.13.

EXAMPLE 8.14 For the two-input NAND gate operating as a negative OR

gate, determine the output waveform when the input waveforms A and B
are as shown in Figure 8.29(a).
Solution: The output of an active-LOW OR gate is HIGH, if either A is
LOW or B is LOW or both A and B are LOW. The output waveform is
shown in Figure 8.29(b).

Figure 8.29 Example 8.14.

EXAMPLE 8.15 If the waveforms A and B shown in Figure 8.30(a) are

applied to a two-input NOR gate, determine the resulting output waveform.
Solution: The output of a NOR gate is HIGH only when all its inputs are
LOW. The output waveform is shown in Figure 8.30(b).

Figure 8.30 Example 8.15.

EXAMPLE 8.16 If the waveforms A and B shown in Figure 8.31(a) are

applied to a two-input X-OR gate, determine the output waveform.
Solution: The output of an X-OR gate is HIGH, only when the inputs are
not equal. The output waveform is shown in Figure 8.31(b).
 Figure 8.31 Example 8.16.

EXAMPLE 8.17 If the waveforms A and B shown in Figure 8.32(a) are

applied to a two-input X-NOR gate, determine the output waveform.
Solution: The output of an X-NOR gate is HIGH, only when the inputs are
equal. The output waveform is shown in Figure 8.32(b).

Figure 8.32 Example 8.17.

EXAMPLE 8.18 Determine the output waveform for the circuit shown in
Figure 8.33(c), when the inputs A and B shown in Figure 8.33(a) are
applied to it.
Solution: The output waveform Y in proper time relationship to inputs A
and B is shown in Figure 8.33(b). When both the inputs are HIGH, or both
the inputs are LOW, the output is LOW. The output is HIGH only when one
of the inputs is HIGH. So, it is an X-OR operation. It is an anti-coincidence
circuit.
 Figure 8.33 Example 8.18.

SHORT QUESTIONS AND ANSWERS

1. What are logic gates?
A. Logic gates are the fundamental building blocks of digital systems.
Logic gates are electronic circuits with one or more inputs and only
one output. They produce one output level when some combinations of
input levels are present and different output level when other
combinations of inputs are present.
2. How many basic gates are there? Name them.
A. There are three basic gates. They are: AND gate, OR gate and NOT
gate (Inverter).
3. Why are AND, OR and NOT gates called basic gates?
A. The AND, OR and NOT gates are called basic gates or basic
building blocks of a digital system because any digital circuit of any
complexity can be built by using only these three gates.
4. What do you mean be logic design?
A. The inter-connection of gates to perform a variety of logical
operations is called logic design.
5. What is a truth table?
A. A truth table is a table which lists all possible combinations of
inputs and the corresponding outputs.
6. What do you mean by level logic?
A. A level logic is a system in which the voltage levels represent logic
1 and logic 0. It may be a positive logic or negative logic.
7. What do you mean by a positive logic system?
A. A positive logic system is one in which the higher of the two
voltage levels represents logic 1 and the lower of the two voltage
levels represent logic 0.
8. What do you mean by a negative logic system?
A. A negative logic system is one in which the lower of the two
voltage levels represent logic 1 and the higher of the two voltage levels
represent logic 0.
 9. What are the voltage levels used in the TTL system?
A. The voltage levels used in the TTL system are:
(a) +5 V for logic 1 and 0 V for logic 0 in the positive logic system.
(b) +5 V for logic 0 and 0 V for logic 1 in the negative logic system.
10. What is an AND gate?
A. An AND gate is a circuit with two or more inputs and only one
output. Its output is logic 1 if and only if all its inputs are logic 1.
11. What is the other name of an AND gate?
A. An AND gate is also called an ‘all or nothing gate’.
12. What is an OR gate?
A. An OR gate is a circuit with two or more inputs and only one
output. Its output is logic 1 even if one of its inputs is logic 1. Its
output is logic 0 only when each one of its inputs is logic 0.
13. What is the other name of an OR gate?
A. An OR gate is also called ‘any or all gate’.
14. What is a NOT gate?
A. A NOT gate is a digital circuit with only one input and only one
output. Its output is the complement of its input.
15. What is the other name of a NOT gate?
A. A NOT gate is also called an ‘Inverter’.
16. What are universal gates? How many universal gates are there? Name
them.
A. Universal gates are logic gates which can realize any digital circuit
single handedly. There are two universal gates. They are NAND gate
and NOR gate.
17. Why are NAND gate and NOR gate called universal gates?
A. NAND gate and NOR gate are called universal gates because any
digital circuit of any complexity can be built by using only NAND
gates or only NOR gates.
18. What is a NAND gate?
A. A NAND gate is a device with two or more inputs and only one
output. Its output is logic 0 only when each one of its inputs is logic 1.
Its output is logic 1 even if one of its inputs is logic 0.
19. A NAND gate is called what?
A. A NAND gate is called an active-low OR gate. It is equivalent to a
bubbled OR gate or negative OR gate.
20. Why is a NAND gate called an active-low OR gate?
A. A NAND gate is called an active-low OR gate because its output
assumes the logic one state even if one of its inputs is logic 0.
21. What is a NOR gate?
A. A NOR gate is a device or circuit with two or more inputs and only
one output. Its output is logic 1 only when each one of its inputs is
logic 0. Its output is logic 0 even if one of its inputs is logic 1.
22. A NOR gate is called what?
A. A NOR gate is called an active-low AND gate. It is equivalent to a
bubbled AND gate or negative AND gate.
23. Why is a NOR gate called an active-low AND gate?
A. A NOR gate is called an active-low AND gate because its output
assumes the high state only when all its inputs are in low state.
24. How do you use a NAND gate as an inverter?
A. A NAND gate can be used as an inverter by tying all its input
terminals together and applying the signal to be inverted to the
common terminal, or by connecting all its input terminals except one
to logic 1 and applying the signal to be inverted to the remaining
terminal.
25. How do you use a NOR gate as an inverter?
A. A NOR gate can be used as an inverter by tying all its input
terminals together and applying the signal to be inverted to the
common terminal or by connecting all its input terminals except one to
logic zero and applying the signal to be inverted to the remaining
terminal.
26. What is exclusive-OR gate?
A. An exclusive-OR gate (X-OR gate) is a two-input, one-output logic
circuit whose output assumes a logic 1 state when one and only one of
its two inputs assume a logic 1 state, i.e. only when the inputs do not
coincide.
27. Why an X-OR gate is called an anticoincidence gate or inequality
detector?
A. An X-OR gate is called an anticoincidence gate or inequality
detector because it produces an output 1 only when the inputs do not
coincide, i.e. they are not equal.
28. How do you use an X-OR gate as an inverter?
A. An X-OR gate can be used as an Inverter by connecting one of the
two input terminals to logic 1 and feeding the input sequence to be
inverted to the other terminal.
29. What is an exclusive-NOR gate?
A. An exclusive-NOR gate (X-NOR gate) is a two-input, one-output
logic circuit whose output assumes a logic 1 state only when both the
inputs assume a logic 0 state or when both the inputs assume a logic 1
state, i.e. only when the inputs coincide.
30. Why is an X-NOR gate called coincidence gate or equality detector?
A. An X-NOR gate is called a coincidence gate or equality detector
because it outputs a 1 only when its inputs coincide, i.e. they are equal.
31. How do you use an X-NOR gate as an inverter?
A. An X-NOR gate can be used as an inverter by connecting one of the
two input terminals to logic 0 and feeding the input sequence to be
inverted to the other terminal.
32. How do you say that X-OR and X-NOR gates can be used as
controlled inverters?
A. X-OR and X-NOR gates can be used as controlled inverters because
one of the inputs to them can be used to decide whether the signal at
the other input can be inverted or not.
33. What do you mean by an active-low input gate?
A. An active-low input gate is one in which the inputs are normally in
high state and become effective when they go from high to low state.
34. What do you mean by a bubbled AND gate?
A. A bubbled AND gate is an AND gate with inverted inputs. It is also
called a negative AND gate. It is a NOR gate.
35. What do you mean by a bubbled OR gate?
A. A bubbled OR gate is an OR gate with inverted inputs. It is also
called a negative OR gate. It is a NAND gate.
36. Which gate is equivalent to a NAND gate followed by an inverter?
A. AND gate is equivalent to a NAND gate followed by an inverter.
37. Which gate is equivalent to a NOR gate followed by an inverter?
A. OR gate is equivalent to a NOR gate followed by an inverter.
 REVIEW QUESTIONS
1. Draw the logic symbols and truth tables of (a) OR, (b) AND, (c) NOT,
(d) NAND, (e) NOR, (f) X-OR, and (g) X-NOR gates.
2. With the help of a neat circuit diagram and truth table explain the
working of (a) a DL AND gate and (b) an RTL AND gate.
3. With the help of a neat circuit diagram and truth table explain the
working of (a) a DL OR gate and (b) an RTL OR gate.
4. With the help of a neat circuit diagram and truth table explain the
working of a NOT gate.
5. With the help of a neat circuit diagram and truth table explain the
working of (a) a DTL NAND gate and (b) an RTL NAND gate.
6. With the help of a neat circuit diagram and truth table explain the
working of (a) a DTL NOR gate and (b) RTL NOR gate.
7. Write notes on X-OR and X-NOR gates?
8. Show that NAND gate and NOR gate are universal gates.
9. Show an arrangement to X-OR and X-NOR the inputs A, B, C and D.
10. Draw the logic diagram of an X-OR gate using AOI logic.
11. Draw the logic diagram of an X-NOR gate using AOI logic.

FILL IN THE BLANKS

1. ___________ are the fundamental building blocks of digital systems.
2. AND, OR, and NOT gates are called the ________________ gates.
3. The interconnection of gates to perform a variety of logical operations
is called ___________.
4. A ____________ lists all possible combinations of inputs and the
corresponding outputs.
5. In ____________ logic system, the higher of the two voltage levels
represents logic 1 and the lower logic 0.
6. In ____________ logic system, the higher of the two voltage levels
represents logic 0 and the lower logic 1.
7. An __________ gate is an all or nothing gate.
8. An __________ gate is an any or all gate.
 9. A _________ gate is an Inverter.
10. NAND and NOR gates are ____________ gates.
11. An X-OR gate is an __________ gate. It is an ____________ detector.
12. An X-NOR gate is a ___________ gate. It is a __________ detector.
13. _____________ or more input X-OR and X-NOR gates do not exist.
14. A NOR gate is also called an _________ AND gate.
15. An AND gate with inverted inputs is called a _________ AND gate or
a _________AND gate.
16. A NAND gate is also called an ______________ OR gate.
17. An OR gate with inverted inputs is called ____________ OR gate or a
__________ OR gate.
18. Any digital circuit of any complexity can be built using ___________
gates, ________ gates and __________ gates.
19. Any digital circuit of any complexity can be built using only
_________ gates or only _______ gates.
20. In addition to an Inverter, NOT operation can be performed by
_________ gate, or ________ gate, or _________ gate, or
_____________ gate.
21. When discrete gates are realized using only resistors and diodes, it is
called ____________.
22. When discrete gates are realized using only resistors and transistors, it
is called _______.
23. When discrete gates are realized using diodes, transistors and resistors
it is called _______.
24. A positive logic NAND gate is equivalent to a negative logic
__________ gate.
25. A positive logic NOR gate is equivalent to a negative logic
____________ gate.

OBJECTIVE TYPE QUESTIONS

1. __________ gate is an all or nothing gate.
(a) OR
(b) AND
 (c) NAND
(d) NOR
2. _________ gate is any or all gate.
(a) OR
(b) AND
(c) X-OR
(d) X-NOR
3. A NAND gate followed by a NAND gate is equivalent to a _______
gate.
(a) NAND
(b) NOR
(c) AND
(d) OR
4. A NOR gate followed by a NOR gate is equivalent to a _________
gate.
(a) NAND
(b) NOR
(c) OR
(d) AND
5. _________ gate is an anticoincidence gate.
(a) NAND
(b) NOR
(c) X-OR
(d) X-NOR
6. __________ gate is a coincidence gate.
(a) OR
(b) AND
(c) X-OR
(d) X-NOR
7. __________ gate is an inequality detector.
(a) OR
(b) AND
(c) X-OR
(d) X-NOR
8. ____________ gate is an equality detector.
(a) OR
 (b) AND
(c) X-OR
(d) X-NOR
9. X-OR and X-NOR gates can have _________ inputs.
(a) only two
(b) only three
(c) any number of
(d) maximum of four
10. A NOR gate is a negative
(a) OR gate
(b) AND gate
(c) X-OR gate
(d) X-NOR gate
11. A NAND gate is a negative
(a) OR gate
(b) AND gate
(c) X-OR gate
(d) X-NOR gate
12. NOR gate is also called an active-low
(a) OR gate
(b) AND gate
(c) X-OR gate
(d) X-NOR gate
13. NAND gate is also called an active-low
(a) OR gate
(b) AND gate
(c) X-OR gate
(d) X-NOR gate
14. In TTL positive logic system, logic 0 and logic 1 are respectively
(a) 0 V and + 5 V
(b) 0 V and –5 V
(c) +5 V and 0 V
(d) –5 V and 0 V
15. Logic gates are the basic elements that make a
(a) digital system
(b) analog system
 (c) gating system
(d) basic system
16. The gate whose output is low when all the inputs are low and high for
other combinations of inputs is
(a) OR gate
(b) AND gate
(c) NAND gate
(d) NOR gate
17. The gate whose output is high when all the inputs are high and low for
other combinations of inputs is
(a) OR gate
(b) AND gate
(c) NAND gate
(d) NOR gate
18. The gate whose output is low when all the inputs are high and high for
other combinations of inputs is
(a) OR gate
(b) AND gate
(c) NAND gate
(d) NOR gate
19. The gate whose output is high when all the inputs are low and low for
other combinations of inputs is
(a) OR gate
(b) AND gate
(c) NAND gate
(d) NOR gate
20. The gate whose output is high only when one of its inputs is high is
(a) NAND gate
(b) NOR gate
(c) X-OR gate
(d) X-NOR gate
21. The gate whose output is high only when both the inputs are high is
(a) NAND gate
(b) NOR gate
(c) X-OR gate
(d) X-NOR gate
 PROBLEMS
8.1 Draw the logic diagram and construct the truth table for each of the
following expressions:

8.2 Draw a logic diagram that implements:

(a) A = (Y1  Y2) (Y3  Y4) + (Y5  Y6  Y7)
(b) A = (X1  X2)  (X3  X4) + (X4  X5)  (X6  X7)
8.3 Two square waves, A of 1 kHz and B of 2 kHz frequency, are applied
as inputs to the following logic gates. Draw the output waveform in
each case.
(a) AND
(b) OR
(c) NAND
(d) NOR
(e) X-OR
(f) X-NOR
8.4 Three square waves A, B and C of frequency 1, 2 and 4 kHz,
respectively, are to be
(a) ANDed
(b) ORed
(c) NANDed
(d) NORed
(e) X-ORed
(f) X-NORed
Draw the resultant waveform in each case.
 Chapter 9
Logic Families

Because of the advances in microelectronics, the digital IC technology in

less than four decades has rapidly advanced from small scale integration
(SSI), through medium scale integration (MSI), large scale integration
(LSI), very large scale integration (VLSI), to ultra large scale integration
(ULSI). The technology is now entering giant scale integration (GSI) in
which millions of gate equivalent circuits are integrated on a single chip.
The use of ICs has thus reduced the overall size of a digital system
drastically. Consequently, the cost of digital systems has also reduced. The
reliability has improved as well, because the number of external
interconnections from one device to another has reduced. The power
consumption of digital systems has also reduced greatly, because the
miniature circuitry requires much less power.
ICs have certain limitations too. ICs cannot handle very large voltages or
currents and also electrical devices like precision resistors, inductors,
transformers, and large capacitors cannot be implemented on chips. So, ICs
are principally used to perform low power circuit operations. The
operations that require high power levels or devices that cannot be
integrated are still handled by discrete components.
ICs are fabricated using various technologies such as TTL, ECL, and IIL
which use bipolar transistors, and the MOS and CMOS technologies which
use unipolar MOSFETs.

9.1 DIGITAL IC SPECIFICATION

TERMINOLOGY
Threshold voltage: The threshold voltage is defined as that voltage at the
input of a gate which causes a change in the state of the output from one
logic level to the other.
Propagation delay: The propagation delay of a logic gate is defined as the
time taken by a pulse to propagate from input to output.
Power dissipation: The power dissipation of a logic gate is the power
required by the gate to operate with 50% duty cycle at a specified frequency
and is expressed in milliwatts.
Fan-in: The fan-in of a logic gate is defined as the number of inputs that
the gate is designed to handle.
Fan-out: The fan-out of a logic gate is defined as the maximum number of
similar gates that the output of the gate can drive without impairing its
normal operation.
Noise margin: The noise margin is the maximum noise signal (expressed in
volts) that can be added to the input signal of a digital circuit without
causing an undesirable change in the circuit output.
Speed power product: The speed power product is the product of the
average propagation delay (ns) and the average power dissipation (mW) of
a logic gate. It is the figure of merit of an IC family.

9.2 LOGIC FAMILIES

Many logic families have been developed. They are: Resistor Transistor
Logic (RTL), Direct Coupled Transistor Logic (DCTL), Diode Transistor
Logic (DTL), High Threshold Logic (HTL), Transistor Transistor Logic
(TTL), Emitter Coupled Logic (ECL), Integrated Injection Logic (IIL),
Metal-oxide Semiconductor Logic (MOS), and Complementary Metal-
oxide Semiconductor Logic (CMOS). Out of these, RTL, DCTL, DTL, and
HTL are obsolete. The logic families TTL, ECL, IIL, MOS, and CMOS are
currently in use. The basic function of any type of gate is always the same
regardless of the circuit technology used. The TTL and CMOS are suitable
for SSI and MSI. The MOS and CMOS are particularly suitable for LSI.
The IIL is mainly suitable for VLSI and ULSI. The ECL is mainly used in
superfast computers. The logic families currently in use are compared in
Table 9.1 in terms of the commonly used specification parameters.
Table 9.1 Comparison of logic families
9.3 TRANSISTOR TRANSISTOR LOGIC (TTL)
The TTL or T2L family is so named because of its dependence on
transistors alone to perform basic logic operations. It is the most popular
logic family. It is also the most widely used bipolar digital IC family. The
TTL uses transistors operating in saturated mode. It is the fastest of the
saturated logic families. The basic TTL logic circuit is the NAND gate.
Good speed, low manufacturing cost, wide range of circuits, and the
availability in SSI and MSI are its merits. Tight VCC tolerance, relatively
high power consumption, moderate packing density, generation of noise
spikes and susceptibility to power transients are its demerits.
The TTL logic family consists of several subfamilies or series such as:
Standard TTL, High Speed TTL, Low power TTL, Schottky TTL,
Low power Schottky TTL, Advanced Schottky TTL, Advanced low
power Schottky TTL and F(fast)TTL.
The differences between the various TTL subfamilies are in their
electrical characteristics such as delay time, power dissipation, switching
speed, fan-out, fan-in, noise margin, etc. For standard TTL, propagation
delay time = 9 ns, power dissipation per gate = 10 mW, noise margin = 0.4
mV, fan-in = 8, and fan-out = 10.
For standard TTL, 0 V to 0.8 V is treated as a logic 0 and 2 V to 5 V is
treated as a logic 1. Signals in 0.8 V to 2 V range should not be applied as
input as the corresponding response will be indeterminate. If a terminal is
left open in TTL, it is equivalent to connecting it to HIGH, i.e. + 5 V. But
such a practice is not recommended, since the floating TTL is extremely
susceptible to picking up noise signals that can adversely affect the
operation of the device.
9.3.1 Two-Input TTL NAND Gate (Standard TTL)
In the circuit of the two-input TTL NAND gate shown in Figure 9.1 the
input transistor Q1 is a multiple emitter transistor. Transistor Q2 is called
the phase splitter. Transistor Q3 ‘sits above’ Q4 and, therefore, Q3 and Q4
make a totem pole arrangement. Diodes D1 and D2 protect Q1 from being
damaged by the negative spikes of voltages at the inputs. When negative
spikes appear at the input terminals, the diodes conduct and bypass the
spikes to ground. Diode D ensures that Q3 and Q4 do not conduct
simultaneously. Transistor Q3 acts as an emitter follower.

Figure 9.1 TTL NAND gate.

When both the inputs A and B are HIGH (+ 5 V), both the base-emitter
junctions of Q1 are reverse biased. So, no current flows to the emitters of
Q1. However, the collector-base junction of Q1 is forward biased. So, a
current flows through R1 to the base of Q2, and Q2 turns on. Current from
Q2’s emitter flows into the base of Q4. So, Q4 is turned on. The collector
current of Q2 flows through R2 and, so, produces a drop across it thereby
reducing the voltage at the collector of Q2. Therefore, Q3 is OFF. Since Q4
is ON, Vo is at its low level (VCE (sat)). So, the output is a logic 0, When
either A or B or both are LOW, the corresponding base-emitter junction(s)
is (are) forward biased and the collector-base junction of Q1 is reverse
biased. So, the current flows to ground through the emitters of Q1.
Therefore, the base of Q1 is at 0.7 V, which cannot forward bias the base-
emitter junction of Q2. So, Q2 is OFF. With Q2 OFF, Q4 does not get the
required base drive. So, Q4 is also OFF. Transistor Q3 gets enough base
drive because Q2 is OFF, i.e. since no current flows into the collector of Q2,
all the current flows into the base of Q3, and therefore, Q3 is ON. The
output voltage, Vo = VCC – VR2 – VBE3 – VD  3.4 to 3.8 V, which is a
logic HIGH level. So, the circuit acts as a two-input NAND gate. When Q4
is OFF, no current flows through it, but the stray and output capacitances
between the output terminal, i.e. the collector of Q4, and ground get
charged to this voltage of 3.4 to 3.8 V.
9.3.2 Totem-Pole Output
In the circuit diagram of the two-input TTL NAND gate, transistor Q3 sits
above transistor Q4. As shown in Figure 9.1, Q3 and Q4 are connected in
totem pole fashion. At any time, only one of them will be conducting. Both
cannot be ON or OFF simultaneously. Diode D ensures this. If Q4 is ON, its
base is at 0.7 V w.r.t. ground. Q4 gets base drive from Q2. So, when Q4 is
ON, Q2 has to be ON. Therefore, its collector-to-emitter voltage is VCE
(sat)  0.3 V. Hence, VB3 = VC2  0.7 V + 0.3 V  1 V. For Q3 to be ON,
its base-emitter junction must be forward biased. When Q4 is ON, D has to
be ON for Q3 to be ON simultaneously. So, the base voltage of Q3 must be
VB3 = VCE4(sat) + VD + VBE3  0.7 + 0.3 + 0.7  1.7 V, for it to be ON.
Since VB3 is only 1 V when Q4 is ON, Q3 cannot be ON. Hence, it can be
concluded that Q3 and Q4 do not conduct simultaneously.
Advantages of totem-pole

1. Even though the circuit can work with Q3 and D removed and R4
connected directly to the collector of Q4, with Q3 in the circuit, there
is no current through R4 in the output LOW state. So, the inclusion of
Q3 and D keeps the circuit power dissipation low.
 2. In the output HIGH state, Q3 acts as an emitter follower with its
associated low output impedance. This low output impedance provides
a small time constant for charging up any capacitive load on the
output. This action is commonly referred to as active pull-up and it
provides very fast rise time waveforms at TTL output.

Disadvantages of totem-pole

1. During transition of the output from LOW to HIGH, Q4 turns off more
slowly than Q3 turns on and so, there is a period of a few nanoseconds
during which both Q3 and Q4 are conducting and, therefore, relatively
large currents will be drawn from the supply. So, TTL circuits suffer
from internally generated current transients or current spikes because
of the totem-pole connection.
2. Totem-pole outputs cannot be wire ANDed, that is, the outputs of a
number of gates cannot be tied together to obtain AND operation of
those outputs.

A TTL circuit acts as a current sink in LOW state in that, it receives current
from the input of the gate it is driving. Q4 is the current-sinking transistor
or the pull-down transistor, because it brings the output voltage down to its
LOW state.
A TTL circuit acts as a current source in the HIGH state, in that, it
supplies current to the gate it is driving. Q3 is the current-sourcing
transistor or the pull-up transistor, because it pulls up the output voltage to
its HIGH state.
9.3.3 Open-Collector Gates
The TTL gates may have totem-pole output or open-collector output. In
open-collector TTL, the output is at the collector of Q4 with nothing
connected to it, (i.e. pull-up transistor Q3 and diode D of the totem-pole
output are omitted), therefore, the name open collector. The open-collector
inverter circuit is shown in Figure 9.1. In order to get the proper HIGH and
LOW logic levels out of the circuit, an external pull-up resistor is connected
to VCC from the collector of Q4 as shown in Figure 9.2 When Q4 is OFF,
the output is pulled to VCC through the external resistor R. When Q4 is ON,
the output is connected to near ground through the saturated transistor. The
value of R must be so chosen that when one gate output goes LOW while
the others are HIGH, the sink current through the LOW output does not
exceed the IOL(max) limit. Since the output is pulled to logic HIGH level
through a resistor, it is called the passive pull-up. The open-collector
arrangement is much slower than the totem-pole arrangement, because the
time constant with which the load capacitance charges in this case is
considerably larger. (In the case of totem-pole, it is active pull-up, i.e. pull-
up is through transistor Q3. The RON of Q3 is very small; so, the charging
time constant is low and the output rises fast.) The speed can be increased
only a little bit by choosing a smaller resistance. For this reason, the open-
collector circuits should not be used in applications where switching speed
is a principal consideration. The advantage of open collector gates is they
can be wire ANDed.

Figure 9.2 Circuit diagram of open-collector inverter.

9.3.4 Tri-State (3-State) TTL

The third TTL configuration is the tri-state configuration. It utilizes the
advantage of high speed of operation of the totem-pole configuration and
wire ANDing of the open-collector configuration. It is called the tri-state
TTL, because it allows three possible output states: HIGH, LOW, and
HIGH impedance (Hi-Z). In the Hi-Z state, both the transistors in the totem-
pole arrangement are turned off, so that the output terminal is a HIGH
impedance to ground or VCC. In fact, the output is an open or floating
terminal, that is, neither a LOW nor a HIGH. In practice, the output
terminal is not an exact open circuit, but has a resistance of several M or
more relative to ground and VCC.
The circuit of a tri-state inverter is shown in Figure 9.3. The tri-state
operation is obtained by modifying the basic totem-pole circuit of Figure
9.1. The circuit has two inputs—A is the normal logic input and E is an
enable input that can produce the Hi-Z.

Figure 9.3 Tri-state TTL inverter.

The enabled state

With E = 1, the circuit operates as a normal inverter because the high
voltage at E has no effect on Q1 or Q2. In this enabled condition, the output
is simply the inversion of logic input A.
The disabled state (Hi-Z)
When E = 0, the circuit goes into its Hi-Z state regardless of the state of
logic input A. The Low at E forward biases the emitter base junction of Q1
and shunts the current in R1 away from Q2, so that, Q2 turns off, which in
turns Q4 off. The LOW at E also forward biases diode D1 to shunt current
away from the base of Q3, and therefore, Q3 also turns off. With both
totem-pole transistors in the non-conducting state, the output terminal is
essentially an open circuit.
There are many ICs that are designed with tri-state outputs. The
advantage of the tri-state configuration is that the outputs of the tri-state ICs
can be connected together without sacrificing the switching speed. Figure
9.3(b) shows the logic symbol of a tri-state TTL inverter.
9.3.5 Schottky TTL
The standard TTL, low power TTL, and high speed TTL series operate
using saturated switching. When a transistor is saturated, excess charge
carriers will be stored in the base region and they must be removed before
the transistor can be turned off. So, owing to storage time delay, the speed is
reduced. The Schottky TTL reduces this storage time delay by not allowing
the transistor to go into full saturation. This is accomplished by using a
Schottky barrier diode (SBD) between the base and the collector of each
transistor. Virtually, all modern TTL devices incorporate this so-called
Schottky clamp. The SBD has a forward voltage of only 0.25 V. The
Schottky TTL also uses smaller resistance values to improve the speed of
operation. The speed of the Schottky TTL is twice that of the 74H series.
The Schottky TTL has more than three times the switching speed of
standard TTL, at the expense of approximately doubling the power
consumption. Figure 9.4 shows the circuit diagram of a two-input Schottky
TTL NAND gate.
 Figure 9.4 Circuit diagram of a two-input Schottky TTL NAND gate.

9.4 INTEGRATED INJECTION LOGIC (IIL OR

I2L)
Integrated injection logic (IIL or I2L) or current injection logic (CIL) is the
newest of the logic families, which is finding widespread use in LSI and
VLSI circuits. It is not suitable for discrete gate ICs. The I2L logic gates are
constructed using bipolar transistors only. The absence of resistors makes it
possible to integrate a large number of gates on a single package. Complete
microprocessors can be obtained on a single chip. The I2L circuits are
easily fabricated and are economical. Their power consumption is also low.
The speed–power product is constant and very small of the order of 4 pJ,
comparable to advanced low power Schottky TTL. The I2L has, tpd = 1 ns,
PD = 1 mW, NM = 0.35 V, fan-out = 8 and the relative cost is very low.
In I2L, since the currents are constant, no transients are produced as in
TTL and MOS. It can easily be integrated on the same chip with bipolar
analog circuits such as op-amps. By programming the injector currents, the
propagation delay and power dissipation can be varied over a wide range.
The disadvantage is that, it requires one more step in its manufacturing
process than those used in MOS.

9.4.1 I2L Inverter

Since discrete gates are not available in I2L, the operation of an I2L inverter
can be explained by considering the inverter of Figure 9.5(a) that behaves in
the same way as an I2L inverter. The P–N–P transistor Q1 serves as a
constant current source that ‘injects’ current into node X. The direction in
which the current flows after entering node X depends on the input level. A
LOW input is a current sink. When the input is LOW, the injected current
flows into the input, thus, diverting current from the base of Q2. Transistor
Q2 is, therefore, OFF and the output is HIGH. If the input is HIGH, the
injected current flows into the base of Q2 turning it ON and making the
output LOW as shown in Figure 9.5(b). Figure 9.5(c) shows an actual I2L
inverter. The output transistor has two collectors (sometimes three), making
it equivalent to two transistors with parallel bases and emitters. Thus, it
produces two equal outputs. Instead of a collector resistor, the outputs are
connected directly to the inputs of other I2L gates.

Figure 9.5 I2L inverters.

9.4.2 I2L NAND Gate

The I2L NAND gate shown in Figure 9.6 is simply an inverter with inputs
connected directly together at the inverter input. If, either input A, or input
B, or both the inputs A and B are LOW (current sinks), the injected current
flows into those inputs and Q2 remains OFF (HIGH). If both the inputs are
HIGH, the injected current turns on Q2 making the output LOW. Thus,
NAND operation is performed. The transistor Q1 is called a current injector
transistor, because when its emitter is connected to an external power
source, it can supply current to the base of Q2.

Figure 9.6 Two-input I2L NAND gate.

9.4.3 I2L NOR Gate

The I2L NOR gate shown in Figure 9.7 is simply two inverters with their
outputs connected together. If either or both the inputs are HIGH, the
corresponding output transistor is ON and the output is a current sink. So,
the output is LOW. If both the inputs are LOW, both the output transistors
are OFF, and so, the output is HIGH. This is a NOR operation.

Figure 9.7 Two-input I2L NOR gate.

9.5 EMITTER-COUPLED LOGIC (ECL)
Emitter-coupled logic (ECL), also called current-mode logic or current-
steering logic, is the fastest of all logic families because of the following
reasons:

1. It is a non-saturated logic, in the sense that the transistors are not

allowed to go into saturation. So, storage time delays are eliminated
and, therefore, the speed of operation is increased.
2. Currents are kept high, and the output impedance is so low that circuit
and stray capacitances can be quickly charged and discharged.
3. The limited voltage swing.

The ECL is so named because of its use of BJTs that are coupled (joined)
at their emitters. In ECL, the transistors are prevented from going into
saturation when the input changes from LOW to HIGH, by choosing logic
levels very close to each other. One disadvantage of having logic levels
close to each other is that, it is difficult to achieve good noise immunity.
Also, the power consumption is increased since the transistors are not
saturated. But the advantage is that the current drawn from the supply is
more steady and ECL gates do not experience large switching transients.
The ECL family has considerably greater power consumption compared to
other families.
The ECL operates on the principle of current switching, whereby a fixed
bias current less than IC(sat) is switched from one transistor’s collector to
another. Because of this current-mode operation, this logic form is also
referred to as current-mode logic (CML). It is also called current-steering
logic (CSL), because current is steered from one device to another. The
ECL family is not as popular and widely used as the TTL and MOS, except
in very high frequency applications where its speed is superior. It has the
following drawbacks:

1. High cost
2. Low noise margin
3. High power dissipation
 4. Its negative supply voltage and logic levels are not compatible with
other logic families (making it difficult to use ECL in conjunction with
TTL and MOS circuits).
5. Problem of cooling

Still, the ECL is used in superfast computers and high-speed special

purpose applications. The ECL gates can be wired ORed, no noise spikes
are generated, and complementary outputs are also available. The important
characteristics of ECL gates are as follows:

1. Transistors never saturate. So, speed is high with tpd = 1 ns.

2. Logic levels are negative, – 0.9 V for a logic 1 and – 1.7 V for a logic
0.
3. Noise margin is less, about 250 mV. This makes ECL unreliable for
use in heavy industrial environment.
4. ECL circuits produce the output and its complement, and therefore,
eliminate the need for inverters.
5. Fan-out is large because the output impedance is low. It is about 25.
6. Power dissipation per gate is large, PD = 40 mW.
7. The total current flow in ECL is more or less constant. So, no noise
spikes will be internally generated.

9.5.1 ECL OR/NOR Gate

Figure 9.8 shows a two-input ECL OR/NOR gate. It has two outputs
which are complements of each other. Transistors Q2 and Q1A form a
differential amplifier. Transistors Q1A and Q1B are in parallel. Transistors
Q3 and Q4 are emitter followers whose emitter voltages are the same as the
base voltages (less than 0.8 V base to emitter drops). Inputs are applied to
Q1A and Q1B, and Q2 is supplied with constant –1.3 V.
 Figure 9.8 Two-input ECL OR/NOR gate.

When the inputs A and B are both LOW, i.e. – 1.7 V, Q2 is more forward
biased than Q1A and Q1B, and so, Q2 is ON and Q1A and Q1B are OFF.
The value of R2 is such that current flowing through Q2 puts the collector at
about – 0.9 V. Therefore, the emitter of Q4 is at, – 0.9 – 0.8 = – 1.7 V, and
so, the OR output is LOW. The base current of Q3 passing through R1 is
very small. The value of R1 is such that this current puts the collectors of
Q1A and Q1B at about – 0.1 V. So, the emitter of Q3 is at, – 0.1 – 0.8 = –
0.9 V, that is, the NOR output is HIGH.
When A is HIGH, or B is HIGH, or both A and B are HIGH, the
corresponding transistors are ON, because they are more forward biased
than Q2, and Q2 is OFF. So, the collectors of Q1A and Q1B are at – 0.9 V,
which makes the NOR output = – 0.9 – 0.8 = – 1.7 V, i.e. a logic 0. Only the
small base current of Q4 flows through R2. So, the collector of Q2 is
approximately at – 0.1 V, and therefore, the OR output is, – 0.1 – 0.8 = – 0.9
V, i.e. a logic 1. This shows that the above circuit works as a OR/NOR gate.
One advantage of the differential input circuitry in ECL gates is that, it
provides common mode rejection—power supply noise common to both
sides of the differential configuration is effectively cancelled out
(differenced out). Also, since the ECL output is produced at an emitter
follower, the output impedance is desirably low. As a consequence, the ECL
gates not only have a large fan-out, but also are relatively unaffected by
capacitive loads. Some ECL gates are available with multiple outputs, that
are derived from multiple emitter transistors in the emitter-follower output.
For example, one OR/NOR gate may have two OR outputs and two NOR
outputs.
The ECL gates are available with open-emitter outputs, that is, with
resistors in the output emitter followers omitted. The open-emitter outputs
can be connected together directly, and the common emitter output terminal
may be connected through an external resistor to a negative supply voltage
(–5.2 V) to perform a wired OR operation.

9.6 METAL OXIDE SEMICONDUCTOR (MOS)

LOGIC
The MOS logic is so named because it uses metal oxide semiconductor field
effect transistors (MOSFETs). Compared to the bipolar logic families, the
MOS families are simpler and inexpensive to fabricate, require much less
power, have a better noise margin, a greater supply voltage range, a higher
fan-out, and require much less chip area. But they are slower in operating
speed and are susceptible to static charge damage. For MOS logic, tpd = 50
ns, NM = 1.5 V (for + 5 V supply), PD = 0.1 mW, and fan-out = 50 for
frequencies greater than 100 Hz and it is virtually unlimited for dc or low
frequencies. The propagation delay associated with MOS gates is large (50
ns) because of their high output resistance (100 k) and capacitive loading
presented by the driven gates.
The MOS logic is the simplest to fabricate and occupies very small space,
because it requires only one basic element—an NMOS or a PMOS
transistor. It does not require other elements like resistors and diodes, which
occupy large space. Because of its ease of fabrication and lower power
dissipation per gate PD, it is ideally suited for LSI, VLSI, and ULSI for
dedicated applications such as large memories, calculator chips, large
microprocessors, etc. The operating speed of MOS is slower than that of
TTL, so, they are hardly used in SSI and MSI applications. The greater
packing density of MOS ICs results in higher reliability because of the
reduction in the number of external connections.
Because of the very high impedance present at a MOSFET’s input, the
MOS logic families are more susceptible to static charge damage. The
CMOS family is less susceptible to static charge damage.
 There are presently two general types of MOSFETs—depletion type and
enhancement type. The MOS digital ICs use enhancement MOSFETs
exclusively. The MOSFETs can be of NMOS type or PMOS type. Most
modern MOSFET circuitry is constructed using NMOS devices, because
they operate at about three times the speed of their PMOS counterparts, and
also have twice the packing density of PMOS.
Both NMOS and PMOS have greater packing density than that of CMOS,
and are therefore, more economical than CMOS. The CMOS family has the
greatest complexity and the lowest packing density of all the MOS families,
but it possesses the important advantages of higher speed and much lower
power dissipation. The CMOS can be operated at high voltage resulting in
improved noise margin.
9.6.1 Symbols and Switching Action of NMOS and PMOS
Figure 9.9(a) shows the circuit symbol of NMOSFET. Figure 9.9(b) shows
its equivalent as a closed switch when it is ON, and Figure 9.9(c) shows its
equivalent as an open switch when it is OFF.

Figure 9.9 Circuit symbol and ON and OFF equivalents of NMOSFET.

Figure 9.10(a) shows the circuit symbol of PMOSFET. Figure 9.10(b)

shows its equivalent as a closed switch when it is ON, and Figure 9.10(c)
shows its equivalent as an open switch when it is OFF.

Figure 9.10 Circuit symbol and ON and OFF equivalents of PMOSFET.

The arrow in the symbols of MOSFETs indicates either P or N channel.

In the channel, the broken line between the source and the drain indicates
that normally there is no conducting channel between these electrodes. The
separation between the gate and the other terminals indicates the existence
of very high resistance (10,000 M) between the gate and the channel. The
switch in a MOSFET is between the drain and source terminals. The gate-
to-source voltage VGS controls the switch. In an N-channel MOSFET,
switch closes and current flows from drain to source when VGS is positive,
and switch opens when VGS is negative or zero w.r.t. the source.

9.6.2 Resistor
A MOS transistor can be connected as a resistor as shown in Figure 9.11.
The value of the resistance presented by a resistor-connected NMOS device
depends on the current through it. The gate is permanently connected to + 5
V, and so, it is always in the ON state and the transistor acts as a resistor of
value RON. The load resistor is designed to have a narrower channel, so, its
RON is much greater than the RON of the switching transistor. Typically, its
RON = 100 k.

Figure 9.11 NMOS connected as a resistor.

9.6.3 NMOS Inverter

The basic NMOS inverter shown in Figure 9.12 contains two N-channel
MOSFETs. Q1 is called the load MOSFET and Q2 the switching MOSFET.
Q2 will switch from ON to OFF in response to Vin. These two MOSFETs
can be considered as resistors and the circuit as a potential divider.
 Figure 9.12 Circuit diagram and equivalent circuits for various inputs of the NMOS inverter.

• When Vin = 0 V, Q2 is OFF. So, its ROFF = 1010 , and the equivalent
circuit (b) results. Therefore,
Vout =   5 V
• When Vin = 5 V, Q2 is ON. So, its RON = 1 k, and the equivalent
circuit (c) results. Therefore,
Vout = =  0 V
This shows that the above circuit acts as an inverter. The truth table is
shown in Figure 9.12(d).
9.6.4 NMOS NAND Gate
Figure 9.13 shows an NMOS two-input NAND gate and its equivalent
circuits for different possible combinations of inputs in terms of resistance
values of transistors in ON and OFF positions.
 Figure 9.13 Circuit diagram and equivalent circuits for various inputs of the NMOS NAND gate.

In the NMOS NAND gate shown, Q1 is acting as a load resistor and Q2

and Q3 as switches controlled by input levels A and B, respectively.
• When both A and B are 0 V, both Q2 and Q3 are OFF. So, the
equivalent circuit (b) results with Vout = + 5 V.
• When A = 0 V and B = + 5 V, Q2 is OFF and Q3 is ON. So, the
equivalent circuit (c) results with Vout = + 5 V.
• When A = + 5 V and B = 0 V, Q2 is ON and Q3 is OFF. So, the
equivalent circuit (d) results with Vout = + 5 V.
• When A = + 5 V and B = + 5 V, both Q2 and Q3 are ON. So, the
equivalent circuit (e) results with Vout = 0 V.
Thus, the above circuit works as a positive logic two-input NAND gate.
9.6.5 NMOS NOR Gate
Figure 9.14 shows an NMOS two-input NOR gate and its equivalent
circuits for different possible combinations of inputs in terms of resistance
values of transistors in ON and OFF positions. Q1 is the resistor-connected
NMOS transistor that serves as a load and Q2 and Q3 are the switching
transistors controlled by the inputs A and B, respectively.
 Figure 9.14 Circuit diagram and equivalent circuits for various inputs of the NMOS NOR gate.

• When A is LOW and B is LOW, Q2 is OFF and Q3 is OFF. So, the

equivalent circuit (b) results with Vout = + 5 V.
• When A is LOW and B is HIGH, Q2 is OFF and Q3 is ON. So, the
equivalent circuit (c) results with Vout = 0 V.
• When A is HIGH and B is LOW, Q2 is ON and Q3 is OFF. So, the
equivalent circuit (d) results with Vout = 0 V.
• When A is HIGH and B is HIGH, Q2 is ON and Q3 is ON. So, the
equivalent circuit (e) results with Vout = 0 V.
Thus, the above circuit works as a positive logic two-input NOR gate. The
truth table is shown in Figure 9.14.

9.7 COMPLEMENTARY METAL OXIDE

SEMICONDUCTOR (CMOS) LOGIC
The CMOS logic family uses both P and N channel MOSFETs in the same
circuit to realize several advantages over the PMOS and NMOS families.
The CMOS family is faster and consumes less power than the other MOS
families. These advantages are offset somewhat by the increased
complexity of the IC fabrication process and a lower packing density. The
CMOS can be operated at higher voltages resulting in improved noise
immunity. It is widely used for general purpose logic circuitry. The CMOS
technology has been used to construct small, medium, and large scale ICs
for a wide variety of applications ranging from general-purpose logic to
microprocessors. Because of its extremely small power consumption, it is
useful for applications in watches and calculators. The CMOS, however,
cannot yet compete with MOS in applications requiring the utmost in LSI.
The CMOS has very high input resistance. Thus, it draws almost zero
current from the driving gate and, therefore, its fan-out is very high. Its
output resistance is small (1 k) compared to that of NMOS (100 k).
Hence, it is faster than NMOS. The speed of CMOS decreases with increase
in load. In CMOS, there is always a very high resistance between the VDD
terminal and ground, because of the MOSFET in the current path. Hence,
its power consumption is very low. The noise margin of CMOS is the same
in both the LOW and HIGH states and it is 30% of VDD, indicating that
noise margin increases with an increase in power supply voltage. So in
noisy environments, CMOS with large VDD is preferred. However, an
increase in VDD results in the corresponding increase in PD. The CMOS
loses some of its advantages at high frequencies.
In MSI, the CMOS is also competitive with TTL. The CMOS fabrication
process is simpler than that of the TTL and it has greater packing density,
thereby permitting more circuitry in a given area and reducing the cost per
function. The CMOS uses only a fraction of the power needed even for low
power TTL and is, thus, ideally suited for applications requiring battery
power or battery backup power. The CMOS is, however, generally slower
than TTL.
9.7.1 CMOS Inverter
Figure 9.15 shows a CMOS inverter and its equivalent circuits for different
inputs. It consists of an NMOS transistor Q1 and a PMOS transistor Q2.
The input is connected to the gates of both the devices and the output is at
the drain of both the devices. The positive supply voltage is connected to
the source of the PMOS transistor Q2, and the source of Q1 is grounded.
 • When Vin = 0 V (LOW), VGS2 = – 5 V, and VGS1 = 0 V. So, Q2 is ON
and Q1 is OFF. Therefore, the switching circuit (b) results with Vout = 5
V.
• When Vin = + 5 V (HIGH), VGS2 = 0 V and VGS1 = + 5 V. So, Q2 is
OFF and Q1 is ON. Therefore, the switching circuit (c) results with Vout
= 0 V.
Thus, the above circuit acts as an inverter.

Figure 9.15 Circuit diagram and equivalent circuits for various inputs of the CMOS inverter.

9.7.2 CMOS NAND Gate

Figure 9.16 shows a CMOS two-input NAND gate and its equivalent
circuits for various input combinations. Here, Q1 and Q2 are parallel-
connected PMOS transistors, and Q3 and Q4 are series-connected NMOS
transistors.
• When A = 0 V and B = 0 V, VGS1 = VGS2 = – 5 V, VGS3 = VGS4 = 0
V. So, Q1 is ON, Q3 is OFF, Q2 is ON and Q4 is OFF. Thus, the
switching circuit (b) results with Vout = + 5 V.
• When A = 0 V and B = + 5 V, VGS1 = – 5 V, VGS2 = 0 V, VGS3 = 0 V,
VGS4 = 5 V. So, Q1 is ON, Q3 is OFF, Q2 is OFF and Q4 is ON. Thus,
the switching circuit (c) results with Vout = + 5 V.
• When A = + 5 V and B = 0 V, VGS1 = 0 V, VGS2 = – 5 V, VGS3 = 5 V,
VGS4 = 0 V. So, Q1 is OFF, Q3 is ON, Q2 is ON and Q4 is OFF. Thus,
 the switching circuit (d) results with Vout = + 5 V.
• When A = + 5 V and B = + 5 V, VGS1 = VGS2 = 0 V, VGS3 = VGS4 =
5 V. So, Q1 is OFF, Q3 is ON, Q2 is OFF and Q4 is ON. Thus, the
switching circuit (e) results with Vout = 0 V.
Thus, the circuit works as a two-input NAND gate. The truth table is shown
in Figure 9.16(f).

Figure 9.16 Circuit diagram and equivalent circuits for various inputs of the CMOS NAND gate.

9.7.3 CMOS NOR Gate

Figure 9.17 shows a CMOS two-input NOR gate and its equivalent circuits
for various input combinations. Here, the NMOS transistors Q3 and Q4 are
connected in parallel and the PMOS transistors Q1 and Q2 in series.
The operation of the CMOS NOR gate can be explained as follows:
• When A = 0 V and B = 0 V, VGS1 = VGS2 = – 5 V, VGS3 = VGS4 = 0
V. So, Q1 and Q2 are ON, and Q3 and Q4 are OFF. Thus, the equivalent
circuit (b) results with Vout = + 5 V.
• When A = 0 V and B = + 5 V, VGS1 = – 5 V, VGS2 = 0 V, VGS3 = 0 V,
VGS4 = 5 V. So, Q1 and Q4 are ON, and Q2 and Q3 are OFF. Thus, the
equivalent circuit (c) results with Vout = 0 V.
• When A = + 5 V and B = 0 V, VGS1 = 0 V, VGS2 = – 5 V, VGS3 = 5 V,
VGS4 = 0 V. So, Q1 and Q4 are OFF, and Q2 and Q3 are ON. Thus, the
equivalent circuit (d) results with Vout = 0 V.
• When A = + 5 V and B = + 5 V, VGS1 = VGS2 = 0 V, VGS3 = VGS4 =
5 V. So, Q1 and Q2 are OFF, and Q3 and Q4 are ON. Thus, the
equivalent circuit (e) results with Vout = 0 V.
The above analysis shows that the circuit works as a two-input NOR gate.
The truth table is shown in Figure 9.17(f).
 Figure 9.17 Circuit diagram and equivalent circuits for various inputs of the CMOS NOR gate.

9.7.4 Transmission Gate

A transmission gate is simply a digitally controlled CMOS switch. When
the switch is open (OFF), the impedance between its terminals is very large.
It is used to implement special logic functions. Since the CMOS gate can
transmit signals in both directions, it is called a bilateral transmission gate.
It is also called a bilateral switch. It is useful for digital and analog
applications. The TTL and ECL gates are essentially unidirectional.
Figure 9.18 shows a schematic diagram and logic symbols of a CMOS
transmission gate. The NMOS and PMOS transistors are connected in
parallel. So, both polarities of input voltages can be switched. The
CONTROL signal is connected to the NMOSFET and its inverse is
connected to the PMOSFET. When the CONTROL is HIGH, the gate of
PMOSFET Q1 is LOW and the gate of NMOSFET Q2 is HIGH. If the
input (data) is LOW, VGS1 is 0 V and VGS2 is positive. So, Q1 is OFF and
Q2 is ON. If the input is HIGH, VGS1 is negative and VGS2 is 0 V. So, Q1
is ON and Q2 is OFF. Thus, there is always one conducting path from input
to output when the CONTROL is HIGH.

Figure 9.18 Circuit diagram and logic symbols of the CMOS transmission gate.

On the other hand, when the CONTROL is LOW, the gate of PMOSFET
Q1 is HIGH and the gate of NMOSFET Q2 is LOW. If the input (data) is
LOW, VGS1 is positive and VGS2 is 0 V. Therefore, Q1 is OFF and Q2 is
also OFF. If the input (data) is HIGH, VGS1 is 0 V and VGS2 is negative.
So, again Q1 is OFF and Q2 is also OFF. Thus, there is no conducting path
from input to output when the CONTROL is LOW.
So, we can conclude that when the CONTROL is HIGH, the circuit acts
as a closed switch and allows the transmission of the signal from input to
output. When the CONTROL is LOW, the circuit acts as an open switch
and blocks the transmission of the signal from input to output. The
CONTROL acts as an active-HIGH enabling signal. Active-LOW enabling
is possible, if the CONTROL is connected to the gate of PMOS and to the
gate of NMOS.
Since the input and output terminals can be interchanged, the circuit can
also transmit signals in the opposite direction. Hence, it acts as a bilateral
switch.

9.8 DYNAMIC MOS LOGIC

When power consumption and physical size are the prime design
considerations as in digital watches and calculators dynamic MOS logic is
usually the family selected to meet these requirements. Each transistor used
in a dynamic MOS circuit is identical to the other, and each can be
fabricated in a very small amount of space on a chip. Consequently, large
and very large scale integrations are possible.
In dynamic MOS logic, power consumption is minimized by relying on
the inherent capacitance of the MOS transistors to store logic levels, i.e. to
remain charged or discharged—and by using clock signals to turn on
transistors for very brief intervals of time only. The clock signals turn
transistors on to allow the capacitance to recharge or discharge at periodic
intervals. Since a transistor is OFF during most of any given time interval,
the average power consumption is quite small.
The NMOS transmission gate shown in Figure 9.19(a) is a fundamental
component of dynamic logic circuits. Because the NMOSFET is completely
symmetrical, the drain and source terminals are indistinguishable, i.e.
current can flow in either direction. In dynamic logic applications, there is a
shunt capacitance at each of these terminals identified in the figure as C1
and C2.

Figure 9.19 NMOS transmission gate.

When the gate terminal G is LOW, the transistor will be OFF irrespective
of the potentials at drain and source, i.e. irrespective of charges on C1 and
C2, because the gate-to-source voltage may be either 0 V or negative. Once
the transistor is OFF, it acts as an open switch as shown in Figure 9.19(b)
and the charges on capacitors remain as they are. That is, no transfer of
charge takes place, and therefore, no signal transmission takes place.
When G is HIGH, the transistor is ON and acts as a closed switch as
shown in Figure 9.19(c). If capacitors C1 and C2 are charged to the same
level, no transfer of charge takes place. But if one capacitor is charged and
the other discharged, transfer of charge takes place from one capacitor to
the other, i.e. the input is transmitted to the output.
9.8.1 Dynamic MOS Inverter
Figure 9.20 shows a dynamic MOS inverter. The capacitance shown by
dotted lines represents the inherent device (interelectrode) capacitance. The
f1 and f2 are the control signals that are used to control the ON and OFF of
Q2 and Q3. The two together are called a two-phase non-overlapping clock,
because f1 and f2 are never both HIGH at the same time. As in the case of a
normal MOS inverter, Q1 acts as a switching transistor and Q2 as a load
resistor. The only difference is that, in this case Q2 acts as an active load
only when clock f1 is HIGH. The rest of the time (i.e. when f1 is LOW), Q2
is OFF and does not allow any current to pass through it. The transistor Q3
acts as a transmission gate, i.e. it transfers charge only when clock f2 is
HIGH. The rest of the time (i.e. when f2 is LOW), no transfer of charge
takes place.

Figure 9.20 Dynamic MOS inverter.

 When Vin is LOW, Q1 is OFF. When f1 goes HIGH, Q2 conducts and C1
is charged, but when f1 goes LOW, there is no path for C1 to discharge, and
so, C1 remains charged. When f2 goes HIGH, this charge on C1 is
transferred to C2, and so, Vout goes HIGH. Thus, a LOW at the input
results in a HIGH at the output.
Suppose Vin is HIGH, when f1 goes HIGH, Q2 conducts and Q1 also
turns on. So, C1 cannot charge. When f2 goes HIGH, Q3 acts as a closed
switch and C2 discharges into C1. So, Vout goes LOW. Vout remains LOW
when f2 is LOW. Thus, a HIGH at the input results in a LOW at the output.
Therefore, the above circuit acts as an inverter.
The output of a dynamic logic gate is ‘valid’ only when f2 is HIGH.
Thus, we can say that the gates are sampled at the frequency of f2. A
sampled output becomes the input to other gates, whose responses become
available only at the next sampling time. The disadvantage of dynamic logic
is the complexity added by the clocking requirements. The capacitors need
to be recharged periodically so that the charge on the capacitors does not
decay very much. This process of recharging is called refreshing. The
minimum clock frequency is, therefore, determined by the amount of time
taken by the capacitance to decay significantly. A typical period is 1 ms,
giving a minimum clock frequency of 1 kHz.
9.8.2 Dynamic MOS NAND Gate
Figure 9.21 shows a dynamic two-input MOS NAND gate and its
equivalent switching circuit. The only difference between this and the static
NMOS NAND gate is that, the load MOSFET is clocked by f1 and a
transmission gate is added at the output and the outputs are clocked through
the transmission gate by f2.
 Figure 9.21 Dynamic MOS NAND gate.

When f1 goes HIGH, C1 is charged according to the NAND logic of

inputs A and B and when f2 goes HIGH, this charge is transferred from C1
to C2. So, the output Vout follows the NAND logic.
When either A is LOW, or B is LOW, or both A and B are LOW, the
corresponding MOSFETs (QA and QB) will be OFF and no current passes
through them. Thus, C1 is charged when f1 goes HIGH, and this charge on
C1 is transferred to C2, when f2 goes HIGH. Therefore, the output goes
HIGH (C1 remains discharged after f2 goes LOW).
Only when both A and B are HIGH, QA and QB will turn on when f1
goes HIGH and, therefore, no current flows through C1 and it does not
charge and remains in the discharged condition only. When f2 goes HIGH,
C2 discharges into C1, and so the output goes LOW. Hence, this circuit
works as a two-input NAND gate.
9.8.3 Dynamic MOS NOR Gate
Figure 9.22 shows a dynamic two-input MOS NOR gate and its equivalent
switching circuit. The only difference between this and the static NMOS
NOR gate is that, the load MOSFET is clocked by f1 and a transmission
gate is added at the output and the outputs are clocked through the
transmission gate by f2.
 Figure 9.22 Dynamic MOS NOR gate.

When f1 goes HIGH, C1 is charged according to the NOR logic of inputs

A and B, and when f2 goes HIGH, this charge is transferred from C1 to C2.
So, the output Vout follows the NOR logic.
When both A and B are LOW, QA, and QB will be OFF. So, C1 charges
when f1 goes HIGH and this charge on C1 is transferred to C2 when f2 goes
HIGH, and so, the output goes HIGH. (C1 remains discharged, after f2 goes
LOW).
When either A is HIGH or B is HIGH or both A and B are HIGH, either
QA or QB or both QA and QB will turn on when f1 goes HIGH, keeping
C1 in the discharged condition only. When f2 goes HIGH, the charge on C2
is transferred to C1, and so, the output goes LOW. Hence, this circuit works
as a two-input NOR gate.

SHORT QUESTIONS AND ANSWERS

1. What are the merits of ICs?
A. The merits of ICs are as follows:
Use of ICs (a) reduces the overall size of the digital system drastically,
(b) reduces the cost of the digital system, (c) improves the reliability of
the system by reducing the number of external connections from one
device to another, and (d) greatly reduces the power consumption of
digital systems.
2. What are the limitations of ICs?
A. The limitations of ICs are as follows: (a) ICs cannot handle large
voltages or currents, (b) electrical devices like precision resistors,
inductors, transformers and large capacitors cannot be implemented on
chips and (c) they are mainly suitable for low power applications only.
3. ICs are fabricated using which technologies?
A. Presently ICs are fabricated using TTL, ECL, IIL, MOS and CMOS
technologies.
4. Name the technologies which use bipolar transistors.
A. TTL, ECL and IIL technologies use bipolar transistors.
5. Name the technologies which use unipolar transistors.
A. MOS and CMOS technologies use unipolar transistors.
6. Define the terms: (a) Threshold voltage, (b) propagation delay, (c)
power dissipation, (d) fan-in, (e) fan-out, (f) noise margin, and (g)
speed power product.
A. (a) The threshold voltage is defined as that voltage at the input of a
gate which causes a change in the state of the output from one logic
level to the other.
(b) The propagation delay of a gate is defined as the time taken by the
pulse to propagate from input to output.
(c) The power dissipation of a gate is defined as the power required by
the gate to operate with 50% duty cycle at a specified frequency.
(d) The fan-in of a logic gate is defined as the number of inputs that
the gate is designed to handle.
(e) The fan-out of a logic gate is defined as the maximum number of
similar gates that the output of the gate can drive without impairing its
normal operation.
(f) The noise margin is defined as the maximum noise signal that can
be added to the input signal of a digital circuit without causing an
undesirable change in the circuit output.
(g) The speed power product of a logic gate is defined as the product
of the gate propagation delay and the gate power dissipation.
7. Which technologies are obsolete?
A. The RTL, DCTL, DTL, and HTL technologies are obsolete.
8. Define standard load.
A. A standard load is defined as the amount of current needed by an
 input of another gate of the same logic family.
9. Which is the most popular and most widely used digital IC family.
A. TTL is the most popular and most widely used digital IC family.
10. Name the three types of TTL gates.
A. The three types of TTL gates are: (a) totem pole type, (b) open
collector type, and (c) tri-state type.
11. What are the three possible output states of a tri-state IC?
A. The three possible output states of a tri-state IC are: LOW, HIGH
and HIGH impedance state.
12. When does a TTL circuit act as a current sink? Source?
A. A TTL circuit acts as a current sink in the low state and as a current
source in the high-state.
13. What do you mean by Schottky TTL? Why is it faster than standard
TTL?
A. Schottky TTL is one which uses transistors having a Schottky
barrier diode between the base and collector of each transistor. It is
more than three times faster than standard TTL because in this the
transistors are not allowed to go fully into saturation and also it uses
smaller resisters.
14. Which TTL series is most suitable at high frequencies?
A. F (fast) TTL, 74F series is the most suitable at high frequencies.
15. Which gates are suitable for wired AND operation?
A. TTL open collector gates are suitable for wired and operation.
16. What are the merits and demerits of TTL?
A. Good speed, low manufacturing cost, wide range of circuits and the
availability in SSI and MSI are the merits of TTL. Tight VCC
tolerance, relatively high power consumption, moderate packing
density, generation of noise spikes and susceptibility to power
transients are the demerits of TTL.
17. How many TTL subfamilies are there? Name them.
A. There are eight TTL subfamilies. They are: (a) standard TTL, (b)
high speed TTL, (c) low power TTL, (d) Schottky TTL, (e) low power
Schottky TTL, (f) advanced Schottky TTL, (g) advanced low power
Schottky TTL, and (h) F(fast) TTL.
18. What are the advantages and disadvantages of totem-pole
configuration?
A. The totem-pole configuration has the advantages of high speed and
low power dissipation,but the disadvantages of generation of current
spikes and the inability to be wire ANDed.
19. What are the characteristics of ECL gates?
A. The important characteristics of ECL gates are: (a) Transistors
never saturate so speed is high with tpd = 1ns, (b) Logic levels are
negative, –0.9 V for logic 1 and –0.17 V for logic 0, (c) Noise margin
is less, about 250 mV. This makes ECL unreliable for use in heavy
industrial environments, (d) ECL circuits produce the output and its
complement and therefore eliminate the need for invertors, (e) Fan-out
is large because the output impedance is low. It is about 25, (f) Power
dissipation per gate is large, PD = 40 mW, (g) The total current flow in
ECL is more or less constant. No noise spikes will be internally
generated.
20. Which is the nonsaturated logic?
A. ECL is the nonsaturated logic.
21. Which logic gives complementary outputs?
A. Emitter Coupled Logic (ECL) gives complementary outputs.
22. Which logic is preferred in super fast computers?
A. ECL is preferred in super fast computers.
23. What are the drawbacks of ECL?
A. The drawbacks of ECL are: (a) high cost, (b) low noise margin, (c)
high power dissipation, (d) its negative supply voltage and logic levels
are not compatible with other logic families, and (e) problem of
cooling.
24. What are the merits of ECL?
A. The merits of ECL are: (a) The speed of operation is very high, and
(b) The current drawn from the supply is more steady and they do not
experience large switching transients.
25. Which logic gates are suitable for wired OR operation?
A. ECL open emitter gates are suitable for wired OR operation.
26. Why does the MOS family mostly use NMOS devices?
A. The MOS family mostly uses NMOS devices because they operate
 at about three times the speed of their PMOS counter parts, and also
have twice the packing density of PMOS.
27. Why are MOS ICs especially sensitive to static charge?
A. MOS ICs are sensitive to static charge because of the very high
impedance at the MOSFET’s input.
28. What are the advantages of MOS families over bipolar families?
A. Compared to the bipolar families, the MOS families are simpler and
inexpensive to fabricate, require much less power, have a better noise
margin, a greater supply voltage range, a higher fan-out and require
much less chip area.
29. What are the disadvantages of MOS families compared to bipolar
families?
A. The MOS families are slower in operating speed and are susceptible
to static charge damage.
30. What are the parameters of MOS?
A. For MOS logic: tpd = 50 ns, NM = 1.5 V (for +5 V supply), PD =
0.1 mw, and fan-out = 50 for frequencies greater than 100 Hz and
virtually unlimited for dc or low frequencies.
31. What are the two types of MOSFETs and which type is used in MOS
ICs?
A. The two types of MOSFETs are: (a) depletion type, and (b)
enhancement type. The MOS digital ICs use enhancement MOSFETs
exclusively.
32. What are the merits and demerits of MOS logic compared to TTL?
A. The MOS logic is the simplest to fabricate and has a high packing
density and low power dissipation per gate, but is more susceptible to
static charge damage and it is slow compared to TTL.
33. Where are MOS ICs used?
A. MOS ICs are ideally suited for LSI, VLSI, and ULSI for dedicated
applications such as large memories, calculator chips, large
microprocessors, etc. The operating speed of MOS is slower than that
of TTL, so they are hardly used in SSI and MSI applications.
34. What are the merits and demerits of CMOS?
A. The demerits and merits of CMOS are as follows: The CMOS
family has the greatest complexity and lowest packing density, but it
 possesses the important advantages of higher speed and much lower
dissipation. It can be operated at higher voltages resulting in improved
noise immunity.
35. Where is CMOS technology used?
A. The CMOS technology is used to construct small, medium and
large scale ICs for a wide variety of applications ranging from general
purpose logic to microprocessors.
36. Which ICs are used in watches and calculators?
A. CMOS ICs are used in watches and calculators.
37. Why is the fan-out of CMOS very high?
A. The CMOS has very high input resistance. Thus it draws almost
zero current from the driving gate, and therefore its fan-out is very
high.
38. How do you compare CMOS with TTL?
A. The CMOS fabrication processes is simpler than that of TTL and it
has greater packing density. The CMOS uses only a fraction of the
power needed even for low power TTL. The CMOS is however
generally slower than TTL.
39. For which applications is CMOS ideally suited?
A. The CMOS is ideally suited for applications requiring battery
power or battery backup power.
40. Which CMOS series is compatible pin for pin with TTL?
A. CMOS 74C series is compatible pin for pin and function for
function with TTL devices having the same number.
41. Which is the fastest logic family? The slowest family?
A. ECL is the fastest logic family and MOS is the slowest logic family.
42. Which family has the highest packing density? The lowest packing
density?
A. IIL has the highest packing density and ECL has the lowest packing
density.
43. Which logic family consumes the maximum power? The least power?
A. ECL family consumes the maximum power and CMOS family
consumes the least power.
44. Which logic family is the simplest to fabricate? Most complex to
fabricate?
 A. MOS logic family is the simplest to fabricate and TTL family is the
most complex to fabricate.
45. Which logic family has the highest fan-out? The least fan-out?
A. CMOS family has the highest fan-out and IIL family has the least
fan-out.
46. Which logic family has the highest noise margin? The least noise
margin?
A. CMOS family has the highest noise margin and ECL family has the
least noise margin.
47. What is a transmission gate?
A. A transmission gate is simply a digitally controlled CMOS switch.
It is a bilateral device.
48. When is dynamic MOS logic selected?
A. When physical size and power consumption are the prime design
considerations as in digital watches and calculators, dynamic MOS
logic is selected.
49. What are level shifters?
A. Level shifters are specially designed ICs which are used to make
devices from different logic families compatible with each other.
50. What do you mean by interfacing? Why is it required?
A. Interfacing means connecting the output(s) of one circuit or system
to the input(s) of another system with different electrical
characteristics.
51. There are a number of logic families, each having its own strong
points. In designing more complex digital systems, the designers
utilize different logic families for different parts of the system in order
to take advantage of the strong points of each family. When the
designed parts are assembled, since the electrical characteristics of
different logic families vary widely, interfacing circuits or logic level
translators are used to connect the driver circuit belonging to one
family to the load circuit belonging to another family.
52. Which logic family is suitable for SSI and MSI? For LSI, and VLSI?
And for VLSI, and ULSI?
A. TTL is the most suitable for SSI and MSI. CMOS can also be used
for SSI and MSI. MOS is more suitable for LSI, and VLSI. IIL and
MOS are suitable for VLSI and ULSI.
 REVIEW QUESTIONS
1. With the help of neat diagrams explain the working of (a) a two-input
TTL NAND gate, (b) a two-input ECL OR/NOR gate, (c) IIL NAND,
and NOR gates.
2. With the help of neat circuit diagram explain the working of (a) a MOS
inverter, (b) a two-input MOS NAND gate, and (c) a two-input MOS
NOR gate.
3. With the help of a neat circuit diagram, explain the working of (a) a
CMOS inverter, (b) a two-input CMOS NAND gate, and (c) a two-
input CMOS NOR gate.
4. With the help of a neat circuit diagram explain the working of a
transmission gate.
5. Write short notes on dynamic logic.
6. With the help of circuit diagrams explain the working of (a) dynamic
MOS inverter, (b) dynamic NAND gate, and (c) dynamic NOR gate.

FILL IN THE BLANKS

1. The IC technologies which use bipolar transistors are _________,
________, and ________.
2. The IC technologies which use unipolar transistors are _______, and
__________.
3. The _________ voltage is defined as that voltage at the input of a gate
which causes a change in the state of the output from one logic level to
the other.
4. The __________ of a gate is defined as the time taken by the pulse to
propagate from input to output.
5. The _________ of a gate is defined as the power required by the gate
to operate with 50% duty cycle at a specified frequency.
6. The ________ of a logic gate is defined as the number of inputs that
the gate is designed to handle.
7. The _______ of a logic gate is defined as the maximum number of
similar gates that the output of the gate can drive without impairing its
 normal operation.
8. The ____________ is defined as the maximum noise signal that can be
added to the input signal of a digital circuit without causing an
undesirable change in the circuit output.
9. The _____________ of a logic gate is defined as the product of the
gate propagation delay and the gate power dissipation.
10. A ____________ is defined as the amount of current needed by an
input of another gate of the same logic family.
11. _________ is the most popular and most widely used digital IC family.
12. __________ is the fastest of the saturated logic families.
13. _________, ___________, and _________ are the three types of TTL
gates.
14. The three possible output states of a tri-state TTL are __________,
_________, and __________.
15. ____________ series is the most suitable for high frequencies.
16. ____________ is the fastest logic family.
17. ____________ family has got both the logic levels negative.
18. ____________ is a non saturated logic.
19. MOS family mostly uses ___________ devices.
20. The two types of MOSFETs are ___________ and ___________.
21. The MOS digital ICs use ____________ MOSFETs exclusively.
22. MOS ICs are ideally suited for _________, ___________, and
__________.
23. The __________ technology is used to construct small, medium and
large scale ICs for a wide variety of applications.
24. __________ ICs are used in watches and calculators.
25. __________ is ideally suited for applications involving battery power
and battery backup power.
26. __________ family consumes maximum power and ________ family
consumes the least power.
27. __________ family has the highest fan-out and ________ family has
the least fan-out.
28. __________ family has the highest noise margin and __________
family has the least.
29. __________ gates are suitable for wired AND operation.
30. __________ gates are suitable for wired OR operation.
31. The advantages of totem pole configuration are ________, and
__________.
32. _________ is most suitable for SSI and MSI. _________ can also be
used for SSI and MSI.
33. _________ is more suitable for LSI and VLSI.
34. _________ and ___________ are suitable for VLSI and ULSI.
35. A ___________ gate is simply a digitally controlled CMOS switch.

OBJECTIVE TYPE QUESTIONS

1. The most popular and most widely used IC family is
(a) TTL
(b) IIL
(c) MOS
(d) CMOS
2. A TTL circuit acts as a current sink in the
(a) low state
(b) high state
(c) high impedance state
(d) none of these
3. A TTL circuit acts as a current source in the
(a) low state
(b) high state
(c) high impedance state
(d) none of these
4. The TTL series most suitable at high frequencies is
(a) standard TTL
(b) schottky TTL
(c) FTTL
(d) low power TTL
5. The fastest saturated logic family is
(a) TTL
(b) ECL
(c) IIL
(d) MOS
 6. The fastest logic family is
(a) TTL
(b) ECL
(c) IIL
(d) MOS
7. _________ gives complementary outputs
(a) TTL
(b) ECL
(c) CMOS
(d) MOS
8. ___________ is preferred in super fast computers.
(a) TTL
(b) ECL
(c) IIL
(d) MOS
9. _________ ICs are used in watches and calculators.
(a) TTL
(b) ECL
(c) MOS
(d) CMOS
10. The slowest logic family is
(a) TTL
(b) IIL
(c) MOS
(d) CMOS
11. The logic family which consumes maximum power is
(a) ECL
(b) TTL
(c) CMOS
(d) MOS
12. The logic family which has highest fan-out is
(a) TTL
(b) IIL
(c) MOS
(d) CMOS
13. The logic family which has highest noise margin is
(a) TTL
(b) IIL
(c) MOS
(d) CMOS
14. The logic family most suitable for SSI and MSI is
(a) TTL
(b) IIL
(c) MOS
(d) CMOS
15. The number of inputs the gate is designed to handle is called
(a) fan-out
(b) fan-in
(c) noise margin
(d) none of these
16. The logic family with both logic levels negative is
(a) TTL
(b) ECL
(c) CMOS
(d) MOS
17. The logic family which consumes least power is
(a) TTL
(b) ECL
(c) MOS
(d) CMOS
18. The number of subfamilies TTL has is
(a) 4
(b) 8
(c) 6
(d) 10
19. The logic family with highest packing density is
(a) TTL
(b) IIL
(c) CMOS
(d) MOS
20. The logic family which is simplest to fabricate is
(a) TTL
(b) ECL
(c) MOS
(d) CMOS
 Chapter 10
Blocking Oscillators

A blocking oscillator is a regenerative feedback circuit used to generate

pulses of high peak power. There are two types of blocking oscillators. The
monostable blocking oscillator which can be used to generate a single pulse
and the astable blocking oscillator which can be used to generate a pulse
train.
In this chapter we will discuss blocking oscillators using transistors in
which the output of the active device is coupled back to the input through a
pulse transformer. The relative winding polarities of the pulse transformer
are chosen such that the feedback is regenerative. The monostable or
triggered blocking oscillator using transistors may be base-timed or emitter-
timed. It may be triggered by either slowly varying input voltages or sharp
pulses. The astable blocking oscillator may be diode-controlled or RC-
controlled.

10.1 MONOSTABLE BLOCKING

OSCILLATOR (BASE TIMING)
Figure 10.1(a) shows the circuit diagram of a monostable blocking
oscillator (base timing) using an n-p-n transistor. This may be triggered by a
slowly varying input voltage waveform. The resistor R in the base circuit
controls the pulse width and hence the name monostable blocking oscillator
with base timing. It uses a two-winding pulse transformer. Depending on
the parameters of the pulse transformer and the circuit, the pulse width may
lie in the range from nanoseconds to microseconds. One winding of the
pulse transformer is connected in the collector circuit and the second
winding with n times as many turns as that of the first winding is connected
in the base circuit. The relative winding polarities are such that polarity
inversion is provided as indicated by the dots on the windings.
In the quiescent state, the transistor is OFF. Since the cut-in base-to-
emitter voltage of a transistor is approximately 0.1 V for germanium and
0.5 V for silicon, VBB shown in
Figure 10.1(b) may be reduced to zero. But to avoid free-running operation
at elevated temperatures and also to avoid false triggering due to noise
spikes, VBB is selected to be of the order of a few tenths of a volt. Since
VBB << VCC and does not basically affect the operation of the circuit, VBB
may be neglected for analysis. When a triggering signal is momentarily
applied to the collector to lower its potential, by transformer action and with
the winding polarities shown in Figure 10.1(a), the base potential rises.
When the base-to-emitter voltage exceeds the cut-in voltage of the
transistor, the transistor conducts. This increase in collector current reduces
the collector voltage further, which, in turn, increases the base potential
further. So the transistor conducts more and hence the collector voltage
decreases further, and so on. Due to regenerative feedback the transistor
goes into saturation quickly if the ac loop gain exceeds unity.
The equivalent circuit of the blocking oscillator when the transistor goes
into saturation is shown in Figure 10.1(b). Here the pulse transformer is
replaced by an ideal transformer in shunt with the magnetizing inductance L
of the collector winding. The junction voltages VCE(sat) and VBE(sat) are
very small compared to VCC and hence these are neglected. The pulse
amplitude, the pulse width and the wave shape can be obtained from the
equivalent circuit of Figure 10.1(b). For an ideal transformer the sum of the
ampere-turns is a constant and the induced voltages are proportional to the
number of turns in the windings. In the quiescent state all the currents are
zero, hence the algebraic sum of the ampere-turns within the dashed box of
Figure 10.1(b) must be zero.

Figure 10.1 (a) Circuit diagram of a monostable blocking oscillator with base timing and (b) the
equivalent circuit during pulse formation.

Let i be the current in the ideal transformer collector winding. Taking

winding polarities into account,

i – niB = 0.......or.......i = niB

If V is the amplitude of the step across the collector winding, then, nV is the
corresponding voltage across the base winding. The polarities assigned to
the winding voltages V and nV are opposite to each other to be consistent
with the polarity inversion indicated by the dots.
Since the junction voltages are neglected, from the collector circuit of
Figure 10.1(b), V = VCC.

The above equations for iB and iC indicate that the base current is constant
whereas the collector current is trapezoidal as shown in Figures 10.2(a) and
(b), respectively.
 Figure 10.2 (a) The collector current and (b) the base current in the circuit of Figure 10.1(a).

+
The collector characteristics are shown in Figure 10.3. At t = 0 , the
operating point is at point P where

The transistor is in saturation provided that hFEiB > iC. For t > 0, as t
increases the collector current increases but the base current remains
constant and hence the operating point moves up the curve in Figure 10.3
corresponding to the constant base current,

At t = tp, the operating point is at P, vCE increases rapidly and this
decreases the base voltage and hence the base current, and therefore the
transistor comes out of saturation. Since the loop gain exceeds unity in the
active region, due to regenerative action the transistor is driven quickly into
cut-off and the pulse ends.

Figure 10.3 The path of collector current is PP when the transistor is ON.

Since the regeneration which terminates the pulse starts when the
transistor comes out of saturation, the pulse width can be determined by the
condition

This result indicates that the pulse width is a linear function of hFE. Since
hFE varies with temperature and transistor replacement, this circuit cannot
be used where stable pulse widths are required. At t = tp, the pulse ends,
and the current iB falls to zero and remains at the zero level for t > tp.
10.2 MONOSTABLE BLOCKING
OSCILLATOR (EMITTER TIMING)
Figure 10.4(a) shows the circuit diagram of a transistor monostable
blocking oscillator with emitter timing. It consists of an n-p-n transistor
with a resistor R in the emitter lead and a three-winding pulse transformer.
The resistor in the emitter lead controls the pulse width and hence the name
monostable blocking oscillator with emitter timing. One winding of the
pulse transformer is in the collector circuit. The second winding with n
times as many turns as that of the first winding is in the base circuit and the
third winding with n1 times as many turns as that of the first feeds a resistor
RL which may be the actual load or may be that required for damping. The
base and collector turns must be connected in such a way as to provide
regenerative feedback, but the relative winding polarity of the third leg of
the transformer is arbitrary. It may be chosen to obtain either a positive
pulse or a negative pulse across the load.
Figure 10.4 (a) Circuit diagram of a monostable blocking oscillator with emitter timing and (b) its
equivalent circuit when the transistor is in saturation.

In the quiescent state the transistor is OFF. VBB is of the order of a few
tenths of a volt. Even though it can be zero, it is chosen as a fraction of a
volt to avoid free-running operation at elevated temperatures and to avoid
false triggering due to noise spikes. When a triggering signal is
momentarily applied at the collector to lower its potential, by transformer
action and with the winding polarities chosen, the base potential rises.
When the base-to-emitter voltage exceeds the cut-in voltage of the
transistor, the transistor starts to draw current. The increase in collector
current lowers the collector voltage, which in turn raises the base voltage.
Hence the transistor conducts more and the collector current increases
further, the collector voltage reduces further, and so on. If the ac loop gain
exceeds unity, regeneration takes place and the transistor is quickly driven
into saturation.
The pulse amplitude, the pulse width and the wave shape can be
determined from the equivalent circuit shown in Figure 10.4(b) where the
three-winding pulse transformer is replaced by an ideal three-winding
transformer in shunt with a magnetizing inductance L of the collector
winding. The transistor saturation voltages VCE(sat) and VBE(sat) are very
small compared to VCC and hence are neglected for analysis.
For an ideal transformer, the sum of the ampere-turns is a constant and
the induced voltages are proportional to the number of turns. Since in the
quiescent state all the currents are zero, the algebraic sum of the ampere-
turns within the dashed box must be zero.
If i is the current in the transformer collector winding, iB is the current in
the base winding and i1 the current in the load winding, then

Applying KVL to the outside loop encompassing both the collector and
the base meshes,
The waveforms for iC, iB, iE, vCN, vBN and vL are shown in Figures
10.5(a), (b), (c), (d), (e), and (f) respectively. The collector current
waveform is trapezoidal with a positive slope and the base current
waveform is trapezoidal with a negative slope and the emitter current is
constant during the pulse.
 Figure 10.5 The current and voltage waveforms in a transistor monostable blocking oscillator.

+
At t = 0 , the operating point is at point P on the collector characteristic
shown in Figure 10.3, iC < hFEiB and the transistor is in saturation. As time
passes, iC increases and iB decreases and the operating point moves up the
saturation line. Eventually at t = tp, point P is reached where iB = IB and
iC = hFEiB. At this time vCE increases rapidly, the base voltage reduces,
the transistor enters its active region and due to regenerative action the
transistor is driven into cut-off and the pulse ends. The expression for the
pulse width tp can be obtained by solving the equation,
 This indicates that subject to the reasonable approximations made above,
tp is independent of hFE and depends only on the passive elements n, L, R,
n1, and RL. Hence this circuit yields a pulse of very stable duration.
Since tp cannot be negative, the necessary condition for regeneration to
take place and a pulse to form is

10.3 ASTABLE BLOCKING OSCILLATOR

(DIODE CONTROLLED)
An astable blocking oscillator requires no triggering and the moment it is
switched on to the supply it keeps generating a sequence of pulses.
Figure 10.6(a) shows the circuit diagram of a diode-controlled transistor
astable blocking oscillator. It consists of an n-p-n transistor, a resistor R in
the emitter lead, a two-winding pulse transformer, a diode network, and a
dividing network. The symbol D is used to represent a diode network which
may consist of one or more p-n junction diodes in series or a p-n diode in
series with a zener diode or a p-n diode in series with a battery. The diode D
is responsible for the free-running operation and controls the duty cycle.
Hence the name diode-controlled. The piece-wise linear approximation for
the diode combination is indicated in Figure 10.6(b) where Vg is the offset
voltage of the p-n diode or the zener voltage or the battery voltage. Rf is the
diode forward resistance. One winding of the pulse transformer is in the
collector circuit and the second winding with n times as many turns as that
of the first is in the base circuit.

Figure 10.6 (a) Diode-controlled transistor astable blocking oscillator and (b) the piece-wise linear
model for the diode.

The divider supplies a small bias VBB ( 1 V) which is in the direction

to forward bias the emitter junction. So a current starts to flow in the base,
collector and emitter circuits of the transistor. The collector current reduces
the collector potential. This reduction in collector potential results in an
increase in base potential and so on, and due to regenerative feedback the
transistor goes into saturation (Figure 10.7) and the waveforms shown in
Figure 10.8 are generated in the interval 0  t  tp.

Figure 10.7 Equivalent circuit of the circuit diagram in Figure 10.6(a) when the transistor is in
saturation.

For t > 0, when the transistor goes into saturation, the equivalent circuit
shown in Figure 10.7 results. The diode is OFF. The junction voltages and
VBB are very small compared to the supply voltage VCC and hence are
neglected for analysis.
Applying KVL to the outside loop encompassing both the collector and
base meshes,

–VCC + V + nV = 0

or the drop across the collector winding during the pulse is

Since the emitter current is constant, to find the base and collector currents
independently, one more relationship between iC and iB is required.
Since the sum of the ampere-turns in the ideal transformer is zero,

These equations show that the collector current waveform is a trapezoid

with a positive slope and the base current waveform is a trapezoid with a
negative slope and the emitter current is a constant as shown in Figure 10.8.
 Figure 10.8 The collector, the base and the emitter current waveforms in the interval 0  t  tp.

+
At t = 0 , the operating point is at point P on the collector characteristics
shown in Figure 10.3, iC < hFEiB and the transistor is in saturation. As time
passes, iC increases and iB decreases and at t = tp, the operating point is at
P on the collector characteristics, VBB increases rapidly and due to
regenerative feedback the transistor is driven into cut-off.
At the end of the pulse, the magnetizing current im is given by

This indicates that the peak magnetizing current is independent of the

inductance. At t = tp the transistor is cut-off and the inductor current must
flow through the diode and through the transformer capacitance as shown in
Figure 10.9(a). Neglecting the small diode forward resistance Rf, Vg
appears directly across L and the shunt capacitance C. Hence the collector
voltage rises above VCC by Vg as indicated in Figure 10.9(a).

Figure 10.9 (a) The collector circuit for t > tp when D is ON and (b) the collector circuit for t > tp +
tf when D is OFF.
 Since for t > tp, L(dim/dt) = Vg, shifting the time origin to the end of the
pulse,

This indicates that the current decreases linearly with time after the pulse
ends as indicated in Figure 10.10(c).
The diode current falls to zero at a time tf given by

After im is reduced to zero, the diode becomes an open-circuit and the

underdamped ringing circuit of Figure 10.9(b) results. Since the shunt
capacitor C is initially charged to Vg, a sinusoidal oscillation of amplitude
Vg and period begins as indicated in Figure 10.10(a).
 Figure 10.10 (a) Collector voltage, (b) base voltage, and (c) magnetizing current waveforms.

After one quarter of a cycle, in a time

the collector voltage falls below VCC.

The negative swing at the collector is reflected in a positive swing at the
base. When vBE exceeds the cut-in voltage of the transistor, the transistor
conducts and due to regenerative action it goes into saturation and the cycle
of events repeats. Hence without the aid of an external trigger, a new cycle
starts. Since the diode has caused the circuit to function in an astable mode
with period T = tp + tf + ta, this circuit is called a diode-controlled one. The
collector and base voltages are nearly rectangular without any overshoots as
shown in Figures 10.10(a) and (b) respectively. The transistor current
waveforms are those shown in Figure 10.8 for tp < t < tp + tf + ta.

EXAMPLE 10.1 The circuit of Figure 10.6(a) has the following

parameters: L = 2 mH, C = 100 pF, VCC = 12 V, R = 750 , Vg = 6 V, n =
1, VBB = 0.5 V. Calculate (a) the period and the duty cycle of the free
oscillations, (b) the peak voltages and currents, and (c) the current in the
magnetizing inductance at the end of one cycle.

The collector voltage extends from VCC – V = 12 – 6 = 6 V to VCC + Vg =

12 + 6 = 18 V. The base voltage extends from nV to – nVg, i.e. from 6 V to
–6 V. The emitter current is constant and is given by
The peak magnetizing current is

(c) The current in the magnetizing inductance at the end of the cycle can
be calculated as follows.
At time t = tp + tf, the capacitor is charged to a voltage Vg and the
magnetizing current is zero. The LC circuit then rings and in one quarter of
a cycle (in time ta) the capacitive energy is transformed to magnetic energy,
i.e.

The current im goes below zero (reverses) by the amount Im.

EXAMPLE 10.2 The astable blocking oscillator of Figure 10.6(a) has the
following parameters: VCC = 10 V, VBB = 0.5 V, n = 2, R = 1.5 k, Rf = 10
, Vg = 9 V, L = 3 mH and C = 100 pF. Calculate the frequency of
oscillation and the duty cycle.

EXAMPLE 10.3 Design a free-running blocking oscillator of the astable

type subject to the following specifications: VCC = 30 V, VBB = 1 V, the
frequency is 20 kHz, the duty cycle is 1/10, the peak of the pulse at the
collector is 10 V, and the peak emitter current is 5 mA. Find the values for
n, Vg, R, and L. Make reasonable assumptions.
10.4 ASTABLE BLOCKING OSCILLATOR (RC
CONTROLLED)
An RC-controlled astable transistor blocking oscillator may be obtained by
adding an R1C1 network either in the emitter lead as shown in Figure
10.11(a) or in the base lead as shown in Figure 10.11(b) to the emitter-timed
monostable blocking oscillator of Figure 10.4(a). The circuits of Figures
10.11(a) and 10.11(b) differ from that of Figure 10.4(a) not only in the
addition of the R1C1 network but also in the reversal of the polarity of
VBB. The operation of the circuit of Figure 10.11(a) is as follows.

Figure 10.11 (a) and (b) RC-controlled astable transistor blocking oscillators.

Assume initially that there is a voltage v1 on C1 which is greater than

VBB – Vg, where Vg is the cut-in voltage of the transistor. Hence the base-
emitter junction is reverse biased and the transistor is cut-off. The capacitor
C1 discharges exponentially towards ground with a time constant R1C1.
When the voltage falls to VBB – Vg, the base-emitter junction of the
transistor will be forward biased, the base and collector currents flow and
due to the regenerative feedback the transistor goes into saturation. The
equivalent circuit when the transistor is ON is shown in Figure 10.12. The
values of tp and V1 may be found from this equivalent circuit. The collector
waveform and the waveform across the capacitor are shown in Figures
10.13(a) and 10.13(b) respectively. When the transistor is ON, the capacitor
C1 charges towards VCC. When it recharges to a voltage V1 which is larger
than that which it had at the beginning of the pulse, the transistor goes to the
OFF state. It remains OFF for a time tf during which C1 discharges to the
voltage at which the transistor enters the active region. At this point the
cycle repeats itself.

Figure 10.12 Equivalent circuit of Figure 10.11(a) when the transistor is ON.
 Figure 10.13 (a) The waveform across the R1C1 combination of
Figure 10.11(a) and (b) the collector waveform.

From Figure 10.13(a) assuming that the discharge of the capacitor is

exponential with a time constant R1C1, the fall time tf can be obtained as
follows:

The period of the frequency of oscillation is, T = tp + tf.

A comparison of the diode-controlled and RC-controlled astable blocking
oscillators is as follows:
• The diode-controlled circuits have advantages of better voltage
waveforms, simpler design equations and less possibility of oscillations
preceding the pulse.
 • The RC-controlled circuits have advantages of low duty cycle
operation, simple and continuous variation of oscillations and stability
with respect to temperature changes.

10.5 APPLICATIONS OF BLOCKING

OSCILLATORS
The applications of blocking oscillators are listed below:

1. Both monostable and astable blocking oscillators are used for

generating pulses of large peak power.
2. The monostable blocking oscillator is used to obtain abrupt pulses
from slowly varying input voltages.
3. The astable blocking oscillator is used as a master oscillator to supply
triggers for synchronizing a system of pulse type waveforms.
4. Blocking oscillator is used as a frequency divider or counter.
5. Blocking oscillator as a low impedance switch is used to discharge a
capacitor rapidly.
6. The output of the blocking oscillator may be used as a gating
waveform with very small mark space ratio.
7. Both positive and negative pulses can be obtained from a blocking
oscillator by using a tertiary winding.

SHORT QUESTIONS AND ANSWERS

1. What do you mean by a blocking oscillator?
A. A blocking oscillator is a regenerative feedback circuit used to
generate pulses of high peak power.
2. How is the transistor blocking oscillator constructed?
A. In blocking oscillators using transistors, the output of the active
device is coupled back to the input through a pulse transformer. The
relative winding polarities of the pulse transformer are chosen such
that the feedback is regenerative.
 3. How many types of blocking oscillators are there? Name them.
A. There are two types of blocking oscillators. They are (a)
monostable or triggered blocking oscillator and (b) astable blocking
oscillator.
4. What do the monostable and astable blocking oscillators generate?
A. The monostable blocking oscillator can be used to generate a single
pulse and the astable blocking oscillator can be used to generate a
sequence of pulses. Both generate pulses of high peak power.
5. How can a monostable blocking oscillator be triggered?
A. The monostable blocking oscillator can be triggered by either
slowly varying input voltages or sharp pulses.
6. What is the range of widths of output pulses of blocking oscillators?
A. The width of the output pulses of blocking oscillators ranges from
nanoseconds to microseconds.
7. Which blocking oscillator is used to obtain abrupt pulses from slowly
varying input voltages?
A. A monostable blocking oscillator is used to obtain abrupt pulses
from slowly varying input voltages.
8. What are the types of monostable transistor blocking oscillators?
A. The monostable blocking oscillator using transistors may be base
timing type or emitter timing type.
9. How do you compare the monostable transistor blocking oscillators of
base-timing and emitter-timing types?
A. The monostable blocking oscillators of base timing and emitter
timing types are compared as follows. (a) The monostable blocking
oscillator of base timing type requires a 2-winding pulse transformer
whereas the emitter timing type requires a 3-winding pulse
transformer. (b) In base-timing type, the pulse width tp is a linear
function of hFE. Since hFE varies with temperature and transistor
replacement, this circuit cannot be used where stable pulse widths are
required, whereas the emitter timing type yields a pulse of very stable
operation. tp is independent of hFE and depends on the circuit passive
elements.
10. What are the types of astable transistor blocking oscillators?
A. The astable blocking oscillator may be diode-controlled type or RC-
 controlled type.
11. Which blocking oscillator requires no triggering?
A. The astable blocking oscillator requires no triggering.
12. Which type of monostable blocking oscillator is impractical if stable
pulse widths are required and why?
A. The monostable transistor blocking oscillator of base-timing type is
impractical if predictable pulse widths are desired as its pulse width is
a function of hFE and hFE varies with temperature and transistor
replacement.
13. Which type of monostable blocking oscillator yields a pulse of stable
duration and why?
A. The monostable blocking oscillator of emitter-timing type yields a
pulse of very stable duration because tp is independent of hFE and
depends only on the circuit passive elements.
14. What are the relative advantages of diode-controlled and RC-
controlled astable blocking oscillators?
A. The diode-controlled astable blocking oscillators have advantages
of better voltage wave forms, simpler design equations and less
possibility of oscillations preceding the pulse.
The RC-controlled astable blocking oscillators have advantages of low
duty cycle operation, simple and continuous variation of oscillations
and stability with respect to temperature changes.
15. Write the expressions for tp, tf and ta of a diode controlled astable
blocking oscillator.

16. Write the expression for tp of a monostable blocking oscillator with (a)
base-timing (b) emitter-timing.

17. What are the applications of blocking oscillators?

A. The applications of blocking oscillators are listed as follows:
(a) Both monostable and astable blocking oscillators are used for
generating pulses of large peak power.
 (b) The monostable blocking oscillator is used to obtain abrupt pulses
from slowly varying input voltages.
(c) The astable blocking oscillator is used as a master oscillator to
supply triggers for synchronizing a system of pulse type waveforms.
(d) A blocking oscillator is used as a frequency divider or counter.
(e) A blocking oscillator as a low impedance switch is used to
discharge a capacitor rapidly.
(f) The output of the blocking oscillator may be used as a gating
waveform with very small mark space ratio.
(g) Both positive and negative pulses can be obtained from a blocking
oscillator by using a tertiary winding.

REVIEW QUESTIONS
1. With the help of a neat circuit diagram and waveforms, explain the
working of a monostable transistor blocking oscillator (base timing).
Derive an expression for the pulse width.
2. With the help of a neat circuit diagram and waveforms, explain the
working of a triggered transistor blocking oscillator (emitter timing).
Derive an expression for the pulse width.
3. With the help of a neat circuit diagram and waveforms, explain the
working of a diode-controlled astable blocking oscillator. Derive an
expression for the period.
4. With the help of a neat circuit diagram and waveforms, explain the
working of an RC-controlled astable blocking oscillator.

FILL IN THE BLANKS

1. A blocking oscillator is a ___________ circuit used to generate pulses
of high peak power.
2. A _________ is basically a transistor circuit in which the output is
coupled to the input regeneratively through a pulse transformer.
3. Blocking oscillators may be of _________ type or _________ type.
 4. Both monostable and astable blocking oscillators are used to generate
pulses of _________.
5. A _______ blocking oscillator is used to generate a single pulse and an
__________ blocking oscillator is used to generate a sequence of
pulses.
6. The width of the output pulses of blocking oscillators ranges from
_________ to _________.
7. Monostable blocking oscillators using transistors may be of
_________ type or _________ type.
8. The monostable blocking oscillator of _________ type is impracticable
if predictable pulse widths are desired because its pulse width is a
function of _________.
9. An astable blocking oscillator is used as a _________ for supplying
triggering pulses.
10. A _________ blocking oscillator is used to obtain abrupt pulses from
slowly varying input waveforms.
11. A blocking oscillator can be used as a _________ to discharge a
capacitor rapidly.
12. Astable blocking oscillators may be of _________ type or _________
type.
13. A _________ blocking oscillator may be triggered by either slowly
varying input voltages or sharp pulses.
14. An _________ blocking oscillator requires no triggering.
15. The output pulses of either polarity can be obtained using a _________
winding on the pulse transformer in a blocking oscillator.
16. The output of a blocking oscillator may be used as a gating waveform
with very small _________.
17. The diode controlled astable blocking oscillators have the advantages
of _________, _________, and ____________.
18. The RC-controlled astable blocking oscillators have the advantages of
__________, __________ and ____________.

OBJECTIVE TYPE QUESTIONS

 1. A blocking oscillator uses
(a) degenerative feedback
(b) regenerative feedback
(c) negative feedback
(d) no feedback
2. Blocking oscillators generate pulses of
(a) low peak power
(b) medium peak power
(c) high peak power
(d) no peak power
3. _________ blocking oscillators require triggering.
(a) bistable
(b) monostable
(c) astable
(d) none of these
4. _________ blocking oscillators require no triggering.
(a) bistable
(b) monostable
(c) astable
(d) none of these
5. A ___________ blocking oscillator is used to obtain abrupt pulses
from slowly varying input voltages.
(a) bistable
(b) monostable
(c) astable
(d) none of these
6. For a monostable blocking oscillator with emitter-timing, the necessary
condition for regeneration to take place and a pulse to form is

PROBLEMS
10.1 The astable blocking oscillator of Figure 10.6(a) has the following
parameters: L = 1.5 mH, C = 120 pF, VCC = 10 V, R = 500 , Vg = 5
V, n = 1, VBB = 0.75 V. Calculate (a) the period and the duty cycle of
the free oscillations, (b) the peak voltages and currents, and (c) the
current in the magnetizing inductance at the end of one cycle.
10.2 Design an astable blocking oscillator subject to the following
specifications: VCC = 25 V, VBB = 0.8 V, the frequency is 20 kHz, the
duty cycle is 1/10, the peak of the pulse at the collector is 12 V and the
peak emitter current is 5 mA. Find the values of n, Vg, R, C, and L.
Make reasonable assumptions.
 Glossary

AND gate. A digital logic circuit used to implement the AND operation.
The output of this circuit is a 1 only when each one of its inputs is a 1.
Anti coincidence gate. An X-OR gate which outputs a HIGH only when its
two inputs differ.
Astable blocking-oscillator. A regenerative feedback circuit used to
generate a train of pulses of high peak power.
Astable multivibrator. A multivibrator with no stable state, both the states
being quasi-stable.
Attenuator. A resistive network used to reduce the amplitude of the input
signal.
Bandwidth. The range of frequencies over which the gain is more than
70.7% of its maximum value. BW = f2 – f1.
Biased clamping. Clamping positively or negatively with respect to a
reference voltage VR.
Bidirectional sampling gate. A sampling gate which transmits signals of
both the polarities.
Bilateral switch. A CMOS circuit which acts like a single pole, single
throw switch controlled by an input logic level.
Bistable multivibrator. A multivibrator with two stable states.
Blocking capacitor. The capacitor in the series arm of a high-pass circuit
which blocks all dc signals.
Blocking oscillator. A regenerative feedback circuit used to generate pulses
of high peak power.
Breakover voltage. It is the voltage at which the device fires and heavy
current flows.
Bubbled AND gate. The AND gate with inverted inputs. It performs the
NOR operation.
Bubbled OR gate. The OR gate with inverted inputs. It performs the
NAND operation.
Capacitive coupling circuit. The RC high-pass circuit with a capacitor in
the series arm.
Characteristic equation. The denominator of a transfer function equated to
zero.
Clamping. The process of fixing the extremity of a periodic waveform to
some constant reference level.
Clamping circuit theorem. A theorem applicable to clamping circuits
which states that for any input waveform under steady-state conditions, the
ratio of the area under the output voltage curve in the forward direction to
that in the reverse direction is equal to the ratio Rf/R.
Clamping circuits. The circuits which are used to clamp or fix the
extremity of a periodic waveform to some constant reference level VR.
Clipping. Cutting and removing a part of the waveform.
Clipping circuits. Also called voltage (or current) limiters, amplitude
selectors or slicers. These are circuits which are used to select for
transmission that part of an arbitrary waveform which lies above or below a
particular reference level.
CMOS. Complimentary metal oxide semiconductor. The IC technology
which uses both NMOS and PMOS FETs as the principal circuit elements.
Coincidence gate. The X-NOR gate which outputs a HIGH only when its
two inputs are the same.
Collector catching diodes. The diodes used in a bistable multivibrator to
obtain constant output swing.
Commutating capacitors. Also called speed-up capacitors or transpose
capacitors. These are small capacitors connected in parallel with the
coupling resistors to increase the speed of operation of the circuit.
Comparator. A circuit used to mark the instant at which an arbitrary
waveform attains some particular reference level.
Compensated attenuator. An attenuator in which R1 is shunted by a
capacitor C1.
Current time-base generator. A circuit that provides an output current
waveform, a portion of which exhibits a linear variation with respect to
time.
Cut-off frequency. The frequency at which the gain is of its
maximum value.
DC restorer. Another name for a clamping circuit. Also called dc re-
inserter.
Diode clipper. A circuit consisting of diodes, which is used to remove a
part of the waveform.
Direct-connected binary. A binary with no coupling elements. The output
of each device is shorted to the input of the other.
Displacement error, ed. The ratio of the maximum difference between the
actual sweep voltage and the linear sweep which passes through the
beginning and the end points of the actual sweep to the amplitude of the
sweep at the end of the sweep time.
Double differentiator. Two RC coupling networks with very low time
constants connected in cascade.
Double-base diode. The original name of UJT.
Double-ended clipping. It is clipping off of both the top and bottom
portions of the waveform.
Eccles-Jordan circuit. Another name for bistable multivibrator; also called
binary, flip-flop, scale-of-two toggle circuit, trigger circuit.
ECL. Emitter coupled logic. Also referred to as current mode logic CML.
Emitter-coupled binary. Also called Schmitt trigger. It is an emitter-
coupled bistable multivibrator.
Emitter-coupled clipper. An emitter coupled differential amplifier used as
a two-level clipper.
Equilibrium point. The point of intersection of the load line with the
device characteristic.
Exclusive-NOR gate. A logic circuit which produces a 1 output only when
the inputs coincide.
Exclusive-OR gate. A logic circuit which produces a 1 output only when
the inputs are different.
Fan-out. The maximum number of equivalent gate inputs that the output of
a gate can drive without impairing its normal function.
Fixed-bias bistable multivibrator. A bistable multivibrator which uses a
separate source for supplying a bias voltage.
Free-running circuit. A circuit which keeps generating waveforms the
moment it is connected to the supply.
Gain of a gate. The ratio of the output voltage to the input voltage of a gate
during the transmission interval.
Gate. A circuit that performs a specified logic operation.
Gate signal. Also called a control pulse, a selector pulse or an enabling
pulse. It is an externally impressed signal used to select the time interval for
transmission.
Gated astable multivibrator. An astable multivibrator with an additional
transistor which can start or stop oscillations at definite times.
High-pass circuit. A circuit which blocks all dc and low frequency signals
and transmits all high frequency signals with little or no attenuation.
IC. Integrated circuit: A type of circuit in which all the components are
integrated on a single silicon chip of very small size.
Ideal attenuator. An attenuator whose attenuation is independent of
frequency.
Inhibit circuits. Logic circuits that control the passage of an input signal
through to the output.
Interfacing. Joining of dissimilar devices in such a way that they are able
to function in a compatible and coordinated manner; connection of the
output of a system to the input of a different system with different electrical
characteristics.
Intrinsic stand-off ratio. It is the ratio of RB1/(RB1 + RB2) in the case of
a UJT.
Inverter. A logic circuit that implements the NOT operation.
Linear network. A network which can be described by linear constant
coefficient differential equations or a network for which the principle of
superposition and the principle of homogeneity hold good.
Linear wave shaping. The process whereby the form of a non-sinusoidal
signal is altered by transmission through a linear network.
Loading. Connecting a resistance or some other load at the output of a
multivibrator and drawing current.
Logic circuit. A circuit that behaves according to a set of logic rules.
Logic level. State of a voltage variable. States HIGH and LOW correspond
to the two usable voltage levels of a digital device.
Lower cut-off frequency, f1. The frequency in the low-frequency range of
the gain versus frequency plot at which the gain is 70.7% of its maximum
value.
Lower Triggering Point (LTP). The input voltage V2 at which the
transistor Q2 of the Schmitt trigger resumes conduction.
Low-pass circuit. A circuit which transmits all low frequency signals and
attenuates or blocks all high frequency signals.
Monostable blocking oscillator. A regenerative feedback circuit used to
generate a single pulse of high peak power.
Monostable multivibrator. A multivibrator with only one stable state, the
other state being quasi-stable.
MSI. Medium scale integration: A level of integration in which 12–99 gate
circuits are fabricated on a single chip.
Multivibrator. A circuit which can operate at a number of different
frequencies.
NAND gate. The logic gate that outputs a 0 only when all its inputs are 1s.
It gives the compliment of the AND output.
Negative logic. The system of logic in which a LOW represents a 1 and a
HIGH represents a 0.
Negative-resistance device. A device which exhibits a negative resistance
over a portion of its V-I characteristic.
Negative clamping. Clamping in which the positive extremity of a
waveform is fixed at the reference level and the entire waveform appears
below the reference.
NMOS. N-channel metal oxide semiconductor.
Noise immunity. The ability of a circuit to tolerate noise voltages on its
inputs.
Noise margin. Quantitative measure of the noise immunity. It is the
maximum noise voltage that can be added at the input of a gate without
affecting its operation.
Non-regenerative comparators. Comparators like clipping circuits which
do not employ feedback.
Non-saturating binary. The binary in which the transistors always operate
in the active region.
NOR gate. A logic circuit that outputs a 1 only when each one of its inputs
is a 0. It is equivalent to an OR gate followed by an inverter.
NOT circuit. A logic circuit that inverts its only input.
One-level clipping. Same as single-ended clipping.
One-way clamp. A clamping circuit which restrains the voltage change in
only one direction.
Open-collector gates. The TTL gates which use only one transistor with a
floating collector in the output structure.
OR gate. A logic circuit that outputs a HIGH whenever one or more of its
inputs are HIGH.
Overcompensated attenuator. An attenuator for which vo(0+) > vo().
Peak current, IP. The magnitude of the current at the peak point.
Peak forward point. The point on the high voltage region where I = IP.
Peak point. The top-most point on the V-I characteristic of the device.
Peak voltage, VP. The magnitude of the voltage at the peak point.
Peaking. The process of converting pulses into pips or spikes by means of a
circuit of short time constant.
Peaking circuit. A high-pass circuit with a very small time constant or any
circuit which converts pulses into spikes.
Peaking coil. A coil used to convert a square wave into pulses.
Perfectly compensated attenuator. An attenuator for which vo(0+) =
vo().
PMOS. P-channel metal oxide semiconductor.
Positive clamping. Clamping in which the negative extremity of a
waveform is fixed at the reference level and the entire waveform appears
above the reference.
Positive logic system. The system of logic in which a HIGH represents a 1
and a LOW represents a 0.
Propagation delay. The time interval between the occurrence of an input
transition and the corresponding output transition.
Pulse. A signal whose magnitude is zero for t < 0, and for t > tp and
constant in the range 0 < t < tp. It is a positive step followed by a delayed
negative step.
Quasi-stable state. A temporarily stable state. The circuit cannot remain in
this state permanently.
Quiescent conditions. The conditions before the application of the input.
Ramp signal. A signal which is 0 for t < 0, and which increases linearly
with time for t > 0.
Regenerative comparators. Comparators like Schmitt trigger which
employ positive feedback.
Resolution time. The sum of the transition time and the settling time.
Resolving time. The smallest allowable interval between triggers.
Restoration time. Also called the return time or the flyback time. It is the
time taken by the signal to return to its initial value.
Ringing circuit. An RLC circuit which provides as nearly undamped
oscillations as possible.
Rise time. The time taken by the output voltage waveform of a low-pass
circuit excited by a step-input to rise from 10% to 90% of its final value.
Sampling gates. Also called linear gates, transmission gates, or time-
selection circuits. These are transmission circuits in which the output is an
exact reproduction of the input during a selected time interval and is zero
otherwise.
Saw-tooth generator. A relaxation circuit which generates an output
waveform that rises linearly but falls abruptly.
Saw-tooth waveform. A waveform for which the restoration time is zero
and the next linear voltage is initiated the moment the present one is
terminated.
Schottky TTL. A TTL subfamily that uses the basic standard TTL circuit
except that it uses a Schottky barrier diode between the base and collector
of each transistor.
Self-bias bistable multivibrator. A bistable multivibrator which uses an
emitter resistance instead of a separate supply to provide the required bias.
Settling time. The additional time required for the purpose of completing
the recharging of capacitors after the transfer of conduction in a binary.
Single-ended clipping. It is clipping off of either the top or the bottom
portion of the waveform.
Slicer. The other name of a clipper.
Slope or sweep-speed error, es. The ratio of the difference in slopes at the
beginning and end of a sweep to the initial value of slope.
Speed power product. Numerical value (in joules) often used to compare
different logic families. It is obtained by multiplying the propagation delay
(ns) by the power dissipation (mw) of a logic gate.
Square wave. A periodic waveform which maintains itself at one constant
level V with respect to ground for a time T1 and changes abruptly to
another level V≤ and remains constant at that level for a time T2 and repeats
itself at regular intervals of T = T1 + T2.
Squaring circuit. A circuit which converts a sine wave or any other slowly
varying input waveform into a square wave.
SSI. Small scale integration (less than 12 gates per chip)
Stable state. A state in which the device can remain permanently.
Steady-state response. The response or output obtained after the transient
is over (i.e. as t  ).
Step signal. A signal which maintains the value ‘0’ for all times t < 0, and
maintains a value V for all times t > 0.
Sweep circuit. A circuit which generates waveforms used to sweep the
electron beam horizontally across the screen, the other name of time-base
generator.
Sweep time. The time during which the output of a time-base generator
increases linearly.
Symmetrical triggering. A method of triggering in which each successive
triggering signal induces a transition regardless of the state in which the
binary happens to be.
Tilt. The almost linear decrease in output voltage of a high-pass circuit.
Time constant. The time taken by the output to reach the final value if the
initial slope is maintained constant. It is equal to the product of R and C for
an RC circuit and the ratio of L to R for an RL circuit.
Time-base generator. A circuit that provides an output waveform, a
portion of which exhibits a linear variation of voltage or current with
respect to time.
Totem-pole. A term used to describe the way in which two bipolar
transistors are connected one above the other at the outputs of most TTL
gates.
Transfer function. The ratio of the Laplace transform of the output to the
Laplace transform of the input with initial conditions neglected.
Transient response. The output or response obtained immediately after the
application of the input (i.e. immediately after t = 0+).
Transistor clipper. A clipping circuit which clips off a part of a waveform
by using the nonlinearities of the transistor.
Transition time. The interval during which conduction transfers from one
device to another.
Transmission characteristic. A plot showing the variation of output for a
ramp input extending from –  to .
Transmission error, et. The difference between the input and the output
divided by the input at t = T.
Transmission gate. A digitally controlled bi-lateral CMOS switch.
Triggering. The process of applying an external signal to induce transition
from one state to the other.
Tri-state. A type of output structure which allows three types of output
states-HIGH, LOW and high- impedance.
Truth table. A tabular representation of the outputs of a logic circuit for all
possible combinations of inputs.
TTL(Transistor Transistor Logic). An IC technology that uses the bipolar
transistor as the basic circuit element.
Two-level clipping. Same as double-ended clipping.
Two-stage regenerative amplifiers. Amplifiers made up of two cross-
coupled inverters.
Two-way clamp. A clamping circuit which restrains the voltage change in
both the directions.
Undercompensated attenuator. An attenuator for which vo(0+) < vo().
Unidirectional sampling gate. A sampling gate which transmits signals of
only one polarity.
Unijunction Transistor (UJT). A current-controlled negative-resistance
device with two bases and one emitter. Commonly used as a relaxation
oscillator.
Unipolar ICs. The ICs in which the MOSFETs are the main circuit
elements.
Unit load. The current drawn by the input of logic gate when connected to
the output of an identical gate.
Universal gates. The gates using which the basic logic functions (AND,
OR and NOT) can be realized.
Unsymmetrical triggering. A method of triggering in which the triggering
signal is effective in inducing transition in only one direction.
Upper cut-off frequency, f2. The frequency in the high frequency range of
the gain versus frequency plot at which the gain is 70.7% of its maximum
value.
Upper Triggering Point (UTP). The input voltage V1 at which the
transistor Q2 of the Schmitt trigger just enters into conduction.
Valley current, IV. The magnitude of current at the valley point.
Valley point. The bottom-most point on the V-I characteristic of the device.
Valley voltage, VV. The magnitude of voltage at the valley point.
VLSI. Very large scale integration (10,000 to 99,999 gates per chip)
Voltage time-base generator. A circuit that provides an output voltage
waveform, a portion of which exhibits a linear variation with respect to
time.
Wired AND. A term used to describe the logic function created when open-
collector outputs are tied together.
 Answers to Fill in the Blanks

CHAPTER 1
1. linear network 2. linear wave shaping 3. sinusoidal 4. low-pass 5. 6.
zero 7. finite, bandwidth, 1/2pRC 8. short circuit, open circuit 9. blocks 10.
capacitive, resistance, 0.707 of maximum value 11. step signal 12. vf – (vf –
vin)e–t/t 13. rise time 14. time constant, bandwidth 15. 2.2RC = 0.35/f2 16.
time constant 17. 5t 18. positive step, negative step 19. reciprocal 20. square
wave 21. steady-state 22. ramp, sweep 23. transmission error 24.
25. an integrator 26. >15T 27. high-pass circuit 28. finite, 1/2pRC 29.
infinite, infinite 30. blocking capacitor 31. capacitive coupling 32. peaking
33. peaking circuit 34. high-pass 35. differentiator 36. an impulse of infinite
amplitude 37. positive impulse, delayed negative impulse 38. impulses of
infinite amplitude, zero width 39. 89.4° 40. 0.01 41. high-pass, cascade 42.
integrators, differentiators 43. differentiator, integrator 44. integrator,
differentiator 45. differentiator 46. integrators, differentiators 47. resistive
networks 48. independent 49. compensated 50. capacitors, resistors 51. is
equal to 52. is greater than 53. is less than 54. a 55. L/R 56. large 57.
infinite voltage 58. infinite current 59. ringing 60. ringing.

CHAPTER 2
1. Clipping 2. Clipping 3. voltage, current, amplitude, slicers 4. energy
storage 5. geometric mean, 6. when the diode is OFF and it is
intended that there be no transmission, fast signals or high frequency
waveforms may be transmitted to the output through the diode capacitance
7. when the diode is OFF and it is intended that there be transmission the
diode capacitance together with all other capacitances in shunt with the
output terminals will round off sharp edges of the output waveform and
attenuate the high frequency signals 8. two 9. one 10. one level 11. two
level 12. OFF, ON 13. (a) cut-off, active (b) active, saturation 14. two-level,
differential 15. square 16. comparator 17. non-regenerative, regenerative 18.
clipping 19. non-regenerative 20. regenerative 21. positive 22. shunt 23.
series 24. in a clipping circuit, part of the waveform is to be reproduced
whereas in a comparator circuit there is no interest in reproducing any part
of the signal waveform 25. clipping circuit 26. Schmitt trigger 27. a step
signal 28. a pulse. 29. clamping circuits 30. extremity 31. one way, two way
32. one way 33. two way 34. clamping 35. dc inserter 36. positive, negative
37. positive 38. negative 39. clamping 40. while the clipper clipps OFF the
unwanted portion of the input waveform, the clamper simply clamps the
maximum positive or negative peak to a desired level 41. for any input
waveform under steady-state conditions, the ratio of the area under the
output voltage curve in the forward direction (Af) to that in the reverse
direction (Ar) is equal to the ratio Rf/R 42. R >> Rf and Rr >> R 43. the
absolute levels V and V≤, amplitude V 44. Rs = 0 45. practical 46. biased

47. forward, reverse

CHAPTER 3
1. voltage, current 2. change in voltage, change in current 3. open, closed 4.
diffusion 5. diffusion. 6. resistor and inductor 7. resistor, inductor and
capacitor 8. resistor, capacitor, 9. 10% point of the diode voltage, 10% of its
final value 10. forward 11. storage time 12. transition time 13. piece-wise
linear 14. external circuit 15. avalanche 16. Zener 17. Zener 18. avalanche
19. decreases, increases 20. doping 21. very small, large 22. large, zero 23.
0.2 V, 0.6 V, Vz 24. delay time 25. rise time 26. turn ON 27. storage time
28. fall time 29. turn OFF 30. cut-off, active and saturation 31. decreases
32. reverse biased, open switch 33. forward biased, closed switch 34.
forward biased, reverse biased, amplifier 35. operating point, semi
conductor material, construction 36. transistor 37. 38. BVCEO 39.
RL 40. noise, supply voltage fluctuations, transistor ageing, replacement 41.
alloy junction, epitaxial, grown junction 42. lower 43. increases, insensitive.
CHAPTER 4
1. multivibrator 2. three, bistable multivibrator, monostable multivibrator,
astable multivibrator 3. d.c., a.c. 4. bistable 5. resistor and resistor 6. resistor
and capacitor 7. capacitor and capacitor. 8. bistable 9. Eccles-jordan circuit,
multi, trigger circuit, scale-of-two toggle circuit, binary 10. bistable 11.
stable state 12. stable 13. less than one 14. less than one 15. greater than one
16. output swing, Vw = VC1 – VC2 17. loading 18. saturation, cut-off 19.
less than 20. collector catching 21. transition time 22. capacitors,
commutating capacitors 23. speed-up, transpose 24. resolving time 25.
maximum frequency 26. settling time 27. resolution time 28. transition,
settling 29. (a) reducing all stray capacitances, (b) reducing the resistors R1,
R2 and Rc (c) not allowing the transistors to go into saturation 30. (a) it is
more complicated (b) it consumes more power (c) its voltage swing is less
stable 31. triggering 32. pulse of short duration, step voltage 33.
unsymmetrical triggering 34. symmetrical triggering 35. unsymmetrical 36.
symmetrical 37. unsymmetrically 38. Schmitt trigger 39. greater than one
40. hysteresis 41. unity 42. Schmitt trigger 43. UTP 44. LTP 45. sine,
square 46. Schmitt trigger 47. bistable 48. monostable circuit 49. temporary
50. one shot, a single-cycle, a single step circuit, a univibrator, a gating
circuit, delay circuit 51. gating circuit 52. delay circuit 53. monostable 54.
unsymmetrical 55. astable 56. astable 57. voltage-to-frequency converter
58. free running, square wave 59. master oscillator 60. astable 61. square
wave 62. voltage, frequency.

CHAPTER 5
1. voltage time-base generators, current time-base generators 2. linear time-
base generator 3. current time-base generator 4. voltage time-base generator
5. CROs 6. sweep voltage, sweep circuits 7. CRO’s, in TV and radar
indicators, in precise time measurements, in time modulation 8. sweep time,
restoration time, or return time or flyback time 9. restoration time 10. sweep
waveforms 11. (a) the slope or sweep speed error es, (b) the displacement
error ed, (c) the transmission error et 12. slope error or sweep speed error
13. displacement error 14. transmission error 15. es = 2et = 8ed 16. saw-
tooth waveform 17. seven 18. miller 19. phantastron 20. compensating
networks 21. inverting, infinite 22. non-inverting, unity 23. negative,
positive 24. an inductor 25. relaxation 26. Linearly varying 27. trapezoidal,
step.

CHAPTER 6
1. synchronously 2. one-to-one basis, frequency division 3. integral multiple
4. one-to-one basis 5. synchronization with frequency division 6. frequency
division 7. relaxation circuits 8. relaxation circuits 9. the interval between
pulses Tp is less than or equal to the natural period T0 of the waveform
generator 10. Tp  T0, Tp > T0 11. the range of synchronization, synch
signal amplitude 12. phase delay 13. phase jitter. 14. current.

CHAPTER 7
1. sampling gate 2. exact replica 3. linear gate, transmission gate, time
selection circuit 4. unidirectional, bidirectional 5. gating signal 6.
unidirectional gate 7. bidirectional gate 8. a control pulse, a selector pulse,
enabling pulse 9. gating signal 10. pedestal 11. the ratio of the output
voltage to the input voltage during transmission 12. linearity of operation,
zero pedestal 13. (a) multiplexers, (b) sample and hold circuits, (c) D/A
converters, (d) chopper stabilized amplifiers, (e) sampling scopes 14. low
gain, sensitivity to control voltage imbalance, the possibility that (Vn)min
may be excessive, the possibility of leakage through the diode capacitance
15. its simplicity, very little time delay through the gate, no current in its
quiescent condition, easy extension into a multi-input OR circuit 16. (a)
interaction between the signal source and control voltage source, (b) limited
use of gate because of the slow rise of the control voltage at the diode 17.
millivolts, dv/dt 18. modulator.

CHAPTER 8
1. logic gates 2. basic 3. logic design 4. truth table 5. positive 6. negative 7.
AND 8. OR 9. NOT 10. universal 11. anticoincidence, inequality 12.
coincidence, equality 13. three 14. active-low 15. bubbled, negative 16.
active-low 17. bubbled, negative 18. AND, OR, NOT 19. NAND, NOR 20.
NAND, NOR, X-OR, X-NOR 21. diode logic 22. resistor transistor logic
23. diode transistor logic 24. NOR 25. NAND.

CHAPTER 9
1. TTL, ECL, IIL 2. MOS, CMOS 3. threshold 4. propagation delay 5.
power dissipation 6. fan-in 7. fan-out 8. noise margin 9. speed power
product 10. standard load 11. TTL 12. TTL 13. totem pole type, open
collector type, tri-state type 14. low, high, high impedance 15. F(fast) TTL
16. ECL 17. ECL 18. ECL 19. NMOS 20. depletion type, enhancement type
21. enhancement 22. LSI, VLSI, ULSI 23. CMOS 24. CMOS 25. CMOS
26. ECL, CMOS 27. CMOS, IIL 28. CMOS, ECL 29. TTL open collector
30. ECL open emitter 31. high speed, low power dissipation 32. TTL,
CMOS 33. MOS 34. MOS, IIL 35. transmission.

CHAPTER 10
1. regenerative feedback 2. blocking oscillator 3. monostable, astable 4.
high peak power 5. monostable, astable 6. nanoseconds, microseconds 7.
base timing, emitter timing 8. base timing, hFE 9. master oscillator 10.
monostable 11. low impedance switch 12. diode-controlled, RC-controlled
13. monostable 14. astable 15. tertiary 16. mark-space ratio 17. better
voltage waveforms, simpler design equations, less possibility of oscillations
preceding the pulses 18. low duty cycle operation, simple and continuous
variation of oscillations, stability with respect to temperature changes.
 Answers to Objective
Type Questions

CHAPTER 1
1. (a)
2. (c)
3. (b)
4. (a)
5. (b)
6. (a)
7. (a)
8. (a)
9. (b)
10. (a)
11. (b)
12. (a)
13. (b)
14. (a)
15. (d)
16. (a)
17. (b)
18. (b)
19. (c)
20. (d)
21. (b)
22. (a)
23. (a)
24. (a)
25. (b)
26. (c)
27. (c)
28. (a)
29. (c)
30. (c)
31. (c)
32. (a)
33. (d)
34. (a)
35. (b)
36. (b)
37. (c)
38. (b)
39. (a)
40. (b)
41. (d)
42. (b)
43. (b)
44. (c)
45. (c)
46. (b)
47. (c)
48. (a)
49. (a)
50. (a)
51. (a)
52. (a)
53. (c)
54. (d)
55. (a)
56. (b)
57. (b)
58. (b)
59. (b)
60. (b)
61. (c)
62. (a)
63. (b)
64. (a)
65. (a)
66. (b)
67. (b)
68. (a)
69. (c)
70. (a)
71. (a)
72. (b)
73. (b)
74. (a)
75. (b)
76. (b)
77. (a)
78. (a)
79. (a)

CHAPTER 2
1. (c)
2. (a)
3. (d)
4. (a)
5. (a)
6. (c)
7. (b)
8. (a)
9. (a)
10. (a)
11. (b)
12. (a)
13. (b)
14. (c)
15. (b)
16. (b)
17. (b)
18. (a)
19. (c)
20. (a)
21. (b)
22. (b)
23. (a)
24. (a)
25. (b)
26. (b)
27. (b)
28. (c)
29. (c)
30. (b),(c)
31. (d)
32. (b)
33. (a)

CHAPTER 3
1. (a)
2. (c)
3. (a)
4. (b)
5. (d)
6. (c)
7. (a)
8. (b)
9. (a)
10. (b)
11. (a)
12. (b)
13. (a)

CHAPTER 4
1. (a)
2. (a)
3. (a)
4. (c)
5. (a)
6. (a)
7. (c)
8. (b)
9. (c)
10. (b)
11. (c)
12. (a)
13. (c)
14. (b)
15. (a)
16. (a)
17. (b)
18. (a)
19. (a)
20. (b)
21. (c)
22. (b)
23. (c)
24. (a)
25. (b)
26. (b)
27. (d)
28. (b)
29. (c)
30. (a)
31. (a)
32. (a)
33. (c)
34. (b)
35. (b)
36. (c)
37. (c)
38. (c)
39. (c)
40. (a)
41. (a)
42. (a)
43. (a)
44. (c)
45. (c)
46. (c)
47. (a)
48. (c)
49. (a)
50. (a)

CHAPTER 5
1. (a)
2. (c)
3. (a)
4. (a)
5. (b)
6. (c)
7. (b)
8. (d)
9. (a)
10. (c)
11. (b)
12. (a)
13. (a)
14. (a)
15. (a)
16. (a)
17. (c)
18. (b)
19. (c)
20. (a)
21. (b)
22. (c)
23. (a)

CHAPTER 6
1. (a)
2. (a)
3. (a)
4. (b)
5. (c)
6. (a)
7. (b)

CHAPTER 7
1. (a)
2. (a)
3. (c)
4. (a)
5. (b)
6. (a)
7. (c)
8. (a)
9. (b)
10. (b)
CHAPTER 8
1. (b)
2. (a)
3. (c)
4. (c)
5. (c)
6. (d)
7. (c)
8. (d)
9. (a)
10. (b)
11. (a)
12. (b)
13. (a)
14. (a)
15. (a)
16. (a)
17. (b)
18. (c)
19. (d)
20. (c)
21. (d)

CHAPTER 9
1. (a)
2. (a)
3. (b)
4. (c)
5. (a)
6. (b)
7. (b)
8. (b)
 9. (d)
10. (c)
11. (a)
12. (d)
13. (d)
14. (a)
15. (b)
16. (b)
17. (d)
18. (b)
19. (b)
20. (c)

CHAPTER 10
1. (b)
2. (c)
3. (b)
4. (c)
5. (b)
6. (b)
 Answers to Problems

CHAPTER 1
1.1

1.2 Vp–p = 0.2448 V

1.3 Vmax = –0.457 V, Vmin = – 1.432 V, Vdc = –1 V

1.4 Vmax = 14.54 V, Vmin = 5.35 V under steady-state

1.5(a)
 V1 = 78.693 V, V2 = 87.076 V, V3 = 131.48 V, V4 = 119.104 V, V5 = 150.93 V, V6 = 130.89 V

Steady-state response

V1 = 161.98 V, V2 = 137.5 V

1.5(b)

Transient response

V1 = 172.93 V, V2 = 109.877 V, V3 = 187.8 V, V4 = 111.88 V, V5 = 188.08 V, V6 = 111.90 V

 Steady-state response

V1 = 188.03 V, V2 = 111.85 V

1.6

1.7

1.8 V1 = 1.54 V, V2 = – 3.433 V, V1 = 0.566 V, V2 = – 2.45 V

1.9(a)

1.9(b)

1.10
 V1 = 101.309 V, V 1 = 37.282 V, V2 = –162.718 V, V 2 = – 98.609 V

1.11 f2 = 1.4 MHz, f1 = 31.84 Hz

1.12 Vp = 10 kV

1.13

1.14
1.15 (a) a = 0.09, (b) C = 16 pF, (c) Zi = 4.4 M

CHAPTER 2
2.6
2.9

2.10
2.11

2.12

2.13

2.14
2.15

2.16
2.17 (a) 2 mV below the top; (b) 198 mV below the top.
2.18

2.19

2.20
2.21

CHAPTER 4
4.1 (a) Q2 ON, Q1 OFF
IC2 = 9.547 mA, IB2 = 1.28 mA, VB2 = 0.7 V, VB1 = 0.3 V, IC1 = 0 mA,
IB1 = 0 mA, VC1 = 8.45 V, VB1 = – 0.466 V, IB2(actual) (=1.28 mA) >
IB2(min) (= 0.38 mA). Hence Q2 is ON. VB1 is –ve, so Q1 is OFF.
(b) IBCO(max) = 139.9 A; (c) RL= 735 
4.2 (a) Q2 ON, Q1 OFF
IC2 = – 9.28 mA, IB2 = – 1.2 mA, VC2 = – 0.5 V, VB2 = – 1V, IC1 = 0
mA, IB1 = 0 mA, VC1 = – 8.5 V, VB1 = 0.6 V, hFE(min) = 7.73.
o
(b) T(max) = 63.96 C.

4.3 (a) Q2 ON, Q1 OFF

IC2 = 14.792 mA, IB2 = 1.25 mA, VC2 = 0 V, VB2 = 0 V, IC1 = 0 mA,
IB1 = 0 mA, VB1 = – 0.832 V, VC1 = 6 V
IB2(actual) (= 1.25 mA) > IB2(min) (= 0.59 mA). So Q2 is ON. vB1 is
negative, so Q1 is OFF.
(b) RL(max) = 800 
o
(c) T(max) = 76.1 C

4.4 RC = 2 k, R1 = 33.76 k, R2 = 168.8 k

4.5 VCC = VBB = 10 V, IC(sat) = 10 mA, RC = 1 k, R1 = 11.2 k, R2 =

133.3 k
4.6 (a) IC1 = 0 mA, IB1 = 0 mA, VCN1 = 16.589 V, VBN1 = 4.69 V, VEN
= 6.166 V,
IC2 = 11.151 mA, IB2 = 1.18 mA, VCN2 = 6.565 V, VBN2 = 6.965 V,
VW = 10.1 V

(b) hFE(min) = 9.45

(c) ICBO(max) = 325.2 A

4.7 (a) Q2 ON, Q1 OFF

 IC1 = 0 mA, IB1 = 0 mA, VCN1 = –8.998 V, VBN1 = –2.39 V, VEN = –
3.385 V,
IC2 = –6.176 mA, IB2 = –0.594 mA, VCN2 = –3.585 V, VBN2 = –3.985
V, VW = 5.41 V,
IB2(min) = –0.3088 mA

(b) RL(max) = 4.248 k

(c) ICBO(max) = 266 A

4.8 Let IC(sat) = 10 mA, VBE = –1 V, IB2(actual) = 2  IB2(min)

RC = 0.8 k, RE = 0.1875 k, R1 = 7.9 k, R2 = 7.9 k

4.9 RC = 1.8 k, RE = 0.185 k, R1 = R2 = 18.35 k

o o
4.10 UTP = V1 = 8.446 V, LTP = V2 = 6.653 V, a1 = 43.82 , a2 = 34.28 ,
Upper level of output = 15 V, Lower level of output = 13.74 V
o o
4.11 UTP = V1 = 13.729 V, LTP = V2 = 9.743 V, a1 = 43.35 , a2 = 29.34 ,
Upper level of output = 20 V, Lower level of output = 16.82 V
4.12 RE = 2.375 k, RS = 2 k, R1 = 7.01 k, R2 = 25.5 k, RC1 = 2.59
k, RC2 = 0.5 k

4.13 RE = 2.875 k, RS = 2 k, R1 = 9.712 k, R2 = 24.87 k, RC1 =

2.428 k,
RC2 = 0.125 k

4.14 (a) In stable state, Q2 is ON, Q1 is OFF, IB2(actual) (= 0.753) >

IB2(min)(=0.464 mA), so Q2 is ON. VB1 = –1.85 V, so Q1 is OFF.
 (b) The waveforms are as shown in Figure 5.32.
d = d = 2.274 V, IB rBB = 2.073 V, IBRC = 9.426 V, VC2 = 11.68
V
VB1(OFF) = –1.85 V, VB2(OFF) (t = 0) = –10.9 V, t = 15 s, t = 1.22
s

(c) Width of output pulse = 10.395 s

In quasi-stable-state Q1 is ON, Q2 is OFF
IB1(actual) (= 0.526 mA) > IB1(min) (= 0.375 mA), so Q1 is ON
+
At t = 0 , VB2 = – 10.9 V, so Q2 is OFF.

5.15 RC1 = RC2 = RC = 4 k, R1 = R2 = 34.5 k, R = 53.33 k, C =

0.0541 F
Taking tp = 1 s and RC = tp/10 and R = 5 k, C = 20 pF

5.16 ICBO, VCE(sat), and VBE(sat) are neglected

Assumed hFE = 25, IB(actual) = 1.5/IB(min), VBE(OFF) = –1 V
R1 = R2, VCC = 10 V, IC(sat) = 5 mA, RC1 = RC2 = RC = 2 k, R1 = R2
= 20.3 k, R = 33.33 k, C = 0.216 F, VBB = 2 V
Triggering circuit tp = 1 s, RC = tP/10 if R = 10 k, C = 10 pF

5.17 RC1 = RC2 = RC = 2 k, R1 = R2 = R = 13.33 k, C1 = C2 = C =

0.2165 F
Assumed hFE = 20, IC(sat) = 5 mA, VCC = 10 V, IB(actual) = 1.5,
IB(min), VCE(sat) = 0 V, VBE(sat) = 0 V
5.18 RC1 = RC2 = RC = 1.46 k, R1 = R2 = R = 19.06 k, C1 = 0.0132
F, C2 = 0.0246 F
Assumed hFE = 25, IC(sat) = 10 mA, VCC = 15 V, IB(actual) =
1.5IB(min), VCE(sat) = 0.4 V, VBE(sat) = 0.8 V

CHAPTER 5
5.1 (a) IC1(sat) = 1.25 mA, IC1(max) = 22.5 mA
5
(b) Sweep speed = 5  10 V/s, Vs(max) = 15 V, Ts = 30 s
(c) Tr = 1.765 s
VC1 = 0.259 V, T1 = 21.569 s, es = 7.82%

5.2 (a) IC1(sat) = 2 mA, IC1(max) = 10 mA

 (b) es = 1.34%
4
(c) Sweep speed = 4  10 V/s, Vs(max) = 10 V, Ts = 250 s
(d) Tr = 62.5 s
(e) T1 = 416 s

5.3 (a) Rb = 200 k

(b) C = 0.0625 F
(c) es = 1.93%
(d) C1 = 75 F
(e) Tr = 500 s
(f) T1 = 3.1625 s

5.4 R = 2.16 k, C = 2.08 F, RB = 86.9 k, C1 = 20.8 F

5.5 R = 4.8 k, RB = 120.625 k, C = 1.666 F, C1 = 16.66 F

5.6 (a) VCC = 37.5 V, ILRd = 3 V, t = 0.01255

(b)
 (c) Rd(max) = 83.33 , Recovery time = 4.5 ms

5.7 (a) IL(max) = 42.46 mA, Tr = 7.14 ms, Tf = 0.909 ms, spike = 10.615 V
(b) es = 6.755%.

CHAPTER 8
8.1 (a)
(b)
(c)
8.2 (a)

(b)
8.3

8.4
CHAPTER 10
10.1 (a) T = 6.66 s, Duty cycle = 0.45
(b) IB(max) = 5 mA, IC(max) = 10 mA, IL(max) = 10 mA, VC extends
from 5 to 15, VB extends from 5 V to –5 V
(c) Im = 1.414 mA

10.2 L = 12.5 ms, C = 100 pF, n = 1, R = 2.5 k, Vg = 1.445 V

 Index

AC coupling, 223
Active pull up, 467
Alternative form of 4-diode gate, 420
All or nothing gate, 435
Anti-coincidence gate, 447
Any or all gate, 432
AOI logic, 439
Astable circuits (see Multivibrators, astable), 298
Attenuator, 65
as a CRO probe, 69
compensated, 66
over compensation, 67
perfect compensation, 67
under compensation, 67

Bandwidth, 2, 31
Basic building blocks, 432
Basic gates, 432
Binary circuit, 224
bistable, 224
collector-coupled, 224
commutating capacitor, 252
direct-connected, 259
emitter-coupled, 260
fixed bias, 224
methods of improving resolution, 253
non-saturating, 254
resolving time of, 253
Schmitt trigger circuit, 260
 applications, 263
hysteresis, 264
self-biased, 240
settling time of, 253
stable states, 224
transition time of, 252
triggering, 255
symmetrically, 257
through unilateral device, 257
unsymmetrically, 256
Blocking capacitor, 31
Blocking oscillator, 495
applications of, 513
astable, 502
diode-controlled, 503
RC-controlled, 511
monostable, 495
base timing, 496
emitter timing, 499
pulse width, 498
Bootstrap sweep circuit, 356
Breakdown, 200
avalanche, 201
junction diode, 200
voltages of a transistor, 204
zener, 201
Bubbled AND gate, 444
Bubbled OR gate, 440

Capacitive coupling circuit, 31

Chopper amplifier, 424
Clamping circuit theorem, 161
Clamping circuits, 150
biased clamping, 154
clamping operation, 150
classification, 150
 design of, 195
negative clamping, 151
positive clamping, 153
practical circuits, 163
relation between tilts, 159
synchronized clamping, 167
with source and diode resistances, 156
Clipping circuits, 104
diode clippers, 104
compensation for variation in temperature, 120
double-ended, 116
single-ended, 110
emitter-coupled clippers, 124
noise clippers, 118
series, 118
shunt, 119
series clippers, 108
shunt clippers, 105
transistor clippers, 121
Coincidence gate, 447
Commutating capacitors, 252
Comparators, 148
applications of, 150
diode, 149
emitter-coupled binary, 260
regenerative (see Blocking oscillator, Schmitt trigger circuit), 260
Schmitt circuit as, 263
voltage, 263
Current mode logic, 473
Current steering logic, 473
Current time base generators, 373

DC coupling, 223
DC inserter, 150
DC restorer, 150
Delay circuit (see Multivibrator monostable), 279
Differentiation, double, 43
Diode
catching, 226
double base (see Unijunction transistor), 339
Direct connected binary, 259
Displacement error (see Sweep circuits), 333
Divider, frequency (see Synchronization), 391
Double-base diode (see Unijunction transistor), 339
DTL NAND gate, 441
DTL NOR gate, 445
Dynamic MOS logic, 483
dynamic MOS inverter, 484
dynamic NAND gate, 485
dynamic NOR gate, 486

Eccles-Jordan circuit (see Binary circuit), 224

Emitter coupled binary, 260
Equality detector, 447
Exclusive NOR-gate, 447
Exclusive OR-gate, 446

Fan-in, 464
Fan-out, 465
Fly back time, 332
Frequency division (see Synchronization), 389

Gain of sampling gate, 417

Gates, sampling, 407
applications, 424
bidirectional, 412
using diodes, 415
using transistors, 412
emitter-coupled, 413
four-diode, 419
reduction of pedestal, 414
six-diode, 423
 unidirectional, 408

High-pass RC circuit (see RC circuits, wave shaping), 31

Inclusive OR gate, 432

Inequality detector, 446
Inhibit circuits, 448
Inverter, 438

Limiting circuits (see Clipping circuits), 104

Linear network, 1
Loading, 225
Logic design, 431
Logic families, 464
Logic gates, 431
AND gate, 435
NAND gate, 439
NOR gate, 443
NOT gate, 438
OR gate, 432
X-NOR gate, 447
X-OR gate, 446
Low-pass RC circuit (see RC circuits, wave shaping), 1
LTP, 266
CMOS, 479
inverter, 479
NAND gate, 480
NOR gate, 481
ECL, 472
OR/NOR gate, 473
I2L, 470
inverter, 471
NAND gate, 471
NOR, 472
MOS, 475
 inverter, 476
NAND gate, 477
NOR gate, 478
TTL, 465
current sinking, 468
current sourcing, 468
open collector output, 468
schottky TTL, 470
sub families, 466
totem pole output, 467
tri-state, 469
two-input NAND gate, 466
wired AND operation, 468

Low-pass RC circuit, 1

LTP, 266

Methods of improving resolution, 253

Miller sweep circuit, 355
Monostable circuits (see Multivibrator, monostable), 223, 279
Multivibrator, astable, 224, 298
collector-coupled, 298
emitter-coupled, 312
gated, 304
period of, 301
unijunction transistor, 338
voltage-to-frequency converter, 301
Multivibrator, bistable (see Binary circuit), 224
Multivibrator, monostable, 279
collector-coupled, 279
delay time, 280
emitter-coupled, 295
gate width of, 280
triggering of, 297
univibrator, 279
NAND logic, 439
Negative AND gate, 444
Negative logic system, 431
Negative OR gate, 440
Noise margin, 465
Non saturating binary, 254

One-shot (see Multivibrator, monostable), 279

One-way clamps, 150
Open-collector gates, 468
Oscillator, blocking (see Blocking oscillator), 495

Phantastron circuit, 335

Phase delay, 398
Phasejitter, 398
Positive logic system, 431
Pulse generator (see Blocking oscillator), 495

Ramp voltage (see Sweep circuits), 334

Rate-of-rise amplifier, 43
RC circuits, wave shaping, 1
high-pass, 31
differentiator, 42
exponential input, 39
pulse input, 33
ramp input, 38
sinusoidal input, 31
square-wave input, 34
step-voltage input, 33
low-pass, 1
exponential input, 11
integrator, 12
pulse input, 5
ramp input, 9
sinusoidal input, 2
square-wave input, 7
 step-voltage input, 3
Regenerative circuits (see Blocking oscillator, Comparators, Multivibrators), 495, 148, 223
Relaxation circuits, 299
Resolution time, 253
Ringing circuit, 80
RL circuits, wave shaping, 76
RLC circuits, wave shaping, 77
characteristic impedance, 78
RTL NAND gate, 441
RTL NOR gate, 445

Sampling gates (see Gates sampling), 407

Sampling scope, 426
Saturation parameters, 227
Saw-tooth generator, 332
Schmitt trigger circuit, 260
Schottky barrier diode, 470
Schottky TTL, 470
Selector circuits (see Clipping circuits, Gates sampling), 407
Self-biased binary, 240
Speed power product, 465
Speed up capacitor, 252
Standard TTL, 465
Sweep circuits, 332
current, 373
constant-voltage, 373
driving waveform, 374
linearity improvement, 374
transistor, 377
voltage, 232
bootstrap, 356
constant-current, 334
displacement error, 333
exponential, 335
using UJT, 340
Miller, circuit, 355
 restoration time, 332
slope error (see Sweep speed error), 333, 336
sweep speed error, 333, 336
sweep time, 332
sweep voltage, 332
transmission error, 334
using a transistor switch, 347
Switch transistor, 202
Switching times
junction diode, 196
transistor, 203
Synchronization, 389
pulse synchronization of relaxation circuits, 389
as a divider, 392
sweep generator, 390
with frequency division, 389, 391
astable blocking oscillator, 392
astable multivibrator, 393
monostable multivibrator, 396
sine-wave, 399
with symmetrical signals, 399

Tilt, 34
Totem pole gates, 467
Transition time, 253
Transmission error, 334
Transmission gates (see Gates sampling), 407, 482
Tri-state TTL, 469
Truth table, 431
Two-way clamps, 150

Unijunction transistor (UJT), 338

applications, 340
Universal gate, 432, 439
Univibrator (see Multivibrator, monostable), 279
UTP, 264
Wired AND operation, 468
Wired OR operation, 474