PL022 Errata v5

Synchronous Serial Port (PL022)
Date of Issue: 27 January 2016 ARM Errata Notice Document Revision 5.0
ARM PrimeCell
Errata Notice
This document contains all errata known at the date of issue in releases up to and including revision r1p4 of
PL022 Synch Serial IFace -Perpetual
PL022-GENC-004952 v5.0 Confidential Page 1 of 19

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Contents
INTRODUCTION 6
ERRATA SUMMARY TABLE 8
ERRATA - CATEGORY 1 9
835269: Slave mode can sample new TX data from PCLK domain using SSPCLK with no
synchronisation 9
852371: Motorola SPI format slave mode writes to transmit FIFO can lose data 10
327544: TX/RXDMABREQ and TX/RXSREQ signals not fully compatible with DMAC 11
257559: Width Inconsistency in SspTrAbif.vhd/v file 12
257912: Questions conflict in tbench files 13
ERRATA - DOCUMENTATION 14
322587: PL022 TRM Figure 2-2 is incorrect 14
328377: Figure 2-12 in TRM (DDI0194D) Incorrect 15

332947: Figures 2-13 to 2-15 In Technical Reference Manual Are Incorrect 16
338113: TRM 4.3.3 Integration test output register, SSPITOP Incorrect 17
340341: State machine documentation inconsistent with RTL & Diagrams 18
ERRATA – DRIVER SOFTWARE 19

There are no Errata in this Category 19

Introduction
Scope
This document describes errata categorised by level of severity. Each description includes:
 the current status of the defect
 where the implementation deviates from the specification and the conditions under which erroneous
behavior occurs
 the implications of the erratum with respect to typical applications
 the application and limitations of a ‘work-around’ where possible
Categorisation of Errata
Errata recorded in this document are split into three levels of severity:
Category 1 Behavior that is impossible to work around and that severely restricts the use of
the product in all, or the majority of applications, rendering the device unusable.
Category 2 Behavior that contravenes the specified behavior and that might limit or severely
impair the intended use of specified features, but does not render the product
unusable in all or the majority of applications.
Category 3 Behavior that was not the originally intended behavior but should not cause any
problems in applications.

Change Control
29 January 2016: Changes in Document v5
Page Status ID Cat Summary
9 Updated 835269 Cat 1 Slave mode can sample new TX data from PCLK domain using SSPCLK
with no synchronisation
10 Updated 852371 Cat 1 Motorola SPI format slave mode writes to transmit FIFO can lose data
18 Updated 340341 Doc State machine documentation inconsistent with RTL & Diagrams
16 Nov 2015: Changes in Document v4

9 New 835269 Cat 1 Slave mode can sample new TX data from PCLK domain using SSPCLK
with no synchronisation
10 New 852371 Cat 1 Motorola SPI format slave mode writes to transmit FIFO can lose data
09 Oct 2007: Changes in Document v2

11 Updated 327544 Cat 2 TX/RXDMABREQ and TX/RXSREQ signals not fully compatible with DMAC
13 Updated 257912 Cat 3 Questions conflict in tbench files
15 New 328377 Doc Figure 2-12 in TRM (DDI0194D) Incorrect
16 New 332947 Doc Figures 2-13 to 2-15 In Technical Reference Manual Are Incorrect
17 New 338113 Doc TRM 4.3.3 Integration test output register, SSPITOP Incorrect
18 New 340341 Doc State machine documentation inconsistent with RTL & Diagrams
30 Jun 2004: Changes in Document v1

11 New 327544 Cat 2 TX/RXDMABREQ and TX/RXSREQ signals not fully compatible with DMAC
12 New 257559 Cat 3 Width Inconsistency in SspTrAbif.vhd/v file
13 New 257912 Cat 3 PL022 Questions conflict in tbench files
14 New 322587 Doc PL022 TRM Figure 2-2 is incorrect

Errata Summary Table

The errata associated with this product affect product versions as below.
A cell shown thus X indicates that the defect affects the revision shown at the top of that column.
ID Cat Summary of Erratum
r1p3-00rel1
r1p4-00rel0
1-01
1-02
322587 Doc PL022 TRM Figure 2-2 is incorrect X X
328377 Doc Figure 2-12 in TRM (DDI0194D) Incorrect X X
332947 Doc Figures 2-13 to 2-15 In Technical Reference Manual Are Incorrect X X
338113 Doc TRM 4.3.3 Integration test output register, SSPITOP Incorrect X X
340341 Doc State machine documentation inconsistent with RTL & Diagrams X X X
835269 Cat 1 Slave mode can sample new TX data from PCLK domain using X X X
SSPCLK with no synchronisation
852371 Cat 1 Motorola SPI format slave mode writes to transmit FIFO can lose X X X
data
327544 Cat 2 TX/RXDMABREQ and TX/RXSREQ signals not fully compatible X X
with DMAC
257559 Cat 3 Width Inconsistency in SspTrAbif.vhd/v file X
257912 Cat 3 Questions conflict in tbench files X

Errata - Category 1
835269: Slave mode can sample new TX data from PCLK domain using SSPCLK with
no synchronisation
Status
Affects: product PL022 Synch Serial IFace -Perpetual.

Fault status: Cat 1, Present in: 1-01,1-02,r1p3-00rel1, Fixed in r1p4-00rel0.
Description
If the SSP is programmed to operate in slave mode, data written to the SSP data register in the PCLK domain
can be sampled in the SSPCLK domain without any synchronisation.
Conditions
For this to occur, the SSP Transmit FIFO must be empty, and the SSP data register write access occurs just as
a new SPI master transfer starts and the SSP slave state machine samples data to transmit.
Implications
Write data can be lost.
Workaround
There is no software workaround.

852371: Motorola SPI format slave mode writes to transmit FIFO can lose data
Status

Fault status: Cat 1, Present in: 1-01,1-02,r1p3-00rel1, Fixed in r1p4-00rel0.
Description
If the SSP is programmed to operate in Motorola SPI slave mode then it is possible that write data can be lost.
Conditions
For this to occur, the SSP Transmit FIFO must be empty, and either:
 The write to the SSP data register occurs between a new SPI master transfer starting and the end of
the first bit of incoming data, or
 The write to the SSP data register occurs during the first bit of new incoming data in back-to-back
transfer sequences.
Implications
Write data can be lost.
Workaround
There is no software workaround.

Errata - Category 2
327544: TX/RXDMABREQ and TX/RXSREQ signals not fully compatible with DMAC
Status

Fault status: Cat 2, Present in: 1-01,1-02, Fixed in r1p3-00rel1.
Description
The DMA interface in PL022 is not fully compliant for the ARM DMAC interface protocol.
The PL022 neglects DMACCLR from DMA for cancelling DMA request signals(DMABREQ/DMASREQ) which
may cause overflow or underflow in PL022 Data FIFO, especially if the DMAC data transfer size is set to a
burst.
Affected Items
SspDMA.v
TXDMASREQ assertion logic:Line-175-182
TXDMABREQ assertion logic:Line-191-198
RXDMASREQ assertion logic:Line-215-222
RXDMABREQ assertion logic:Line-234-242
Implications
PL022 neglects DMACCLR from DMA for cancelling DMA request signals(DMABREQ/DMASREQ) which may
cause overflow or underflow in PL022 Data FIFO, especially if the DMAC data transfer size is set to a burst.
Workaround
None

Errata - Category 3
257559: Width Inconsistency in SspTrAbif.vhd/v file
Status

Fault status: Cat 3, Present in: 1-01, Fixed in 1-02.
Description
Summary:
There is a width inconsistency in the SspTrApbif.vhd/v files.
This does not affect the functionality as it is part of the test infrastructure
Symptoms
A compilation error will occur in :"verification/vhdl/trickbox/SspTrApbif.vhd/v".
Affected items
SspTrApbif.vhd/v
Implications
None
Workaround
At the line 401, in the SspTrApbif.vhd, the code can be modified as follows:
From:
ZEROFILL(15 downto 6) & SSPTBSETPINS when (SSPTBSETPINSRd = '1')
To:
ZEROFILL(15 downto 7) & SSPTBSETPINS when (SSPTBSETPINSRd = '1')
Likewise for the SspTrApbif.v file

257912: Questions conflict in tbench files
Status

Fault status: Cat 3, Present in: 1-01, Fixed in 1-02.
Description
There is a conflict of output signals (SCANOUTPCLK and SCANOUTSSPCLK) in the testbench.
This does not affect the functionality as it is part of the test infrastructure
There will be a conflict of signals in the netlist simulations and the simulation may fail.
Affected items
Tbench.v/vhd
Implications
None
Workaround
The code can be modified as follows:

(line 103)
wire DUMMY;
-->
wire DUMMY1;
wire DUMMY2;
(line 267,268)
.SCANOUTPCLK (DUMMY),
.SCANOUTSSPCLK (DUMMY),
-->
.SCANOUTPCLK (DUMMY1),
.SCANOUTSSPCLK (DUMMY2),
The testbench for VHDL is same problem.

Errata - Documentation
322587: PL022 TRM Figure 2-2 is incorrect
Status

Fault status: Doc, Present in: 1-01,1-02, Fixed in r1p3-00rel1.
Description
In the TRM, Figure 2-2, the diagram for the TI Single Transfer, Figure 2-2, is incorrect.
SSPCLKOUT is forced LOW when the SSP should be IDLE, in-between the single transfers and so the figure
should show SSPCLKOUT going LOW after the LSB.
SSPCLKOUT should be held inactive while the SSP is idle and so it transitions at the programmed frequency
only during active transmission or reception of data.
Implications
None
Workaround
None

328377: Figure 2-12 in TRM (DDI0194D) Incorrect
Status

Description
In the Technical Reference Manual Figure 2-12, Chapter 2 page 2-21, the hold time should be with respect to
the rising edge, with a whole SSPCLKIN used for the hold period.
Implications
None
Workaround
None

332947: Figures 2-13 to 2-15 In Technical Reference Manual Are Incorrect
Status

Description
Figures 2-13 to 2-15 In Technical Reference Manual are incorrect as they depict something that the PL022 is
not capable of doing.
It is not possible with the PL022 to attach multiple slaves as shown in the diagrams.
The PL022 is purely a point to point connection from one master to one slave and there is no address decoding
or slave select logic within the PL022 to enable the connection to multiple slaves.
Implications
It is not possible with the PL022 to attach multiple slaves.
Workaround
None

338113: TRM 4.3.3 Integration test output register, SSPITOP Incorrect
Status

Description
Section 4.3., Table 4-4. on Page 4-6 states that in the Integration test output register, SSPITOP
--------------------------------------------------------------------
bit name
--------------------------------------------------------------------
4 nSSPCTLOE
3 nSSPOE
--------------------------------------------------------------------
This is incorrect and should be:
bit name
--------------------------------------------------------------------
4 nSSPOE
3 nSSPCTLOE
--------------------------------------------------------------------
Implications
None
Workaround
None

340341: State machine documentation inconsistent with RTL & Diagrams
Status

Fault status: Doc, Present in: 1-01,1-02,r1p3-00rel1, Fixed in r1p4-00rel0.
Description
In the PL022 SSP Design Manual (PL022 DDES 0000 A), the text description of the SspSTxRxCntl state
machine does not match the graphical description and the RTL.
Figure 5.14-4 "A section of the SspSTxRxCntl state machine for the TI Synchronous Serial Frame Format"
correctly indicates that there is no path from the ST_STIDSSPOE1 state to the ST_STIIDLE (this matches the
RTL implementation).
The second paragraph on page 51 incorrectly states "In the ST_STIDnSSPOE1 state and the
ST_STIDnSSPOE2 state, the state machine checks whether SSPFSSINSync is asserted in between to denote
the start of a new frame". This should instead state "In the ST_STIDnSSPOE2 state, the state machine checks
whether SSPFSSINSync is asserted to denote the start of a new frame".
Implications
Not applicable
Workaround
Not applicable

Errata – Driver Software
There are no Errata in this Category


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Synchronous Serial Port (PL022)

PL022-GENC-004952 v5.0 Confidential Page 1 of 19

Confidential Proprietary notice

THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO

This document may include technical inaccuracies or typographical errors.

PL022-GENC-004952 v5.0 Confidential Page 2 of 19

ARM Limited. Company 02557590 registered in England.

110 Fulbourn Road, Cambridge, England CB1 9NJ.

Document confidentiality status

PL022-GENC-004952 v5.0 Confidential Page 3 of 19

Feedback on the product

Feedback on this document

General suggestion for additions and improvements are also welcome.

PL022-GENC-004952 v5.0 Confidential Page 4 of 19

ERRATA SUMMARY TABLE 8

257912: Questions conflict in tbench files 13

328377: Figure 2-12 in TRM (DDI0194D) Incorrect 15

340341: State machine documentation inconsistent with RTL & Diagrams 18

ERRATA – DRIVER SOFTWARE 19

PL022-GENC-004952 v5.0 Confidential Page 5 of 19

PL022-GENC-004952 v5.0 Confidential Page 6 of 19

16 Nov 2015: Changes in Document v4

09 Oct 2007: Changes in Document v2

30 Jun 2004: Changes in Document v1

PL022-GENC-004952 v5.0 Confidential Page 7 of 19

Errata Summary Table

ID Cat Summary of Erratum

PL022-GENC-004952 v5.0 Confidential Page 8 of 19

Affects: product PL022 Synch Serial IFace -Perpetual.

PL022-GENC-004952 v5.0 Confidential Page 9 of 19

Affects: product PL022 Synch Serial IFace -Perpetual.

PL022-GENC-004952 v5.0 Confidential Page 10 of 19

Affects: product PL022 Synch Serial IFace -Perpetual.

PL022-GENC-004952 v5.0 Confidential Page 11 of 19

257559: Width Inconsistency in SspTrAbif.vhd/v file

Affects: product PL022 Synch Serial IFace -Perpetual.

PL022-GENC-004952 v5.0 Confidential Page 12 of 19

257912: Questions conflict in tbench files

Affects: product PL022 Synch Serial IFace -Perpetual.

There is a conflict of output signals (SCANOUTPCLK and SCANOUTSSPCLK) in the testbench.

The code can be modified as follows:

The testbench for VHDL is same problem.

PL022-GENC-004952 v5.0 Confidential Page 13 of 19

322587: PL022 TRM Figure 2-2 is incorrect

Affects: product PL022 Synch Serial IFace -Perpetual.

PL022-GENC-004952 v5.0 Confidential Page 14 of 19

328377: Figure 2-12 in TRM (DDI0194D) Incorrect

Affects: product PL022 Synch Serial IFace -Perpetual.

PL022-GENC-004952 v5.0 Confidential Page 15 of 19

332947: Figures 2-13 to 2-15 In Technical Reference Manual Are Incorrect

Affects: product PL022 Synch Serial IFace -Perpetual.

It is not possible with the PL022 to attach multiple slaves.

PL022-GENC-004952 v5.0 Confidential Page 16 of 19

338113: TRM 4.3.3 Integration test output register, SSPITOP Incorrect

Affects: product PL022 Synch Serial IFace -Perpetual.

PL022-GENC-004952 v5.0 Confidential Page 17 of 19

340341: State machine documentation inconsistent with RTL & Diagrams

Affects: product PL022 Synch Serial IFace -Perpetual.

PL022-GENC-004952 v5.0 Confidential Page 18 of 19

Errata – Driver Software

There are no Errata in this Category

PL022-GENC-004952 v5.0 Confidential Page 19 of 19

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