New Approach to LUT Implementation and

Accumulation for Memory-Based Multiplication

Pramod Kumar Meher
Communication Systems Department, Institute for Infocomm Research,
Agency for Science, Technology and Research (A*STAR), Singapore.

TABLE I
Abstract—A new approach to look-up-table (LUT) implemen- LUT W ORDS AND P RODUCT VALUES FOR I NPUT W ORD L ENGTH L = 4
tation for memory-based multiplication is presented, where the
memory-size is reduced to half at the cost of some increase in address word stored input product # of control
combinational circuit complexity. The proposed design offers a d2 d1 d0 symbol value x3 x2 x1 x0 value shifts s1 s0
saving of nearly 42% area and 38% area-delay product (ADP) 0 0 0 1 A 0 0 0
at the cost of 6% increase in computational delay for memory- 0 0 1 0 21 × A 1 0 1
based multiplication of 8-bit inputs with 16-bit coefficient. For 000 P0 A
0 1 0 0 22 × A 2 1 0
high-precision multiplication, a shift-save-accumulation scheme
is proposed to accumulate the LUT outputs corresponding to 1 0 0 0 23 × A 3 1 1
the segments of input-operand, which requires nearly 1.5 times 0011 3A 0 0 0
more area, but offers more than twice the throughput and nearly 001 P1 3A 0110 21 × 3A 1 0 1
two-third the ADP of direct shift-accumulation approach. 1100 22 × 3A 2 1 0
0101 5A 0 0 0
010 P2 5A
I. I NTRODUCTION 1010 21 × 5A 1 0 1
As the device scaling has progressed over the last four 011 P3 7A 0111 7A 0 0 0
decades, semiconductor memory has become cheaper, faster 1110 21 × 7A 1 0 1
and more power-efficient. According to the projections of the 100 P4 9A 1001 9A 0 0 0
international technology roadmap for semiconductors (ITRS) 101 P5 11A 1011 11A 0 0 0
[1], embedded memories will continue to have dominating 110 P6 13A 1101 13A 0 0 0
presence in the system-on-chip (SoC), which may exceed
111 P7 15A 1111 15A 0 0 0
90% of total SoC content. It has also been found that the
transistor packing density of SRAM is not only high but also s0 and s1 are control bits of the logarithmic barrel-shifter.
increasing much faster than the transistor density of logic
devices. Moreover, the memory-based structures are more reg- X be an input word to be multiplied with A. Assuming X
ular than the multiply-accumulate structures; and have many to be a positive binary number with word-length L, there can
other advantages, e.g., greater potential for high-throughput be 2L possible values of X, and accordingly, there can be
and reduced-latency implementation and less dynamic power 2L possible values of product C = A · X. Therefore, for
consumption (due to less switching activities for memory read memory-based multiplication, an LUT of 2L words consisting
operations compared to the conventional multipliers). of pre-computed product values corresponding to all possible
Memory-based structures are well-suited for many DSP values of X, is conventionally used. The product-word A · Xi
algorithms, which involve multiplication with fixed set of is stored at the location whose address is the same as Xi for
coefficients. Several architectures have been reported in the lit- 0 ≤ 2L − 1, such that if L-bit binary value of Xi is used
erature for memory-based implementation of DSP algorithms as address for the LUT, then the corresponding product value
involving orthogonal transforms and digital filters [2]–[5]. But, A · Xi is available as its output.
we do not find any work on efficient implementation of lool- Although 2L possible values of X correspond to 2L possible
up-table (LUT) for memory-based computation. In this paper, values of C = A · X, only (2L /2) words corresponding to the
we aim at presenting a design approach for reducing the LUT- odd multiples of A may only be stored in the LUT. One of
size for memory-based multiplication, which could be used the product word is zero while all the rest (2L /2) − 1 are even
efficiently for small input-widths. Besides, we show that the multiples of A which could be derived by left-shift operations
multiplications for large operand-width could be implemented of one of the odd multiples of A. We illustrate this in Table I
by input decomposition using shift-save-accumulation.
ADDRESS

OUTPUT

II. P ROPOSED LUT D ESIGN FOR C ONSTANT L MEMORY‐CORE (W+L)

PORT
PORT

X AX
M ULTIPLICATION (2L WORDS)

The principle of memory-based implementation of multi-

plication is shown in Fig.2. Let A be a fixed coefficient and Fig. 1. Conventional LUT-Based Multiplier.

978-1-4244-3828-0/09/$25.00 ©2009 IEEE 453

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 x0 w0
d0 w1
w2
x1
4‐TO‐3 BIT
d1 3‐TO‐8 w3
8 x (W+4)
x2 ADDRESS LINE w4
MEMORY ARRAY
ENCODER ADDRESS w5
DECODER
x3 d2 w6
w7
s0
CONTROL s1
CIRCUIT
RESET
(a)
Fig. 2. Proposed reduced-size LUT architecture for multiplication of W -bit fixed coefficient A with 4-bit input operand, X = x3 x2 x1 x0 . (a) The proposed
LUT-based multiplier. (b) The 4-to-3 bits input encoder. (c) Control circuit for generation of control-word for the two-stage logarithmic barrel-shifter.
for L = 4. At eight memory locations, eight odd multiples,
A × (2i + 1) are stored as Pi for i = 0, 1, 2, · · ·, 7. The even
multiples, 2A, 4A and 8A are derived by left-shift operations
of A. Similarly, 6A and 12A are derived by left-shifting 3A,
while 10A and 14A are derived by left-shifting 5A and 7A,
respectively. The address X = (0 0 0 0) corresponds to A ·
X = 0, which can be obtained by resetting the memory output.
For any value of word-size L similarly, only half of (2L /2)
odd multiple values need to be stored in the LUT, while the
other (2L /2−1) non-zero values could be derived by left-shift
operations of stored values. Based on the above, an LUT for
multiplication of an L-bit input with W -bit coefficient could
be designed by the following strategy:
L number of shifts required to be performed on the output of
• A memory-unit of (2 /2) words of (W + L)-bit width
is used to store the odd multiples of A.
• A barrel-shifter for producing a maximum of (L − 1)
left-shifts is used to derive all the even multiples of A.
• The L-bit input word is mapped to (L − 1)-bit address
of the LUT by an encoder.
• The control-bits for the barrel-shifter are derived by a
control-circuit to perform the necessary shifts of the LUT
output. Besides, a RESET signal is generated by the same
control circuit to reset the LUT output when the X = 0.
The proposed LUT design for L = 4 is shown in Fig.2.
It consists of a memory-array of eight words of (W + 4)-bit
width and a 3-to-8 line address decoder, along with an AND-
cell, a barrel-shifter, a 4-to-3 bit encoder, and a control circuit.
The 4-to-3 bit input encoder is shown in Fig.2(b). It receives
a four-bit input word (x3 x2 x1 x0 ) and maps that onto the
three-bit address word (d2 d1 d0 ), according to the relations:
d0 = (x0 · x1 ) · (x1 · x2 ) · (x0 + (x2 · x3 )
d1 = (x0 · x2 ) · (x0 + (x1 · x3 ))
d2 = x0 · x3
The pre-computed values of A × (2i + 1) are stored as Pi
for i = 0, 1, 2, · · ·, 7 at the 8 consecutive locations of the
memory-array as specified in Table I. The decoder takes the
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x3 x2 x1 x0 x3
x2
x1
d0
W+4
x0
AND CELL
s0
d1
s1
output, AX
(W+4)‐bit
SHIFTER
BARREL
RESET
d2
(b) (c)
3-bit address from the input encoder, and generates 8 word-
select signals, {wi , for 0 ≤ i ≤ 7}, to select the referenced-
word from the memory-array. The output of the memory-array
is either AX or a sub-multiple of AX depending on the value
of X. From Table I, we find that the LUT output is required to
be shifted through 1 location to left when the input operand X
is one of the values {(0 0 1 0), (0 1 1 0), (1 0 1 0), (1 1 1 0)}.
Two left-shifts are required if X is either (0 1 0 0) or (1 1 0 0).
Only when the input word X = (1 0 0 0), three shifts are
required. For all other possible input operands, no shifts are
required. Since the maximum number of left-shifts required on
the stored-word is three, a two-stage logarithmic barrel-shifter
is adequate to perform the necessary left-shift operations. The
the LUT and the control-bits s0 and s1 for different values of
X are shown Table I. The control circuit [shown in Fig.2(c)]
accordingly generates these control-bits given by
s0 = x0 + (x1 + x2 ) (2a)
s1 = (x0 + x1 ) (2b)
When the input operand word X = (0 0 0 0), the output
of the memory array is reset by the AND cell, consisting of
(W + 4) AND gates. The output bits of memory-array are fed
as one of the inputs of the AND gates in parallel, while the
RESET signal is fed as the other input of all the AND gates.
When RESET= 0, all the AND gates produce output value 0,
while for RESET= 1, the LUT output is passed unchanged to
the barrel-shifter. The reset could alternatively be implemented
by a NOR-cell consisting of (W +4) NOR gates, instead of the
AND gates, by using an active-high RESET, where the product
values Pi of i = 0, 1, ··, 7 are stored in complement form.
(1a) The control circuit, generates an active-low RESET under the
condition X = (0 0 0 0) according to the logic expression:
(1b)
RESET = (x0 + x1 ) · (x2 + x3 ) (3)
(1c)
Proposed LUT design can also be used by a dual-port
memory unit, where the input word-size could be doubled
without increasing the memory space. A dual-port memory-
based multiplier for 8-bit input is shown in Fig.3.
454
 OUTPUT UNIT

x03

x02

x01

x00
2S
RP/2

(2S/2) WORDS) AND SHIFT-ADDER

DUAL-PORT MEMORY UNIT OF
2S RP/2-1

INPUT LOADING UNIT

OUTPUT REGISTER ARRAY

4‐TO‐3 BIT
ENCODER
CONTROL
CIRCUIT
2S

T-BIT REGISTER
&

T-BIT ADDER
T T
2S
2S

RESET

d2

d1

d0
s1
s0
R2
R2
2S

DECODER
ADDRESS
W

PORT‐1

3‐TO‐8
2S

LINE
R1 R1

ACCUMULATOR
w7
w6
w5
w4
w3
w2
w1
w0
AND
CELL
SHIFTER‐1
BARREL

Fig. 4. Memory-based multiplier using shift-accumulation.

MEMORY ARRAY
SHIFT‐ADDER

DUAL‐PORT
8 x (W+4)

registers move across the input loading unit such that during
SHIFTER‐2
BARREL

each cycle the content of (i + 1)-th register is transferred to

Q

the i-th register in parallel. During each cycle, the first register
AND
w7
w6
w5
w4
w3
w2
w1
w0

CELL R1 feeds a segment of 2S-bit sub-word to the pair of ports of

the dual-port memory unit as address-bits.
DECODER
ADDRESS
PORT‐2

3‐TO‐8
LINE

2) The Memory Unit: It contains a dual-port memory array,

(W+8)‐bit output, AX

with a pair of S-bit ports, consisting of (2S /2) words (as

RESET

shown in Fig.3). It uses a shift-adder to left-shift the more

s1
s0

d2

d1

d0

significant LUT-output by S bit locations, and then to add

4‐TO‐3 BIT
ENCODER
CONTROL
CIRCUIT

that to the other LUT-output to produce an output of T =

&

(W + 2S)-bit size (W is the width of the fixed coefficient).

3) Shift-Accumulator-and-Output Unit: The shift-
x13

x12

x11

x10

accumulator, accumulates the successive LUT outputs

Fig. 3. LUT-based multiplier using dual-port memory-array. Q = (W + 4).
III. H IGH -P RECISION M EMORY-BASED M ULTIPLICATION
BY I NPUT-O PERAND D ECOMPOSITION
The LUT-based multiplier discussed in the section-II cannot
be used when the width of input X is large since the memory-
size increases exponentially with operand-width. Therefore,
when the width of input multiplicand X is large, let it be
decomposed into P/2 number of 2S-bit segments of sub-
words. Without loss of generality, we can assume L = P S,
since the input word can be zero-padded to make an even
multiple of S (S is assumed to be ≤ 4). We discuss here two
designs for pipelined memory-based multiplication by such
input decomposition. The first one is based on direct shift-
accumulation of successive memory outputs, while for the
other, we propose here a shift-save-accumulation approach.
A. Memory-Based Multiplier using Shift-Accumulator
The memory-based multiplier using shift-accumulator
(shown in Fig.4) consists of (i) an input loading unit, (ii) a
memory unit, and (iii) a shift-accumulate-and-output unit.
1) The Input Loading Unit: It consists of a set of P/2
parallel-in parallel-out array of registers of size 2S-bit each.
The 2S-bit segments of input X are loaded to the P/2 registers
in parallel, such that when the least significant segment is
loaded to register R1 , the successive registers are loaded with
the successively more significant segments. Content of the
whose numerical values successively increase by a factor of
22S . It consists of a T -bit adder followed by a T -bit delay
register. D flip flops of this register are reset for initialization,
and in each cycle thereafter loaded with the output of the
adder. During each cycle the adder receives a T -bit word
from the LUT and the most significant W bits from the delay
register as operands. The least significant 2S-bits of the delay
register are transferred to an array of (P/2 − 1) number of
2S-bit output registers. After P/2 cycles the output register
array holds the 2S(P/2 − 1) least significant bits of product
word, while the delay register contains the most significant
T -bits of product. The critical-path of this multiplier is
TA + TD , where TA and TD are T -bit addition-time and a D
flip-flop delay, respectively. The latency for multiplication of
two L-bit words is L(TA + TD )/2S.
B. Memory-Based Multiplier using Shift-Save-Accumulator
The memory-based multiplier using the proposed shift-save-
accumulator (SSA) is shown in Fig.5. It consists of five units:
(i) input loading unit, (ii) a memory unit, (iii) a pair of shift-
save-accumulators, (iv) a pair of shift-adders and (iv) an output
shift-adder. Input loading unit is similar to that shown in Fig.4
except that it has two arrays of S-bits registers, where the
upper-array loads the more significant half and lower array
loads the less significant half of X.
The memory unit is a dual-port memory of (2S /2) words
similar to that shown in Fig.3. The structure of shift-save-
accumulator for S = 2 and L = W = 8 (for accumulation
of four words) is shown in Fig.5(b). It is a modified form of

455
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 W+S CARRIES W+L/2

OUTPUT
LOADING
DUAL-PORT SHIFT-SAVE ACCUMULATOR SHIFT-ADDER-1
RP/2 S S
R2 S S

WORD
R1
INPUT

OUPUT
UNIT
SUMS 2L
MEMORY UNIT OF
RP/2 S S R2 S R1 S CARRIES W+L/2 SHIFT-ADDER
(2S/2) WORDS W+S SHIFT-SAVE ACCUMULATOR SHIFT-ADDER-2
SUMS
(a)
OUTPUT BI T S FR O M THE ROM
y9 y8 y7 y6 y5 y4 y3 y2 y1 y0 SHIFTED SUMS AN D CARRIES

H D A D A D A D A D A D A D A D H D H D H D H D H D H D

D D D D D D D D D D D D D D D D

(b)
Fig. 5. Memory-based multiplier using the proposed shift-save-accumulator. (a) The multiplier. (b) The shift-save-accumulator for S = 2 and W = L = 8.
A, H and D stand for a full-adder, half-adder and a D flip-flop, respectively.

carry-save-accumulator where the carries and the sums of the TABLE II

full-adders (A) and half-adders (H) are shifted, respectively,
by 1 and 2 locations towards right, such that all the input-bits
arriving at a full-adder or a half-adder are of the same weight.
The two MSBs do not need any adder since they do not receive
any sum or carry from any other locations. The input bit at
two locations right to the MSB is fed to a half-adder since
it is added with only one more bit. The rest 7 input bits are
fed to seven full-adders. Since the SSA is designed to add
four words it is required to shift the partial results three times
and therefore requires six more half-adders for the additions
of shifted-out sums and carries. It requires 30 D flip-flops to
store the 14 bits of carries and 16 bits of sums. After 4 shift-
accumulations, the SSAs produces two words: where one is
constituted by all the sums and the other by all the carries of
half-adders and full-adders. The pair of outputs of each SSAs
are shift-added by a 14-bit adder, where word of carries is
left-shifted by one location before being added with the word
of sums. The output of the pair of shift-adders are finally shift-
added where the less significant word is right-shifted by (L/2)
locations.
For multiplication of two L-bit words each of the SSAs, in
general, involves (L−1) full-adders, (L/2−S +1) half-adders
and (3L − S) D flip-flops to store the sums and carries. Each
of shift-adder-1 and 2 needs a (3L/2−S)-bit adder and output
shift-adder needs a (3L/2)-bit adder. The critical-path of SSA
is TM +TF A +TD , where TF A and TD are the worst-case prop-
agation delays of a full-adder and a D flip-flop respectively.
TM is the memory-read time. The minimum clock-period of
the multiplier is max{(L/2S)(TM + TF A + TD ), TA }, where
TA is (3L/2)-bit addition-time. Since the output-shift-adder
and shift-adders-1 and 2 work in two separate pipeline stages,
additional 3L latches are required before the output-shift-
adder. It has throughput of one multiplication per clock after
latency of 3 cycles.
IV. R ESULTS AND D ISCUSSION
The area of the dual-port memories and adders along with
their data arrival times are determined by using Synopsys
DesignWare 0.18 micron TSMC library [6]. The area and max-
imum propagation delays of MUXes and gates for unit drive-
strength are obtained from TSMC 0.l8µm process 1.8Volt
C OMPLEXITIES OF LUT-BASED M ULTIPLIERS FOR L = 8 AND W = 16.
LUT design area delay (ns) ADP
conventional design using dual-port memory 41303.2 5.16 213124.7
proposed design using dual-port memory 23975.7 5.48 131279.3
Area is in µm2 . Delay=multiplication-time=1 clock-period. ADP:area-delay product.
TABLE III
C OMPLEXITIES OF M ULTIPLIERS FOR L = W = 16 AND S = 4.
implementation scheme area delay (ns) ADP
shift-accumulation using proposed LUT 25741.3 10.04 258561.0
shift-save accumulation using proposed LUT 38026.5 4.66 177203.4
SAGE-XTM standard cell library data [7]. The area and delay
complexities of multipliers based on the proposed reduced-
LUT design and conventional design are accordingly estimated
(Table II), and found that the proposed design involves nearly
6% more delay, but offers a saving of nearly 42% in area and
38% in area-delay product (ADP) for L = 8 and W = 16. The
area and time complexities of the multipliers for L = W = 16
and S = 4 using the proposed SSA scheme and direct-shift-
accumulation are listed in Table III. The SSA scheme is found
to require ≈ 1.5 times more area, but offers more than twice
the throughput and nearly two-third the ADP of direct shift-
accumulation approach. The proposed LUT design is expected
to be useful for hardware implementation of DSP algorithms.
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