Professional Documents
Culture Documents
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REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 1 OF 63 Content & History RELEASE DATE : Alice Shih
A B C D E
A B C D E
CHARGE
CPU 55
CAP/RES RESET SM_BUS
TV CONN
21 CLOCK GEN.
Dothan .... 6 45 36
PIC16C54
478 uFCPGA
ICS954213 4,5 54
12
2 LVDS & HOST BUS BATLOW/SD# 2
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 2 OF 63 BLOCK DIAGRAM RELEASE DATE : Alice Shih
A B C D E
A B C D E
bom
REVISION Monday, January 17, 2005 SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: W3V
DATE: DESCRIPTION: <OrgName>
SHEET OF SYSTEM INFORMATION RELEASE DATE : M.Y.
2.1 3 63
A B C D E
5 4 3 2 1
H_D#[63:0] 7
U52B U52A
7 H_A#[16:3]
H_A#16 AA2 N2 H_D#15 C25 Y25 H_D#47
A[16]# ADS# H_ADS# 7 D[15]# D[47]#
H_A#15 Y3 A10 H_D#14 E23 AA26 H_D#46
A[15]# PRDY# H_BPM#4 6 D[14]# D[46]#
H_A#14 AA3 B10 H_D#13 B23 Y23 H_D#45
A[14]# PREQ# H_BPM#5 6 D[13]# D[45]#
H_A#13 U1 H_D#12 C26 V26 H_D#44
H_A#12 A[13]# H_D#11 D[12]# D[44]# H_D#43
Y1 A[12]# BNR# L1 H_BNR# 7 E24 D[11]# D[43]# U25
H_A#11 Y4 J3 H_D#10 D24 V24 H_D#42
A[11]# BPRI# H_BPRI# 7 D[10]# D[42]#
ADDRESS GROUP 0
DATA GROUP 0
H_A#10 H_D#9 H_D#41
2
W2 A[10]# B24 D[9]# D[41]# U26
H_A#9 T4 H_D#8 C20 AA23 H_D#40
A[9]# D[8]# D[40]#
DATA GROUP
H_A#8 W1 A7 H_D#7 B20 R23 H_D#39
A[8]# DBR# H_DBRESET# 6,22 D[7]# D[39]#
D H_A#7 V2 H_D#6 A21 R26 H_D#38 D
H_A#6 A[7]# H_D#5 D[6]# D[38]# H_D#37
R3 A[6]# B26 D[5]# D[37]# R24
H_A#5 V3 H_D#4 A24 V23 H_D#36
H_A#4 A[5]# H_D#3 D[4]# D[36]# H_D#35
U4 A[4]# DEFER# L4 H_DEFER# 7 B21 D[3]# D[35]# U23
H_A#3 P4 H2 H_D#2 A22 T25 H_D#34
A[3]# DRDY# H_DRDY# 7 D[2]# D[34]#
U3 M2 H_D#1 A25 AA24 H_D#33
7 H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# 7 D[1]# D[33]#
H_REQ#4 T1 H_D#0 A19 Y26 H_D#32
H_REQ#3 REQ[4]# D[0]# D[32]#
P1 REQ[3]# 7 H_DINV#0 D25 DINV[0]# DINV[2]# T24 H_DINV#2 7
H_REQ#2 T2 C23 W25
REQ[2]# 7 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 7
H_REQ#1 P3 C22 W24
REQ[1]# 7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7
H_REQ#0 R2 REQ[0]# H_D#31 H_D#63
7 H_REQ#[4:0] N4 H_BR0# 7 K25 AF26
CONTROL
BR0# +VCCP H_D#30 D[31]# D[63]# H_D#62
N25 D[30]# D[62]# AF22
H_D#29 H26 AF25 H_D#61
H_IERR# R738 2 D[29]# D[61]#
IERR# A4 1 56Ohm H_D#28 M25 D[28]# D[60]# AD21 H_D#60
H_D#27 N24 AE21 H_D#59
7 H_A#[31:17] D[27]# D[59]#
H_A#31 AF1 H_D#26 L26 AF20 H_D#58
A[31]# D[26]# D[58]#
3
DATA GROUP 1
H_A#30 AE1 B5 H_D#25 J25 AD24 H_D#57
A[30]# INIT# H_INIT# 22 +VCCP D[25]# D[57]#
H_A#29 H_D#24 H_D#56
DATA GROUP
AF3 A[29]# M23 D[24]# D[56]# AF23
H_A#28 AD6 H_D#23 J23 AE22 H_D#55
A[28]# D[23]# D[55]#
ADDRESS GROUP 1
H_A#27 AE2 J2 H_D#22 G24 AD23 H_D#54
A[27]# LOCK# H_LOCK# 7 D[22]# D[54]#
1
H_A#26 AD5 H_D#21 F25 AC25 H_D#53
H_A#25 A[26]# R748 H_D#20 D[21]# D[53]# H_D#52
AC6 A[25]# H24 D[20]# D[52]# AC22
H_A#24 AB4 54.9Ohm H_D#19 M26 AC20 H_D#51
H_A#23 A[24]# 1% H_D#18 D[19]# D[51]# H_D#50
AD2 A[23]# L23 D[18]# D[50]# AB24
H_A#22 AE4 /* H_D#17 G25 AC23 H_D#49
H_A#21 A[22]# H_D#16 D[17]# D[49]# H_D#48
2
AD3 A[21]# RESET# B11 H_CPURST# 6,7 H23 D[16]# D[48]# AB25
H_A#20 AC3 L2 H_RS#2 J26 AD20
A[20]# RS[2]# 7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7
H_A#19 AC7 K1 H_RS#1 K24 AE24
A[19]# RS[1]# 7 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 7
C H_A#18 AC4 H1 H_RS#0 L24 AE25 C
A[18]# RS[0]# 7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7
H_A#17 AF4 A[17]# H_RS#[2:0] 7
AE5 M3 SOCKET479P
7 H_ADSTB#1 ADSTB[1]# TRDY# H_TRDY# 7
1
C769 C770 C198 C201 C200 C202 C778 C768
2
U52C
12 CLK_CPU_BCLK B15 BCLK[0]
B14
HOSTCLK
22 H_IGNNE# A3 IGNNE#
Layout note:
22 H_DPSLP# B7 DPSLP# BPM[3]# C9 H_BPM#3 6 COMP0 and COMP2 need to be Zo=27.4ohm traces.
7,22 H_CPUSLP# A6 SLP# BPM[2]# A9 H_BPM#2 6
D1 B8 +VCCP Best estimate is 18mil wide trace for outer layers and
B 22 H_INTR LINT0 BPM[1]# H_BPM#1 6 B
22 H_NMI D4 LINT1 BPM[0]# C8 H_BPM#0 6 14mil if on internal layer. See RDDP of Banias.
22 H_SMI# B4 SMI# Traces should be shorter than 0.5". Refer to latest CS layout
1
22 H_STPCLK# C6 STPCLK# R791
H_PWRGD E4 AC1 1
22 H_PWRGD PWRGOOD GTLREF[3] COMP1, COMP3 should be routed as Zo=55ohm
G1 T126 1KOhm
49 VR_VID[5:0] GTLREF[2] H_DPRSTP# 22 traces shorter than 0.5"
VR_VID5 H4 E26 1
VR_VID4 VID[5] GTLREF[1] T326 GTLREF0
2
VR_VID2 F3
VR_VID1 VID[2] R790 H_COMP3 R190 54.9Ohm 1%
F2 VID[1] 2 1
VCCA layout: T/S: VR_VID0 E2 C5 R740 2 1 1KOhm /* H_COMP2 R189 2 1 27.4Ohm 1%
VID[0] TEST1 R781 2
100mil/25mil TEST2 F23 1 1KOhm /* 2KOhm H_COMP1 R786 2 1 54.9Ohm 1%
MISC
AC26 VCCA[3]
N1
120mA B1
VCCA[2]
A13
TDI 6
+1.8VS_PROC VCCA[1] TCK TCK 6
F26 VCCA[0] TDI C12 1 2 +VCCP
A12 R750 150Ohm 1%
TDO TDO 6 +VCCP +VCCP +VCCP
6 THERMDA B18 THERMDA TMS C11 TMS 6
6 THERMDC A18 THERMDC TRST# B13 1 2
C17 R753 680Ohm
6 H_THRMTRIP_S# THERMTRIP# TRST# 6
1
H_PROCHOT_S# B17 PROCHOT# VCCSENSE R745 R757 R737
VCCSENSE AE7 2 1
2 1 E1 R195 54.9Ohm 1%
49 PM_PSI# RSVD5
R192 0Ohm C16 /* Reserve for ITP 56Ohm 56Ohm 200Ohm
12,48 CPU_BSEL0 RSVD4
1 C3 /*
T124 RSVD3 => check
2
12 CPU_BSEL1 C14 RSVD2
1 AF7 H_BPM#5
A RSVD1 A
T312 1 B2 AF6 VSSSENSE 2 1 H_PROCHOT_S#
T125 RSVD0 VSSSENSE R194 54.9Ohm 1% H_PWRGD R736 2 1 1KOhm
A-STEP B-STEP SOCKET479P /* /*
H_PWRGD_ITP 6
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 4 OF 63 DOTHAN CPU(1) RELEASE DATE : M.Y.
5 4 3 2 1
5 4 3 2 1
+VCCP +VCORE
D D
AD25
AD22
AD19
AD17
AD15
AD13
AD11
AE26
AE23
AE20
AE18
AE16
AE14
AE12
AE10
AF24
AF21
AF19
AF17
AF15
AF13
AF11
U52D
AD9
AD7
AD4
AD1
AE8
AE6
AE3
AF9
AF5
AF2
VCC1 D6
W4 D8 U52E
VCCQ[1] VCC2
P23 D18 A2 AC24
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VCCQ[0] VCC3 VSS1 VSS160
VCC4 D20 A5 VSS2 VSS159 AC21
VCC5 D22 A8 VSS3 VSS158 AC18
VCC6 E5 A11 VSS4 VSS157 AC16
E7 A14 AC14
VCC7
VCC8 E9 A17
VSS5
VSS6
VSS156
VSS155 AC12 Mobile Dothan VID Table
D10 VCCP1 VCC9 E17 A20 VSS7 VSS154 AC10
D12 VCCP2 VCC10 E19 A23 VSS8 VSS153 AC8
D14 VCCP3 VCC11 E21 A26 VSS9 VSS152 AC5 VID[5..0] Voltage VID[5..0] Voltage
D16 VCCP4 VCC12 F6 B3 VSS10 VSS151 AC2
E11 VCCP5 VCC13 F8 B6 VSS11 VSS150 AB26
E13 VCCP6 VCC14 F18 B9 VSS12 VSS149 AB23
E15 VCCP7 VCC15 F20 B12 VSS13 VSS148 AB21 000000 1.708V 100000 1.196V
F10 VCCP8 VCC16 F22 B16 VSS14 VSS147 AB19
F12 VCCP9 VCC17 G5 B19 VSS15 VSS146 AB17 000001 1.692V 100001 1.180V
F14 VCCP10 VCC18 G21 B22 VSS16 VSS145 AB15 000010 1.676V 100010 1.164V
F16 VCCP11 VCC19 H6 B25 VSS17 VSS144 AB13
K6 VCCP12 VCC20 H22 C1 VSS18 VSS143 AB11 000011 1.660V 100011 1.148V
L5 J5 C4 AB9
000100 1.644V 100100 1.132V
L21
M6
M22
VCCP13
VCCP14
VCCP15
VCCP16
VCC VCC21
VCC22
VCC23
VCC24
J21
K22
U5
C7
C10
C13
VSS19
VSS20
VSS21
VSS22
VSS142
VSS141
VSS140
VSS139
AB7
AB5
AB3
000101 1.628V 100101 1.116V
N5 V6 C15 AA25 000110 1.612V 100110 1.100V
VCCP17 VCC25 VSS23 VSS138
N21 VCCP18 VCC26 V22 C18 VSS24 VSS137 AA22 000111 1.596V 100111 1.084V
P6 VCCP19 VCC27 W5 C21 VSS25 VSS136 AA20
C P22 VCCP20 VCC28 W21 C24 VSS26 VSS135 AA18 001000 1.580V 101000 1.068V C
R5 Y6 D2 AA16
001001 1.564V 101001 1.052V
R21
T6
T22
VCCP21
VCCP22
VCCP23
VCCP24
VCC29
VCC30
VCC31
VCC32
Y22
AA5
AA7
D5
D7
D9
VSS27
VSS28
VSS29
VSS30
GND VSS134
VSS133
VSS132
VSS131
AA14
AA12
AA10
001010 1.548V 101010 1.036V
U21 AA9 D11 AA8 001011 1.532V 101011 1.020V
VCCP25 VCC33 VSS31 VSS130
VCC34 AA11 D13 VSS32 VSS129 AA6 001100 1.516V 101100 1.004V
VCC35 AA13 D15 VSS33 VSS128 AA4
VCC36 AA15 D17 VSS34 VSS127 AA1 001101 1.500V 101101 0.988V
AA17 D19 Y24
VCC37
AA19 D21
VSS35 VSS126
Y21
001110 1.484V 101110 0.972V
VCC38 VSS36 VSS125
VCC39 AA21 D23 VSS37 VSS124 Y5 001111 1.468V 101111 0.956V
AB6 D26 Y2
VCC40
AB8 E3
VSS38 VSS123
W26 010000 1.452V 110000 0.940V
VCC41 VSS39 VSS122
VCC42 AB10 E6 VSS40 VSS121 W23 010001 1.436V 110001 0.924V
VCC43 AB12 E8 VSS41 VSS120 W22
VCC44 AB14 E10 VSS42 VSS119 W6 010010 1.420V 110010 0.908V
AB16 E12 W3
VCC45
AB18 E14
VSS43 VSS118
V25
010011 1.404V 110011 0.892V
VCC46 VSS44 VSS117
VCC47 AB20 E16 VSS45 VSS116 V21 010100 1.388V 110100 0.876V
AB22 E18 V5
VCC48
AC9 E20
VSS46 VSS115
V4 010101 1.372V 110101 0.860V
VCC49 VSS47 VSS114
VCC50 AC11 E22 VSS48 VSS113 V1 010110 1.356V 110110 0.844V
VCC51 AC13 E25 VSS49 VSS112 U24
VCC52 AC15 F1 VSS50 VSS111 U22 010111 1.340V 110111 0.828V
AC17 F4 U6
VCC53
AC19 F5
VSS51 VSS110
U2
011000 1.324V 111000 0.812V
VCC54 VSS52 VSS109
VCC55 AD8 F7 VSS53 VSS108 T26 011001 1.308V 111001 0.796V
AD10 F9 T23
B VCC56
AD12 F11
VSS54 VSS107
T21 011010 1.292V 111010 0.780V B
VCC57 VSS55 VSS106
VCC58 AD14 F13 VSS56 VSS105 T5 011011 1.276V 111011 0.764V
VCC59 AD16 F15 VSS57 VSS104 T3
AD18 F17 R25 011100 1.260V 111100 0.748V
AF18 VCC72
AF16 VCC71
AF14 VCC70
AF12 VCC69
AF10 VCC68
AF8 VCC67
AE19 VCC66
AE17 VCC65
AE15 VCC64
AE13 VCC63
AE11 VCC62
AE9 VCC61
M21
M24
G23
G26
H21
H25
N22
N23
N26
K21
K23
K26
L22
L25
J22
J24
M1
M4
M5
H3
H5
N3
N6
K2
K5
P2
P5
L3
L6
J1
J4
J6
SOCKET479P
A A
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 5 OF 63 DOTHAN CPU (2) RELEASE DATE : M.Y.
5 4 3 2 1
A B C D E
VCORE 10uF/10V * 35
CN28
220uF/2V *4
1 1 2 2
VCCP 0.1uF * 10 for CPU 4 H_BPM#5 3 4
3 4
150uF * 1 for CPU 4 H_BPM#4 5 5 6 6
7 8
0.1uF * 10 for Alviso 9
7 8
10
4 H_BPM#3 9 10
150uF * 2 for Alviso 4 H_BPM#2 11 11 12 12
4.7uF * 1 for Alviso 13 13 14 14
4 H_BPM#1 15 15 16 16
1
2.2uF * 1 for Alviso 17 18 ITP: Stuff 1
4 H_BPM#0 17 18 +VCCP
0.47uF * 2 for Alviso on A6 B2 G1 V1 19 19 20 20 No ITP: N/A
21 22
+VCORE 0.22uF * 2 for Alviso on A6 B2 G1 V1 23
21 22
24
23 24
Decoupling guide from INTEL 25 25 26 26
2
27A for 1.8G 27
29
27 28 28
30 R796 R798 R797
+VCCP 29 30
31 31 32 32
33 34 220Ohm 54.9Ohm 39.2Ohm
33 34
1
1
C231 C210 C211 C749 C748 C237 C756 C754 C753 C722 ITP: Stuff 35 36 /* 1% 1%
35 36
No ITP: N/A /*
1
37 37 38 38
10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 39 40
4 H_PWRGD_ITP 39 40 CLK_ITP_BCLK 12
2
2
1 2 41 41 42 42 CLK_ITP_BCLK# 12
R789 54.9Ohm 43 44
1% /* 43 44
45 45 46 46
47 47 48 48 H_DBRESET# 4,22
49 49 50 50
8 CTL_DATA 51 51 52 52 2 1 TDO 4
1
1
C228 53 54 R799 27.4Ohm
8 CTL_CLK 53 54 TRST# 4
C241 C242 C234 C230 C224 C746 C723 C728 C732 55 56 1% /*
55 56 TDI 4
10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 57 58
4 TCK 57 58 TMS 4
2
2
59 59 60 60
2
61 NP_NC1 2 1 H_CPURST# 4,7
2 R788 R821 R822 62 R800 22.6Ohm 2
NP_NC2 1% /*
2.2KOhm 2.2KOhm 27.4Ohm ITP_CON_60P 1 2
+2.5VS /* /* 1% /* R801 220Ohm
1
1
/*
1
ITP
C217 C218 C245 C229 C235 C221 C219 C215 C214 C227
10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V 10UF/10V Reserve for ITP
ITP: Stuff
2
2
Place resistance close ITP
No ITP: N/A
1
+ + + +
1
2
+3VS R212
200Ohm
1%
R1.1#16
2
1
3 3
2
R210
1
R240 R239 C239
100KOhm
1
Do Not Stuff Do Not Stuff U18 0.1UF
+VCCP NEAR CPU NEAR CPU /* /*
1
VCC
1
1
2.5A for 1.8G PIN W4 PIN P23
8 4
12,13,14,19,21,36 SCL_3S SMBCLK OVERT OS#_OC 47
1
1
CE29 C212 C216 C209 C208 C222 C244 C206 10/10/10 mil
19,22,25 PM_THRM# 6 ALERT# DXN 3 THERMDC 4
150U/4.0V 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
GND
2
1 2
MAX6657 C243 2200PF/10V
5
SM Bus Address fix at:
1
4 4
+VCCP H_THRMTRIP#_R
1
R772 +VCCP
CPU HFM LFM C3/C4
FREQ. VOLTAGE 1.6G 1.4G 1.2G 1G 0.6G 75Ohm
1
R775
2
1.8G 1.308V 1.292V 1.260V 1.228V 1.196V 0.844V 0.748V R769 1 2 0Ohm
4 H_THRMTRIP_S#
330Ohm R766 1 2 56Ohm H_THRMTRIP# 22
R767 1 2 0Ohm
8 GMCH_THRMTRIP#
2
1.7G /* C767 C920
2
1 2
R1.1#33 100PF
1 B
0.1UF /*
1
S 2
D
OTP_RESET# 47,53
3
2
E
3
Q132 Q134
G
1
5 PMBS3904 2N7002 5
8,21,22,23,28,30,31,32 BUF_PLT_RST#
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 6 OF 63 Caps & THERMAL & ITP RELEASE DATE : M.Y.
A B C D E
5 4 3 2 1
H_XRCOMP
2
24.9 R682
1% 24.9Ohm
1%
1
4 H_D#[0..63]
H_A#[3..31] 4
U48D
D H_D#0 E4 G9 H_A#3 D
H_D#1 HD0# HA3# H_A#4
E1 HD1# HA4# C9
H_D#2 F4 E9 H_A#5
H_D#3 HD2# HA5# H_A#6
H7 HD3# HA6# B7
+VCCP H_D#4 E2 A10 H_A#7
H_D#5 HD4# HA7# H_A#8
F1 HD5# HA8# F9
H_D#6 E3 D8 H_A#9
H_D#7 HD6# HA9# H_A#10
2 D3 HD7# HA10# B10
54.9 H_D#8 K7 E10 H_A#11
R675 H_D#9 HD8# HA11# H_A#12
1% F2 HD9# HA12# G10
54.9Ohm H_D#10 J7 D9 H_A#13
1% H_D#11 HD10# HA13# H_A#14
J8 HD11# HA14# E11
H_D#12 H6 F10 H_A#15
H_D#13 HD12# HA15# H_A#16
1
2
H_XSWING H_D#27 P7 A13 H_A#30
H_D#28 HD27# HA30# H_A#31 R125
L7 HD28# HA31# F13
2
C H_D#29 J3 100Ohm C
HD29#
1
1
U7 HD32# HADSTB1# E13 H_ADSTB#1 4
/* H_D#33 H_VREF
2
2
H_D#36 P3 E7 H_BR0#
HD36# HBREQ0# H_BR0# 4
1
H_D#37 T8 H10 H_CPURST# R124 C120
HD37# HCPURST# H_CPURST# 4,6
H_D#38 200Ohm
HOST
R7 HD38#
H_D#39 R8 1% 0.1UF
H_YRCOMP H_D#40 HD39#
2
U8 HD40#
H_D#41
1
R4 HD41# HCLKINN AB1 CLK_MCH_BCLK# 12
H_D#42 T4 AB2
HD42# HCLKINP CLK_MCH_BCLK 12
2
H_D#43 T5
24.9 1% R706 H_D#44 HD43#
R1 HD44# HDBSY# C6 H_DBSY# 4
24.9Ohm H_D#45 T3 E6
HD45# HDEFER# H_DINV#0 H_DEFER# 4
1% H_D#46 V8 H8
HD46# HDINV0# H_DINV#1 H_DINV#0 4
H_D#47 U6 K3
HD47# HDINV1# H_DINV#2 H_DINV#1 4
H_D#48
1
HPCREQ# A11 1
H_YSCOMP H_XRCOMP C1 A7 H_REQ#0
HXRCOMP HREQ0# H_REQ#0 4
H_XSCOMP C2 D7 H_REQ#1
HXSCOMP HREQ1# H_REQ#1 4
H_XSWING D1 B8 H_REQ#2
HXSWING HREQ2# H_REQ#2 4
H_YRCOMP T1 C7 H_REQ#3
HYRCOMP HREQ3# H_REQ#3 4
H_YSCOMP L1 A8 H_REQ#4
+VCCP HYSCOMP HREQ4# H_RS#0 H_REQ#4 4
H_YSWING P1 A4
HYSWING HRS0# H_RS#1 H_RS#0 4
HRS1# C5 H_RS#1 4
B4 H_RS#2
HRS2# H_RS#2 4
2
G8 R115 1 2 0Ohm
HCPUSLP# H_CPUSLP# 4,22
221 1% R705 B5 /*
HTRDY# H_TRDY# 4
221Ohm
1% ALVISO_BGA1257
1
H_YSWING
2
2
1
A A
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 7 OF 63 MCH: CPU RELEASE DATE : M.Y.
5 4 3 2 1
5 4 3 2 1
+2.5VS +1.5VS_PCIE
SDVO SMbus Int PD R1.1#4
U48F
MISC
1 2 SDVO_SMDATA H24 D36 1 2
SDVOCRTL_DATA Int PD SDVOCTRL_DATA EXP_COMPI
0: No SDVO device
R941 2.2KOhm T85 1 SDVO_SMCLK H25 SDVOCTRL_CLK EXP_ICOMPO D34 R680 24.9Ohm 1%
/* AB29
1: SDVO device present 12 CLK_MCH_3GPLL# GCLKN PEG_RXN[0..15] 16
AC29 E30 PEG_RXN0
12 CLK_MCH_3GPLL GCLKP EXP_RXN0
F34 PEG_RXN1
23 DMI_TXN[0..3] EXP_RXN1
U48A G30 PEG_RXN2
DMI_TXN0 TVDAC_A_GM EXP_RXN2
AA31 DMIRXN0 CFG0 G16 R119 2 1 1KOhm +2.5VS 21 TVDAC_A_GM A15 TVDAC_A EXP_RXN3 H34 PEG_RXN3
DMI_TXN1 AB35 H13 TVDAC_B_GM C16 J30 PEG_RXN4
DMIRXN1 CFG1 MCH_SEL1 12 21 TVDAC_B_GM TVDAC_C_GM TVDAC_B EXP_RXN4
DMI_TXN2 AC31 G14 A17 K34 PEG_RXN5
DMIRXN2 CFG2 MCH_SEL0 12 21 TVDAC_C_GM TVDAC_C EXP_RXN5
TV
DMI_TXN3 AD35 F16 CFG3 1 T63 TV_REFSET_GM J18 L30 PEG_RXN6
23 DMI_TXP[0..3] DMIRXN3 CFG3 CFG4 TVDAC_A_GM# TV_REFSET EXP_RXN6
D F15 1 T75 B15 M34 PEG_RXN7 D
DMI_TXP0 CFG4 CFG5 TVDAC_B_GM# TV_IRTNA EXP_RXN7 PEG_RXN8
Y31 DMIRXP0 CFG5 G15 CFG5 11 B16 TV_IRTNB EXP_RXN8 N30
DMI_TXP1 AA35 E16 CFG6 TVDAC_C_GM# B17 P34 PEG_RXN9
DMIRXP1 CFG6 CFG7 CFG6 11 TV_IRTNC EXP_RXN9
DMI_TXP2 AB31 D17 R30 PEG_RXN10
DMIRXP2 CFG7 CFG8 CFG7 11 EXP_RXN10
DMI_TXP3 AC35 J16 1 T80 T34 PEG_RXN11
23 DMI_RXN[0..3] DMIRXP3 CFG8 CFG9 EXP_RXN11
D15 U30 PEG_RXN12
CFG9 CFG10 CFG9 11 EXP_RXN12
DMI_RXN0 AA33 E15 1 T69 V34 PEG_RXN13
DMI_RXN1 DMITXN0 CFG10 CFG11 T42 EXP_RXN13 PEG_RXN14
DMI
AB37 DMITXN1 CFG11 D14 1 EXP_RXN14 W30
DMI_RXN2 AC33 E14 CFG12 1 T61 E24 Y34 PEG_RXN15
DMITXN2 CFG12 CFG13 21 DDC2BC_GM DDCCLK EXP_RXN15
DMI_RXN3 AD37 H12 1 T71 E23
23 DMI_RXP[0..3] DMITXN3 CFG13 21 DDC2BD_GM DDCDATA PEG_RXP[0..15] 16
VGA
C14 CFG14 1 T62 DAC_B_GM E21 D30 PEG_RXP0
CFG14 CFG15 21 DAC_B_GM DAC_B_GM# BLUE EXP_RXP0
DMI_RXP0 Y33 H15 1 T70 D21 E34 PEG_RXP1
DMI_RXP1 DMITXP0 CFG15 CFG16 DAC_G_GM BLUE# EXP_RXP1 PEG_RXP2
AA37 DMITXP1 CFG16 J15 CFG16 11 21 DAC_G_GM C20 GREEN EXP_RXP2 F30
CFG17 DAC_G_GM#
PCI-EXPRESS GRAPHICS
DMI_RXP2 AB33 H14 1 T83 B20 G34 PEG_RXP3
DMI_RXP3 DMITXP2 CFG17 CFG18 DAC_R_GM GREEN# EXP_RXP3 PEG_RXP4
AC37 DMITXP3 CFG18 G22 CFG18 11 21 DAC_R_GM A19 RED EXP_RXP4 H30
G23 CFG19 DAC_R_GM# B19 J34 PEG_RXP5
CFG19 CFG20 CFG19 11 VSYNC_GM RED# EXP_RXP5
AM33 D23 1 T57 H21 K30 PEG_RXP6
14 DCLK0 SM_CK0 CFG20 HSYNC_GM VSYNC EXP_RXP6
AL1 G25 1 T77 G21 L34 PEG_RXP7
14 DCLK1 SM_CK1 RSVD21 HSYNC EXP_RXP7
1 TP_SMCK2 AE11 SM_CK2 RSVD22 G24 1 T68 REFSET_GM J20 REFSET EXP_RXP8 M30 PEG_RXP8
T109 AJ34 J17 1 T87 N34 PEG_RXP9
13 DCLK3 SM_CK3 RSVD23 EXP_RXP9
AF6 A31 1 T268 P30 PEG_RXP10
13 DCLK4 SM_CK4 RSVD24 EXP_RXP10
1 TP_SMCK5 AC10 SM_CK5 RSVD25 A30 1 T267
EXP_RXP11 R34 PEG_RXP11
T99 D26 1 T76 T30 PEG_RXP12
RSVD26 T263 EXP_RXP12 PEG_RXP13
14 DCLK0# AN33 SM_CK0# RSVD27 D25 1 EXP_RXP13 U34
DDR MUXING
AK1 T262 1 E25 V30 PEG_RXP14
14 DCLK1# SM_CK1# LBKLT_CRTL EXP_RXP14
1 TP_SMCK#2 AE10 SM_CK2# 20 LCD_BACKEN_GM F25 LBKLT_EN EXP_RXP15 W34 PEG_RXP15
T106 AJ33 C23
13 DCLK3# SM_CK3# 6 CTL_CLK LCTLA_CLK
AF5 C22 E32 PEG_TXN0
13 DCLK4# SM_CK4# 6 CTL_DATA LCTLB_DATA EXP_TXN0
1 TP_SMCK#5 AD10 SM_CK5# 20 EDID_CLK_GM
EDID_CLK_GM F23 LDDC_CLK EXP_TXN1 F36 PEG_TXN1
C T105 EDID_DAT_GM F22 G32 PEG_TXN2 C
20 EDID_DAT_GM LDDC_DATA EXP_TXN2
AP21 F26 H36 PEG_TXN3
14,15 SCKE0 SM_CKE0 20 LCD_VDD_EN_GM L_IBG LVDD_EN EXP_TXN3
AM21 1 C33 J32 PEG_TXN4
14,15 SCKE1 SM_CKE1 LIBG EXP_TXN4
LVDS
AH21 J23 T47 1 L_LVBG C31 K36 PEG_TXN5
13,15 SCKE2 SM_CKE2 BM_BUSY# PM_BMBUSY# 22 LVBG EXP_TXN5
PM
AK21 J21 PM_EXTTS#0 T58 1 L_LVREFH F28 L32 PEG_TXN6
13,15 SCKE3 SM_CKE3 EXT_TS0# LVREFH EXP_TXN6
EXT_TS1# H22 PM_EXTTS#1 R1.1_No5 T78 1 L_LVREFL F27 LVREFL EXP_TXN7 M36 PEG_TXN7
AN16 F5 T65 N32 PEG_TXN8
14,15 SCS0# SM_CS0# THRMTRIP# GMCH_THRMTRIP# 6 EXP_TXN8
Layout Note: AM14 AD30 B30 P36 PEG_TXN9
14,15 SCS1# SM_CS1# PWROK VRM_PWRGD 12,45,48,49,54 20 LVDS_CLKAM_GM LACLKN EXP_TXN9
AH15 AE29 2 1 B29 R32 PEG_TXN10
Route as short as 13,15 SCS2# SM_CS2# RSTIN# R164 100Ohm
BUF_PLT_RST# 6,21,22,23,28,30,31,32
20 LVDS_CLKAP_GM LACLKP EXP_TXN10 PEG_TXN11
13,15 SCS3# AG16 SM_CS3# 20 LVDS_CLKBM_GM C25 LBCLKN EXP_TXN11 T36 Ext VGA: stuff
possible.
CLK
C118 0.1UF
R/G/B, R#/G#/B#, REFSET, VCCA_CRTDAC connect to GMCH Core. PEG_TXN7 1 PEG_G_RXN7
2
HSYNC/VSYNC/VCC_SYNC connect to GND. PEG_TXP7 C633 0.1UF 1 2 PEG_G_RXP7
C620 0.1UF
1
1 1 2
/* R648 1 2 0Ohm DREFCLK PEG_TXN10 1 2 PEG_G_RXN10
TVDAC_B_GM R650 1 2 0Ohm TVDAC_B_GM# DAC_G_GM R88 1 2 0Ohm DAC_G_GM# R670 1 2 0Ohm DREFSSCLK# PEG_TXP10C147 0.1UF 1 2 PEG_G_RXP10
/* R671 1 2 0Ohm DREFSSCLK C141 0.1UF
TVDAC_C_GM R649 1 2 0Ohm TVDAC_C_GM# DAC_R_GM R93 1 2 0Ohm DAC_R_GM# PEG_TXN11 1 2 PEG_G_RXN11
/* PEG_TXP11C656 0.1UF 1 2 PEG_G_RXP11
C653 0.1UF
PEG_TXN12 1 2 PEG_G_RXN12
R120 1 2 0Ohm REFSET_GM R101 1 2 0Ohm 1 2 PEG_TXP12C151 0.1UF 1 2 PEG_G_RXP12
+VCC_GMCH_CORE
Ext VGA: 0 ohm R99 0Ohm /* C149 0.1UF
Ext VGA: 0 ohm Ext VGA: 0 ohm Ext VGA: N/A PEG_TXN13 1 2 PEG_G_RXN13
Int VGA: 4.99K ohm_1% L_IBG PEG_TXP13C665
Int VGA: N/A Int VGA: 255 ohm_1% Int VGA: 0 ohm 1 2 0.1UF 1 2 PEG_G_RXP13
R81 1.5KOhm C657 0.1UF
TV_REFSET_GM R130 1 2 0Ohm 1% PEG_TXN14 1 2 PEG_G_RXN14
PEG_TXP14C157 0.1UF 1 2 PEG_G_RXP14
A A
R76 1 2 39Ohm /* VSYNC_GM 1 2 C153 0.1UF
16 DAC_VSYNC_GM PEG_TXN15 1 PEG_G_RXN15
R90 0Ohm 2
R77 1 2 39Ohm /* HSYNC_GM 1 2 +2.5VS PEG_TXP15C668 0.1UF 1 2 PEG_G_RXP15
16 DAC_HSYNC_GM
R91 0Ohm C666 0.1UF
Disable TV_OUT: 1 2 RN4A PM_EXTTS#0
10KOhm PM_EXTTS#1
Ext VGA: N/A Ext VGA: 0 ohm 3 4 RN4B
TVDAC A/B/C, TVIRTN A/B/C, TV_REFSET, VCCA_TV,DAC 10KOhm EDID_DAT_GM
5 6 RN4C
A/B/C... (ALL TV POWER) connect to GND. Int VGA: 39 ohm Int VGA: N/A 10KOhm
RN4D EDID_CLK_GM
7 10KOhm 8
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 8 OF 63 MCH: DDR2/DMI/PEG RELEASE DATE : M.Y.
5 4 3 2 1
5 4 3 2 1
D D
13 M_B_DQ[0..63]
14 M_A_DQ[0..63]
U48B U48C
M_A_DQ0 AG35 AK15 M_B_DQ0 AE31
SADQ0 SA_BS0# M_A_BS#0 14,15 SBDQ0
M_A_DQ1 AH35 AK16 M_B_DQ1 AE32 AJ15
SADQ1 SA_BS1# M_A_BS#1 14,15 SBDQ1 SB_BS0# M_B_BS#0 13,15
M_A_DQ2 AL35 AL21 M_B_DQ2 AG32 AG17
SADQ2 SA_BS2# M_A_BS#2 14,15 SBDQ2 SB_BS1# M_B_BS#1 13,15
M_A_DQ3 AL37 M_B_DQ3 AG36 AG21
SADQ3 M_A_DM[0..7] 14 SBDQ3 SB_BS2# M_B_BS#2 13,15
M_A_DQ4 AH36 AJ37 M_A_DM0 M_B_DQ4 AE34
SADQ4 SA_DM0 SBDQ4 M_B_DM[0..7] 13
M_A_DQ5 AJ35 AP35 M_A_DM1 M_B_DQ5 AE33 AF32 M_B_DM0
M_A_DQ6 AK37 SADQ5 SA_DM1 M_A_DM2 M_B_DQ6 AF31 SBDQ5 SB_DM0 M_B_DM1
SADQ6 SA_DM2 AL29 SBDQ6 SB_DM1 AK34
M_A_DQ7 AL34 AP24 M_A_DM3 M_B_DQ7 AF30 AK27 M_B_DM2
M_A_DQ8 AM36 SADQ7 SA_DM3 M_A_DM4 M_B_DQ8 AH33 SBDQ7 SB_DM2 M_B_DM3
SADQ8 SA_DM4 AP9 SBDQ8 SB_DM3 AK24
M_A_DQ9 AN35 AP4 M_A_DM5 M_B_DQ9 AH32 AJ10 M_B_DM4
M_A_DQ10 AP32 SADQ9 SA_DM5 M_A_DM6 M_B_DQ10 AK31 SBDQ9 SB_DM4 M_B_DM5
SADQ10 SA_DM6 AJ2 SBDQ10 SB_DM5 AK5
M_A_DQ11 AM31 AD3 M_A_DM7 M_B_DQ11 AG30 AE7 M_B_DM6
M_A_DQ12 AM34 SADQ11 SA_DM7 M_B_DQ12 AG34 SBDQ11 SB_DM6 M_B_DM7
SADQ12 M_A_DQS[0..7] 14 SBDQ12 SB_DM7 AB7
M_A_DQ13 AM35 AK36 M_A_DQS0 M_B_DQ13 AG33
SADQ13 SA_DQS0 SBDQ13 M_B_DQS[0..7] 13
1
M_A_DQ52 AL3 C189 M_B_DQ52 AH4
SADQ52 SBDQ52
1
M_A_DQ53 AM2 M_B_DQ53 AG6 C174
M_A_DQ54 AH3 SADQ53 10UF/10V M_B_DQ54 AE8 SBDQ53
M_A_DQ55 AG3 SADQ54 /* M_B_DQ55 AD7 SBDQ54 10UF/10V
2
M_A_DQ56 AF3 SADQ55 M_B_DQ56 AC5 SBDQ55 /*
2
M_A_DQ57 AE3 SADQ56 M_B_DQ57 AB8 SBDQ56
M_A_DQ58 AD6 SADQ57 M_B_DQ58 AB6 SBDQ57
M_A_DQ59 AC4 SADQ58 M_B_DQ59 AA8 SBDQ58
M_A_DQ60 AF2 SADQ59 M_B_DQ60 AC8 SBDQ59
M_A_DQ61 AF1 SADQ60 M_B_DQ61 AC7 SBDQ60
M_A_DQ62 AD4 SADQ61 M_B_DQ62 AA4 SBDQ61
M_A_DQ63 AD5 SADQ62 M_B_DQ63 AA5 SBDQ62
SADQ63 SBDQ63
ALVISO_BGA1257 ALVISO_BGA1257
A A
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 9 OF 63 MCH: DDR2 RELEASE DATE : M.Y.
5 4 3 2 1
A
B
C
D
bom
stuff
2 1 2 1
Int VGA:
+1.5VS
+1.5VS
1
1
L35
L101
C581
C559
Int VGA: N/A
0.1UF
0.1UF
Ext VGA: N/A
Ext VGA: stuff
+VCC_GMCH_CORE
+2.5VS
2
2
2 1 2 1
2
/* 1
C669
C618
1
1
0.1UF
0.1UF
L29
L32
C138
0.1UF
5
5
120Ohm/100Mhz
CAP4
+2.5VS
120Ohm/100Mhz
2 1 1 2 VTT51 G1
+VCCP
+
2 1 M1
+1.5VS
/*
/*
VTT50
VCCP_GMCH_CAP3
VCCP_GMCH_CAP2
VCCP_GMCH_CAP1
L102
N1
2
2
1
C82
VTT49
1.05V
V1
CE26
0Ohm
0Ohm
0.1UF
G37 VSSA_3GBG VTT48
+1.5VS_3GPLL
C163
B2
0.1UF
F37 VCCA_3GBG VTT47
M2 2 1
150U/4.0V
VTT46
+
2 1 2 1 N2 2 1
2
/*
+1.5VS_PCIE
C684
C158
C100
M4
0.1UF
VTT42
0.01UF
2 1 N4
150U/4.0V
10UF/10V
L37 VCC3G5 VTT40 M5 2 1 2 1
N37 VCC3G4 VTT39 N5
120Ohm/100Mhz
C687
R37 VCC3G3 VTT38 A6
PROJECT: W3V
C650
C101
2 1 M6
0.1UF
0.1UF
10UF/10V
W37 VCC3G1 VTT36 N6
AE37 VCC3G0 VTT35 M7 2 1
C708
N7
+1.5VS_DDRDLL
0.1UF
VTT34
2 1 AF18 VCCA_SM3 VTT33 M8
+
C639
CE9
10UF/10V
2.1
VTT29
N9
150U/4.0V
+2.5VS
VTT28
P9
REVISION
A27 VCCTX_LVDS2 VTT27
A28 VCCTX_LVDS1 VTT26 R9
2 1 B28 VCCTX_LVDS0 VTT25 U9
VTT24 W9
AE1 VCCSM64 VTT23 Y9
C107
J10
0.1UF
AM1 VCCSM63 VTT22
AP8 VCCSM62 VTT21 K10
Ext VGA: GND
4
4
N10
+1.5VS
/*
AB10 VCCSM60 VTT19
P10
DATE:
AB11 VCCSM59 VTT18
SHEET
C556
C143
R10
0.1UF
AC11VCCSM58 VTT17
+2.5VS
10UF/10V
2 1 AE12 VCCSM56 VTT15 U10 2 1
+
2 1 V10
V1.8_DDR_CAP3
V1.8_DDR_CAP4
V1.8_DDR_CAP6
AF12 VCCSM55 VTT14
W10
2
2
AG12VCCSM54 VTT13
R140
R126
C688
K11
CE27
0.1UF
AH12VCCSM53 VTT12
C555
L11
10
AJ12 VCCSM52 VTT11
2 1 M11
150U/4.0V
10UF/10V
shorted internally.
N11
R1.1#34
AL12 VCCSM50 VTT9
P11 2 1
1
1
AM12VCCSM49 VTT8
Note: All VCCSM pins
C699
R11
0Ohm
0.1UF
AN12VCCSM48 VTT7
OF
A25, B25, B26
AP12 VCCSM47 VTT6 T11
0Ohm /*
L100
C672
2 1 U11
1
0.1UF
63
Monday, January 17, 2005
2 1 AK13 VCCSM41 VTT0 K13
VCC_SYNC
AL13 VCCSM40
AM13VCCSM39 VCC_SYNC H20
VCCA_CRTDAC
C285
AN13VCCSM38
AP13 VCCSM37
10UF/10V
2 1 AE14 VCCSM36 VSSA_CRTDAC G19
120Ohm/100Mhz
2 1 2 1 E19
+2.5VS
AE15 VCCSM35 VCCA_CRTDAC1
AE16 VCCSM34 VCCA_CRTDAC0 F19
C557
0.1UF
AE17 VCCSM33
C776
C707
AA2
0.1UF
0.1UF
B23
+1.8V
DESCRIPTION:
AE22 VCCSM28 VCCH_MPLL0 AC1
CE8
3
3
C558
C694
shorted internally.
AC2 2 1 2 1
0.1UF
0.01UF
/*
AE24 VCCSM26
Note: All VCCSM pins
2 1 K17
150U/4.0V
T18
Ext VGA: N/A
AG25VCCSM23 VCC46
Int VGA: stuff
C702
V18
R1.1#34
150U/4.0V
150U/4.0V
0.1UF
AH25VCCSM22 VCC45
C675
K20
1
0.1UF
0.1UF
L99
AN25VCCSM17 VCC40
T20
POWER
1
L25
AG26VCCSM13 VCC36
K22
V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5
2
+2.5VS
AH26VCCSM12 VCC35
AJ26 VCCSM11 VCC34 K23
2 1 AK26 VCCSM10 VCC33 K24
MCH: POWER
AL26 VCCSM9 VCC32 J25
AM26VCCSM8 VCC31 K25
C71
10UF/10V
M27
0.1UF
AH37VCCSM1 VCC24
2 1 2 1 2 1 AM37VCCSM0 VCC23 N27 2 1
+
VCC22 P27
/*
R27
R1.1#34
0Ohm
0Ohm
0Ohm
/*
/*
/*
VCC18
2
2
G28 2 1
+1.5VS
C134
C156
H28 2 1
0.1UF
0.1UF
0.1UF
VCC16
J28
C678
0.1UF
VCCA_TVBG
VCCD_TVDAC
2 1 L28
+1.5VS_DPLLA
RELEASE DATE :
0.1UF
L16
/*
/*
VCC12 M28
VCCDQ_TVDAC
C133
C155
N28 2 1
1
1
L34
L37
VCCD_TVDAC
0.01UF
0.01UF
P28
C681
R28
2
VCC9
C119
T28
SCHEMATIC FILE NAME :
V28
2
2
/*
VCC6
E18 VCCA_TVDACC1 VCC5 J29 2 1
VCCA_TVDACC F18 K29
0Ohm /*
VCCA_TVDACC0 VCC4
C18 VCCA_TVDACB1 VCC3 M29
120Ohm/100Mhz
VCCA_TVDACB
C140
120Ohm/100MHz
F17 T29
+1.5VS
VCCA_TVDACA0 VCC0
+3VS
120Ohm/100MHz
2 1
+1.5VS
+1.5VS
1.05V
C154
U48G
0.1UF
2 1 2 1 2 1 2 1
3VS:
<OrgName>
1.8V:
R94
R64
R138
C113
0Ohm
0Ohm
0Ohm
0.1UF
2 1 2 1 2 1 2 1
Ext VGA: N/A
Int VGA: stuff
ALVISO_BGA1257
/*
/*
/*
C87
C68
C142
C144
0.1UF
0.1UF
0.1UF
0.1UF
120mA
2.5VS: 293mA
+VCC_GMCH_CORE
1.5VS: 1264mA
+2.5VS
2 1 2 1 2 1
2
/*
/*
/*
VCCA_TVDACB
VCCA_TVDACA
VCCA_TVDACC
1
1
1 23
C94
C67
C148
1
/*
0.01UF
0.01UF
0.01UF
1
1
1
L36
L26
L23
/*
1KOhm
+VCC_GMCH_CORE
M.Y.
BAT54C
/*
DESIGN ENGINEER :
2
2
2
/*
/*
+3VS
2
1 23
1
+1.5VS
/*
120Ohm/100MHz
R632
1KOhm
120Ohm/100MHz
120Ohm/100MHz
2.7A for DDR2 533 2 channel
1.3A for DDR2 533 1 channel
+3VS
BAT54C
A
B
C
D
A
B
C
D
bom
8
8
CFG7
CFG5
B36 VSSALVDS
VSS267 AL24
VSS266 AN24
Y1 VSS271 VSS265 A26
5
5
/*
/*
G2 VSS269 VSS263
J2 VSS268 VSS262 J26
R68
R67
L2 VSS260 VSS261 B27
2.2KOhm
2.2KOhm
G27
+1.8V
T2 VSS258 VSS128
V2 VSS257 VSS127 W27
AD2 VSS256 VSS126 AA27
+VCC_GMCH_CORE
AB27
PROJECT: W3V
VCCSM_NCTF26 AD13 AB3 VSS248 VSS118 W28
8
VCCSM_NCTF22 H4 VSS244 VSS114
AC16 D29
8
VCCSM_NCTF21 L4 VSS243 VSS113
VCCSM_NCTF20 AD16 P4 VSS242 VSS112 E29
VCCSM_NCTF19 AC17 U4 VSS241 VSS111 F29
AD17 G29
2.1
VCCSM_NCTF18 Y4 VSS240 VSS110
VCCSM_NCTF17 AC18 AF4 VSS239 VSS109 H29
AD18 L29
REVISION
VCCSM_NCTF16 AN4 VSS238 VSS108
AC19 P29
CFG18
VCCSM_NCTF15 E5 VSS237 VSS107
CFG9
VCCSM_NCTF14 AD19 W5 VSS236 VSS106 U29
VCCSM_NCTF13 AC20 AL5 VSS235 VSS105 V29
VCCSM_NCTF12 AD20 AP5 VSS234 VSS104 W29
L12 VTT_NCTF17 VCCSM_NCTF11 AC21 B6 VSS233 VSS103 AA29
M12 VTT_NCTF16 VCCSM_NCTF10 AD21 J6 VSS232 VSS102 AD29
N12 VTT_NCTF15 VCCSM_NCTF9 AC22 L6 VSS231 VSS101 AG29
4
4
DATE:
/*
VTT_NCTF13 VCCSM_NCTF7 T6 VSS229 VSS99
+2.5VS
SHEET
T12 AD23 C30
/*
VTT_NCTF12 VCCSM_NCTF6 AA6 VSS228 VSS98
R56
U12 VTT_NCTF11 VCCSM_NCTF5 AC24 AC6 VSS227 VSS97 Y30
R69
1KOhm
V12 VTT_NCTF10 VCCSM_NCTF4 AD24 AE6 VSS226 VSS96 AA30
W12 VTT_NCTF9 VCCSM_NCTF3 AC25 AJ6 VSS225 VSS95 AB30
2.2KOhm
L13 VTT_NCTF8 VCCSM_NCTF2 AD25 G7 VSS224 VSS94 AC30
M13 VTT_NCTF7 VCCSM_NCTF1 AC26 V7 VSS223 VSS93 AE30
N13 AD26 AP30
11
VTT_NCTF6 VCCSM_NCTF0 AA7 VSS222 VSS92
P13 VTT_NCTF5 AG7 VSS221 VSS91 D31
R13 VTT_NCTF4 VCC_NCTF78 L17 AK7 VSS220 VSS90 E31
HIGH = 1.5V
VTT_NCTF3 VCC_NCTF77 AN7 VSS219 VSS89
U13 VTT_NCTF2 VCC_NCTF76 N17 C8 VSS218 VSS88 G31
OF
V13 VTT_NCTF1 VCC_NCTF75 P17 E8 VSS217 VSS87 H31
W13 VTT_NCTF0 VCC_NCTF74 T17 L8 VSS216 VSS86 J31
VCC_NCTF73 U17 P8 VSS215 VSS85 K31
VCC_NCTF72 V17 Y8 VSS214 VSS84 L31
W17 M31
63
Monday, January 17, 2005
VCC_NCTF69 M18 H9 VSS211 VSS81 P31
DESCRIPTION:
W14 VSS_NCTF56 VCC_NCTF56 N20 F11 VSS198 VSS68 AB32
3
3
NCTF
resistors.
AA14 VSS_NCTF54 VCC_NCTF54 Y11 VSS196 VSS66
AB14 VSS_NCTF53 VCC_NCTF53 Y20 AA11 VSS195 VSS65 AJ32
L15 VSS_NCTF52 VCC_NCTF52 L21 AF11 VSS194 VSS64 AN32
M21 D33
CFG16
T22 T33
SDVOCRTL_DATA :
W22 W33
SDVOCRTL_DATA has internal pulldown
R16 VSS_NCTF36 VCC_NCTF36 AN14VSS178 VSS48
CFG[17..3] have internal pullup resistors.
CFG16: FSB DYNAMIC ODT
MCH: GND/NCTF/Strap
AB16 VSS_NCTF29 VCC_NCTF29 U23 AL16 VSS171 VSS41 AC34
R17 VSS_NCTF28 VCC_NCTF28 V23 C17 VSS170 VSS40 AD34
Y17 VSS_NCTF27 VCC_NCTF27 W23 G17 VSS169 VSS39 AH34
AA17 VSS_NCTF26 VCC_NCTF26 L24 AF17 VSS168 VSS38 AN34
AB17 VSS_NCTF25 VCC_NCTF25 M24 AJ17 VSS167 VSS37 B35
LOW = Dynamic ODT Disabled
R25 R35
SCHEMATIC FILE NAME :
CFG19
V37
HIGH = DDR SDRAM (Default)
Y37
LOW = 1.05V (Default)
AG24VSS131 VSS1
AJ24 VSS130 VSS0 AG37
U48H
M.Y.
DESIGN ENGINEER :
ALVISO_BGA1257
A
B
C
D
5 4 3 2 1
1
C264 C265 C287 C290 C277 C313 C293 C288 C306 L51 120Ohm/100Mhz CLK_MCH_BCLK R254 1 2 49.9Ohm
1%
0.1UF 0.1UF 0.1UF 10UF/10V 0.47U 0.1UF 0.1UF 0.1UF 0.1UF +3.3VS_CLKVDD CLK_MCH_BCLK# R255 1 2 49.9Ohm
1%
2
1
+3.3VS_CLK48 C308 C311
2
ITP: Stuff CLK_ITP_BCLK R258 1 2 49.9Ohm
1
R361 C312 0.1UF 0.1UF No ITP: N/A 1% /*
2
+3VS_CLK U24 CLK_ITP_BCLK# R259 2 49.9Ohm
2
1
2.2OHM 0.1UF 1% /*
VDDPCI0
D
VDDPCI
D
1
C296 C294 R252
2
1Ohm CLK_PCIE_PEG R260 2 49.9Ohm
1
1
10UF/10V 0.1UF 13 1%
VDD48 CLK_PCIE_PEG# R261 2 49.9Ohm
1
22 VDDSRC1 1
29 1%
VDDSRC2 VDD_REF_CR
33 VDDSRC3 VDDREF 48 1 2
R303 C286 0.1UF CLK_PCIE_SATA R337 1 2 49.9Ohm
2.2OHM 1%
X3 14.318Mhz 2 1 42 18 S_PCI# R335 1 2 0Ohm CLK_PCIE_SATA# R336 1 2 49.9Ohm
+3.3VS_CLKVDD 1 2 VDDCPU PCI_SRC_STOP# S_CPU# STP_PCI# 22
10 R309 1 2 0Ohm 1%
CPU_STOP# STP_CPU# 22,49
+3VS_CLKA 37 VDDA
1
C309 C310 41 CPU1 R271 1 2 33Ohm CLK_MCH_3GPLL R349 1 2 49.9Ohm
CPUCLKT1 CLK_CPU_BCLK 4
2
38 40 CPU1# R272 1 2 33Ohm 1%
GNDA CPUCLKC1 CLK_CPU_BCLK# 4
R360 47pF/50V 47pF/50V CLK_MCH_3GPLL#R350 1 2 49.9Ohm
10KOhm CPU0 R269 2 33Ohm 1%
2
CPUCLKT0 44 1 CLK_MCH_BCLK 7
1% XIN_CLKGEN 50 43 CPU0# R270 1 2 33Ohm
X1 CPUCLKC0 CLK_MCH_BCLK# 7
CLK_PCIE_ICH R347 1 2 49.9Ohm
XOUT_CLKGEN 1%
1
49 X2
35 CPU2 R273 1 2 33Ohm/* CLK_ITP_BCLK 6 ITP: Stuff CLK_PCIE_ICH# R348 1 2 49.9Ohm
27VGA CPUCLKT2_ITP/SRCCLKT5 CPU2#
16,17 CLK_VGA27
R318 1 2 33Ohm 17 27MHZ CPUCLKC2_ITP/SRCCLKC5 34 R274 1 2 33Ohm/* CLK_ITP_BCLK# 6 No ITP: N/A 1%
2
R315 1 2 33Ohm 33PCIF1 9 T332
31 CLK_FWHPCI PCICLK_F1 R374
R314 1 2 33Ohm 8 36 DOC_2 R256 1 2 0Ohm /* 10KOhm
23 CLK_ICHPCI ITP_EN/PCICLK_F0 DOC_2 DOC_1 OVER_CLK2 30
19 R346 1 2 0Ohm /* 1%
DOC_1 OVER_CLK1 30
R1.1#38 46 SCLK CLK_EN_ICS#
1
+3.3VS_CLKVDD 47 SDATA
C321
C320
C317
C316
C300
C278
C279
C280
C281
C319
C318
Q50
R362 2 16 CLK_EN_ICS# 1 2 1 2N7002
GND1 VTT_PWRGD#/PD 8,45,48,49,54 VRM_PWRGD
2
5PF
5PF
5PF
5PF
5PF
5PF
5PF
5PF
5PF
5PF
5PF
1
1% R292 C893
1
12 GND3
/* /* /* /* /* /* /* /* /* /* 475Ohm 30 52 CLK_BSEL1 R291 1 2 33Ohm
GND4 REF1/FSLB CLK_BSEL0 CLK_ICH14 22
1% R297 2 33Ohm 0.47U
1
2
51 GND6
10K PU +3VS: R296 2 15Ohm 1% CLK_14
1
1
pin 34/35 as ICS954213 /*
+VCCP
Install when use
C297
C304
C305
ITP CLK
10K PD GND: R297: Ext VGA: 33 OHM For EMI Dothan B-Step CPU
2
SDA_3S
pin 34/35 as SCL_3S
SDA_3S 6,13,14,19,21,36 Int VGA: 15 OHM
SCL_3S 6,13,14,19,21,36
1
1
1
B
R2.0#8
B
5PF
5PF
5PF
SRC CLK
R917 R919 R930
1
/* /* /*
100KOhm 100KOhm 330Ohm
2
2
2
1 2
C877 0.01UF
B STEP Q169
1 B
+3VS PMBS3904
Ext VGA: N/A Ext VGA: N/A
+3VS_GM_SS CPUSEL0 1 2 CLK_BSEL0
CPU_BSEL0 CPU_BSEL1 HOST CLOCK Int VGA: N/A in default Int VGA: stuff 1 2 4,48 CPU_BSEL0
C
L54 120Ohm/100MHz R920 1KOhm
2
E
3
1
1
0 0 133 C291 C292 C295 /*
1 B
Q168
1 0 100 +3VS +3VS +3VS 0.1UF 0.1UF 10UF/10V PMBS3904
U25 /* /* /* CPUSEL1 1 2 CLK_BSEL1
2
4 CPU_BSEL1
C
CLK_14 R933 1KOhm
2
E
3
1 16
CLKIN VDDA R1.1#12
2
VDD 9
R338 R339 R340 SSC_S3
ICS 954213 FREQUENCY TABLE 10KOhm 10KOhm 10KOhm SSC_S2
2
3
S3 +3.3VS_CLKVDD +VCCP
/* /* /* SSC_S1 S2 DREFSSCK_D R283 1
CPU SRC PCI REF USB DOT 4 S1 CLKOUT 12 2 33Ohm /*
DREFSSCLK 8
FS_C FS_B FS_A 11 DREFSSCK#_D R284 1 2 33Ohm /*
MHz MHz MHz MHz MHz MHz SSC_S1 CLKOUT# DREFSSCLK# 8
SCL_3S R294 1 2 0Ohm /*
1
7 SCLK
1
SSC_S2 SDA_3S R300 1 2 0Ohm /* 8 14 IREF_R1
SSC_S3 SDATA IREF R249 R265 R250 R289
V 0 0 0 266 100 33.33 14.318 48.00 96.00 R1.1#5 CLK_EN_ICS# VSSIREF 13
5 PWRDWN VSS 10
2
0 0 1 133 100 33.33 14.318 48.00 96.00 +3VS_GM_SS 2 1 6 REF/SEL VSSA 15 1KOhm 1KOhm 47KOhm 1KOhm 1 2 MCH_SEL1 8
R310 R311 R312 R313 10KOhm /* /* /* /* R266 1KOhm
0 1 0 200 100 33.33 14.318 48.00 96.00
1
2
A A
0 1 1 166 100 33.33 14.318 48.00 96.00 /* /* /* R285 R282 CLK_BSEL1
0Ohm 475Ohm CLK_BSEL0
1 0 0 333 100 33.33 14.318 48.00 96.00 /* /*
1
1
1 0 1 100 100 33.33 14.318 48.00 96.00 1% 1 2 MCH_SEL0 8
R251 R286 R267 1KOhm
2
2
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 12 OF 63 CLOCK GEN (ICS954213) RELEASE DATE : M.Y.
5 4 3 2 1
5 4 3 2 1
DCLK3 M_B_DQ[0..63] 9
9,15 M_B_A[0..13]
D D
2
C747 U16A
PLACE NEAR SO-DIMM_0 M_B_A0 102 5 M_B_DQ0
10PF M_B_A1 A0 DQ0 M_B_DQ1
101 A1 DQ1 7
M_B_A2 M_B_DQ2
1
100 A2 DQ2 17
DCLK3# M_B_A3 99 19 M_B_DQ3 +1.8V
M_B_A4 A3 DQ3 M_B_DQ4
98 A4 DQ4 4
M_B_A5 97 6 M_B_DQ5
M_B_A6 A5 DQ5 M_B_DQ6
94 A6 DQ6 14
DCLK4 M_B_A7 92 16 M_B_DQ7 U16B
M_B_A8 A7 DQ7 M_B_DQ8
93 A8 DQ8 23 112 VDD1 VSS16 18
M_B_A9 91 25 M_B_DQ9 111 24
A9 DQ9 VDD2 VSS17
2
1
32 58 M_B_DQ23 C254 83 171
8 DCLK3# CK0# DQ23 NC1 VSS31
164 61 M_B_DQ24 120 172
8 DCLK4 CK1 DQ24 NC2 VSS32
166 63 M_B_DQ25 0.1UF 50 177
8 DCLK4# CK1# DQ25 NC3 VSS33
C M_B_DQ26 C
2
8,15 SCKE2 79 CKE0 DQ26 73 69 NC4 VSS34 187
80 75 M_B_DQ27 VTT_REF 163 178
8,15 SCKE3 CKE1 DQ27 NCTEST VSS35
+3VS 113 62 M_B_DQ28 190
9,15 M_B_CAS# CAS# DQ28 VSS36
108 64 M_B_DQ29 1 9
9,15 M_B_RAS# RAS# DQ29 VREF VSS37
109 74 M_B_DQ30 21
9,15 M_B_WE# WE# DQ30 VSS38
1
198 76 M_B_DQ31 C258 C253 201 33
SA0 DQ31 M_B_DQ32 GND0 VSS39
2 1 200 SA1 DQ32 123 202 GND1 VSS40 155
R204 10KOhm 197 125 M_B_DQ33 2.2uF/6.3V 0.1UF 34
6,12,14,19,21,36 SCL_3S SCL DQ33 M_B_DQ34 VSS41
2
6,12,14,19,21,36 SDA_3S 195 SDA DQ34 135 203 NP_NC1 VSS42 132
137 M_B_DQ35 204 144
DQ35 NP_NC2 VSS43
2
1
C261
R247
0.1UF
10KOhm
2
Layout Note: Place these High-Freq decoupling Caps near the GMCH Layout Note: Place these Caps near SO DIMM 0 Layout Note: Place these Caps near SO DIMM 0 1%
VTT_REF T108
5
1 V+
+1.8V +1.8V +1.8V +
1
4
1
1 2 3 -
1
1
C706 C709 C713 C710 C774 C777 C252 C255 C744 C752 C259 C743 C731 C266 R248 R1011 0Ohm V- U20
1
/* LMV321 C267
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 1UF/10V 1UF/10V 1UF/10V 1UF/10V 1UF/10V 0.01UF 10KOhm
2
1% 1UF/10V
2
2
A A
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 13 OF 63 DDR2 SO-DIMM (1) RELEASE DATE : M.Y.
5 4 3 2 1
5 4 3 2 1
D D
U53A
M_A_A0 102 5 M_A_DQ0
A0 DQ0
2
M_A_A4 M_A_DQ4
1
98 A4 DQ4 4
DCLK0# M_A_A5 97 6 M_A_DQ5
M_A_A6 A5 DQ5 M_A_DQ6 +1.8V
94 A6 DQ6 14
M_A_A7 92 16 M_A_DQ7 U53B
M_A_A8 A7 DQ7 M_A_DQ8
93 A8 DQ8 23 112 VDD1 VSS16 18
DCLK1 M_A_A9 91 25 M_A_DQ9 111 24
A9 DQ9 VDD2 VSS17
C260
M_A_A12 89 20 M_A_DQ12 95 42
PLACE NEAR SO-DIMM_1 M_A_A13 A12 DQ12 M_A_DQ13 VDD5 VSS20
116 A13 DQ13 22 118 VDD6 VSS21 54
86 36 M_A_DQ14 81 59
A14 DQ14 VDD7 VSS22
10PF
M_A_DQ15
1
1
164 61 M_A_DQ24 C764 120 172
8 DCLK1 CK1 DQ24 NC2 VSS32
C 166 63 M_A_DQ25 50 177 C
8 DCLK1# CK1# DQ25 NC3 VSS33
79 73 M_A_DQ26 0.1UF 69 187
8,15 SCKE0 CKE0 DQ26 VTT_REF NC4 VSS34
M_A_DQ27
2
8,15 SCKE1 80 CKE1 DQ27 75 163 NCTEST VSS35 178
113 62 M_A_DQ28 190
9,15 M_A_CAS# CAS# DQ28 VSS36
108 64 M_A_DQ29 1 9
9,15 M_A_RAS# RAS# DQ29 VREF VSS37
109 74 M_A_DQ30 21
9,15 M_A_WE# WE# DQ30 VSS38
198 76 M_A_DQ31 201 33
SA0 DQ31 GND0 VSS39
1
200 123 M_A_DQ32 C765 202 155
SA1 DQ32 GND1 VSS40
1
2
DQ35 137 204 NP_NC2 VSS43 144
10KOhm 10KOhm 114 124 M_A_DQ36 156
8,15 ODT0 ODT0 DQ36 VSS44
119 126 M_A_DQ37 47 168
8,15 ODT1 ODT1 DQ37 VSS1 VSS45
M_A_DQ38
2
Layout Note: Place these Caps near SO DIMM 1 Layout Note: Place these Caps near SO DIMM 1
+1.8V +1.8V
1
1
C763 C762 C771 C283 C263 C760 C761 C257 C779
2
A A
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 14 OF 63 DDR2 SO-DIMM (2) RELEASE DATE : M.Y.
5 4 3 2 1
5 4 3 2 1
+0.9VS
D D
R758 1 2 56Ohm SCKE0
R803 1 2 56Ohm SCKE1
R231 1 2 56Ohm SCKE2
R751 1 2 56Ohm SCKE3
M_B_BS#[0..2] 9,13
R246 1 2 56Ohm M_A_CAS# 9,14
R245 1 2 56Ohm
SCKE[0:3] 8,13,14 M_A_RAS# 9,14
R763 1 2 56Ohm M_A_WE# 9,14
ODT[0:3] 8,13,14
R234 1 2 56Ohm M_B_BS#0
R741 1 2 56Ohm M_B_BS#1
R232 1 2 56Ohm M_B_BS#2
C C
R805 1 2 56Ohm
SCS0# 8,14
R761 1 2 56Ohm
SCS1# 8,14
R743 1 2 56Ohm
SCS2# 8,13
R237 1 2 56Ohm
SCS3# 8,13
+0.9VS
1 16 RN12A M_A_A12
56Ohm M_A_A11
2 15 RN12B
56Ohm
3 14 RN12C M_A_A8
56Ohm M_A_A7
4 13 RN12D
56Ohm
1
1
C736 C737 C757 C742 C741 C271 C780 C269 C268 C276 C275 C272 C262 5 12 RN12E M_A_A9
56Ohm
6 11 RN12F M_A_A6
56Ohm
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 7 10 RN12G M_A_A5
56Ohm
RN12H M_A_A1
2
2
8 56Ohm 9
1 16 RN13A M_A_A4
56Ohm M_A_A0
2 15 RN13B
56Ohm M_A_A2
3 14 RN13C
56Ohm
4 13 RN13D M_A_A3
B 56Ohm B
RN13E M_A_A10
Layout note: Place one cap close to every 2 pullup resistors terminated to +0.9VS 5
6
56Ohm 12
11 RN13F M_A_A13
56Ohm
7 10 RN13G
+0.9VS 56Ohm
8 9 RN13H
56Ohm
1 16 RN27A M_B_A8
56Ohm
2 15 RN27B M_B_A12
56Ohm
1
1
C735 C738 C726 C758 C759 C725 C775 C274 C724 C740 C739 C273 C270 3 14 RN27C M_B_A9
56Ohm
4 13 RN27D M_B_A5
56Ohm M_B_A7
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 5 12 RN27E
56Ohm M_B_A6
RN27F
2
6 56Ohm 11
7 10 RN27G M_B_A4
56Ohm M_B_A1
8 9 RN27H
56Ohm
1 16 RN28A M_B_A3
56Ohm
2 15 RN28B M_B_A0
56Ohm
3 14 RN28C M_B_A2
56Ohm M_B_A10
4 13 RN28D
56Ohm M_B_A13
5 12 RN28E
56Ohm M_B_A11
6 11 RN28F
56Ohm
7 10 RN28G
56Ohm
8 9 RN28H
56Ohm
A A
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 15 OF 63 DDR2 Res RELEASE DATE : M.Y.
5 4 3 2 1
5 4 3 2 1
8 PEG_G_RXP[0..15]
U6A
8 PEG_G_RXN[0..15]
PEG_G_RXP0 AH30 AJ5 ATI_GPIO0 +3VS
PCIE_RX0P GPIO_0 ATI_GPIO0 19
PEG_G_RXN0 AG30 Part 1 of 6 AH5 ATI_GPIO1
PCIE_RX0N GPIO_1 ATI_GPIO1 19
PEG_G_RXP1 AG29 AJ4 ATI_GPIO2
PCIE_RX1P GPIO_2 ATI_GPIO2 19
2
PEG_G_RXN1 AF29 AK4 ATI_GPIO3
PCIE_RX1N GPIO_3 ATI_GPIO3 19
PEG_G_RXP2 AE29 AH4 ATI_GPIO4 R16
PCIE_RX2P GPIO_4 ATI_GPIO4 19
PEG_G_RXN2 AE30 AF4 ATI_GPIO5 10KOhm
PCIE_RX2N GPIO_5 ATI_GPIO5 19
PEG_G_RXP3 AD30 AJ3 ATI_GPIO6 /*
PCIE_RX3P GPIO_6 ATI_GPIO6 19
PEG_G_RXN3 AD29 AK3 1 2
PCIE_RX3N GPIO_7 ATI_GPIO8 PWR_OK_VGA 52,54
PEG_G_RXP4 R23 0Ohm
1
AC29 PCIE_RX4P GPIO_8 AH3 ATI_GPIO8 19
PEG_G_RXN4 AB29 AJ2 ATI_GPIO9 3 Q5
PCIE_RX4N GPIO_9 ATI_GPIO10 ATI_GPIO9 19 D
PEG_G_RXP5 AB30 AH2 1 T7 2N7002
PEG_G_RXN5 PCIE_RX5P GPIO_10 ATI_GPIO11 GPIO_AUX /*
AA30 PCIE_RX5N GPIO_11 AH1 ATI_GPIO11 19 1 2
PEG_G_RXP6 AA29 AG3 ATI_GPIO12 R17 0Ohm 1
D PCIE_RX6P GPIO_12 ATI_GPIO12 19 M24_THRM# 19 D
PEG_G_RXN6 Y29 AG1 ATI_GPIO13 G
8 PEG_RXP[0..15] PCIE_RX6N GPIO_13 ATI_GPIO13 19 S 2
PEG_G_RXP7 W29 AG2 1 2
PEG_G_RXN7 PCIE_RX7P GPIO_14 R15 0Ohm /*
PCI EXPRESS
PEG_RXN6 C625 0.1UF 1 PEG_G_TXP1 PCIE_TX0N DVPDATA_15
2 PEG_G_TXN6 AC25 PCIE_TX1P DVPDATA_16 AF7 1 T250 (Reserved)
C626 0.1UF PEG_G_TXN1 AB25 AE8 1 T248
PEG_RXP7 PEG_G_TXP7 PEG_G_TXP2 PCIE_TX1N DVPDATA_17 LCDDATA18 R602 1
1 2 AC27 PCIE_TX2P DVPDATA_18 AG8 2 0Ohm /* EDID_DAT_ATI 20
PEG_RXN7 C600 0.1UF 1 2 PEG_G_TXN7 PEG_G_TXN2 AB27 AF8 LCDDATA19 R614 1 2 0Ohm /*
PEG_G_TXP3 PCIE_TX2N DVPDATA_19 EDID_CLK_ATI 20
C601 0.1UF AC26 AE9 R613 1 2 8.2KOhm
PEG_G_TXN3 PCIE_TX3P DVPDATA_20 +3VS
PEG_RXP8 1 2 PEG_G_TXP8 AB26 AF9 1 T249
PEG_RXN8 C644 0.1UF 1 PEG_G_TXP4 PCIE_TX3N DVPDATA_21
2 PEG_G_TXN8 Y25 PCIE_TX4P DVPDATA_22 AG10 1 T51 M22/24: High - no slave VIP host
C C645 0.1UF PEG_G_TXN4 W25 AF10 1 T256 C
PEG_RXP9 PEG_G_TXP9 PEG_G_TXP5 PCIE_TX4N DVPDATA_23 M26: no stuff
1 2 Y27 PCIE_TX5P
PEG_RXN9 C627 0.1UF 1 2 PEG_G_TXN9 PEG_G_TXN5 W27 AJ10 DVPCNTL0 1 2 RN18A
PEG_G_TXP6 PCIE_TX5N DVPCNTL_0 DVPCNTL1 10KOhm +3VS
C628 0.1UF Y26 AK10 3 4 RN18B
PEG_G_TXN6 PCIE_TX6P DVPCNTL_1 DVPCNTL2 10KOhm
PEG_RXP10 1 2 PEG_G_TXP10 W26 AJ11 5 6 RN18C
PCIE_TX6N DVPCNTL_2 10KOhm
PEG_RXN10 C602 0.1UF 1 2 PEG_G_TXN10 PEG_G_TXP7 U25 PCIE_TX7P DVPCNTL_3 AH11 DVPCNTL3 7 10KOhm 8 RN18D R1.1#33
C603 0.1UF PEG_G_TXN7 T25
PEG_RXP11 PEG_G_TXP11 PEG_G_TXP8 PCIE_TX7N
1 2 U27 PCIE_TX8P VREFG AG4 1 2 +3VS
PEG_RXN11 C646 0.1UF 1 2 PEG_G_TXN11 PEG_G_TXN8 T27 PCIE_TX8N For I/O power reference R36 499Ohm
2
C647 0.1UF PEG_G_TXP9 U26 PCIE_TX9P
1
PEG_RXP12 1 2 PEG_G_TXP12 PEG_G_TXN9 T26 AH15 C33 R32
PEG_G_TXP10 PCIE_TX9N TXOUT_L0N LVDS_YA0M_ATI 20
PEG_RXN12 C629 0.1UF 1 2 PEG_G_TXN12 P25 AH16
PEG_G_TXN10 PCIE_TX10P TXOUT_L0P LVDS_YA0P_ATI 20
C630 0.1UF N25 AJ16 0.1UF 499Ohm
PEG_G_TXP11 PCIE_TX10N TXOUT_L1N LVDS_YA1M_ATI 20
PEG_RXP13 PEG_G_TXP13
2
1 2 P27 PCIE_TX11P TXOUT_L1P AJ17 LVDS_YA1P_ATI 20
PEG_RXN13 C604 0.1UF 1 2 PEG_G_TXN13 PEG_G_TXN11
1
N27 PCIE_TX11N TXOUT_L2N AJ18 LVDS_YA2M_ATI 20
C605 0.1UF PEG_G_TXP12 P26 AK18 LVDS_YA2P_ATI 20 place close to ASIC
PEG_RXP14 PEG_G_TXP14 PEG_G_TXN12 PCIE_TX12P TXOUT_L2P
1 2 N26 PCIE_TX12N TXOUT_L3N AJ20
PEG_RXN14 C648 0.1UF 1 2 PEG_G_TXN14 PEG_G_TXP13 L25 AJ21
C649 0.1UF PEG_G_TXN13 PCIE_TX13P TXOUT_L3P
K25 PCIE_TX13N TXCLK_LN AK19 LVDS_CLKAM_ATI 20
PEG_RXP15 1 2 PEG_G_TXP15 PEG_G_TXP14 L27 PCIE_TX14P TXCLK_LP AJ19 LVDS_CLKAP_ATI 20 +3VS
R2.0#14
PEG_RXN15 C631 0.1UF 1 2 PEG_G_TXN15 PEG_G_TXN14
LVDS
K27 PCIE_TX14N TXOUT_U0N AG16 LVDS_YB0M_ATI 20 Ext VGA: N/A
C632 0.1UF PEG_G_TXP15 L26 AG17 U43
PEG_G_TXN15 PCIE_TX15P TXOUT_U0P LVDS_YB0P_ATI 20 Int VGA:
K26 PCIE_TX15N TXOUT_U1N AF16 LVDS_YB1M_ATI 20 1 B VCC 5
AF17 stuff
TXOUT_U1P LVDS_YB1P_ATI 20
TXOUT_U2N AE18 LVDS_YB2M_ATI 20 8 DAC_VSYNC_GM 1 2 2 A
+3VS AF27 AE19 R684 0Ohm
12 CLK_PCIE_PEG PCIE_REFCLKP TXOUT_U2P LVDS_YB2P_ATI 20
AE27 AF19 /* 3 GND 4
12 CLK_PCIE_PEG# PCIE_REFCLKN TXOUT_U3N
AF20 Y
TXOUT_U3P
2
AG23 AK27 Y
19 M24_SDA DDC3DATA R DAC_R_ATI 21
AJ27 74LVC1G32GV
27M_X1 G DAC_G_ATI 21
AJ26 /*
B DAC_B_ATI 21
X2 R105 1 2 1KOhm AJ23 SSIN
Memory SS (Reserved) 1 2 27M_X2 1 AH24 SSOUT HSYNC AJ25 DAC_HSYNC_ATI
CLK SS
XTALIN RSET
17 27M_SSIN_X1
R112 1 2 0Ohm /* 27M_X1 R117 1MOhm R693 499Ohm 1% Ext VGA: 0 ohm
1
C105 /* C126 R123 1 2 0Ohm /* XTALOUT AJ29 XTALOUT DDC1DATA AG25 DDC2BD_ATI 21 Int VGA: N/A
17 27M_SSIN_X2
R127 1 2 0Ohm /* 27M_X2 DDC1CLK AF24 DDC2BC_ATI 21
12PF/50V 12PF/50V
A /* /* R109 1 2 1KOhm TESTEN AH27 GPIO_AUX A
2
2
R697 1 2 0Ohm /* XTALOUT 1 AF25 PLLTEST DPLUS AF11 VGA_THERMDA 19
T274 AE11 R103 R96 R100
DMINUS VGA_THERMDC 19
THERM
1
M24_CSP64
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 16 OF 63
M24: MAIN RELEASE DATE : Alice Shih
5 4 3 2 1
1 2 3 4 5 6 7 8
U6B U6C
H28 VSS169 VSS102 E22 D7 VSS71 VSS205 N5
H29 Part 2 of 6 B22 F7 Part 3 of 6 M1
VSS170 VSS31 VSS114 VSS195
J28 VSS180 VSS32 B23 E7 VSS88 VSS197 M3
J29 VSS181 VSS33 B24 G6 VSS141 VSS191 L3
J26 VSS178 VSS58 C23 G5 VSS140 VSS190 L2
H25 VSS166 VSS57 C22 F5 VSS112 VSS196 M2
H26 VSS167 VSS127 F22 E5 VSS86 VSS198 M5
G26 VSS149 VSS126 F21 C4 VSS42 VSS212 P6
G30 VSS152 VSS56 C21 B5 VSS17 VSS204 N3
D29 VSS82 VSS10 A24 C5 VSS43 VSS183 K2
D28 VSS81 VSS59 C24 A4 VSS2 VSS184 K3
E28 VSS107 VSS11 A25 B4 VSS16 VSS171 J2
A E29 VSS108 VSS101 E21 C2 VSS40 VSS211 P5 A
G29 VSS151 VSS29 B20 D3 VSS68 VSS209 P3
G28 VSS150 VSS54 C19 D1 VSS66 VSS208 P2
F28 VSS133 D2 VSS67
G25 VSS148 VSS177 J25 G4 VSS139 VSS87 E6
F26 VSS131 VSS134 F29 H6 VSS157 VSS14 B2
E26 VSS106 VSS105 E25 H5 VSS156 VSS173 J5
F25 VSS130 VSS12 A27 J6 VSS174 VSS138 G3
E24 VSS104 VSS122 F15 K5 VSS186 VSS260 W6
F23 VSS128 VSS50 C15 K4 VSS185 VSS256 W2
E23 VSS103 VSS46 C11 L6 VSS194 VSS284 AC6
D22 VSS78 VSS91 E11 L5 VSS193 VSS290 AD2
B29 VSS38 G2 VSS137
C29 VSS64 VSS179 J27 F3 VSS111 VSS113 F6
C25 VSS60 VSS135 F30 H2 VSS153 VSS15 B3
C27 VSS62 VSS129 F24 E2 VSS84 VSS187 K6
B28 VSS37 VSS36 B27 F2 VSS110 VSS136 G1
B25 VSS34 VSS96 E16 J3 VSS172 VSS251 V5
C26 VSS61 VSS25 B16 F1 VSS109 VSS255 W1
B26 VSS35 VSS20 B11 H3 VSS154 VSS283 AC5
F17 VSS124 VSS117 F10 U6 VSS244 VSS289 AD1
E17 VSS97 U5 VSS243
D16 VSS75 VSS8 A19 U3 VSS241 VSS215 R2
F16 VSS123 V6 VSS252
E15 VSS95 VSS98 E18 W5 VSS259 VSS231 T5
F14 VSS121 W4 VSS258
E14 VSS94 VSS99 E19 Y6 VSS268 VSS232 T6
F13 +ATI_MEM Y5
VSS120 VSS267
C17 VSS52 VSS100 E20 U2 VSS240 VSS217 R5
B B18 V2 B
VSS27 VSS249
2
B17 VSS26 VSS125 F20 V1 VSS248 VSS218 R6
B15 R33 V3
VSS24 VSS250
C13 VSS48 VSS28 B19 W3 VSS257 VSS216 R3
B14 100Ohm Y2
VSS23 1% VSS264
C14 VSS49 Y3 VSS265 VSS202 N1
VDDR1 MEMVMODE_0 MEMVMODE_1
1
C16 VSS51 VSS30 B21 AA2 VSS269 VSS203 N2
A13 VSS5 VSS55 C20 AA6 VSS272
2
A12 +ATI_MEM AA5 T2
VSS4 VSS271 VSS229
1
C12 C18 C43 R37 AB6 T3 V 1.8V GND +1.8VS
VSS47 VSS53 VSS277 VSS230
B12 VSS21 VSS7 A18 AB5 VSS276
2
C10 0.1UF 100Ohm AD6
VSS45 1% R54 VSS293
2.5V +1.8VS GND
2
C9 VSS44 AD5 VSS292 VSS85 E3
1
B9 VSS18 AE5 VSS301 VSS270 AA3
B10 B7 MVREFA 100Ohm AE4
VSS19 MVREFA 1% VSS300
E13 VSS93 AB2 VSS274
MVREFM
1
E12 VSS92 MVREFM B8 AB3 VSS275 ROMCSb AF5
E10 VSS90 AC2 VSS280
2
F12 AC3 C6 R29 1 2 4.7KOhm /*
VSS119 VSS281 MEMVMODE_0 +1.8VS
1
F11 D30 C51 R53 AD3 C7 1 2
VSS118 VSS83 VSS291 MEMVMODE_1 R42 4.7KOhm
E9 VSS89 VSS22 B13 AE1 VSS297
F9 0.1UF 100Ohm AE2 C8
VSS116 1% VSS298 MEMTEST
2
F8 VSS115 AE3 VSS299
2
As close to
1
M24_CSP64 ASIC as M24_CSP64 R65 R44 R25
possible
47Ohm 4.7KOhm 4.7KOhm
MEMORY CHANNEL A MEMORY CHANNEL B 1% /*
1
C C
M26: no staff
1 2 CLK_VGA27 12,16
R678 0Ohm
R1.1#35
Memory Clock SS 1.2V
1 2 27M_SSOUT 1 2
(Reserved) 16 27M_ATI
R667 71.5Ohm R71 22.1Ohm
2
1% 1% /*
R679
71.5Ohm Place close to
S0 (Spread Percentage Select): 1% MK1726
GND: -1.8%
Place close
1
16 27M_SSIN_X2
U7 +3VS
16 27M_SSIN_X1 1 X1/ICLK X2 8
2 GND VDD 7 1 2
3 6 L28 120Ohm/100MHz /*
S0 PD#
16 MEM_SSIN 1 2 4 SSCLK REFCLK 5
R70 22.1Ohm 1% /*
2
1
D
MK1726_08STR /* C77 C111 D
Place close to MK1726 R75
0.1UF 22UF/6.3V
10KOhm /* /*
2
/*
1
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 17 OF 63 M24: MEMORY & SS RELEASE DATE : Alice Shih
1 2 3 4 5 6 7 8
5 4 3 2 1
CP5A
CP5B
CP4A
CP4B
CP7A
CP7B
CP8A
CP8B
MMSZ4681T1 /*
CP5C
CP5D
CP4C
CP4D
CP7C
CP7D
CP8C
CP8D
P19 VDDC18 VSS206 N15
U12 VDDC19 VSS213 P15
0.1UF 2
0.1UF 4
0.1UF 6
0.1UF 8
0.1UF 2
0.1UF 4
0.1UF 6
0.1UF 8
0.1UF 2
0.1UF 4
0.1UF 6
0.1UF 8
0.1UF 2
0.1UF 4
0.1UF 6
0.1UF 8
+ VDDC: U13 P16
VDDC20 VSS214
1
+ATI_MEM 1.8V U6D CE6 C548 M22= 1.15/ 1.0V U14 R18
VDDC21 VSS227
M24= 1.2/ 1.0V U17 VDDC22 VSS226 R17
VDDR1_VDDM T7 Part 4 of 6 AC13 220UF/2V 10UF/10V U18 R16
VDDR1_45 VDDC37 /* VDDC23 VSS225
2
R4 VDDR1_44 VDDC40 AD13 U19 VDDC24 VSS224 R15
7
+ R1 VDDR1_43 VDDC41 AD15 V19 VDDC30 VSS223 R14
1
1
D C538 C591 C533 C532 C14 C578 C523 C544 C13 CE23 N8 AC15 V18 R13 D
VDDR1_42 VDDC38 VDDC29 VSS222
N7 VDDR1_41 VDDC39 AC17 V17 VDDC28 VSS221 R12
CENTER ARRAY
0.1UF 1000PF 0.1UF 1000PF 0.1UF 1000PF 0.1UF 1000PF 0.1UF 150U/4.0V M4 2.4V V14 T13
VDDR1_39 +3.3V_BUS VDDC27 VSS233
2
2
L8 VDDR1_37 VDD15_4 P8 2 1 V13 VDDC26 VSS234 T14
K23 VDDR1_35 VDD15_5 Y8 V12 VDDC25 VSS235 T15
K24 AC11 D40 MMSZ4681T1 /* N18 W15
VDDR1_36 VDD15_7 VDDC11 VSS263
N4 VDDR1_40 VDD15_8 AC20 N17 VDDC10 VSS254 V16
L84 J8 H20 +VDDC_CT N14 V15
+VDD_MEM_CLK VDDR1_34 VDD15_2 VDDC9 VSS253
+ATI_MEM 1 2 J7 VDDR1_33 VDD15_1 H11 W17 VDDC34 VSS246 U15
1
J4 M23 C531 C540 C565 C552 W18 U16
VDDR1_32 VDD15_3 VDDC35 VSS247
1
120Ohm/100Mhz + J1 Y23 W12 T19
VDDR1_31 VDD15_6 VDDC31 VSS239
1
C526 CE22 C577 C527 H10 10UF/10V 0.1UF 0.1UF 0.1UF W13 T18
VDDR1_25 VDDC32 VSS238
2
H13 VDDR1_26 VDDR3_5 AD7 W14 VDDC33 VSS237 T17
+3.3V_BUS 10UF/10V 150U/4.0V 0.1UF 1000PF H15 AD19 +ATI_VCORE N13 T16
+3VS VDDR1_27 VDDR3_6 VDDC8 VSS236
/*
2
2
H17 VDDR1_28 VDDR3_7 AD21 N19 VDDC12
+VDDR4 T8 AC22 L81 L87 M19
VDDR1_46 VDDR3_4 VDDC6
V4 VDDR1_47 VDDR3_1 AC8 1 2 +3.3V_BUS 1 2 VDDC M18 VDDC5
V7 AC21 120Ohm/100Mhz M12
VDDR1_48 VDDR3_3 VDDC1
1
V8 AC19 C522 C579 120Ohm/100Mhz C566 C575 C576 C562 N12
+A2VDD VDDR1_49 VDDR3_2 VDDC7
+2.5VS 1 2 AA1 VDDR1_50 M13 VDDC2
L90 120Ohm/100Mhz AA4 AG7 1UF/10V 1UF/10V 0.1UF 0.1UF 0.1UF 0.1UF M14 W16 VDDC
VDDR1_51 VDDR4_5 VDDC3 VDDCI4
2
AA7 VDDR1_52 VDDR4_3 AD9 P12 VDDC13 VDDCI1 M15
AA8 VDDR1_53 VDDR4_1 AC9 P13 VDDC14 VDDCI2 R19
1 2 +A2VDDQ A3 AC10 L79 P14 T12
+1.8VS VDDR1_1 VDDR4_2 +VDDR4 VDDC15 VDDCI3
L92 120Ohm/100Mhz A9 AD10 1 2 M17
+AVDD VDDR1_2 VDDR4_4 VDDC4
1 2 A15 VDDR1_3 W19 VDDC36
1
L94 120Ohm/100Mhz A21 AG26 C520 C539 120Ohm/100Mhz
+PCIE_PVDD_18 VDDR1_4 PCIE_VDDR_12_1 M24_CSP64
1 2 A28 VDDR1_5 PCIE_VDDR_12_5 AK29
L89 120Ohm/100Mhz B1 AJ30 10UF/10V 1UF/10V
C +MPVDD VDDR1_6 PCIE_VDDR_12_4 C
2
1 2 B30 VDDR1_7 PCIE_VDDR_12_3 AG28
L82 120Ohm/100Mhz D26 AG27 +PCIE_VDDR
+PVDD VDDR1_15 PCIE_VDDR_12_2 +PCIE_VDDR U6E
1 2 D23 VDDR1_14
L97 120Ohm/100Mhz D20 N24 A2 U4
+PNL_PLL VDDR1_13 PCIE_PVDD_12_2 VSS1 Part 5 of 6 VSS242
1 2 D17 VDDR1_12 PCIE_PVDD_12_1 N23 A10 VSS3 VSS245 U8
CP1A
CP1B
L86 120Ohm/100Mhz +PCIE_PVDD_12
CP1C
CP1D
D14 VDDR1_11 PCIE_PVDD_12_3 P23 A16 VSS6 VSS261 W7
D11 VDDR1_10 A22 VSS9 VSS262 W8
0.01UF 2
0.01UF 4
0.01UF 6
0.01UF 8
D8 VDDR1_9 PCIE_PVDD_18_2 U23 A29 VSS13 VSS266 Y4
1
1 2 +VDDC_CT D5 T23 C167 C165 C1 AB8
+1.5VS VDDR1_8 PCIE_PVDD_18_1 VSS39 VSS279
L80 120Ohm/100Mhz E27 V23 C3 AB7
+LVDDR_25 VDDR1_16 PCIE_PVDD_18_3 +PCIE_PVDD_18 10UF/16V 1UF/10V VSS41 VSS278
LVDDR 1 2 F4 VDDR1_17 PCIE_PVDD_18_4 W23 C28 VSS63 VSS273 AB1
R645 0Ohm
2
G7 VDDR1_18 C30 VSS65 VSS282 AC4
1
7
+1.2VSP 1 2 G10 VDDR1_19 VDDM1 D9 D27 VSS80 VSS285 AC12
R160 0Ohm G13 D13 D24 AC14
10UF/10V 0.1UF VDDR1_20 VDDM2 VSS79 VSS286
G15 VDDR1_21 VDDM3 D19 D21 VSS77 VSS295 AD16
+PCIE_PVDD_12
2
CORE GND
G27 VDDR1_24 VDDM6 T4 D12 VSS73 VSS296 AD18
CP2A
CP2B
VDDR1_VDDM
CP2C
CP2D
H22 VDDR1_30 VDDM7 AB4 D10 VSS72 VSS306 AK2
+PNL_PLL H19 D6 AJ1
VDDR1_29 VSS70 VSS305
0.01UF 2
0.01UF 4
0.01UF 6
0.01UF 8
AD4 VDDR1_54 D4 VSS69
1
1
C593 C550 C580 C547 L23 C166 C175 K28
VDDR1_38 PCIE_VSS1
PCIE_VSS2 L28
10UF/10V 1UF/10V 1UF/10V 100PF 10UF/16V 1UF/10V M27
PCIE_VSS6
2
2
F27 VSS132 PCIE_VSS5 M26
7
AVSSQ AD22 G9 VSS142 PCIE_VSS3 M24
G12 VSS143 PCIE_VSS4 M25
+AVDD G16 M28
VSS144 PCIE_VSS7
AE16 LVDDR_25_1 LVSSR1 AF18 G18 VSS145 PCIE_VSS9 P28
1
CP9A
CP9B
10UF/10V 1UF/10V
CP9C
CP9D
AE15 LVDDR_18_2 LVSSR3 AG18 H27 VSS168 PCIE_VSS10 R23
1
0.01UF 2
0.01UF 4
0.01UF 6
0.01UF 8
JP23 SHORT_PIN /* H21 R26
VSS164 PCIE_VSS13
1
10UF/10V 1UF/10V 100PF AH19 AH18 LPVSS 1 2 C589 C583 H18 R27
LPVDD LPVSS VSS163 PCIE_VSS14
2
2
AF13 TXVDDR1 TXVSSR3 AH14 H12 VSS160 PCIE_VSS16 T24
+A2VDD
7
AF14 TXVDDR2 TXVSSR1 AG13 H9 VSS159 PCIE_VSS18 U28
1
PCIE_VSS23 V28
POWER
PCIE_VSS26 Y28
AF21 A2VDD2 A2VSSN2 AH20 AD12 VSS294 PCIE_VSS24 W24
+MPVDD +A2VDDQ AE20 AG21 AG5 W28
A2VDD1 A2VSSN1 VSS302 PCIE_VSS25
Power Sequence: AG9 VSS303 PCIE_VSS30 AA26
1
AF23 A2VDDQ A2VSSQ AF22 VDDR3(+3VS)->VDDR4(+3VS)< 1ms AG11 VSS304 PCIE_VSS31 AA27
PCIE_VSS27 AA23
10UF/10V 1UF/10V 10UF/10V 1UF/10V +AVDD AH23 AH22 VDDR3(+3VS)->VDDR1(+1.8VS)< 1ms AA24
AVDD AVSSN PCIE_VSS28
2
+VDDI/10mA +LVDDR_25/200mA A7 MPVDD MPVSS A6 +3VS -> 1.8VS -> 1.2VSP -> VCORE -> 1.5VS R8 VSS220 PCIE_VSS39 AF28
JP22 SHORT_PIN /* T1 AH29
+AVDD/70mA +VDDC_CT/40mA MPVSS 1 <1ms VSS228 PCIE_VSS40
2 >0ms >0ms <1ms
+A2VDDQ/5mA PCIE_VDDR, PCIE_PVDD_12/1.52A M24_CSP64 M24_CSP64
---------------------> VCORE
+A2VDD/120mA PCIE_PVDD_18/500mA
VDDR4/1.3mA +ATI_VCORE/8A
<1ms
VDDR1_VDDM/N/A
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 18 OF 63 M24: POWER RELEASE DATE : Alice Shih
5 4 3 2 1
8 7 6 5 4 3 2 1
+3VS R59
SMBus, Alert (ICH6): turn on FAN
200Ohm Overtemp (ICH6): Windows Shutdown
1%
+3VS_ATI_TS
1
2
2
1
1
16 M24_SCL
SCLK_S 8 4 OD 1 2 ATI_OVERTEMP# 22,25
SMBCLK OVERT R46 0Ohm /*
SDATA_S 7 2
16 M24_SDA SMBDATA DXP VGA_THERMDA 16
A 16 M24_THRM#
M24_THRM# R617 1 2 0Ohm OD 6 3 VGA_THERMDC 16 (10/10/10 mil) A
ALERT# DXN
GND
R607 1 2 0Ohm 1 2
6,22,25 PM_THRM#
/* C54 2200PF/10V
G781_1
/*
5
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 19 OF 63 M24: STRAPING/THERMAL RELEASE DATE : Alice Shih
8 7 6 5 4 3 2 1
A B C D E
LVDS Connector
Ext VGA: 0 ohm CN4
Int VGA: N/A LVDS_YA0M 1 1
LCD CABLE ID PID1 PID0 LVDS_YA0P 2 2 GND1 33
1 2 RN3A LVDS_YA0M 3 31
16 LVDS_YA0M_ATI 0Ohm LVDS_YA0P LVDS_YA1M 3 NP_NC1
3 4 RN3B 4 34
1
16 LVDS_YA0P_ATI
5
0Ohm
6 RN3C LVDS_YA1M 14" WXGA (AU/SS/CMO/CPT) 0 0 LVDS_YA1P 5
4 34
1
16 LVDS_YA1M_ATI 0Ohm 5
7 8 RN3D LVDS_YA1P 6
16 LVDS_YA1P_ATI 0Ohm LVDS_YA2M 6
1 2 RN6A LVDS_YA2M 7
16 LVDS_YA2M_ATI 0Ohm LVDS_YA2P 7
3 4 RN6B LVDS_YA2P 8
16 LVDS_YA2P_ATI 0Ohm 8
5 6 RN6C LVDS_CLKAM 9
16 LVDS_CLKAM_ATI 0Ohm LVDS_CLKAM 9
7 8 RN6D LVDS_CLKAP 10
16 LVDS_CLKAP_ATI 0Ohm LVDS_CLKAP 10
1 2 RN5A LVDS_YB0M 11
16 LVDS_YB0M_ATI 0Ohm 11
3 4 RN5B LVDS_YB0P 12
16 LVDS_YB0P_ATI 0Ohm +3VS LVDS_YB0M 12
5 6 RN5C LVDS_YB1M Ext VGA: stuff 13
16 LVDS_YB1M_ATI 0Ohm LVDS_YB0P 13
7 8 RN5D LVDS_YB1P 14
16 LVDS_YB1P_ATI 0Ohm
RN7A LVDS_YB2M
Int VGA: N/A 14
16 LVDS_YB2M_ATI 1 0Ohm 2 15 15
3 4 RN7B LVDS_YB2P LVDS_YB1M 16
16 LVDS_YB2P_ATI 0Ohm LVDS_YB1P 16
5 6 RN7C LVDS_CLKBM 17
16 LVDS_CLKBM_ATI 0Ohm 17
1
7 8 RN7D LVDS_CLKBP 18
16 LVDS_CLKBP_ATI 0Ohm LVDS_YB2M 18
R8 R4 19
LVDS_YB2P 19
20 20
100KOhm 100KOhm 21 21
R2.0#18 LVDS_CLKBM 22 22
LVDS_CLKBP
2
23 23
Ext VGA: N/A 22 PID1 2 1 24 24
R5 1KOhm +LCD_VCC 25
Int VGA: 0 ohm 25
26 26
23 PID0 2 1 27 27 35 35
2 1 2 RN21A /* LVDS_YA0M R9 1KOhm 2 1 28 32 2
8 LVDS_YA0M_GM 0Ohm LVDS_YA0P +3VS 28 NP_NC2
3 4 RN21B /* L17 1KOhm/100MHz 29 36
8 LVDS_YA0P_GM 0Ohm 29 GND2
8 LVDS_YA1M_GM 5 0Ohm 6 RN21C /* LVDS_YA1M R1.1#6 For EMI 30 30
7 8 RN21D /* LVDS_YA1P
8 LVDS_YA1P_GM 0Ohm RN23A
2 1 /* LVDS_YA2M WTOB_CON_30P
8 LVDS_YA2M_GM 0Ohm RN23B
4 3 /* LVDS_YA2P
8 LVDS_YA2P_GM 0Ohm +3VS
6 5 RN23C /* LVDS_CLKAM Ext VGA: N/A
8 LVDS_CLKAM_GM 0Ohm
8 7 RN23D /* LVDS_CLKAP
8 LVDS_CLKAP_GM 0Ohm
RN22A /* LVDS_YB0M
Int VGA: stuff
8 LVDS_YB0M_GM 1 0Ohm 2
1
3 4 RN22B /* LVDS_YB0P C515 C50 C508 C49 C514 C46
8 LVDS_YB0P_GM 0Ohm
2
5 6 RN22C /* LVDS_YB1M
8 LVDS_YB1M_GM 0Ohm
7 8 RN22D /* LVDS_YB1P R571 R556 Do Not Stuff
0.1UF Do Not Stuff
Do Not Stuff
Do Not Stuff
Do Not Stuff
8 LVDS_YB1P_GM 0Ohm
RN24A /* LVDS_YB2M 2.2KOhm 2.2KOhm /* /* /* /* /*
2
8 LVDS_YB2M_GM 1 0Ohm 2
3 4 RN24B /* LVDS_YB2P Ext VGA: N/A /* /*
8 LVDS_YB2P_GM 0Ohm
5 6 RN24C /* LVDS_CLKBM
8 LVDS_CLKBM_GM 0Ohm
RN24D /* LVDS_CLKBP Int VGA: stuff
1
8 LVDS_CLKBP_GM 7 0Ohm 8
8 EDID_CLK_GM For EMI
8 EDID_DAT_GM
S 2
S 2
D
D
3
3
Q84 Q88
G
+2.5VS
1
3 2N7002 2N7002 3
/* /*
16 EDID_CLK_ATI
16 EDID_DAT_ATI
R1.1#20
Q9 +LCD_VCC Inverter side pin define
2N7002 R951 1 2 100Ohm
2
R2.0#1
R22 2 100Ohm R48 10 AC_BAT_SYS
S 2
1
9 AC_BAT_SYS
3
100KOhm 8 GND
G
44,45,47 LID_SW#
7 (NC)
1
D11
+3VSUS +12VS +3VS +3V RB717F 6 PWM/DC
1
2 5 EN
AC_BAT_SYS 4 GND
14
3 1 2
1 R988 100Ohm 3 (NC)
2
12 VCC 2 GND
22,25 BACK_OFF#
4 R533 R573 11 R2.0#12 1 GND 4
3
2
1
10KOhm 1MOhm
16 LCD_BACKEN_ATI 13 R2.1
2
G
GND
1
D
7
/* INVERTOR
S
1
1%
4
5
6
2
D
1
C509 CN3
D37 1SS355 Q81 6 8
1 2 1 2N7002 3900PF/50V R2.0/2.1 1 2 5
6 SIDE2
L21 32 ADJ_BL 5
G L12 1KOhm/100MHz
2
4
2 S 1 2 +LCD_VCC 3
4
3
Ext VGA: N/A 1 2 R1.1#20 AC_INV 2 2
R532 470KOhm 400Ohm/100Mhz 1 7
Int VGA: 0 ohm 1 SIDE1
For EMI
1 2 3 WTOB_CON_6P_INVERTER
8 LCD_VDD_EN_GM D
1
1
R534 0Ohm /* C495 C505 C69 C70 C29 C30 C34 C35
Q82
1 2N7002 0.01UF 0.1UF 1UF/10V 10UF/10V 0.1UF 100PF 0.1UF/25V 0.1UF/25V
16 LCD_VDD_EN_ATI
G
2
2
2 S
5 5
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 20 OF 63 LVDS / INVERTER RELEASE DATE : Alice Shih
A B C D E
A B C D E
Place near
CRT connector Ext VGA: 0 ohm
Int VGA: N/A place close to CRT CRT Connector
Zo= 75 ohm connector
16 DAC_R_ATI 1 0Ohm 2 RN1A DAC_R R2.0#20
3 4 RN1B DAC_G
16 DAC_G_ATI 0Ohm DAC_B
5 6 RN1C Ext VGA: 3.3PF/68nH/5PF
16 DAC_B_ATI 0Ohm
7 8 RN1D
0Ohm Int VGA: 10PF/47ohm@100MHz/22PF/47ohm@100MHz/10PF
16
1 CN21 1
17
1 2 DDCCL
L4 120Ohm/100Mhz
S 2
S 2
D
+DAC_IO_P
3
3
Int VGA: 39 ohm
1
Q90 Q92 C73 C65 C41
G
G
1
2N7002 2N7002
1 2 5P 5P 5P
+12VS
1
R593 0Ohm C18 C52 C45 C25 C66 C44 C38 C549 C541 C23 C15
2
2 2
+DAC_IO_P
7PF/50V
7PF/50V
1 2 0.1UF 3.3pf 3.3pf 3.3pf 3.3pf 3.3pf 3.3pf 47P 47P
+5VS
DAC_IO_P D48 F01J4L /* /* /*
2
+3VS 2 1
2
R564 0Ohm
R636 R627 R24 R35 R47 R85 R60 R45
2 1 75Ohm 75Ohm 75Ohm
+2.5VS
R575 0Ohm 4.7KOhm 4.7KOhm D4 1% 1% 1% 0Ohm 0Ohm 0Ohm
/* BAV99
Ext VGA: +3VS DDC_DATA
2
1
1
DDC_CLK 3
Int VGA: +2.5VS
2
3 3
D D
2
D3 R2.0#15
R656 R563 BAV99
2.2KOhm 2.2KOhm 1 Q107 1 Q83 1
G 2N7002 G 2N7002 3 Ext VGA: 75 ohm_1%
2 S 2 S 2 Int VGA: 150 ohm_1%
1
16 DDC2BD_ATI
D2
16 DDC2BC_ATI
BAV99
R668 2 1 0Ohm /* 1
8 DDC2BD_GM
R574 2 1 0Ohm /* 3
8 DDC2BC_GM
3 2 3
Ext VGA: N/A
Int VGA: 0 ohm
2
1
1
R746 C733 C734
R836 150Ohm
1% 82P 82P
22
24
26
28
9
CN29 10KOhm CN25
2
/* CVBS_CON
1
1 2 2
P_GND2
NP_NC2
P_GND3
P_GND5
HC2
12 CLK_TPMPCI 1 2 CVBS1
2
2
4 22,30,31,32,43 LPC_AD0 11 11 12 12 4
1
13 14 R739 C729 C730
6,12,13,14,19,36 SCL_3S 13 14 SDA_3S 6,12,13,14,19,36
P_GND1
P_GND4
P_GND6
NP_NC1
15 16 150Ohm 5
+3VALWAYS 15 16 INT_SERIRQ 22,25,30,32,40 NC
17 18 1% 82P 82P
17 18 PM_CLKRUN# 22,25,30,32,37,39,40
2
22,25,30 PM_SUS_STAT# 19 20 LPC_DRQ#0 22,25,30 1
HC1
19 20 GND0
1
3 GND1
BtoB_CON_20P
21
23
25
27
/* MINI_DIN_7P
TV_C
8
1 2
L105 1.8UH
2
Ext VGA: 0 ohm +3VS
1
D21 R752 C750 C751
Int VGA: N/A BAV99 150Ohm
Zo= 50 ohm 1 1% 82P 82P
RN19A
2
1 0Ohm 2 3
RN19B TV_C
1
16 TV_C_ATI 3 0Ohm 4 2
5 6 RN19C TV_Y
+3VS +3VALWAYS +5V 16 TV_Y_ATI 0Ohm TV_CVBS
7 8 RN19D D17
16 TV_CVBS_ATI 0Ohm
BAV99
1
1
5 Int VGA: 0 5
1
BAV99 C721
ohm
1 RN20A /* TV_CVBS
8 TVDAC_A_GM 0Ohm 2 TV_Y
1
8 TVDAC_B_GM 3 0Ohm 4 RN20B /* 3 0.1UF
6 RN20C /* TV_C
2
8 TVDAC_C_GM 5 0Ohm 2
7 0Ohm 8 RN20D /*
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 21 OF 63 CRT, TV, TPM CONN RELEASE DATE : Alice Shih
A B C D E
5 4 3 2 1
2
28 IDE_PIORDY AF16 IORDY 25 EEP_DOUT D11 EE_DOUT
R373 B12
24.9Ohm EE_SHCLK
1%
EE_DOUT: Internal weak PU MCH_SYNC# AG21 MCH_SYNC# 25
EE_CS: Internal weak PD
1
28 IDE_PDA0 AC16 DA0 F12 LAN_CLK PWRBTN# U1 PM_PWRBTN# 47
28 IDE_PDA1 AB17 DA1 B11 LAN_RSTSYNC RI# T2 PM_RI# 25
28 IDE_PDA2 AC17 DA2 E12 LAN_RXD_0
E11 LAN_RXD_1
Install R315 for future CPU deeper C13 LAN_RXD_2
SMBCLK Y4 SCL_3A 25,36 sleep function. C12 LAN_TXD_0
C AD16 W5 C11 T4 C
28 IDE_PDCS1# DCS1# SMBDATA SDA_3A 25,36 LAN_TXD_1 SLP_S3# PM_SUSB# 33,34,40,43,47,54,57
28 IDE_PDCS3# AE17 DCS3# E13 LAN_TXD_2 SLP_S4# T5 PM_SUSC# 43,44,47,48,57
SLP_S5# T6 1
H_CPUSLP# R365 : B-STEP no stuff T349
H_DPRSTP# R372 : A-STEP no stuff
PM_SUS_STAT# 21,25,30
Y1 AE18 AF25 V2
GND1GND2
X2
4 H_STPCLK# STPCLK#
R368 1 0Ohm AE23 R393 10KOhm
2
6 H_THRMTRIP# 2 THRMTRIP#
RSMRST# Y3 PM_RSMRST# 45
RTC_X2
2
1 2
C356 12P
Y1 RTC_X1 +3VALWAYS +VCC_RTC
B RTCX1 PM_VGATE R369 1 ICH6_PWROK B
VRMPWRGD AF21 2 0Ohm
T367
2 THRM# AC20 PM_THRM# 6,19,25
Y2 RTC_X2 3
RTCX2
1
46 RTC_BAT 1 2 1
1
+VCC_RTC R378 1KOhm C345
D25
1
RB715F 1UF/10V
1
2
RTCRST# AA2
+VCC_RTC R379 DELAY 18~25ms T390
- Connect RX, RBIAS, CLK 1 2
to GND AA5 R332 10KOhm 180KOhm
INTVRMEN
2 1
- Leave TX, LED# as NC R333 0Ohm /*
2
J3 ICH6_PWROK
1MM_OPEN_5MIL
ACZ_SYNC_AUD 33
ICH6_M RTC CMOS R450 39Ohm
2
0.1U ACZ_RST# 1 2 1 2
CLEAR ACZ_RST#_AUD 33,34 POWERGD 54
/* X7R R467 39Ohm R390 0Ohm /*
2
SATA_ICH_TXN0 ACZ_SDOUT
2
2 1 SATA_HDD_RXN0 27 1 2 ACZ_SDOUT_AUD 33
SATA_ICH_TXP0 C337 3900PF/50V 2 1 R470 39Ohm ICH6_M
SATA_HDD_RXP0 27 ACZ_BCLK
/* C335 3900PF/50V 1 2 ACZ_BCLK_AUD 33
/* R465 39Ohm
2 1 SATA_BRIDGE_RXN0 26
C336 3900PF/50V 2 1 SATA_BRIDGE_RXP0 26
1
1 2 ACZ_SDOUT_MDC 38
R452 39Ohm
SATA_ICH_TXN2 2 1 1 2
SATA_ICH_TXP2 SATA_SWAP_RXN2 28 ACZ_BCLK_MDC 38
C333 3900PF/50V 2 1 R466 39Ohm
SATA_SWAP_RXP2 28
C332 3900PF/50V
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 22 OF 63 ICH6: SATA/LPC/IDE/ACZ(1) RELEASE DATE : Alice Shih
5 4 3 2 1
5 4 3 2 1
U30A
PCI_AD[0..31] 37,39,40
U30B
E1 E2 PCI_AD0
37,39,40 PCI_PAR PAR AD_0
C3 E5 PCI_AD1 T25 C21
25,37,39,40 PCI_DEVSEL# DEVSEL# AD_1 8 DMI_RXN0 DMI_0RXN USBP_0N USB_PN0 29
G6 C2 PCI_AD2 T24 D21
12 CLK_ICHPCI PCI_RST#_ICH R2 PCICLK AD_2 8 DMI_RXP0 DMI_0RXP USBP_0P USB_PP0 29
F5 PCI_AD3 R27 A20
PCIRST# AD_3 8 DMI_TXN0 DMI_0TXN USBP_1N USB_PN1 29
R1.1#14 PLT_RST#_SB R949 1 2 33Ohm PLT_RST#_SB1 R5
PLTRST# AD_4 F3 PCI_AD4
8 DMI_TXP0 R26 DMI_0TXP USBP_1P B20 USB_PP1 29
D A3 E9 PCI_AD5 V25 D19 D
25,37,39,40 PCI_IRDY# IRDY# AD_5 8 DMI_RXN1 DMI_1RXN USBP_2N USB_PN2 29
P6 F2 PCI_AD6 V24 C19
25,37,39,40 PCI_PME# PME# AD_6 8 DMI_RXP1 DMI_1RXP USBP_2P USB_PP2 29
G5 D6 PCI_AD7 U27 A18
25,37,39,40 PCI_SERR# 8 DMI_TXN1 USB_PN3 38
25,37,39,40 PCI_STOP# J1
SERR# AD_7
E6 PCI_AD8
8 DMI_TXP1 U26
DMI_1TXN USBP_3N
B18 USB_PP3 38
R1.1#10
STOP# AD_8 PCI_AD9 DMI_1TXP USBP_3P
25 PCI_LOCK# C5 PLOCK# AD_9 D3 8 DMI_RXN2 Y25 DMI_2RXN USBP_4N E17 USB_PN4 40
J2 A2 PCI_AD10 Y24 D17
25,37,39,40 PCI_TRDY# TRDY# AD_10 8 DMI_RXP2 DMI_2RXP USBP_4P USB_PP4 40
E3 D2 PCI_AD11 W27 B16 USB_PN5 1 T376
25,37,39,40 PCI_PERR# PERR# AD_11 8 DMI_TXN2 DMI_2TXN USBP_5N
25,37,39,40 PCI_FRAME# J3 FRAME# AD_12 D5 PCI_AD12
PCI_AD13
8 DMI_TXP2 W26 DMI_2TXP USBP_5P A16 USB_PP5
USB_PN6
1 T190
T374
for Express Card
AD_13 H3 8 DMI_RXN3 AB24 DMI_3RXN USBP_6N C15 1
B4 PCI_AD14 AB23 D15 USB_PP6 1 T370
AD_14 8 DMI_RXP3 DMI_3RXP USBP_6P
J5 PCI_AD15 AA27 A14 USB_PN7 1 T378
AD_15 8 DMI_TXN3 DMI_3TXN USBP_7N
K2 PCI_AD16 AA26 B14 USB_PP7 1 T377
AD_16 8 DMI_TXP3 DMI_3TXP USBP_7P
C1 K5 PCI_AD17
37 PCI_GNT#0 GNT_0# AD_17
B6 D4 PCI_AD18
40 PCI_GNT#1 GNT_1# AD_18
1 PCI_GNT#2 F1 GNT_2# AD_19 L6 PCI_AD19
OC_0# C27 USB_OC#0 25,29
T185 C8 G3 PCI_AD20 B27
39 PCI_GNT#3 GNT_3# AD_20 OC_1# USB_OC#12 25,29
1 E7 H4 PCI_AD21 B26
T369 GNT_4#/GPIO48 AD_21 PCI_AD22 OC_2#
25 GPO17 F6 GNT_5#/GPIO17 AD_22 H2 OC_3# C26 USB_OC#3 25
D8 H5 PCI_AD23 C23
25 GPO16 GNT_6#/GPIO16 AD_23 OC_4#/GPIO9
B3 PCI_AD24 D23
AD_24 OC_5#/GPIO10 USB_OC#45 25
M6 PCI_AD25 H25 C25
AD_25 HSIN_0 OC_6#/GPIO14 GPI14 25
B2 PCI_AD26 H24 C24 1 2
AD_26 HSIP_0 OC_7#/GPIO15 CHG_EN# 54,55
K6 PCI_AD27 1 G27 D29 1SS355
AD_27 PCI_AD28 T184 HSON_0
25,37 PCI_REQ#0 L5 REQ_0# AD_28 K3 1 G26 HSOP_0 CHG_EN#_OC 25
B5 A5 PCI_AD29 T182 K25 1
25,40 PCI_REQ#1 REQ_1# AD_29 HSIN_1
M5 L1 PCI_AD30 K24 B22 USBRBIAS T391
25 PCI_REQ#2 REQ_2# AD_30 HSIP_1 USBRBIAS
B8 K4 PCI_AD31 1 J27 A22 1 2
25,39 PCI_REQ#3 REQ_3# AD_31 HSON_1 USBRBIAS#
F7 T364 1 J26 R464 22.6Ohm
20 PID0 REQ_4#/GPIO40 HSOP_1
E8 T365 M25 1%
C
25,32 KBDDT1 REQ_5#/GPIO1 HSIN_2 C
25,32 KBDDT0 B7 REQ_6#/GPIO0 M24 HSIP_2
1 L27 HSON_2 Place within 500
T359 1 L26 HSOP_2 mils of ICH.
T356 P24 HSIN_3
25,40 PCI_INTA# N2 PIRQA# P23 HSIP_3
25,39,40 PCI_INTB# L2 PIRQB# 1 N27 HSON_3
M1 T354 1 N26
25,37,39,40 PCI_INTC# PIRQC# HSOP_3
L3 T351
25,39 PCI_INTD# PIRQD#
25 PCI_INTE# D9 PIRQE#/GPIO2
C7 +1.5VS
25 PCI_INTF# PIRQF#/GPIO3
25 PCI_INTG# C6 PIRQG#/GPIO4 F24 DMI_ZCOMP CLK48 A27 CLK_USB48 12
25 PCI_INTH# M3 PIRQH#/GPIO5 C_BE_3# G2 PCI_C/BE#3 37,39,40 1 2 F23 DMI_IRCOMP
G4 R436 24.9Ohm
C_BE_2# PCI_C/BE#2 37,39,40
H6 1%
C_BE_1# PCI_C/BE#1 37,39,40
C_BE_0# J6 PCI_C/BE#0 37,39,40
Place within 500 mils of ICH.
ICH6_M
ICH6_M
+3V
2
C324
U28C
14
0.1UF U28A LV08A
14
LV08A VCC R358 1 2 47KOhm PLT_RST#_SB
1
9
VCC 1 PCI_RST#_ICH 8
16 PLT_RST#
28,37,39,40 PCI_RST# 1 2 3 10 SW_RST# 30
R984 33Ohm 2 GND
GND Ext VGA: stuff
1
+3V
R2.0#7 C325
7
Int VGA: N/A
7
0.1UF/25V
2
1
C302
R1.1#36
0.1UF +3V
U26
2
PCI_RST# U28B
14
1 A VCC 5
32 SET_PCIRSTNS# 1 2 2 B
LV08A Can be issue SCI or SMI List: GPIO0~GPIO15
R329 10KOhm 3 4 1 2 VCC 4 1 2 PLT_RST#_SB
GND Y PCI_RSTNS# 32,37
1
A
R328 C314 SN74LVC1G32 5 Resume Power Well GPIO List: GPIO8,11,13,14,15,24,25,27,28 A
R2.0#6 GND
Only GPI Pin: GPI0~8,11~15,26,29,30,31,40(5V),41
1
47KOhm 0.01UF C303
Only GPO Pin: GPIO16~17,19,21,23,48
2
2 /*
Resume Power Input Pin List: BATLOW#,AC_SDIN[0:1],LAN_RST#,
OC[7:0]#,PME#,PWRBTN#,RI#,SMBALERT#,SYS_RESET#,USBRBIAS#
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 23 OF 63 ICH6: PCI/DMI/USB/PCIE(2) RELEASE DATE : Alice Shih
5 4 3 2 1
5 4 3 2 1
ICH6_CORE U30E
AA19 A8 V5REF 1 T392 U30F
+1.5VS VCC1_5_21 V5REF1
Place 0.01uF AA20 VCC1_5_22 V5REF2 AA18 A1 VSS1 VSS87 G21
1
C338 C374 C396 C432 C408 AA21 A12 G7
within 100mils of L11
VCC1_5_23
AB18 +2.5VS_PCI_IDE A15
VSS2 VSS88
G9
VCC1_5_24 VCC2_5_1 VSS3 VSS89
ICH near pin AA19 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF L12 VCC1_5_25 VCC2_5_2 P7 +2.5VS A19 VSS4 VSS90 H23
2
L14 VCC1_5_26 A21 VSS5 VSS91 H26
L16 VCC1_5_27 A23 VSS6 VSS92 H27
1
L17 C328 A26 J23
VCC1_5_28 V5REF_SUS T393 VSS7 VSS93
Place 4X0.1uF M11 VCC1_5_29 V5REF_SUS F21 1 A4 VSS8 VSS94 J24
M17 0.1UF A7 J25
Distribute near VCC1_5_30 VSS9 VSS95
2
P11 VCC1_5_31 A9 VSS10 VSS96 J4
pin ICH6 P17 VCC1_5_32 AA11 VSS11 VSS97 K1
D T11 AA13 K23 D
Package edge T17
VCC1_5_33
AA16
VSS12 VSS98
K26
VCC1_5_34 VSS13 VSS99
U11 VCC1_5_35 AA4 VSS14 VSS100 K27
U12 VCC1_5_36 AB1 VSS15 VSS101 K7
U14 VCC1_5_37 AB10 VSS16 VSS102 L13
U16 VCC1_5_38 AB19 VSS17 VSS103 L15
U17 VCC1_5_39 AB2 VSS18 VSS104 L23
G8 VCC1_5_40 AB7 VSS19 VSS105 L24
D24 VCC1_5_41 AB9 VSS20 VSS106 L25
D25 VCC1_5_42 AC10 VSS21 VSS107 M12
D26 VCC1_5_43 AC12 VSS22 VSS108 M13
USB_CORE D27 AC22 M14
VCC1_5_44 VSS23 VSS109
Place BOTH E20 VCC1_5_45 AC23 VSS24 VSS110 M15
1
C420 C380 E21 L55 AC24 M16
within 100mils of E22
VCC1_5_46 VCCDPLL 1 2 AC26
VSS25 VSS111
M23
VCC1_5_47 +1.5VS VSS26 VSS112
ICH near pin D27 0.1UF 0.1UF E23 VCC1_5_48 AC3 VSS27 VSS113 M26
120Ohm/100Mhz
2
E24 VCC1_5_49 AC6 VSS28 VSS114 M27
1
F20 C342 C322 AD1 M4
VCC1_5_50 VSS29 VSS115
G20 VCC1_5_51 AD10 VSS30 VSS116 N1
F9 0.01UF 10UF/10V AD15 N11
VCC1_5_52 VSS31 VSS117
2
AD18 VSS32 VSS118 N12
AD2 VSS33 VSS119 N13
+VCCP AB22 V_CPU_IO_1 AD24 VSS34 VSS120 N14
AD26 AC27 AD6 N15
1
C339 V_CPU_IO_2 VCCDMIPLL VSS35 VSS121
AG23 V_CPU_IO_3 AE10 VSS36 VSS122 N16
Place 0.1uF within 100mils AE1 +1.5VS_SATAPLL AE11 N17
0.1UF VCCSATAPLL VSS37 VSS123
AE12 N7
of ICH near pin AG23 VSS38 VSS124
2
A25 +1.5VS_USBPLL AE2 P12
VCCUSBPLL VSS39 VSS125
AE21 VSS40 VSS126 P13
C +3VS AA22 AE25 P14 C
VCCDMIPWR1 +1.5VS VSS41 VSS127
PCI_IDE_CORE VCCDMIPWR2 AA23 AE6 VSS42 VSS128 P15
AA12 VCC3_3_1 VCCDMIPWR3 AA24 AE7 VSS43 VSS129 P16
1
AA14 VCC3_3_2 VCCDMIPWR4 AA25 + AF1 VSS44 VSS130 P22
1
C323 C433 C330 C416 AA15 AB25 CE16 C327 C434 C331 AF12 R11
VCC3_3_3 VCCDMIPWR5 VSS45 VSS131
AA17 VCC3_3_4 VCCDMIPWR6 AB26 AF26 VSS46 VSS132 R12
10UF/10V 0.1UF 0.1UF 0.1UF AC15 AB27 150U/4.0V 0.1UF 0.1UF 0.1UF AF3 R13
VCC3_3_5 VCCDMIPWR7 VSS47 VSS133
Place 0.1uFx1 near AG10
2
2
AD17 VCC3_3_6 VCCDMIPWR8 F25 AF7 VSS48 VSS134 R14
AG13 F26 AG1 R15
Place 0.1uFx1 near E26, E27 AG16
VCC3_3_7 VCCDMIPWR9
F27 Place 150uF, 3 X 0.1uF AG12
VSS49 VSS135
R16
VCC3_3_8 VCCDMIPWR10 VSS50 VSS136
Place 0.1uFx2 near AG13, AG16 AG19 VCC3_3_9 VCCDMIPWR11 G22
within 100mils of ICH near AG14 VSS51 VSS137 R17
A6 G23 AG17 R23
Place 0.1uFx3 near A2~A6, D1~H1 B1
VCC3_3_10 VCCDMIPWR12
G24 pin F27, P27, AB27 AG20
VSS52 VSS138
R24
+5VS +3VS VCC3_3_11 VCCDMIPWR13 VSS53 VSS139
E4 VCC3_3_12 VCCDMIPWR14 G25 AG22 VSS54 VSS140 R25
H1 VCC3_3_13 VCCDMIPWR15 H21 AG3 VSS55 VSS141 R4
1
1
C413 C398 C329 C402 H7 H22 AG7 T1
VCC3_3_14 VCCDMIPWR16 VSS56 VSS142
1
2
L7 VCC3_3_17 VCCDMIPWR19 K21 1 2 +1.5VS B19 VSS59 VSS145 T14
100Ohm F01J4L M7 K22 B21 T15
VCC3_3_18 VCCDMIPWR20 0Ohm VSS60 VSS146
P1 VCC3_3_19 VCCDMIPWR21 L21 B23 VSS61 VSS147 T16
1
C344
2
2
N21 C20 T7
1
2
2
1
W2 R22 C422 D7 W1
VCCSUS3_3_9 VCCDMIPWR35 VSS75 VSS161
2
2
B17 U21 E18 W7
1
1
2
C400
2
AD4 0.1UF
+1.5VSUS VCC1_5_6 100mils of ICH 2.5VS: 15mA +1.8V rise time < 2ms
2
AB3 VCCRTC VCC1_5_7 AE4
1
C412 C409
VCC1_5_8 AE5 near pin AG5 3VS: 243mA +1.5VS --> +VCCP
1 2 R7 VCCSUS1_5_A VCC1_5_9 AG5
1UF/10V 0.1UF R846 0Ohm AF5 3VSUS: 23mA +5VS --> +3VS --> +2.5VS
1
U7 VCCSUS1_5_B VCC1_5_11 AA7 1.5VSUS: 170mA +5VSUS --> +3VSUS --> +1.5VSUS
A 0.1UF 0.1UF 0.1UF VCC1_5_12 AA8 A
+1.5VA_USB G19 AA9 5VSUS: 10mA VCCRTC --> RTCRST# > 5ms
VCCSUS1_5_C VCC1_5_13
2
VCC1_5_14 AB8 Place within VCCP: 14mA +3VALWAYS --> RSMRST# > 5ms
1
G10 AC8 C346
Place near PIN F21
VCCSUS1_5_D VCC1_5_15 100mils of ICH RTC: 5uA
+1.5VS_LAN VCC1_5_16 AD8 +3VALWAYS --> LAN_RST# > 10ms
+1.5VS 1 2 G11 VCCSUS1_5_E VCC1_5_17 AE8 0.1UF near pin AG9
R457 0Ohm +3VS(LAN) --> LAN_RST# > 10ms
2
VCC1_5_18 AE9
2 1 VCC1_5_19 AF9 +3VS,+1.5VS --> PWROK,PM_VATE > 99ms
C419 0.1UF AG9
VCC1_5_20 ICH6_M
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 24 OF 63 ICH6: PWR/GND/CAPS(3) RELEASE DATE : M.Y.
5 4 3 2 1
5 4 3 2 1
+3VS +3VSUS
+3VS
INTERNAL PULL-DOWN
1 RP3A
23,37,39,40 PCI_FRAME# 8.2KOhm5 PULL-UP : PCI Express Port config bit 1
10 R385 2 1 10KOhm
22 LINKALERT#
2 RP3B
23,37,39,40 PCI_IRDY# 8.2KOhm5
10 R469 2 1 10KOhm ACZ_SDOUT 22
3 RP3C /*
23,37,39,40 PCI_TRDY# 8.2KOhm5
10 R401 1 2 2.2KOhm
22,36 SCL_3A
4 RP3D
23,37,39,40 PCI_STOP# 8.2KOhm5 +3VS
10
6 RP3E INTERNAL PULL-DOWN
D 23,37,39,40 PCI_SERR# 8.2KOhm5 D
1
10 C441 PULL-UP : PCI Express Port config bit 0 R386 1 2 2.2KOhm
22,36 SDA_3A
7 RP3F
23,37,39,40 PCI_DEVSEL# 8.2KOhm5
10 0.1UF
RP3G R468 2 1 10KOhm
2
23,37,39,40 PCI_PERR# 8 8.2KOhm5 ACZ_SYNC 22
10 /*
9 RP3H RN15A
23 PCI_LOCK# 8.2KOhm5 22,36 SM_LINK0 1 10KOhm 2
10 3 4 RN15B
22,36 SM_LINK1 10KOhm
1 RP6A RN15C
21,22,30,32,40 INT_SERIRQ 8.2KOhm5 22 PM_BATLOW# 5 10KOhm 6
10 7 8 RN15D
22,40 CB_SD# 10KOhm
2 RP6B R409 2 1 10KOhm
6,19,22 PM_THRM# 8.2KOhm5 TP3 22
10 /*
3 RP6C
23,37 PCI_REQ#0 8.2KOhm5
10 INTERNAL PULL-UP R412 2 1 10KOhm
23,37,39,40 PCI_PME#
4 RP6D
23,40 PCI_REQ#1 8.2KOhm5 PULL-DOWN : PCI Express Port chain test
10
6 RP6E R931 2 1 10KOhm
23 PCI_REQ#2 8.2KOhm5 22,43 ICH6_1HZ
10
7 RP6F
23,39 PCI_REQ#3 8.2KOhm5
10
8 RP6G +3VS
8.2KOhm5
10
9 RP6H INTERNAL PULL-DOWN
22,32 KBDSCI_3 8.2KOhm5 +3VS
10 PULL-UP : NO REBOOT
1 RP4A
23,39 PCI_INTD# 8.2KOhm5
10
2 RP4B R473 1 2 1KOhm
23,37,39,40 PCI_INTC# 8.2KOhm5 ICH_SPKR 22,33
10 /* RP4D 4
23,32 KBDDT0 8.2KOhm5
3 RP4C
23,40 PCI_INTA# 8.2KOhm5 10
C 10 RP4F 7 C
23,32 KBDDT1 8.2KOhm5
6 RP4E
23,39,40 PCI_INTB# 8.2KOhm5 10
10 RP4H 9
23 PCI_INTE# 8.2KOhm5
8 RP4G R474 1 2 1KOhm
22,27 SATA_DET_#0 8.2KOhm5 EEP_DOUT 22 10
10 /* RP2B 2
23 PCI_INTF# 8.2KOhm5
1 RP2A
22,28 SATA_DET_#2 8.2KOhm5 10
10 INTERNAL PULL-UP RP2D 4
23 PCI_INTG# 8.2KOhm5
3 RP2C
22 MCH_SYNC# 8.2KOhm5 PULL-DOWN : RESERVED 10
10 RP2F 7
23 PCI_INTH# 8.2KOhm5
6 RP2E
8.2KOhm5 10
10 RP2G 8
21,22,30,32,37,39,40 PM_CLKRUN# 8.2KOhm5
10
RP2H 9
22,28 INT_IRQ14 8.2KOhm5
R448 1 2 1KOhm 10
+3VSUS GPO17 23
/*
INTERNAL PULL-UP
PULL-DOWN : Boot BIOS destination select
1 RP5A
23,29 USB_OC#0 10KOhm5
10
2 RP5B
22 PM_RI# 10KOhm5
10
3 RP5C R480 1 2 1KOhm
23 CHG_EN#_OC 10KOhm5 GPO16 23
10 /*
4 RP5D +3VS
23,29 USB_OC#12 10KOhm5
10 INTERNAL PULL-UP
6 RP5E
23 USB_OC#45 10KOhm5 PULL-DOWN :TOP-BLOCK SWAP
10 R359 2 1 10KOhm
20,22 BACK_OFF#
7 RP5F /*
B 23 USB_OC#3 10KOhm5 B
10
8 RP5G
19,22 ATI_OVERTEMP# 10KOhm5
10 R415 1 2 4.7KOhm
21,22,30 PM_SUS_STAT#
9 RP5H /*
23 GPI14 10KOhm5
10
R424 1 2 8.2KOhm
21,22,30 LPC_DRQ#0
INTERNAL PULL-DOWN SIGNALS : /*
+3VSUS +3VS
R2.1
AC_BITCLK, AC_RST# , AC_SDIN[2:0] ,
AC_SDOUT , AC_SYNC , DPSLPVR ,
1
22 PCB_VID0
PCB_VID1 2 1
22 PCB_VID1 22,34 OP_SD#
PCB_VID2 EE_DIN , EE_DOUT , EE_CS , R304 10KOhm
22 PCB_VID2
GPIO[17:16] , LAD[3:0]# ,
1
LDRQ[0:1] , LAN_RXD[2:0] ,
R420 R418 R342 PME# , PWRBTN# , TP3 ,
PCB_VID2 PCB_VID1 PCB_VID0
10KOhm 10KOhm 10KOhm SATALED# ,
A
MB R1.0 0 0 0 /* GNT[4:0] A
2
MB R1.1 0 0 0
MB R2.0 0 0 1
MB R2.1 0 1 0
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 25 OF 63 ICH6M:Res & Straps RELEASE DATE : M.Y.
5 4 3 2 1
A B C D E
27 IDE_BDD[0:15] +3VS
27 IDE_BDA[0:2]
27 IDE_BDCS0# +3VS
27 IDE_BDCS1#
1
R434 +3VS +1.8VS L111 +3VS
1 1
1
FOR 120Ohm/100MHz
10KOhm R431 88SA8040 /* +3VS +1.8VS
T358
/* 1 2
10KOhm
2
/* +1.8VS
1
+3VS C390 C358 C389 C372 C357
2
1
1 2
IDE_BDCS0#
IDE_BDCS1#
2
R426 L112 120Ohm/100Mhz 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
STP_PIN39
STP_PIN38
STP_PIN36
STP_PIN35
STP_PIN34
STP_PIN33
1
0Ohm R435 FOR SIL3811
2
1 2 C378 C375 C382
ODCS
0Ohm
0.1UF 0.1UF 0.1UF
2
1
C377
1
0.1UF
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
U29
+1.8VS
ODCS
IDE_CS0_b
IDE_CS1_b
VSS4
Reserved1
VDDO_3
Reserved2
VSS3
VDDI_3
Reserved3
Reserved4
Reserved5
Reserved6
Reserved7
Reserved8
Reserved9
IDE_BDA2 49 32 SATA_BRIDGE_TXP0 2 1
IDE_BDA0 IDE_DA2 TXP SATA_BRIDGE_TXN0 SATA_ICH_BRIDGE_RXP0 22
2 50 31 C386 3900PF/50V 2 1 2
IDE_BDA1 IDE_DA0 TXN SATA_ICH_BRIDGE_RXN0 22
51 30 C384 3900PF/50V
IDE_DA1 GNDA2
52 VDDO_1 VDDA2 29
27 IDE_BINTRQ 53 IDE_INTRQ RXN 28 SATA_BRIDGE_RXN0 22
27 IDE_BDMACK# 54 IDE_DMACK_b RXP 27 SATA_BRIDGE_RXP0 22
55 26 R849 1 2 1KOhm
27 IDE_BIORDY IDE_IORDY REXT
56 25 1 2 1%
VDDI_1 GNDA1 Sil3811 -1K;
57 VSS1 VDDA1 24
58 23 XO_STP R850 88SA8040 -12.1K
27 IDE_BDIOR# IDE_DIOR_b XTALO
59 22 XI_STP 0Ohm
27 IDE_BDIOW# IDE_DIOW_b XTALI/CLKI STP_DISABLE#
27 IDE_BDMARQ 60 IDE_DMARQ_b DD_DISABLE_b 21
IDE_BDD15 61 20 IOINSEL1 XO_STP
IDE_BDD0 IDE_DD15 IOINSEL1 IOINPIN R416 10MOhm
62 IDE_DD00 IOINPIN 19
IDE_BDD14 63 18 IOINSEL0 1 2 XI_STP
IDE_BDD1 IDE_DD14 IOINSEL0 IDERST#_5
64 IDE_DD01 SYS_RESET_b 17
1 2 65 X4
GND 1 2
IDE_RESET_b
R844
0Ohm 25Mhz
IDE_DD13
IDE_DD02
IDE_DD12
IDE_DD03
IDE_DD11
IDE_DD04
IDE_DD10
IDE_DD05
IDE_DD09
IDE_DD06
IDE_DD08
IDE_DD07
VDDO_2
VDDI_2
2
C350 C354
VSS2
18P 18P
SII3811CNU
1
3 3
10
11
12
13
14
15
16
+3VS +1.8VS
1
2
3
4
5
6
7
8
9
+3VS +3VS
R1.1#17
IDE_BRESET#
IDE_BDD13
IDE_BDD12
IDE_BDD11
IDE_BDD10
IDE_BDD2
IDE_BDD3
IDE_BDD4
IDE_BDD5
IDE_BDD9
IDE_BDD6
IDE_BDD8
IDE_BDD7
1
+3VS +3VS
1
1
10KOhm /*
/* R396 R841
2
STP_DISABLE# IOINPIN
2
10KOhm 10KOhm
1 2 /* /*
27 IDE_BRST#
1
R383 0Ohm
2
R847 R400
2
2 IDERST#_5 28
D27
4 RB717F 4
/*
+3VS
+3VS STP_PIN34 +3VS +3VS STP_PIN38
1
ALL FOR 88SA8040,
1
1
R433
R427 R428 R429 R430 R432 UNINSTALL ALL FOR
10KOhm SIL3811
10KOhm 10KOhm 10KOhm 10KOhm 10KOhm /*
/* /* /* /* /*
2
2
STP_PIN39
STP_PIN33 STP_PIN35 STP_PIN36
5 5
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 26 OF 63 SATA TO PATA BRIDGE RELEASE DATE : M.Y.
A B C D E
A B C D E
E E
IDE_BDD[15:0]
26 IDE_BDD[15:0] R1.1#18
1
C832 C824
R857
4.7KOhm CN32 10UF/10V 0.1UF
BTOB_CON_50P
2
54
53
1
50 49
GND4
GND3
IDE_BRST# 50 49
26 IDE_BRST# 48 48 47 47
IDE_BDD7 46 45 IDE_BDD8
D 46 45 D
IDE_BDD6 44 43 IDE_BDD9
IDE_BDD5 44 43 IDE_BDD10 +3VS
42 42 41 41
IDE_BDD4 40 39 IDE_BDD11
IDE_BDD3 40 39 IDE_BDD12
38 38 37 37
IDE_BDD2 36 35 IDE_BDD13
36 35
1
IDE_BDD1 34 33 IDE_BDD14
IDE_BDD0 34 33 IDE_BDD15 R883
32 32 31 31
30 30 29 29
IDE_BDMARQ 28 27 1KOhm
26 IDE_BDMARQ IDE_BDIOW# 28 27
26 25 /*
26 IDE_BDIOW# IDE_BDIOR# 26 25
2
26 IDE_BDIOR# 24 24 23 23
IDE_BIORDY 22 21 IDE_BCSEL IDE_BCSEL
26 IDE_BIORDY IDE_BDMACK# 22 21
26 IDE_BDMACK# 20 20 19 19
IDE_BINTRQ 18 17
26 IDE_BINTRQ 18 17
2
IDE_BDA1 16 15 IDE_BDIAG 1 T371
26 IDE_BDA1 IDE_BDA0 16 15 IDE_BDA2
14 13 R884
26 IDE_BDA0 IDE_BDCS0# 14 13 IDE_BDCS1# IDE_BDA2 26
26 IDE_BDCS0# 12 12 11 11 IDE_BDCS1# 26
IDE_BDASP# 10 9 1 2 470Ohm
28 IDE_BDASP# 10 9 +3VS
8 7 R885 10KOhm
8 7
1
6 6 5 5 SATA_DET_#0 22,25
GND2
GND1
2 1 SATA_HDD_TXN0 4 3
22 SATA_ICH_HDD_RXN0 4 3 SATA_HDD_RXP0 22
C826 3900PF/50V /* 2 1
2 1 SATA_HDD_RXN0 22
C C
2 1 SATA_HDD_TXP0
22 SATA_ICH_HDD_RXP0
52
51
C827 3900PF/50V /*
A A
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 27 OF 63 HDD CON. RELEASE DATE : M.Y.
A B C D E
A B C D E
+5VS
+5VS +5VDOCK
IDE_PDD[15:0]
22 IDE_PDD[15:0]
1
C718 C715 C717 C781 C787 C785 C791 U27
1 A VCC 5 IDERST#_5 26
0.1UF 10UF/10V 0.1UF 10UF/10V 0.1UF 10UF/10V 0.1UF
2 /* 2 B
2
1 23,37,39,40 PCI_RST# 1 1
R326 0Ohm
3 GND 4 IDERST#_5 2 1 IDERST#_5S
1 2 Y R288 0Ohm
6,8,21,22,23,30,31,32 BUF_PLT_RST# R327 0Ohm NC7SZ08P5X /*
+5VS
R2.0#16
+12VS 1 2 3
+3VS D +3VS
R287 10KOhm
Q47
2
1 6 1 2N7002
D 30 BAY_RST +5VS
R377 2 5 G
3 S 4 2 S
100KOhm G C914 0.1UF
2
4
6
8
+3VS Q124 1 2
SI3456DV
10KOhm
10KOhm
10KOhm
10KOhm
1
XIDE_EN_12VS U23
2
IDERST#_5 1 A VCC 5
R334
Q140 Q144 +5VDOCK 2 1 BAY_RST# 2 B
10KOhm 3 2N7002 3 2N7002 R293 10KOhm
1
3
5
7
2 D D 2
1
IDERST#_5S
RN14A
RN14B
RN14C
RN14D
3 GND 4
2
C720 R299 C719 C783 C301 Y
1
1 1 NC7SZ08P5X
G G 0.1UF 100KOhm 0.1UF 0.1UF 100PF
R353 100KOhm 2 S 2 S +5VDOCK
1
3 BAY_IN0
2
2 1 D
2
Q193 BAY_IN1
1 2 1 2N7002 R812
22 XIDE_EN#_3 BAYDOCK_IN#
D23 1SS355 G
R2.1 2 S 4.7KOhm
1
1
3 C282 C284 C289
1
2 1 D
0.47U
Q192 PIN22_+5V_PH 0.1UF 0.1UF 0.1UF
2
1 2N7002
2
1 2
D74 1SS355 G
2 S
1
C915 R2.1
0.47U
BAYDOCK_IN#
2
3 3
L : Slave H : Slave
R835 R813 +5VDOCK +5VDOCK
For EMI
4.7KOhm 1KOhm
/* 1 2
XIDE_EN_12VS C803 0.1UF
1
61
63
IDE_PIORDY CN27
IDE_PDD1 1 1 31
NP_NC1
GND1
IDE_PDDREQ IDE_PCSEL 31 FLP_STEP#
2 2 32
1
22 IDE_PDDREQ IDE_PDD0 32 SATA_DET_#2 22,25
G
3 3 33 33
1
S 2
22 IDE_PIORDY 22 IDE_PDIOR# 34 BAYDOCK_IN# 32
2
R814 FLP_TRK0#
D
22 IDE_PDIOW# 5 5 35 35
R826 Q146 6 6 36 SATA_SWAP_TXN2
FLP_WDATA# 2 1
22 IDE_PDDACK# 36 SATA_SWAP_TXP2 SATA_ICH_RXN2 22
470Ohm 2N7002 7 7 37 FLP_WP# C801 2 1
5.6KOhm 1 1 IDE_PDIAG
37 3900PF/50V C800
SATA_ICH_RXP2 22
G
8 8 38 38
/* IDE_IRQ14 T167 FLP_RDATA# 3900PF/50V
2
9 9 39
3
22 IDE_PDA2 10 10 40 40 SATA_SWAP_RXP2 22
4 Q145 11 11 41 FLP_HDSEL# 4
2N7002 41 IDE_PDD15
22 IDE_PDCS3# 12 12 42 42
13 13 43 IDE_PDD2
22 IDE_PDA1 43 IDE_PDD14
FLP_DR0# 14 14 44
44 IDE_PDD3
22 IDE_PDA0 15 15 45 45
2 1 16 16 46 IDE_PDD13
+3VS 46 IDE_PDD4
R832 100KOhm 17 17 47
22 IDE_PDCS1# 47 IDE_PDD12
FLP_DSKCHG# 18 18 48
IDE_PDASP# 48 IDE_PDD5
19 19 49 49
1 2 BAY_IN0 20 20 50 IDE_PDD11
43 HDD_LED_EN 30 BAY_IN0 IDE_PCSEL 50 IDE_PDD6
R828 1KOhm 21 21 51
FLP_DRATE0 PIN22_+5V_PH 51 IDE_PDD10
22 22 52 52
3 23 23 53 IDE_PDD7
D 53
D57 FLP_MTR0# 24 24 54 IDE_PDD9
IDE_PDASP# 54 IDERST#_5S
2 25 25 55 55
Q147 1 3 FLP_3MODE# 26 26 56 IDE_PDD8
2N7002 G FLP_INDEX# 56 CD_GND_A
S 2 1 27 27 57 57
NP_NC2
FLP_DIR# 28 28 58 CD_GND_A
58 CD_GND_A 33
GND2
DAP202K 29 29 59 CD_L_A
BAY_IN1 59 CD_R_A CD_L_A 33
30 BAY_IN1 30 30 60 60 CD_R_A 33
1 2 BTOB_CON_60P
IDE_BDASP# 27
62
64
D58 1SS355
5 /* CD_L_A 2 1 5
R809 10KOhm
22 SATALED# CD_R_A 1 2 CD_GND_A
R808 10KOhm
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 28 OF 63 SWAP BAY RELEASE DATE : M.Y.
A B C D E
A B C D E
1 1
R2.0#4
2 1 USB_OC#0 23,25
R981 10KOhm
1
/* C905
0.01UF/16V
/*
2
2 1
R191 0Ohm
/*
USB *1 port For EMI
2 1 FLG#: OD U51 +5V
R193 0Ohm L50 5 4 528: EN#
/* +5V_USB0 +5VUSB_0 FLG EN#/EN
1 2 6 OUT_3 IN_2 3
7 OUT_2 IN_1 2
80Ohm/100Mhz 8 1
OUT_1 GND
4
CN11
1
L49 5 SIDE_G1 7 + G528P1U C204 C903
1
2 180Ohm/330mA 1 VCC SIDE_G3 C203 CE28 2
USBP0-_3 2 DATA0- (Iset = 1.4A) 1UF/10V 10UF/10V
23 USB_PN0 USBP0+_3 0.1UF 150UF/6.3V /*
2
23 USB_PP0 3 DATA0+
2
4 GND
6 SIDE_G2 8
SIDE_G4
USB_CON_1X4P
Co-Layout 2
R982
1
10KOhm
USB_OC#12 23,25
1
/* C906
0.01UF/16V
/*
2
2 1
R530 0Ohm
/*
USB *2 ports For EMI U1
+5V
2 1 L1 5 4
R531 0Ohm +5V_USB12 +5VUSB_12 FLG EN#/EN
1 2 6 OUT_3 IN_2 3
/* 7 2
80Ohm/100Mhz OUT_2 IN_1
8 OUT_1 GND 1
2
1
3 10 C3 C2 + G528P1U C4 C904 3
L77 CN17 CE21
180Ohm/330mA 0.1UF 0.1UF (Iset = 1.4A) 1UF/10V 10UF/10V
USBP1-_3 GND4
150UF/6.3V /*
2
23 USB_PN1 8 GND2
USBP1+_3
3
2
23 USB_PP1 7 0P+
6 0P-
5 VCC2
4 GND1
3 1P+
2 1P-
1 VCC1
USBP2-_3
23 USB_PN2 USBP2+_3 GND3
23 USB_PP2
2
USB_CON_2X4P
L76 9
180Ohm/330mA
3
2 1
4 R528 0Ohm 4
/*
2 1
R529 0Ohm
/*
5 5
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 29 OF 63 USB PORTS RELEASE DATE : M.Y.
A B C D E
A B C D E
1 1
+3VS
1
C793 C790 C792 C773 C782
SYSOPT0=1, SYSOPT1=0 --> 0x004e
SYSOPT0=0, SYSOPT1=1 --> 0x162e 10UF/10V 0.1UF 0.1UF 0.1UF 0.1UF
2
SYSOPT0=1, SYSOPT1=1 --> 0x164e
+3VS +3VS
2 2
2 1 SYSOPT0 2 1 1 2 RN30A DSRA#
10KOhm CTSA#
R793 10KOhm /* R792 10KOhm 3 4 RN30B
SYSOPT1 10KOhm RIA#
2 1 2 1 5 6 RN30C
10KOhm DCDA#
R806 10KOhm /* R807 10KOhm 7 8 RN30D
10KOhm
Super I/O
DCDA#
RIA#
+3VS SYSOPT1
CTSA#
T162
SYSOPT0
DSRA#
FIR_SEL 22,25,31
21,22,31,32,43 LPC_AD0 IR_RXD 31
1
IR_TXD 31
+3VS +3VS +3V
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
3 U54 3
1 48 R794 1 2 0Ohm
LAD0
DLAD0
VSS6
GP37
VCC5
nDCD1
nRI1
nDTR1/SYSOPT1
nCTS1
nRTS1/SYSOPT0
nDSR1
TXD1
RXD1
IRMODE/IRRX3
IRRX2
IRTX2
DLAD1 VTR
21,22,31,32,43 LPC_AD1 2 LAD1 nIO_PME 47
3 46 1 T327 R795 1 2 0Ohm /*
DLAD2 GP36
21,22,31,32,43 LPC_AD2 4 LAD2 VSS5 45
5 VCC1 GP35 44 OVER_CLK2 12
6 DLAD3 GP34 43 OVER_CLK1 12
21,22,31,32,43 LPC_AD3 7 LAD3 VCC4 42 +3VS
8 41 1 T158
VSS1 GP33 T155
9 DLPC_CLK_33 GP32 40 1
10 39 1 T160
LPC_CLK_33 GP31 T157
11 DLDRQ1# GP30 38 1
12 LDRQ1# VSS4 37
13 36 802_EN#
GP12/IO_SMI#
DLFRAME# GP17 802_EN# 39
GP13/IRQIN1
PCI_RESET#
21,22,31,32,43 LPC_FRAME# 14 LFRAME# GP16 35 DJKEY_EN 44
DSER_IRQ
DSIO_14M
15 34 BAY_RST
SER_IRQ
BAY_RST 28
SIO_14M
PCI_CLK
nDCLKRUN GP15
LDRQ0#
LPCPD#
16 33 1 T328
21,22,25,32,37,39,40 PM_CLKRUN# nCLKRUN GP14/IRQIN2
VCC2
VCC3
VSS2
GP10
GP11
VSS3
LPC47N207
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
+3VS
4 4
1
SW_RST#
CLK_SIOPCI 21,22,25,32,40 INT_SERIRQ CLK_SIOPCI SW_RST# 23
12 CLK_SIOPCI
T159
6,8,21,22,23,28,31,32 BUF_PLT_RST#
12 CLK_SIO14 BAY_IN1 28
1
C788
21,22,25 LPC_DRQ#0 BAY_IN0 28
5PF
/*
2
21,22,25 PM_SUS_STAT# 2 1
R810 0Ohm /*
+3VS +3VS
5 5
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 30 OF 63 SUPER I/O (LPC47N207) RELEASE DATE : Alice Shih
A B C D E
A B C D E
+3VS
1
C701 C691 C697
2
U49 +3VS +3VSUS
2
R722 1 2 100Ohm 2 25
6,8,21,22,23,28,30,32 BUF_PLT_RST# RST# VCC1
32 R707 R708
VCC2 10KOhm 10KOhm
12 CLK_FWHPCI 31 CLK VCCA 27
/*
R731 2 1 10KOhm FWH_FGPI4 30 FGPI4
1
C692 2 RN25A FWH_FGPI3
1
1 10KOhm 3 FGPI3 TBL# 8
3 4 RN25B FWH_FGPI2 4 7
10KOhm FWH_FGPI1 FGPI2 WP# FWH_WP# 22,25
10PF 5 6 RN25C 5
10KOhm FWH_FGPI0 FGPI1
/* 8 RN25D
2
7 10KOhm 6 FGPI0 FWH4 23 LPC_FRAME# 21,22,30,32,43
FWH3 17 LPC_AD3 21,22,30,32,43
T104 1 9 15
ID3 FWH2 LPC_AD2 21,22,30,32,43
FWH
T286 1 10 14
ID2 FWH1 LPC_AD1 21,22,30,32,43
43 DIS_FWH 11 ID1 FWH0 13 LPC_AD0 21,22,30,32,43
T103 1 12 ID0
2 IC 29 2
boot device ID[3:0]=0000
Int. PD 16 GND1 RSVD5 22
2
26 GND2 RSVD4 21
28 20 R733
GNDA RSVD3 10KOhm
RSVD2 19
RSVD1 18
(PD: FWH mode)
1
SST 49LF004A-33-4C-N
3 3
W=40mil
1 2 IR_LEDA
+3VS
R815 2.7Ohm
1
10
4.7U 0.1UF 470P U55
2
LEDA
IR_TXD 9
30 IR_TXD TXD
IR_RXD 8
30 IR_RXD RXD
6 NC
4 MD0
5 MD1
AGND
SHLD
GND
VCC
HSDL-3600
11
+3VS
7
2
1
3.3VS: IR_LEAD = 750mA
Isupply = 5mA
1
C786
0.47U
2
5 5
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 31 OF 63 FIR & FWH RELEASE DATE : Alice Shih
A B C D E
A B C D E
2
C84 KSI7 9 KSO13
10KOhm 5 +3V 14 14
RP7H 10 15 KSI0
15
+3V
EC should set OP_SD 5PF
16 16 KSO2
/* KSO4
low in S3,
1
17 17
18 KSO8
keep from leakage. 18
RN2C
RN2D
KSO6
RN2A
RN2B
19 19
1 2 20 KSO11
+3V 20
C88 0.1UF KSO10
10
10
10
10
10
10
10
10
21 21
2
5
22 KSO12
22
2
4
6
8
R107 U8 KSO14
1 2 23
3 10KOhm
2 10KOhm
1 10KOhm
4 10KOhm
6 10KOhm
7 10KOhm
8 10KOhm
9 10KOhm
C97 0.1UF 23 KSO15
10KOhm
10KOhm
10KOhm
10KOhm
21,22,25,30,40 INT_SERIRQ 63 P87/SERIRQ 24 24
470KOhm 64 25
12 CLK_KBCPCI P86/LCLK 25
65 71 26 KBDDT0
6,8,21,22,23,28,30,31 BUF_PLT_RST# P85/LRESET# VCC 26 KBDDT0 23,25
1
RP1A
RP1E
RP1F
RP1G
KBDDT1
RP1C
RP1D
RP1H
21,22,30,31,43 LPC_AD3 67 P83/LAD3 28 28 KBDDT1 23,25
1
3
5
7
21,22,30,31,43 LPC_AD2 68 P82/LAD2 VREF 72 GND2 30
21,22,30,31,43 LPC_AD1 69 P81/LAD1
21,22,30,31,43 LPC_AD0 70 P80/LAD0
31 1 T40 ZIF_FPC_28P_KB
P27 NUM_LED#
35
P54,P55,P43,P50 are P26 32
33 CAP_LED#
NUM_LED# 45
44 MSK_INSTKEY# P23 P25 CAP_LED# 45
55 BAT_LEARN BAT_SEL
36 P22 wake-up event P24 34 SET_PCIRSTNS# 23 KBDDT1 KBDDT0 Matrix
1 2 37
47 KBCRSM
R152 1MOhm 38
P21 inputs when KBC in 1 1 US
P20 1 0 UK
standby mode P17/KSO15 39 KSO15
KSO14
P16/KOS14 40 0 1 JP
46 WATCHDOG 23 41 KSO13
P42/INT0 P15/KSO13 KSO12
44 SWDJ_EN# 22 P43/INT1* P14/KSO12 42
KBCPURST_3Q 21 43 KSO11
KBC_GA20 P44/RXD P13/KSO11 KSO10
20 P45/TXD P12/KSO10 44
KBSCI_3Q 19 45 KSO9
P46/SCLK1 P11/KSO9 KSO8 +3VS
21,22,25,30,37,39,40 PM_CLKRUN# 18 P47/SRDY1#/CLKRUN# P10/KSO8 46
47 KSO7
BAT_LLOW#_KBC P07/KSO7 KSO6
54 BAT_LLOW#_OC 17 P50/INT5* P06/KSO6 48
KSO5
1
43,44 DJ_LED_EN 16 P51/INT20 P05/KSO5 49
15 50 KSO4
43 WIRELESS_LED# P52/INT30/1-WIRE1 P04/KSO4
10K
KSO3
R
3 43 BAT_LOW#_KBC 14 P53/INT40/1-WIRE2 P03/KSO3 51 KSO3 44 3
13 52 KSO2
28 BAYDOCK_IN# P54/CNTR0* P02/KSO2 KSO1
B
56 BAT1_IN#_OC 12 P55/CNTR1* P01/KSO1 53
11 54 KSO0
46 FAN_DA P56/DA1/PWM01 P00/KSO0 KBSCI_3Q
20 ADJ_BL 10 P57/DA2/PWM11 KBDSCI_3 22,25
2
E
C
3
55 KSI7
P37/KSI8 KSI6 Q33
56 BAT2_IN#_OC 74 P67/AN7 P36/KSI7 56 KSI6 44
75 57 KSI5 DTC114TKA
44 PANLOCK_# P66/AN6 P35/KSI6 KSI5 44
76 58 KSI4
44 MARATHON_# P65/AN5 P34/KSI5 KSI4 44
56 ACIN_OC 77 P64/AN4 P33/KSI4 59 KSI3
KSI3 44 R1.1#17
78 60 KSI2
44 WIRELESS_# P63/AN3 P32/KSI3
79 61 KSI1
46 CPUFAN_SPD_A P62/AN2 P31/PWM10/KSI2
80 62 KSI0 X1_KBC 1 2
44 INTERNET_# P61/AN1 P30/PWM00/KSI0
1 C93 5PF
44 BT_# P60/AN0
2
28 X1_KBC
XIN X2_KBC R97
XOUT 29 3
R1.1#29 KBDCLK_5S 4 P75/INT41 R1.1#29 X1
MOUSECLK_5S 5 27 KBC_EXTSMI 1MOhm 8MHZ
INTCLK_5S P74/INT31 P40/XCOUT /*
44 INTCLK_5S 6 P73/INT21 P41/XCIN 26 BT_LED# 38,43,45
KBDDATA_5S X2_KBC
1
7 P72 1 2
MOUSEDATA_5S 8 C78 5PF
INTDATA_5S P71
44 INTDATA_5S 9 P70 RESET# 25 PCI_RSTNS# 23,37
4 R2.0#5 SMC_BAT_KBC
SMD_BAT_KBC
2 P77/SCL CNVSS 24 4
3 P76/SDA VSS 30
AVSS 73
+3VALWAYS +3VSUS
M38857 80mA
2 RN11A 110KOhm SMDATA_BAT1
1
4 RN11B 3 10KOhm SMDATA_BAT2
6 RN11C 510KOhm SMCLK_BAT1 +5VS R161
8 RN11D 7 10KOhm SMCLK_BAT2
10KOhm
+5VS +3VS
+5V
RN9C
RN9D
RN9A
RN9B
2
EXTSMI#_3A 22
U10
BAT_SEL 1 16
S VCC
2
SMCLK_BAT2 2 15 3
54,58 SMCLK_BAT2 IA0 E# D
2
4
6
8
4 YA ID1 13
2
1
SMD_BAT_KBC KBC_GA20
2
1
7 YB IC1 10 6 1 HA20GATE 22
8 9 R162
GND YC
5
Q28A
1
3
5
7
2
KBDDATA_5S Q28B
KBDCLK_5S UM6K1N
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 32 OF 63 KBC (M38857) RELEASE DATE : M.Y.
A B C D E
5 4 3 2 1
+5VA
T394
G913C: Vo=Vref(=>1.25V)*[1+(R_H/R_L)]
22,34,40,43,47,54,57 PM_SUSB#
U33
1
+5V >30 mil or shape
1 SHDN# SET 5 2 1
L68 2 C454 2200P
GND
1 2 +5V_AUD 3 IN OUT 4 2 1 R2.1
R487 100KOhm
2
80Ohm/100Mhz 0.1%
2
C471 C469 G913C R477 C457 C461 C462
D 34.8KOhm D
10UF/10V 0.1UF 1% 10UF/10V 0.1UF 0.1UF
1
1
1 2
DIGITAL R511 0Ohm
34K/1% for MAX8863
34.8K/1% for G913C AGND_A
1
C486
34 EPAD AGND_A AGND_A
10UF/10V
2
34 SPDIF
+3VS
48
47
46
45
44
43
42
41
40
39
38
37
AGND_A
U61
SPDIFO
SPDIFI/EPAD
SURRBACK_OUT_R
SURR_OUT_R
JDREF/NC
LINE1_VREFO_R
SURRBACK_OUT_L
LFE_OUT
AVSS2
SURR_OUT_L
AVDD2
CEN_OUT
1
2
C883 C863 C874
C C
10UF/10V 0.1UF 0.1UF Pin35/36: default OP ON
/*
2
1
LINE_OUT_R C865 2 1 1UF/10V OUTR_A 34
R2.1
1 DVDD1 FRONT_OUT_R 36
2 35 LINE_OUT_L C860 2 1 1UF/10V
34 AUD_GPIO0 GPIO0 FRONT_OUT_L OUTL_A 34
T388 1 3 34
GPIO1 Sense_B
4 DVSS1 DCVOL 33
22 ACZ_SDOUT_AUD 5 SDATA_OUT MIC1_VREFO_R 32
22 ACZ_BCLK_AUD 6 BITCLK LINE2_VREFO 31
7 DVSS2 MIC2_VREFO 30
22 ACZ_SDIN0 1 2 8 SDATA_IN LINE1_VREFO_L 29
R918 33Ohm 9 28
DVDD2 MIC1_VREFO_L VREFOUT 34,35
22 ACZ_SYNC_AUD 10 SYNC VREF 27
22,34 ACZ_RST#_AUD 11 RESET# AVSS1 26
12 PCBEEP AVDD1 25 +5VA
1
1
C879 C475 C854 C849
CD_GND
1
Sense_A
LINE2_R
LINE1_R
LINE2_L
LINE1_L
C888
MIC2_R
MIC1_R
MIC2_L
MIC1_L
CD_R
10PF 10UF/10V 0.1UF 1UF/10V
CD_L
/* 10UF/10V /*
2
2
2
ALC861-VS
13
14
15
16
17
18
19
20
21
22
23
24
AGND_A
2 1
C838 1UF/10V
B B
34 PCBEEP
2 1 MIC_A 35
R1.1#22 C842 1UF/10V
1 2 R506 1 2 1KOhm 2
40 SPKRCB
C487 0.1UF 3 2 1 2 1 1 2 CD_R_A 28
1 C474 1UF/10V C841 1UF/10V R890 47KOhm
1
1 2 R503 1 2 1KOhm
22,25 ICH_SPKR
C480 0.1UF D36 R891
DAN202K 47KOhm
1
2
10KOhm 10KOhm 10KOhm
AGND_A
2
2 1 1 2 CD_GND_A 28
C840 1UF/10V R889 47KOhm
1
R888
47KOhm
2
AGND_A
2 1 1 2 CD_L_A 28
A
C839 1UF/10V R894 47KOhm A
1
R887
47KOhm
2
AGND_A
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 33 OF 63 Azalia AUDIO (ALC861-VS) RELEASE DATE : Alice Shih
5 4 3 2 1
A B C D E
+5VAMP +5VS
AUDIO AMP 1
L57
2
80Ohm/100Mhz
1
C448 C452 C481 C453
+5VAMP +5VAMP
GAIN0 GAIN1 SE/BTL# AV (V/V) 10UF/10V 0.1UF 0.1UF 0.1UF
+5VAMP +5VS
2
0 0 0 -2
1
Q159 U62 0 1 0 -6
SI2301DS
33 SPDIF 1 A VCC 5 R499
1 0 0 -12
1 10KOhm AGND_A 1
1
1 1 0 -24
2 3 OPTIC_VCC 2 B C464
3 D
X X 1 -1
2
1
1
SPDIF_O GAIN1 1UF/10V
2
3 GND 4
1
OPTIC_HP R865 C880 R935 Y
2
11
2
NC7SZ08M5
100KOhm 0.1UF 100KOhm R498
1
AGND_A
G
DIGITAL 0Ohm
2
JACK_IN# OPTIC_VCC_EN# /*
2
2 S
R2.0#13
D
U34
Q160 GAIN0
1
1 GND1 GND4 24
1
2
10 15 SE/BTL# 1 2
R509 LIN SE/BTL# R485 10KOhm R481
11 BYPASS PC-BEEP 14
30KOhm 12 13 30KOhm
GND2 GND3
2
C482 C483 C484 2 1 PCBEEP 33
2 TPA0212 C455 1UF/10V 2
0.47U 0.47U 0.47U /* R1.1#22
1
1
1
AGND_A AGND_A AGND_A AGND_A AGND_A
HEADPHONE/SPDIF +5VAMP
OPTIC_HP# JACK_IN# STATE
+3V
0 0 LINE_OUT : OPTIC VCC OFF R2.1
1
1
1 0 SPDIF_OUT : OPTIC VCC ON
2
R492 R504
1 1 NC : OPTIC VCC OFF 2 1 D60 R868
22,33,40,43,47,54,57 PM_SUSB#
10KOhm 10KOhm R1012 0Ohm DAP202K 100KOhm
2 1 1 /* 2 1 DEPOP#
33 AUD_GPIO0
PHONE_JACK_8P_SPDIF R1013 0Ohm /* D59 1SS355
2
3
CN16 L65 1 2 1KOhm/100MHz JACK_IN#
1
5 2
1
EARL_C 22,25 OP_SD#
1 EARL MUTE
G
4 2 1 2
EARL__J L75 1 2 1KOhm/100MHz EARL__R R971 1 2 33Ohm R507 2 1 33Ohm C878 47UF/6.3V R879 1.5MOhm SE/BTL# HP_IN
+
2
S 2
1
EARR_J L67 1 2 1KOhm/100MHz EARR_R R967 1 2 33Ohm R497 2 1 33Ohm EARR_C 1 EARR C418
D
3 2
L74 1 2 1KOhm/100MHz OPTIC_HP C858 47UF/6.3V Q60 3
+
1 D
3
2
1 2 1UF/10V 2N7002 3
22,33 ACZ_RST#_AUD
2
2
E
R505 R496 2SC5376F 1 2 MUTE 3
D R2.1 2N7002 1 JACK_IN#
/* 1 B R966 1KOhm G
S 2
1KOhm 1KOhm /*
2 C
11
12
E 3 1
33 EPAD
Q188 Q197G
1
1 2 S
2SC5376F R965 1KOhm 2N7002 2
1 B
+3VALWAYS +12V AGND_A
/* /* /*
C
3
AGND_A
R1.1#23
2
SPKR+
10mA D35 RB751V_40 GND_AUDJACK 1 2 R446 R445
8 OPTIC_VCC_J L70 1 2 1KOhm/100MHz OPTIC_VCC_D 2 1 OPTIC_VCC L116 120Ohm/100Mhz 100KOhm 4.7MOhm S 2
AGND_A
7 L73 1 2 1KOhm/100MHz SPDIF_O G
R2.0#17 Q163
1
2N7002
1
AGND_A
10
For EMI
9
6
1 2 D
1
1
GND_AUDJACK 1 2 Q57 C830 EARR
1
1 2
L115 1 2 120Ohm/100Mhz R960 0Ohm Q58 G
2
4 0Ohm 1 2 1 2N7002 2 S S 2 4
G
R881 0Ohm G
2 S 1 Q162
2
AGND_A 1 2
GND_AUDJACK R493 0Ohm 2N7002
D
For EMI
3
AGND_A
EARL
2
C6 C5
100PF 100PF 100PF 1 2 CP3A WtoB_CON_4P_SPEAKER
150PF
/* /* CP3B For EMI 100PF 100PF
1
5 3 150PF 4 5
GND_AUDJACK CP3C /* /*
1
5 150PF 6
7 150PF 8 CP3D R1.1#24
R2.0#17 For EMI
/*
AGND_A
bom AGND_A
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 34 OF 63 AUDIO AMP / JACKS RELEASE DATE : Alice Shih
A B C D E
A B C D E
E E
VREFOUT 2 1 +5VMIC
C465 220PF /*
5
1 2 4490_POS 1 V+
+ MIC_A
R494 75KOhm /* 4
4490_NEG 3 -
V-U32
2
MAX4490AXK
2
C466 R495 /*
2
2.2KOhm
0.01UF /*
/*
1
AGND_A
1
D D
MIC_JACK
2
C467
1 2
1UF/10V R488 56KOhm /*
/*
1
2 1
C459 220PF /*
AGND_A
C 2 1 C
R886 100KOhm
1 2
R491 100KOhm
L114 +5VA
AGND_A
U59 120Ohm/100Mhz
4490_POS 3 A+ + VCC 8 +5VMIC 1 2
1 2 1 2 1 MIC_A
1
C843 39P 4490_NEG 2 A- - AO R478 0Ohm C833
/*
33,34 VREFOUT 2 1 5 B+ + 0.1UF
R898 270KOhm BO 7
2
1
6 B- - GND 4
2
R2.1 R896
1
12
+5VMIC C844
1
1
1UF/10V
R958
2
B B
1KOhm AGND_A AGND_A AGND_A 2 1
/* R892 270KOhm
2
34 MIC_JACK 1 2 2 1 1 2 MIC_A 33
C456 0.1uF/10V R893 10KOhm C835 39P
1
R959
1KOhm
/*
2
AGND_A R2.1
A A
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 35 OF 63 MIC AMP RELEASE DATE : Alice Shih
A B C D E
A B C D E
E E
3
+5VS
Q51A Q51B
1
2 UM6K1N 5 UM6K1N
/* /* R381 R380
+5VS
4
4.7KOhm 4.7KOhm
2
2
22,25 SCL_3A 6 1 SCL_3S 6,12,13,14,19,21 System Thermal Sensor
ATI Thermal Sensor
D D
Q52A
UM6K1N
Clock Generator
ICH6-M
DDR2 SO-DIMM
5
3 4 TPM
22,25 SDA_3A SDA_3S 6,12,13,14,19,21
Q52B
UM6K1N
+VPPCB +VPPCB 41
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 36 OF 63 SMBUS RELEASE DATE : M.Y.
A B C D E
A B C D E
2.5V_CTL
1
+3VSUS 1 2 R116 25mil T395
+2.5V_LAN
Q18 R639 1 2 2.7KOhm Y8K_REQ64# L31 120Ohm/100MHz 4.7KOhm
1 B
1
2
G
2N7002 C658 C570 C588 C572 C634 C568 /* Q26
LAN_REQ# R653 1 2 27Ohm ZN_REF HM772
2 S
3
1 23,25 PCI_REQ#0 1
ZP_REF +3V_LAN_ANALOG
D
R655 1 2 33Ohm 10UF/10V 0.1UF 0.1UF 0.1UF 1000P 1000P
1
+3V 1 2
3
E
C
2
L30 120Ohm/100Mhz
1
R63 0Ohm /* C90 C92 C98 C651 C108 C659 C609
2 1
ZP_REF 10UF/10V 0.1UF 10UF/10V 0.1UF 0.1UF 0.1UF 0.1UF
ZN_REF
2
Y8K_REQ64# 2 1 PM_CLKRUN# 21,22,25,30,32,39,40
R654 0Ohm /*
PCI_AD16 R652 1 2 33Ohm LAN_IDSEL
PCI_DEVSEL# 23,25,39,40
PCI_STOP# 23,25,39,40
12 CLK_LANPCI PCI_IRDY# 23,25,39,40
PCI_TRDY# 23,25,39,40
1
C561
PCI_FRAME# 23,25,39,40
10P
PCI_PAR 23,39,40
/*
2
+1.5V_LAN +3VS
23,25,39,40 PCI_PERR#
PCI_AD19 1.5V_CTL
PCI_AD20
23,25,39,40 PCI_SERR# LAN_REQ#
2 PCI_AD21 place PNP to chip ACAP 2.5V_CTL pin trace is 25MIL 2
PCI_AD22
23 PCI_GNT#0
PCI_AD23
1
PCI_AD18
PCI_AD17 PCI_AD24
PCI_C/BE#3 23,39,40
R163 25mil
PCI_AD16 PCI_AD25 1 2 4.7KOhm +1.5V_LAN
+3VSUS T396
PCI_AD26 L40 120Ohm/100MHz
1 B
23,39,40 PCI_C/BE#2
PCI_AD27 /* Q34
23,39,40 PCI_C/BE#1
HM772
2
+3V_LAN_DIGITAL
1
+3V 1 2
102
101
100
3
E
C
2
U44 L41 120Ohm/100Mhz
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
23,39,40 PCI_AD[31:0]
1
C173 C168 C76 C164 C571 C586 C662 C660
PAR
CBE_[2]n
CBE_[3]n
CBE[1]n
AD16
AD17
AD18
VDDO_PCI4
VDD9
GNTn
REQn
SERRn
ZP_REF
ZN_REF
VDDO_PCI5
PERRn
CLK_RUNn
VDD10
IDSEL
DEVSELn
STOPn
IRDYn
TRDYn
VDDO_PCI6
FRAMEn
VDD11
AD19
AD20
AD21
AD22
VDDO_PCI7
AD23
AD24
AD25
AD26
VDDO_PCI8
AD27
CLK
PCI_AD15 103 10UF/10V 0.1UF 10UF/10V 10UF/10V 0.1UF 0.1UF 0.1UF 0.1UF
AD15 /*
2
+1.5V_LAN 104 VDD0
PCI_AD14 105 64 PCI_AD28
PCI_AD13 AD14 AD28 PCI_AD29
106 AD13 AD29 63
+3VS 107 VDDO_PCI0 VDDO_PCI2 62
PCI_AD12 108 61
AD12 VDD2 +1.5V_LAN
PCI_AD11 109 60 PCI_AD30
PCI_AD10 AD11 AD30 PCI_AD31 +3VS +1.5V_LAN
110 AD10 AD31 59
111 M66EN VDDO_PCI3 58 +3VS
3 PCI_AD9 112 57 3
AD9 PMEn PCI_RSTLAN# PCI_PME# 23,25,39,40
23,39,40 PCI_C/BE#0 113 CBE_[0]n RSTn 56
PCI_AD8 114 55
AD8 VIOB
2
PCI_AD7 115 54 C563 C661 C569 C663
AD7 INTAn PCI_INTC# 23,25,39,40
116 VDDO_PCI1 TSTPT 53
PCI_AD6 117 52 1000P 1000P 1000P 1000P
PCI_AD5 AD6 AVDDL0 L_TRDM3
1
118 AD5 MDIN[3] 51 L_TRDM3 38
PCI_AD4 119 50 L_TRDP3
AD4 MDIP[3] L_TRDP3 38
PCI_AD3 120 49
PCI_AD2 AD3 AVDDL1 L_TRDM2
121 AD2 MDIN[2] 48 L_TRDM2 38
PCI_AD1 122 47 L_TRDP2
AD1 MDIP[2] L_TRDP2 38
PCI_AD0 123 46
AD0 HSDACN
124 VDD1 HSDACP 45
125 44 +3V_LAN_ANALOG 1 2
NC0 AVDDH PCI_RST# 23,28,39,40
LAN_EECLK 126 43 2.5V_CTL R62 0Ohm
VPD_CLK CTRL25
1
LAN_EEDATA 127 42 C115 PCI_RSTLAN#
VPD_DATA AVDDL2 L_RDN
128 41 L_RDN 38
LED_LINK1000n
0.1UF
LED_LINK100n
VAUX_AVLBL
2
VDDO_TTL0
VDDO_TTL1
VDDO_TTL2
VDDO_TTL3
39
LED_STATn
TESTMODE
AVDDL3 +2.5V_LAN
SWITCH[1]
SWITCH[0]
LED_RXn
LED_TXn
SPI_CLK
AVDDLF
CTRL15
SPI_DO
MDIN[0]
MDIP[0]
SPI_CS
XTALO
TRSTn
XTALI
VSSC
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
RSET
TDO
TMS
TCK
NC1
TDI
4 4
88E8001
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
1
2
3
4
5
6
7
8
9
+2.5V_LAN L_TDN
+1.5V_LAN L_TDP L_TDN 38 L_TDP R136 1 2 49.9Ohm C131 1 2 1000P
L_TDP 38 L_TDN
1.5V_CTL R135 1 2 49.9Ohm
LAN_RSET 1 2 L_RDP R139 1 2 49.9Ohm C136 1 2 1000P
+3V_LAN_DIGITAL R141 2.49KOhm L_RDN R131 1 2 49.9Ohm
XIN_LAN
R1.1#13 L_TRDP2 R122 49.9Ohm
1 2
U13 X7 L_TRDM2 R113 1 2 49.9Ohm C117 1 2 1000P
+3V_LAN_DIGITAL 8 1 XOUT_LAN 1 2 L_TRDP3 R110 1 2 49.9Ohm
VCC A0 L_TRDM3 R108 49.9Ohm C109 1
7 WP A1 2 1 2 2 1000P
1
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 37 OF 63 PCI GIGA LAN (88E8001) RELEASE DATE : Alice Shih
A B C D E
A B C D E
BT
[ACZ_SDOUT/SYNC/BITCLK/RST#]: +3V +3VS
Azalia MDC MODEM ICH6: 39 ohm to Audio / 39 ohm to MDC
[ACZ_SDIN]:
R1.1#10
1
1 1
R944
2
0Ohm 2 Q179
S
/* R943 SI2301DS R2.0#3
2
0Ohm 11
G BT_LED# 32,43,45
/*
D 3
3
1
C895 R1.1#37
CN20 CN33
13
15
17
19
BTOB_CON_12P 0.1UF GP5 2 1
/* 2 1
2
4 3
GND1
GND3
GND5
NP_NC2 NP_NC1
+3V 4 3
1 1 2 2 6 6 5 5
3 4 U70 8 7 GP1
22 ACZ_SDOUT_MDC 3 4 8 7
5 6 1 2 1 8 BT_VCC 10 9
5 6 R595 0Ohm GP5 1 8 GP0 GP0 10 9
22 ACZ_SYNC_MDC 7 7 8 8 2 2 7 7 12 12 11 11
1 2 9 10 GP4 3 6 GP1 14 13
22 ACZ_SDIN1 9 10 3 6 14 13
1
GND2
GND4
GND6
R600 33Ohm 11 12 4 5 C894 16 15
22 ACZ_RST#_MDC 11 12 ACZ_BCLK_MDC 22 39 BT_DATA 4 5 16 15
1
C513 GP4 18 17
18 17 USB_PN3 23
PIC12C508 0.1UF 20 19
0.1UF /* 20 19
2
14
16
18
20
AXK5F20545Y
2
2 39 BT_CLK 2
USB_PP3 23
1
1 2 P_GROUND2 16
C128 1000PF L96 LTRLM3 8 18
200Ohm LTRLP3 TRLM3 NP_NC2
7 TRLP3
/* LRXN 6
L_TXP LTXP LTRLM2 RXN
4
5 TRLM2
Co-Layout LTRLP2 4
LRXP TRLP2
3
L_RXN LRXN Reserved for EMI LTXN 2
RXP
LTXP TXN
PLACE NEAR RJ45 1 TXP
1
U46 L95
12 13 L_TXP 200Ohm
37 L_TDP TRD0P MTRD0P L_CMT
10 15 /* 14
CTRD0 MCTRD0 L_TXN L_RXP 3 LRXP RING_J NC2
4
37 L_TDN 11 TRD0N MTRD0N 14 13 RING2
9 16 L_RXP 12
37 L_RDP TRD1P MTRD1P L_RXC RING1
7 18 TIP_J 11
CTRD1 MCTRD1 L_RXN TIP2
37 L_RDN 8 TRD1N MTRD1N 17 10 TIP1
6 19 L_TRLP2 9 17
37 L_TRDP2 TRD2P MTRD2P L_CMT2 NC1 NP_NC1
4 4 CTRD2 MCTRD2 21 P_GROUND1 15 4
5 20 L_TRLM2 L_TRLM2 LTRLM2 19 CHASSIS_GND
37 L_TRDM2 TRD2N MTRD2N L_TRLP3 GND1
37 L_TRDP3 3 TRD3P MTRD3P 22
2
1 24 L_CMT3 MODULAR_JACK_14P
CTRD3 MCTRD3 L_TRLM3 L93 CN23
37 L_TRDM3 2 TRD3N MTRD3N 23
200Ohm 2 4
1GB /* 2 SIDE2
RDC L_TRLP2 LTRLP2 L43 1 2 1KOhm/100MHz TIP
3
+2.5V_LAN RING
Co-Layout L42 1 2 1KOhm/100MHz 1 3
1 SIDE1
1
1
0.1UF 0.1UF 0.1UF 0.1UF C176 C171 fpc_con_2p_modem
2
1
2
2
PLACE NEAR TRANSFORMER /* CHASSIS_GND
L_TRLP3 LTRLP3
3
L_TRLP2 1 2 LTRLP2
L_CMT 7 8 RN8D R699 0Ohm
75Ohm L_TRLM2 LTRLM2
L_RXC 5 6 RN8C 1 2
L_CMT2 75Ohm
3 4 RN8B R696 0Ohm
75Ohm FGND1S L_TRLP3 LTRLP3
5 L_CMT3 1 2 RN8A 1 2 5
75Ohm
R694 0Ohm
1
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 38 OF 63 RJ11+RJ45 / MDC RELEASE DATE : Alice Shih
A B C D E
A B C D E
PCI_AD[31:0]
23,37,40 PCI_AD[31:0]
1 1
Intel PRO/Wireless 2915ABG:
pin11: LED_WLAN_LINK
12: LED_WLAN_ACT
+3VS
13: HW_RadioXMIT_OFF#
14: WLAN_Radio_State# (H:5G/L:2.4G)
+3V
pin11: LED_WLAN_ACT
R18 12: WLAN_Radio_State
10KOhm
/* 13: HW_RadioXMIT_OFF# +3VS
U2
802_LED 1 A
1
VCC 5
125
126
802_EN
CN19 2 1 2 B
3 1 2 R20 0Ohm /*
SIDE1
SIDE2
D TIP RING
3 4 3 GND 4 802_ON
Q7 LAN_RESERV1 LAN_RESERV2 Y
5 LAN_RESERV3 LAN_RESERV5 6
1 2N7002 7 8 NC7SZ08P5X
30 802_EN# LAN_RESERV4 LAN_RESERV7
G /* 9 10 /*
2
2 S 802_ON R19 2 1 0Ohm /* 802_LED 11
LAN_RESERV6 LAN_RESERV10
12 2
43 802_ON LAN_RESERV8 LAN_RESERV12
R13 2 1 0Ohm /* 13 14
LAN_RESERV9 LAN_RESERV13
15 LAN_RESERV11 LAN_RESERV14 16 2 1 PCI_INTC# 23,25,37,40 R1.1#30
17 18 R979 0Ohm /*
23,25 PCI_INTD# INTB# 5V_1 +5VS
19 3.3V_7 INTA# 20 2 1 PCI_INTB# 23,25,40
21 22 R980 0Ohm
RESERVED9 RESERVED3
23 GROUND15 3.3VAUX1 24 +3V
12 CLK_MINIPCI 25 CLK RST# 26 PCI_RST# 23,28,37,40
27 GROUND4 3.3V_3 28
29 30 +3VS
23,25 PCI_REQ#3 REQ# GNT# PCI_GNT#3 23
31 3.3V_4 GROUND7 32
1
C22 PCI_AD31 33 34
AD[31] PME# PCI_PME# 23,25,37,40
PCI_AD29 35 36 R947 2 1 0Ohm
AD[29] RESERVED6 BT_CLK 38
1
5PF 37 38 PCI_AD30 C20 C16 C19 C21 C7 C8 C10
GROUND8 AD[30]
R1.1#10 /* PCI_AD27 R1.1#10
2
39 AD[27] 3.3V_5 40
PCI_AD25 41 42 PCI_AD28 10UF/10V 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
R948 2 AD[25] AD[28]
1 0Ohm PCI_AD26
2
38 BT_DATA 43 RESERVED8 AD[26] 44
45 46 PCI_AD24
23,37,40 PCI_C/BE#3 C/BE[3]# AD[24]
PCI_AD23 47 48 2 1 PCI_AD18
AD[23] IDSEL R21 100Ohm +3V
49 GROUND11 GROUND9 50
PCI_AD21 51 52 PCI_AD22
PCI_AD19 AD[21] AD[22] PCI_AD20
53 AD[19] AD[20] 54
55 GROUND13 PAR 56 PCI_PAR 23,37,40
1
3 PCI_AD17 57 58 PCI_AD18 C26 C24 3
AD[17] AD[18] PCI_AD16
23,37,40 PCI_C/BE#2 59 C/BE[2]# AD[16] 60
61 62 10UF/10V 0.1UF
23,25,37,40 PCI_IRDY# IRDY# GROUND10
2
63 3.3V_8 FRAME# 64 PCI_FRAME# 23,25,37,40
21,22,25,30,32,37,40 PM_CLKRUN# 65 CLKRUN# TRDY# 66 PCI_TRDY# 23,25,37,40
23,25,37,40 PCI_SERR# 67 SERR# STOP# 68 PCI_STOP# 23,25,37,40
69 70 +5VS
GROUND14 3.3V_6
23,25,37,40 PCI_PERR# 71 PERR# DEVSEL# 72 PCI_DEVSEL# 23,25,37,40
23,37,40 PCI_C/BE#1 73 C/BE[1]# GROUND12 74
PCI_AD14 75 76 PCI_AD15
AD[14] AD[15]
1
77 78 PCI_AD13 C11 C525 C9
PCI_AD12 GROUND16 AD[13] PCI_AD11
79 AD[12] AD[11] 80
PCI_AD10 81 82 10UF/10V 0.1UF 0.1UF
AD[10] GROUND1 PCI_AD9
2
83 GROUND2 AD[09] 84
PCI_AD8 85 86
AD[08] C/BE[0]# PCI_C/BE#0 23,37,40
PCI_AD7 87 88
AD[07] 3.3V_1 PCI_AD6
89 3.3V_2 AD[06] 90
PCI_AD5 91 92 PCI_AD4
AD[05] AD[04] PCI_AD2
93 RESERVED4 AD[02] 94
PCI_AD3 95 96 PCI_AD0
AD[03] AD[00]
+5VS 97 5V_2 RESERVED1 98
PCI_AD1 99 100
AD[01] RESERVED2
101 GROUND6 GROUND3 102
4 103 AC_SYNC M66EN 104 4
105 AC_SDATA_IN AC_SDATA_OUT 106
107 108 CODEC_ID#0
CODEC_ID#1 AC_BIT_CLK AC_CODEC_ID0#
109 AC_CODEC_ID1# AC_RESET# 110
111 MOD_AUDIO_MON RESERVED5 112
113 AUDIO_GND2 GROUND5 114
115 S_AUDIO_OUT S_AUDIO_IN 116
117 S_AUDIO_OGND S_AUDIO_I GND 118
119 120
127 POST1
128 POST2
AUDIO_GND1 AUDIO_GND
121 RESERVED7 MCPIACT# 122
123 VCC5A 3.3VAUX2 124 +3V
MINI_PCI
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 39 OF 63 MINIPCI RELEASE DATE : Alice Shih
A B C D E
A B C D E
+3VS
2mA U31A
1
C438 C439 C435
CADR25 J18 AD19/A25 41
10UF/10V 0.1UF 0.1UF J15
CADR24 AD17/A24 41
2
C1 NC2 CADR23 K16 CFRAME#/A23 41
+1.8V L16
CADR22 CTRDY#/A22 41
58mA +3V L18
CADR21 CDEVSEL#/A21 41
1 37mA D1 NC3 CADR20 M16 CSTOP#/A20 41 1
CADR19 N19 CBLOCK#/A19 41,43
1
1
C444 C436 C437 N16 R437
CADR18 RFU/A18 41,43
1
C394 C399 C368 C392 E1 P16 22Ohm
NC4 CADR17 AD16/A17 41
10UF/10V 0.1UF 0.1UF L19 1 2
CADR16 CCLK/A16 41
U31B 10UF/10V 0.1UF 1000PF 1000PF
2
2
CADR15 K15 CIRDY#/A15 41
1
+1.8V_CB C406 SHIELD GND
2
C2 NC5 CADR14 N18 CPERR#/A14 41,43
W3 VCC_PCI3V_1 VCC_3V_1 F5 CADR13 N15 CPAR/A13 41
1 2 R11 J19 K18 5PF
R425 0Ohm VCC_PCI3V_2 VCC_3V_3 CADR12 CBE2#/A12 41 /*
2
R12 VCC_PCI3V_3 VCC_3V_4 K19 D2 NC6 CADR11 R18 AD12/A11 41
1
1
C401 C387 +3V_CB +3V +MC_VCC U19
CADR10 AD9/A10 41
CADR9 R19 AD14/A9 41
0.1UF 0.1UF R6 G5 1 2 E2 P15
VCC_RIN_1 VCC_3V_2 +3V R407 0Ohm NC7 CADR8 CBE1#/A8 41
2
2
E13 VCC_RIN_2 CADR7 J16 AD18/A7 41
1
1 2 L1 C367 1 2 H15
VCC_ROUT_1 CADR6 AD20/A6 41
R458 0Ohm E14 A4 R398 0Ohm /* E4 H18
VCC_ROUT_2 VCC_MD3V NC8 CADR5 AD21/A5 41
2 1 R7 0.1UF G15
REGEN# CADR4 AD22/A4 41
1
R459 100KOhm /* C359 C403
2
CADR3 G18 AD23/A3 41
23,37,39 PCI_AD[31:0] GND1 J1 CADR2 F15 AD24/A2 41
J5 10UF/10V 1000PF F18
GND2 CADR1 AD25/A1 41
PCI_AD31
2
M2 AD31 GND3 K5 CADR0 E16 AD26/A0 41
PCI_AD30 M1 E9
PCI_AD29 AD30 GND4
N5 AD29 GND5 R10 MDIO02--> xD Enable# CDATA15 U18 AD8/D15 41
2 PCI_AD28 N4 T10 W18 2
AD28 GND6 MDIO05--> SD Power1 Control / xD WP# CDATA14 RFU/D14 41,43
PCI_AD27 N2 V10 V17
AD27 GND7 CDATA13 AD6/D13 41
PCI_AD26 N1 W10 MDIO06--> xD/MS/SD LED Control V16
AD26 GND8 CDATA12 AD4/D12 41
PCI_AD25 P5 L15 V15
PCI_AD24 P4
AD25 GND9
M19
MDIO14--> xD Data 4 CDATA11
B19
AD2/D11 41
AD24 GND10 CDATA10 AD31/D10 41
PCI_AD23 R4 AD23 AGND_1 A9 MDIO15--> xD Data 5 CDATA9 C18 AD30/D9 41
PCI_AD22 R2 B9 D18
PCI_AD21 AD22 AGND_2 MDIO16--> xD Data 6 CDATA8 AD28/D8 41
R1 AD21 AGND_3 D9 CDATA7 W17 AD7/D7 41
PCI_AD20 T2 AD20 AGND_4 D14 MDIO17--> xD Data 7 CDATA6 W16 AD5/D6 41
PCI_AD19 T1 A15 W15
PCI_AD18 AD19 AGND_5 +3V
MDIO18--> xD CLE CDATA5 AD3/D5 41
U2 AD18 AGND_6 B15 CDATA4 T15 AD1/D4 41
PCI_AD17 U1 AD17
MDIO19--> xD ALE CDATA3 R14 AD0/D3 41
PCI_AD16 V1 F4 C19
AD16 TEST CDATA2 RFU/D2 41,43
2
Open Drain: PCI_AD15 T7 D19
AD15 CDATA1 AD29/D1 41
PCI_AD14 V7 R387 E19
CLKRUN#, PME#, SERR#, INTn# PCI_AD13 AD14 10KOhm CDATA0 AD27/D0 41
W7 AD13
PCI_AD12 R8 AD12
PCI_AD11 T8 AD11
T360 1 MDIO19 E8 MDIO19 OE# T19 AD11/OE# 41
PCI_AD10 CB_HWSUSP#
1
V8 AD10 HWSPND# F2 1 2 WE# M15 CGNT#/WE# 41
PCI_AD9 W8 AD9
C365 0.1UF T363 1 MDIO18 D8 MDIO18 CE2# T18 AD10/CE2# 41 1 2
PCI_AD8 R9 F1 V19 C393 0.01UF /*
AD8 SPKROUT SPKRCB 33 CE1# CBE0#/CE1# 41
PCI_AD7 V9 F16
AD7 MDIO17 REG# CBE3#/REG# 41
PCI_AD6 W9 2 1 T355 1 B8 H19
AD6 MDIO16 MDIO17 RESET CRST#/RESET 41
3 PCI_AD5 T11 R447 100KOhm T350 1 A8 G16 3
AD5 MDIO15 MDIO16 WAIT# CSERR#/WAIT# 41,43
PCI_AD4 V11 T366 1 E7 A18
AD4 MDIO14 MDIO15 WP/IOIS16# CCLKRUN#/IOIS16# 41,43
PCI_AD3 W11 SPKRCB PD : Use SROM T357 1 D7 M18
AD3 MDIO14 RDY/IREQ# CINT#/IREQ# 41
PCI_AD2 T12 B7 F19
AD2 42 SDD3_MSD3 MDIO13 BVD2 CAUDIO/SPKR_IN#/BVD2 41,43
PCI_AD1 V12 G1 1 A7 E18
AD1 UDIO5 42 SDD2_MSD2 MDIO12 BVD1 CSTSCHG/STSCHG#/BVD1 41,43
PCI_AD0 W12 T361 E6 H16
AD0 42 SDD1_MSD1 MDIO11 VS2# CVS2 41
23,37,39 PCI_PAR V6 PAR UDIO4 H5 1394_SDA 42 42 SDD0_MSD0 D6 MDIO10 VS1# R16 CVS1 41
PCI_C/BE#3 P2 SHIELD GND D15
C/BE3# CD2# CCD2# 41
PCI_C/BE#2 W2 H4 2 1 B6 T14
C/BE2# UDIO3 1394_SCL 42 42 SDCLK_MSCLK MDIO09 CD1# CCD1# 41,43
PCI_C/BE#1 W6 R399 0Ohm G19
C/BE1# INPACK# CREQ#/INPACK# 41
PCI_C/BE#0 T9 H2 1 SHIELD GND 42 SDCMD_MSBS A6
CB_IDSEL_J C/BE0# UDIO2 T181 MDIO08
P1 IDSEL
UDIO1 H1 1 2 1 D5 MDIO07 IORD# P18 AD13/IORD# 41
23,37,39 PCI_C/BE#[3:0] T183 R411 0Ohm
23,25 PCI_REQ#1 M4 REQ# IOWR# P19 AD15/IOWR# 41
23 PCI_GNT#1 M5 GNT# UDIO0/SRIRQ# J4 INT_SERIRQ 21,22,25,30,32
T352 1 MDIO6 B5 MDIO06
23,25,37,39 PCI_FRAME# V3 Zdiff= 90ohm
FRAME#
23,25,37,39 PCI_IRDY# V4 IRDY#
T178 1 MDIO5 A5 MDIO05 USBDP V14 USB_PN4 23
23,25,37,39 PCI_TRDY# W4 TRDY# USBDM W14 USB_PP4 23
23,25,37,39 PCI_DEVSEL# T5 DEVSEL# 42 SDPWR_MSPWR B4 MDIO04
23,25,37,39 PCI_STOP# V5 J2 PCI_INTB# 23,25,39 Zdiff= 90ohm +3V
STOP# INTA#
23,25,37,39 PCI_PERR# W5 PERR# 42 SDWP B3 MDIO03
23,25,37,39 PCI_SERR# T6 SERR# INTB# K4 PCI_INTA# 23,25 1 2
T175 1 MDIO2 A3 MDIO02
R460 100KOhm /*
4
CB_GBRST# G2 K2 2 1 4
GBRST# INTC# PCI_INTC# 23,25,37,39
L4 R456 0Ohm A2 W13
23,28,37,39 PCI_RST# PCIRST# 42 MSCD# MDIO01 VPPEN1 AVPP1 41
K1 L2 V13 +VCCCB
12 CLK_CBPCI PCICLK NC1 VPPEN0 AVPP0 41
42 SDCD# B1 MDIO00 VCC3EN# T13 AVCC3# 41
21,22,25,30,32,37,39 PM_CLKRUN# L5 CLKRUN# VCC5EN# R13 AVCC5# 41
2
23,25,37,39 PCI_PME# G4 RI_OUT#/PME#
1
R414
1
1
2
xD R/B R5C841
MDIO04--> SD Card Power0 Control /
MS/xD Power Control Global Reset POWER SEQ : UDIO03 H : Enable SD
MDIO07--> SD/MS External Clock +3V => CB_GBRST# / CB_HWSUSP# => PCI_RST# UDIO04 H : Enable MS
MDIO08--> SD Command / MS Bus State VPPEN0 H : Enable xD
VCC_3V POWER : R5C841 / xD WE# H/W SUSPEND# POWER SEQ :
PME#, SPKROUT, RI_OUT#, HWSUSP#, GBRST#, IRQn MDIO09--> SD/MS Clock / xD RE# SUSPEND : CB_HWSUSP# LO => PCIRST# LO => +3VS OFF
CCD1#, CCD2#, VS1# , VS2#, TEST, VCC5EN#, VCC3EN#, RESUME : +3VS ON => PCIRST# HI => CB_HWSUSP# HI
PCI_AD17 2 1 CB_IDSEL_J MDIO10--> SD/MS/xD Data 0
VPPEN0, VPPEN1, SD/MS I/F R438 100Ohm
5 MDIO11--> SD/MS/xD Data 1 5
1 PM_SUSB# 22,33,34,43,47,54,57
VCCPCI POWER : PCI BUS CB_GBRST# 2 1 MDIO12--> SD/MS/xD Data 2 CB_HWSUSP# 3
+3V
R410 100KOhm 2
MDIO13--> SD/MS/xD Data 3 CB_SD# 22,25
VCC_SLOT POWER : CARD_BUS, CAUDIO , CSTSCHG 1 2 +3V => CB_GBRST# D26 DAP202K
C366 0.22UF/10V
1ms <T< 100ms
bom R2.1
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 40 OF 63 PCI CARDBUS (R5C841) RELEASE DATE : Alice Shih
A B C D E
5 4 3 2 1
1
1
1
R389 C373 C383 C379 C369 C370 120Ohm/100Mhz R914
1
0Ohm 10KOhm C868 C875 C867 C884
10UF/10V 0.1UF 1000PF 0.1UF 1000PF Q166
1
G
2N7002 10UF/10V 0.1UF 10UF/10V 0.1UF
2
CPS /* /*
1
2
2 S
3
D D11 CPS AVCC_PHY_1 E10 40 AVCC5# D
D
E11 U66
AVCC_PHY_2
AVCC_PHY_3 A17 1 VCC5_EN GND 16
AVCC_PHY_4 B17 40 AVCC3# 2 1 2 VCC3_EN VCC5IN2 15
R915 10KOhm 3 14
40 AVPP0 EN0 VCCOUT3
40 AVPP1 4 EN1 VCC5IN1 13
43 CBDEBUGEN#_Q 2 1 5 FLG VCCOUT2 12
D12 TPBIAS0 D62 1SS355 6 11
TPBIAS0 TPBIAS0 42 NC1 VCC3IN
7 NC2 NC3 10
+VPPCB 8 VPPOUT VCCOUT1 9 +VCCCB
1
X2_1394 A16 C890 R5531V002 C881 C891
XI
0.1UF 0.1UF 0.1UF
2
A13 TPB0-_1
TPBN0 TPB0-_1 42
X1_1394 B16 B13 TPB0+_1
XO TPBP0 TPB0+_1 42
1
+VPPCB C343 C352
1 2 B14 REXT
C R408 10KOhm 0.1UF 10UF/10V C
1%
2
1
1
C326 C340
1394_REF D13 VREF 10UF/10V 0.1UF
2
1 2
C385 0.01UF
E12 NC9
place close to
69
71
73
75
ASIC CN12
1 1 35
SIDE1
P_GND1
NP_NC1
P_GND3
35
40 AD0/D3 2 2 36 36 CCD1# 40,43
40 AD1/D4 3 3 37 37 AD2/D11 40
1
4 4 38 C772
40 AD3/D5 38 AD4/D12 40
40 AD5/D6 5 5 39 39 AD6/D13 40
6 6 40 270P
40 AD7/D7 40 RFU/D14 40,43
2
40 CBE0#/CE1# 7 7 41 41 AD8/D15 40
D10 TPBIAS1 1 8 8 42
TPBIAS1 40 AD9/A10 42 AD10/CE2# 40
T353 9 9 43
40 AD11/OE# 43 CVS1 40
40 AD12/A11 10 10 44 44 AD13/IORD# 40
40 AD14/A9 11 11 45 45 AD15/IOWR# 40
40 CBE1#/A8 12 12 46 46 AD16/A17 40
40 CPAR/A13 13 13 47 47 RFU/A18 40,43
40,43 CPERR#/A14 14 14 48 48 CBLOCK#/A19 40,43
A11 TPB1-_1 2 1 15 15 49
TPBN1 40 CGNT#/WE# 49 CSTOP#/A20 40
R395 0Ohm 16 16 50
TPB1+_1 40 CINT#/IREQ# 50 CDEVSEL#/A21 40
TPBP1 B11 2 1 17 17 51 51
R394 0Ohm 18 18 52
B 52 B
19 19 53 53 CTRDY#/A22 40
40 CCLK/A16
40 CIRDY#/A15 20 20 54 54 CFRAME#/A23 40
40 CBE2#/A12 21 21 55 55 AD17/A24 40
A10 TPA1-_1 1 22 22 56
TPAN1 40 AD18/A7 56 AD19/A25 40
T176 23 23 57
TPA1+_1 40 AD20/A6 57 CVS2 40
TPAP1 B10 1 40 AD21/A5 24 24 58 58 CRST#/RESET 40
T177 25 25 59
40 AD22/A4 59 CSERR#/WAIT# 40,43
40 AD23/A3 26 26 60 60 CREQ#/INPACK# 40
40 AD24/A2 27 27 61 61 CBE3#/REG# 40
40 AD25/A1 28 28 62 62 CAUDIO/SPKR_IN#/BVD2 40,43
40 AD26/A0 29 29 63 63 CSTSCHG/STSCHG#/BVD1 40,43
CINT#/IREQ# 1 T187 30 30 64
40 AD27/D0 64 AD28/D8 40
CSERR#/WAIT# 1 T383 31 31 65
40 AD29/D1 65 AD30/D9 40
P_GND2
P_GND4
NP_NC2
CREQ#/INPACK# 1 T334 32 32 66
40,43 RFU/D2 66 AD31/D10 40
SIDE2
CAUDIO/SPKR_IN#/BVD2 1 T331 40,43 CCLKRUN#/IOIS16# 33 33 67
67 CCD2# 40
34 34 68 68
1
CSTOP#/A20 1 T339 C381
CDEVSEL#/A21 1 T186 BtoB_CON_68
70
72
74
76
CTRDY#/A22 1 T362 270P
CIRDY#/A15 T368 CCD1# CCD2#
2
1
CSTSCHG/STSCHG#/BVD1 T381 L L 16bit
1
CBLOCK#/A19 1 T380 Other 32bit
CPERR#/A14 1 T382
CCLKRUN#/IOIS16# 1 T161
R5C841
X5
PCMCIA Slot
X2_1394 1 2 X1_1394
A A
24.576MHZ
2
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 41 OF 63 CARDBUS SOCKET RELEASE DATE : Alice Shih
5 4 3 2 1
5 4 3 2 1
+3V
1
C889
2
0.1UF R910 R911
U65 10KOhm 10KOhm
2
D D
1 A0 VCC 8
2 1 1 2 2 A1 WP 7
R404 56Ohm C363 0.01UF
1
3 A2 SCL 6 1394_SCL 40
1394A CON
1% 4 5
GND SDA 1394_SDA 40
2 1 1 2
R403 56Ohm C361 0.33U AT24C02N
1%
R2.1 TPBIAS0 41
TPA0+_1 41
6
CN26
LTPA0+
SIDE_G2
4 R768 2 1 0Ohm
TPXA1+
LTPA0- R771 0Ohm TPA0-_1 41
TPXA1- 3 2 1
2 LTPB0+ R773 2 1 0Ohm
TPXB1+
LTPB0- R776 0Ohm TPB0+_1 41 +12V
TPXB1- 1 2 1
SIDE_G1
TPB0-_1 41 To solve MS-Duo short with SD card
IEEE_1394_4P LTPA0+ TPA0+_1
2
5
3
SDCD#
L107 2 1 2 1 Q143 R817
200Ohm R405 56Ohm R392 5.11KOhm 2N7002 100KOhm
1
G
/* 1% 1%
LTPA0- TPA0-_1
1
1
2 S
3
2 1 1 2
D
R406 56Ohm C362 270P
LTPB0- TPB0-_1 1%
2
Q138A
1
2
1. Close to R5C841 UM6K1N
L108 SD_DAT1
C 200Ohm 2. The area is as compact as possible,length < 10 mm 40 SDD1_MSD1 6 1
C
/* 3. TPA Pair and TPB pair mismatch < 2.5mm
LTPB0+ TPB0+_1 4. No via recommend, maxmium is one.
4
2 1
5. Total length < 50 mm R818 0Ohm /*
5
CO-LAYOUT Q138B
6. Differential impedance is 110+/- 6 ohm UM6K1N
7. TPA Pair trace or TPB pair trace mismatch < 1.25mm 40 SDD2_MSD2 3 4 SD_DAT2
2 1
R816 0Ohm /*
MSCD#
MSCD# 40
Layout: SHIELD GND
SDCLK_MSCLK
SDCMD_MSBS
2
C821
SDD3_MSD3
SDD2_MSD2
SDD0_MSD0
SDD1_MSD1
270P
1
+3V
B B
+MC_VCC
2
19
18
17
16
15
14
13
12
11
10
2
R820 2 CN30
S
10KOhm Q142
19
18
17
16
15
14
13
12
11
10
SI2301DS 21 SDCD#
21 SDCD# 40
11
1
2
G +MC_VCC 24 25 C805
3 D NP_NC1 NP_NC2
22
3 22 270P
3
1
Q141 23 8 SD_DAT1
GND 8
1
1
R819
10KOhm
/*
2
A SDWP 40 A
1
C802
270P
/*
2
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 42 OF 63 IEEE1394A / 3in1 CONN RELEASE DATE : Alice Shih
5 4 3 2 1
A B C D E
+3V
U69
40,41 CCD1# 1 INB VCC 5
40,41 CSTSCHG/STSCHG#/BVD1 2 INA
3 GND OUTY 4
+3VALWAYS +5VLCM +5VLCM
2
74LVC1G00GV
R927
1
2
1 1MOhm C870 R726 1
2
2
+3V S
0.1UF 100KOhm
1
Q115
1
C882
R938 CHG_LED# 11 TP0610T
2
13
1
2 1 1 2 U67B G
+3V 3 D
R926
CLR
100KOhm 0.1UF
23
7 GND VCC 14
100KOhm
11 CK Q# 8 R711 R1.1#39
2
CBDEBUGEN# 470Ohm
PR
12 D Q 9 2 1
SN74LVC74APWR D63
1
10
1SS355
CHG_LED 44
1 T398
CBDEBUGEN#_Q 41
1
2 21,22,30,31,32 LPC_FRAME# 7 A1 C1 6 CAUDIO/SPKR_IN#/BVD2 40,41 2
11 10 R176
21,22,30,31,32 LPC_AD0 A2 C2 CPERR#/A14 40,41
2
17 16 2
21,22,30,31,32 LPC_AD1 A3 C3 RFU/D2 40,41 S
21 20 100KOhm
21,22,30,31,32 LPC_AD2 A4 C4 RFU/D14 40,41
Q41
PWR_LED# 11 TP0610T
2
21,22,30,31,32 LPC_AD3 4 B0 D0 5 RFU/A18 40,41
8 9 G
31 DIS_FWH B1 D1 CSERR#/WAIT# 40,41 3 D
1 14 B2 D2 15 CBLOCK#/A19 40,41
T385
23
18 B3 D3 19
22 B4 D4 23
+5V R180 R1.1#39
475Ohm
CBDEBUGEN# 1 24 1%
BE# VCC
13 BX GND 12
1
74CBT3383
PWR_LED 44
1 T397
1
R994 100KOhm
1
R913 R995 +5VLCM Q194
1
2N7002 R572
2
100KOhm 100KOhm 2
S 2
BAT_LOW#_KBC 32 S
1
/* 100KOhm
D
R996 Q89
2
11 TP0610T
2
2 1
3 1MOhm R993 0Ohm /* G
D
T97 3 3 D
+5VLCM D
2
23
Q172 1 Q91
CHG_LED# 2N7002 G 1 2N7002 R601 R1.1#39
1
S 2 28 HDD_LED_EN
1
G
1 2 PM_SUSB R928 2 S 470Ohm
3 3 3 +5VLCM
D D D R924 1MOhm
Q175 Q176 100KOhm
1
1
2N7002 2N7002
G
1 1 ICH6_1HZ 1 HDD_LED 44
Q171
2
3
S 2
54,55,56 AC_APR_UC BAT_LOW#_OC 54
G G 2N7002 G Q170 D
2 S S 2 S 2
2N7002
R1.1#19
1 2 3 3
+5VLCM D D
4 R929 100KOhm Q174 Q177 T299 4
2N7002 2N7002
1 1 PWR_LED#
1
54 CHG_EN_OC PWR_LED# 45
G G
2 S S 2 +3VS +5VS +5VS
3 3
D D
1
3 Q129 Q128
D
R932 Q173 2N7002 2N7002 R1.1#29
1
2N7002 ICH6_1HZ 1 1 1 2
1 PM_SUSC# 22,25 ICH6_1HZ PM_SUSB# 22,33,34,40,47,54,57
0Ohm G G R749 100KOhm R725 R730 R728
2 S S 2
2
G 2
S 2 S
10KOhm 100KOhm 100KOhm
2
3 3 Q120
+5VLCM D D
Q133 Q127 11 TP0610T
2
U63 2N7002 2N7002 G
1 5 PM_SUSB 1 1 D67 3 3 3 D
54,55,56,58 TS1# A VCC 47 PM_SUSB DJ_LED_EN 32,44 D D
G G DAP202K
23
54,55,56,58 TS2# 2
3
B
4 2 S S 2
R2.0#3 1 2 1 Q122 Q121
GND Y 32,38,45 BT_LED#
3
D R970 0Ohm /* 3 1 2N7002 1 2N7002 R727 R1.1#39
SN74LVC1G08 Q131 2 G G
32 WIRELESS_LED# 2 S 2 S
2N7002 470Ohm
PM_SUSC# 1
22,44,47,48,57 PM_SUSC#
G
1
5
2 S 5
WIRELESS_LED 44
39 802_ON 1 2
R724 10KOhm /*
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 43 OF 63 LEDs & DEBUG PORT RELEASE DATE : M.Y.
A B C D E
A B C D E
+3V
For EMI
Q104 C184 2 100PF /*
1
1
G
2N7002
C183 2 100PF /*
2 S
3
32 MSK_INSTKEY# 2 1 +3VALWAYS 1
D
R587 100KOhm
C182 1 2 100PF /*
TOUCHPAD/LED CON.
1
D41 C521
R2.1 C181
1 20,45,47 LID_SW# 1 1 2 100PF /* 1
3 0.01UF
/* +3V +3VALWAYS CN8
2
22,43,47,48,57 PM_SUSC# 1 2 2
C518 1UF/10V LN2 120Ohm/100MHz 14 16
RB717F 14 GND2
43 PWR_LED 7 8 13 13
1
43 CHG_LED 5 6 12 12
R586 R630 R637 3 4 11
43 HDD_LED 11
13
+3VALWAYS 43 WIRELESS_LED 1 2 10 10
1MOhm U39B 100KOhm 1MOhm 9
T406 9
1 8
CLR
8
2
7 GND VCC 14 7 7
D45 +5VS_TPD L45 1 2 120Ohm/100Mhz 6 6
11 CK Q# 8 2 1 SWDJ_EN# 32 5 5
L47 1 2 1KOhm/100MHz 4
32 INTDATA_5S 4
1SS355 L46 1 2 1KOhm/100MHz
PR
12 D Q 9 32 INTCLK_5S 3 3
2 2
SN74LVC74APWR 1 15
SWDJ_SW# 47 1 GND1
10
1
C180 C179 C178
R683 FPC_CON_14P
0.1UF 82PF/50V 82PF/50V
1MOhm /* /*
2
+3VALWAYS 2 1
R612 10KOhm 3
D +5V +5VS_TPD
Q38
2
2
SWDJ_SW#_Q Q105 2N7002 2
1 2N7002
G
2 S
D
2 S
G
1
3 Q110 3 Q106
D D
2N7002 2N7002 2 1
+12VS
R171 220KOhm
2
1 1 2 1 C188
+3V
G G R657 10KOhm
2 S S 2
0.1UF
1
+5V +5V
1
3 R629 3
2
2
S DJ SW MARATHON
100KOhm
Q102
AUDIO_DJ FPC Hotkey FPC
11 TP0610T BWARD Bluetooth
2
G
3 3 D 1 8 1 8
D
Stop/Eject INTERNET
3
Q103
DJ_LED_EN 1 2N7002 R1.1#39 AUDIO DJ CONN HOTKEY CONN
2
R43
R634 475Ohm
+3V
1% FFWARD PANLOCK +3V
100KOhm
1
2
2
DJ_LED 45
R610
4 RN26A
6 RN26B
10KOhm
8 RN26C
RN26D
R183
/*
1
2 1
30 DJKEY_EN
AUDIO_DJ HOTKEY
1
R611 0Ohm +3V
10KOhm
10KOhm
10KOhm
10KOhm
4 4
32,43 DJ_LED_EN
DJ_LED_EN 2 1
CONN. CONN.
2
R635 0Ohm /*
10KOhm
R609
R1.1#21,29 R2.1 R1.1#21,29
2
Q96 1MOhm CN10 For EMI
1
3
5
7
2
1 1
G
R633 PANLOCK#_J
1
2 2 1 2 PANLOCK_# 32
L15 1 2 120Ohm/100Mhz KSO3_DJ WIRELESS#_J
2 S
32 KSO3 3 3 3 4 WIRELESS_# 32
INTERNET#_J
D
1MOhm 4 5 6
4 INTERNET_# 32
1
6 6
100PF 100PF 1 9 7 MARATHON#_J 1 2
1 SIDE1 7 MARATHON_# 32
L48 120Ohm/100Mhz
2
2 2 10 SIDE2 8 8
7 CP10C
CP10D
3 CP10A
5 CP10B
3 3
LN1 FPC_CON_8P_HOTKEY
4 4
C194
7 8 KSI5_DJ_BWARD 5
32 KSI5 KSI6_DJ_STOP_EJECT 5
32 KSI6 5 6 6 6
1
3 4 KSI4_DJ_PLAY_PAUSE 7 9
32 KSI4 KSI3_DJ_FFWARD 7 SIDE1
100PF
100PF
100PF
100PF
32 KSI3 1 2 8 8 SIDE2 10
0.1UF
120Ohm/100MHz FPC_CON_8P_DJ
2
2
2
4
6
8
5 5
100PF 100PF 100PF 100PF
1
For EMI
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 44 OF 63 AUDIO DJ/ HOTKEY/ TP+LEDs RELEASE DATE : M.Y.
A B C D E
A B C D E
43 PWR_LED#
1
Q108 +5VS +5V
2
TP0610T R833
1
1
RESET BUTTON 1
1
G
R831 C807 C809 R839 1 2 0Ohm SYS_RESET# 22
47KOhm T347 /*
3 D
2
3 2 2 1
S
R665 0Ohm T336 100KOhm 1UF/10V 0.1UF
/*
2
POWER SWITCH CON R837 1 2 0Ohm
1
2 1 2 1 PM_RSMRST# 22
R666 0Ohm /* R664 0Ohm R827
1
T399 3
14
2 1 D
1
U56A R834 C810
R1.1#39 SW1 100Ohm VCC 74HC14 Q148
CN7 RESET_BTN# RESET 1 330KOhm 1UF/10V ADD FOR RC-RESET
1
1 1 2 2 1 2
G 2N7002
2
5 NC1 GND 2 S
2
1 1 1 2 3 3 4 4
1
2 2 R134 470Ohm C806 R1.1#7
50mA/12V
7
3 3 1 2 PWR_SW#_Q 47
4 L33 1KOhm/100MHz 4.7U
4
2
6 NC2 RST_BTN# 54
1
C129 C130
1
WTOB_CON_10P_2HOLD C892
100PF 0.01UF 3
D
1
T400 330pF R1.1#3 /*
2
Q149 R838
2
R1.1#2 1
2N7002
2 For EMI G 330KOhm 2
2 S /*
2
+5VS +3VS
R1.1_No28
KB COVER CON
1
+3VALWAYS
Keyboard Cover FPC
R596 R527
2
2
S
10KOhm 220KOhm DJ_LED Bluetooth NUM CAP Magnet Switch
1
Q75 C545
11 TP0610T
2
G 0.1U
3 D CN6
KB Cover CON
3
3
D 1 1 SIDE1 10
3 LN3 120Ohm/100MHz 2 3
2
Q68 R969 1 2 0Ohm T112
20,44,47 LID_SW# 1 2 3 3 1
1 2N7002 /* BT_LED 3 4 4
+3VS G Q189 NUM_LED 4
5 6 5
2 S 5
1
CAP_LED 9
1
RESET# 2 ICH6_PWROK 22 7 8 6 6
1
C512 R512 3 7
VCC 7
1
44 DJ_LED 1 2 8 8
R513 0.47U 220KOhm 1 L27 120Ohm/100Mhz 9 11
GND 9 SIDE2
CP6A
CP6B
/* /*
CP6C
CP6D
2
D
1
C86
C503
Q69 100KOhm
2
1
3
5
7
1 2N7002 0.1UF
8,12,48,49,54 VRM_PWRGD
2
/*
100PF
100PF
100PF
100PF
G
2
2 S
0.1UF
1
2
4
6
8
For EMI
4 4
1
R713 R568 R588
2
2
2 2 2
S S S
100KOhm 100KOhm 100KOhm
Q116 Q85 Q70
+3VS 11 TP0610T +3VS 11 TP0610T +3VS 11 TP0610T
2
2
G G G
3 D 3 D 3 D
1
1
3
3
R714 R553 R514
2
2
3
D R1.1#39 3
D R1.1#39 3
D R1.1#39
100KOhm R712 100KOhm R583 100KOhm R535
Q117 Q76 Q71
1 2N7002 470Ohm 1 2N7002 470Ohm 1 2N7002 470Ohm
2
2
G G G
2 S 2 S 2 S
1
1
BT_LED NUM_LED CAP_LED
32,38,43 BT_LED# 32 NUM_LED# 32 CAP_LED#
5 5
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 45 OF 63 PWR SW / RESET / KBC LEDs RELEASE DATE : M.Y.
A B C D E
A B C D E
1 1
T401
+5VS
+5VS
Q43
FAN CON.
2SB1132
1
+5VS_FAN
3
E
C
2
2
CN24
R2.1
1
B 1
C197 R188 C193 C700 1 1
2 2
0.1UF 2KOhm 10UF/10V 0.1UF 3 3
2
4 H1
2
1
2 1 5 H2
1
U15 R187 1KOhm R182 C190
FAN_FB 3 A+ + VCC 8 WTOB_CON_3P_FAN
1 FAN_ON_R# 1 2 FAN_ON# 5.11KOhm 0.01UF
FAN_DA 2 A- - AO R186 1KOhm /*
2
32 FAN_DA
1
C195
1
1
5 B+ + C196 R1.1#40 For EMI
2
BO 7 22P
R184 6 B- - 0.1UF 3
2
GND 4 D
2
/* +5VS
2
2 100KOhm LM358DR Q44 R181 C192 2
/* 1 2N7002
32 WATCHDOG
G 10KOhm 100PF
1
2 S
1
C199
1
1 2
R185 100KOhm /* R1.1#40 R178
1
1UF/10V
10KOhm
2
/*
1
G
2
FAN_TACH
2 S
3
CPUFAN_SPD_A 32
D
Q42
2N7002
FAN CONTROL
3 3
A/D_VIN_P
1
11 9 L14 680 Ohm/ 100MHz
SIDE2 9 4532 A/D_DOCK_IN 55,56
RTC_BAT 22 8 8
7 7
6 6
2
1
5 C40 C42 C12 C17
5
1
3 4 CN13 C388
4 4
WtoB_3P 3 0.1U 0.1U 1UF/50V 0.1U
0.1U 3
2
2 2
1
10 SIDE1 1 1
1
WtoB_CON_9P_DC
5 5
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 46 OF 63 FAN / RTC / DC_IN RELEASE DATE : M.Y.
A B C D E
A B C D E
3
2 1 1 2
C907 0.1UF R638 100KOhm
+3VALWAYS D8
3 RB717F
D
U39A
4
SN74LVC74APWR Q191 +3VALWAYS +3VALWAYS
2
1 1
R986 1 2N7002
PR
7 14 G
GND VCC 2 S
1
100KOhm
PM_SUSC#
R1.1#8
2 5 R824 R823
2 D Q 3 T402
D
CLR
ACIN# 2
D73
1
RB751V_40
3 CK Q# 6 2
R1010
1
10KOhm
R2.1 100KOhm 100KOhm
2
C919 ACIN# 1
1
56 ACIN#
G Q12
1
2 S 2N7002 VSUS_ON 50,57
100PF U67A
1
R2.1 SN74LVC74APWR 3
1
2 1 D
2
R987 10KOhm PWR_ON 3 C804
Q# 6
CLR
CK
2
C918 Q167
+3VSUS +3VSUS 2 5 1 2N7002 0.1UF
100PF D Q G
1
U4 /* 3 2 S
1
D 7 GND VCC 14
PR
1 A VCC 5
1 2 2 B
R7 1MOhm 3 4 2 1 1 T403 +3VALWAYS
GND Y
/* R1008 10KOhm G Q6 R2.1
4
2 1 SN74LVC1G08 /* 2 S 2N7002
D7 1SS355 /* R1009 100Ohm
1
1
2 /* C57 2 1 1 2 R2.1 74HC74 TRUTH TABLE 2
1 2 R825 10KOhm
1UF/10V R10 0Ohm
2
+5VLCM
2 1 2 1 2 PRE# CLR# CLK D Q Q'
1
R985 100KOhm R916 C885 D61 1SS355
1
150KOhm 2.2uF/6.3V L H X X H L
PM_SUSC# R934 /*
2
22,43,44,48,57 PM_SUSC#
H L X X L H
1
10KOhm
/* L L X X float float
2
6,53 OTP_RESET# 1
3 H H T H H L
56 SHUT_DOWN# 2 R2.1
D64 H H T L L H
1
RB717F
R939 H H L X Qo Qo'
+3VS 470KOhm
(+3VALWAYS)
2
2
R829 R1.1#27
14
14
3 3
100KOhm U56B
VCC 74HC14
U56C
VCC 74HC14 R1.1#3 T36
7
U56D
1
1
8 9 1 2
2 S
D
SWDJ_SW# 44
2
C808
3
VCC Q16
7
G
1000PF 2N7002
1
PM_SUSB 43
14
/* +3VSUS
1
1
R28 T404
Q15 T53
14
14
1
PWR_ON#
1
1 2 10 11 12 13 1 2
2 S
D
22 PM_PWRBTN# PWR_SW#_Q 45
D24 1SS355
3
1
GND GND C32
G
1
2.2uF/6.3V +3VSUS
7
+3VALWAYS
2
4 4
1
R1.1#16 R31
S 2
6 OS#_OC 1 2
3
R830 10KOhm
Q49 +3V 10KOhm
G
+3VALWAYS
R1.1#2
1
2N7002
+3VS
2
LID_ICH#_3A 22
1
1
R301 T165
T169 1 1 2 3 D22 R38 D5
D
R352 10KOhm 100KOhm DAP202K 1SS355
1 1 PM_SUSC# 1MOhm
1
2
1 2 3
1
G R305 1KOhm
2
S 2 2 KBCRSM 32 LID_SW# 20,44,45
J2 Q48
1
1
1MM_OPEN_5MIL 2N7002 C47
2
/*
1
0.1UF
1
C307 J1
2
2
1
1MM_OPEN_5MIL
2
0.33U /*
2
5 5
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 47 OF 63 POWER ON SEQUENCE RELEASE DATE : M.Y.
A B C D E
A B C D E
T405
+1.8VS +1.5VS VCCA_+1.5VS_+1.8VS
1
2 S
D
3
Q135
1
+5VS SI2302DS C896 C897
1
1 2 1 2
R950 10Ohm D65 F01J4L 1UF/10V 0.1UF/25V
R1.1#1 /* /*
2
E E
2 S
D
+3VALWAYS R780 R962
3
Q136
G
10KOhm 10KOhm SI2302DS
1
1
+VCCP R871
2
+3VALWAYS 100KOhm
+3VALWAYS
1
U58 3 3
2
D D
1
R861 1 5
R873 A VCC Q157 Q186 +1.8VS +1.8VS_VCCA
2 B
1
1
SN74LVC1G08
2
1 2
2 S
D
100KOhm C823 0.01UF R859
3
1
/* /* Q153 Q161 Q185
1 B
G
2N7002 2N7002 100KOhm D72 SI2302DS
2
1
1SS355
S 2
S 2
2
D
D
2 S
2 S
D
D
4,12 CPU_BSEL0
C
3
2
E
3
1
Q152 Q158 Q156
R2.0#11
2
G
G
G
G
2
1
1
PMBS3904 R869 C822 2N7002 2N7002
1
D D
1MOhm 0.01U
1
2
CPU Type VCCA Voltage
1
R870 R878 R961
2
3 3 3
D D D
Q155 Q154 Q184
2N7002 1 2N7002 1 2N7002 1
C VRM_PWRGD 8,12,45,49,54 C
G G G
S 2 S 2 S 2
1
R14 R863 R864 R854 R866
1
2
C276D87 C276D87 C276D87 C276D87 C276D98 C276D98 3
D
3
/* /* /* /* /* /*
Q4 Q151A Q151B Q150A Q150B
1 2N7002 UM6K1N UM6K1N UM6K1N UM6K1N
1
2 5 2 5
G /* /* /* /* /*
2 S
4
B B
1
H18 H2 H12 H15
C276D87 C276D87 C276D87 C276D87 R1 R27 R39
/* /* /* /*
47KOhm 330Ohm 330Ohm
/* /* /*
1
2
6
3
AGND_A
Q14A Q14B
SUSC_DIS 2 UM6K1N 5 UM6K1N
H10 H13 H11 H14 H23 H24 H25 R2.0#19 /* /*
CPU screw hole *4 C276D142 C276D142 C276D142 C276D142 c158d158n c158d158n c158d158n 3
4
D
/* /* /* /* /* /* /* For Daughter
1
A Board hole *3 1
Q2 C1
A
2N7002
1
22,43,44,47,57 PM_SUSC#
G /* 1000P
2 S /*
2
bom
REVISION DATE: Monday, January 17, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 48 OF 63 DISCHARGE & EMI RELEASE DATE : M.Y.
A B C D E
A B C D E
+3VO
VR_VID0 1 2
R208 47KOhm
VR_VID1 1 /* 2
VID 0 1 2 3 4 5 R211 47KOhm AC_BAT_SYS
VR_VID2 1 /* 2
1 1.468V 1 1 1 1 0 0 R213 47KOhm AC_BAT_SYS 1
VR_VID3 1 /* 2
0.956V 1 1 1 1 0 1 R214 47KOhm
VR_VID4 1 /* 2
1000P
R216 47KOhm 11/26
VR_VID5 1 /* 2
1
R220 47KOhm
5.6UF/25V
5.6UF/25V
+ +
1U
CE33
CE35
/*
C716
/* /* /* /* /* /*
2
+5VO
R202 0Ohm
R209 0Ohm
R218 0Ohm
R215 0Ohm
R217 0Ohm
R221 0Ohm
2
5
6
7
8
C714
TPC32t R197 10Ohm
2
T137 1 STPCPU# 2 1 +5VO Q126
D
TPC32t
IRF7413Z
1
T324 DPRSLPVR
G
1
S
C250 C220 PCPU_GND
1
TPC32t 4.7u 4.7u
4
3
2
1
GND GND
T325 1 PSI# GND
TPC32t
TPC32t
T314
T315
GND +VCORE
T313 T319 T320
TPC32t TPC32t TPC32t
GND
L106 R755
1
2 1 2 1 2 2
T127
T129
T130
T128
T133
T131
T147
T333
T149
TPC32t
TPC32t
TPC32t
TPC32t
TPC32t
TPC32t
TPC32t
TPC32t
TPC32t
R942 100KOhm
1
U17 0.56UH 3mOhm
51,54 1.8_2.5_1.5_1_PWRGD 1 2
EC31QS04
C248 12 36
VCC VDD
5
6
7
8
1
0.1UF C236 +
R233 100KOhm Q125 C727
2
42
D
V+ 0.1UF
2
/* 2 MCH_OK
1
2
+3VS 1 22 SYSOK IRF7831 220UF/2V
CLK_EN#
G
CLK_EN# 24 32 1 2
S
VR_PWRGD CLKEN# BSTM R206 2.7Ohm
2
8,12,45,48,54 VRM_PWRGD 1 2 23 IMVPOK
TPC32t
TPC32t
TPC32t
TPC32t
TPC32t
D18
R224 0Ohm 34 2
VR_VID0 DHM
T335
T329
T318
T316
T295
4
3
2
1
4 VR_VID0 30 D0 3
VR_VID1
1
4 VR_VID1 29 D1 LXM 33 1
VR_VID2 28 RB717F D19
4 VR_VID2 VR_VID3 D2
27 35 PCPU_GND
4 VR_VID3 VR_VID4 D3 DLM
1
4 VR_VID4 26 D4
VR_VID5 25 37 GND
4 VR_VID5 D5 PGND CMP
GND1 13
6 S0 GND2 49 GND
7 S1 CMN 46
10/11 8 45 T136 T138 T141 T144
S2 CMP
2
1
4 B1 1 2
3 GND 5 18 R228 511Ohm 3
B2 FB
DPRSLPVR
1
1000P
STPCPU#
CSP
R200 0Ohm 11/26
1MOhm
44 DPSLP#
1
PSI#
5.6UF/25V
5.6UF/25V
12,22 STP_CPU# 1 2 21 PSI# + +
1
1U
CE32
CE34
R199 1KOhm 17
R226 100KOhm VRON CCI
9 SHDN#
5
6
7
8
C794
+3VO 1 2 POS 15
R223
C795
Q139
2
2 1 2
D
TON IRF7413Z
1
4 PM_PSI# 1 2
R227 1KOhm C247 470PF
G
14 48
S
/* CCV CSP PCPU_GND
10 47 T139 T143 T148
REF CSN
47P
4
3
2
1
1
100KOhm
/* 2 +VCORE
1
+3VO 1 11 ILIM BSTS 41 1 2 1 2 1 2 1 2
1
C249
5
6
7
8
100KOhm TIME
2
1 2
1 TIME LXS 40
1
C246 100P
D
1
2
T142 1 0.01uF/25V 31 38 220UF/2V C766
DD0# DLS IRF7831
75KOhm
0.1UF/25V
2
S
R196
c0603
2
4 4
TPC32t
TPC32t
TPC32t
TPC32t
MAX1987ETM
2
2
T260
T317
T301
T271
T291
TPC32t
R225 360Ohm R241 1KOhm D55
4
3
2
1
EC31QS04
2
1
1 2 1 2
GND
OCP : 34A R229 R222 R230 C251 R244 1KOhm
01/04 PCPU_GND
1
1 2 1 2 1 2 1 2 1 2
GND GND
100KOhm 1.21KOhm 4.7KOhm
4700P
U19 +5VO 1 2 TIME
R770 15KOhm
6
R774 1 NC VCC 5
DPRSLPVR 1 2 2 A
3 GND Y 4 2 Q130A
R777 0Ohm UM6K1N
1
+3VS 2 1
U21 NC7ST04M5 1 2
100KOhm R764 36.5KOhm
3
R779 1 NC VCC 5
1
CLK_EN# 1 2 2 A
3 GND Y 4 5 Q130B R765
0Ohm UM6K1N 121KOhm
4
5 5
GND NC7ST04M5
2
GND GND
for C4 fast exit event
bom
REVISION DATE: Monday, January 24, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 49 OF 63 VCORE RELEASE DATE : Amos Yu
A B C D E
A B C D E
2
01/03
10KOhm
R147
OUT: +3VO
AC_BAT_SYS +5VO
1
AC_BAT_SYS 11/26
1
1 1 2 1
PLLFLTR C686 C698
1
1UF R732 10Ohm
5.6UF/25V
1000P +
CE38
C187
2
2
0.1UF/25V
/*
c0603
2
GND
PSYS_GND
100KOhm
2
R151
01/03
1
GND
5
6
7
8
Q40
D
3V_5V_PRWGD
SI4800BDY
S
01/03 (5A)
RUN_5VO
1
+5VO T122 T293 T294 T297
C690 TPC32t +5VO TPC32t TPC32t TPC32t
4
3
2
1
4700P L39 R174
1
1 2 1 2
+5VAO GND
R720 107KOhm
3.8UH 10mOhm
5
6
7
8
U50
1
2
180P
32
31
30
29
28
27
26
25
D
1
1
100KOhm
2 LTC3728LX SI4894DY-TI + 2
1
R717
G
NC
PGOOD
SENSE1-
NC_3
SENSE1+
RUN/SS1
TG1
SW1
S
C695 FS1J4TP 1UF/10V
C682
4
3
2
1
2
1 24 PSYS_GND
PLLFLTR VOSENSE1 BOOST1
1
2 PLLFLTR VIN 23
1
20KOhm
RB717F
2
8 17 1 2
VOSENSE2
ITH2 BOOST2 T285
SENSE2+
RUN/SS2
SENSE2- AC_BAT_SYS
TPC32t
NC_1
NC_2
33
SW2
TG2
SIDE1
1
11/26
1
C696
1000P
1
5.6UF/25V
5.6UF/25V
4.7u + +
10
11
12
13
14
15
16
1
1000P
CE37
CE36
9
2
GND
1
C172
C671
1U
RUN_3VO
0Ohm /*
2
5
6
7
8
C670
2
3 3
1
Q32 PSYS_GND
D
C677 220P
C676 220P
SI4800BDY
1
G
GND
S
R718
C689 (5A)
R710 150KOhm
R709 150KOhm
C685
2
4
3
2
1
1
1
1 2 1 2
R716 R721
1 2 1 2 +3VO 3.8UH 10mOhm
5
6
7
8
20KOhm 64.9KOhm Q36 DCR =13 mOHM
D
GND
120UF/4V
SI4894DY-TI +
1
CE7
G
S
Vref = 0.8 V D16 C161
FS1J4TP 1UF/10V
T115 T117 T114
4
3
2
1
2
TPC32t TPC32t TPC32t
1
4 PSYS_GND 4
+3VALWAYS T408
1
TPC32t 6/14 GND
D53 RB715F
1
RUN_3VO
1
2
3
R719 1 RUN_5VO
6
100KOhm
1
Q118A
2
2 UM6K1N T409
TPC32t
1
3
+3VO Q118B
47,57 VSUS_ON 5 UM6K1N
1
4
1
R723
R729 100KOhm
100KOhm /*
2
2
GND
5
3V_5V_PRWGD 5
54 3V_5V_PWRGD
bom
REVISION DATE: Monday, January 24, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 50 OF 63 SYSTEM RELEASE DATE : Amos Yu
A B C D E
A B C D E
100KOhm
+3VO
T210
SUSC#_PWR R906 TPC32t OUT: +1.8V
1
52,57 SUSC#_PWR
AC_BAT_SYS +1.5V
10/11 +2.5V
6
D68 Q165A 11/26 +VCC_GMCH_CORE
1
1 1
1
R900 UM6K1N +5VALWAYS
5.6UF/25V
5.6UF/25V
+ +
1
CE40
CE41
RB520S_30 2 C848 +3VALWAYS
/* 0Ohm 2700P 01/03 C911
3
Q165B C859 0.1UF/25V
5
6
7
8
UM6K1N c0603 JP19 SHORT_PIN
2
2 1
5 Q66 +1.8VGND 1 2 01/03
D
+1.5VO +1.8VO GND T118
0.1UF/25V SI4800BDY
1
C847 T204 T208 T207 (7A) TPC32t
S
+1.8VO TPC32t TPC32t TPC32t
0.01U 09/23 +1.8V
JP17
1
/* 2 L69
4
3
2
1
1
C864 C862 +1.8 VO
1
GND 1 2 1 1 2 2
10KOhm
VREF5 6800P 3300P
5
6
7
8
R904
12/28 1.8UH 01/03 3MM_OPEN_5MIL
2
2
1
ON_1.5 Q63 T98 T154 T151 + + 01/04
D
1
11.8KOhm
100KOhm
2
R912
R909 R907 330UF/2V
S
so8 FS1J4TP
1
SUSB#_PWR R905 D34 120UF/4V
2
1 2 1 1 2 2
330Ohm R903 /*
2
12/28 10.2KOhm 1SS355 8/16 3MM_OPEN_5MIL
4
3
2
1
1
330Ohm
2
R899 Q164A
2
2
GND GND
10/11 11KOhm UM6K1N 09/23 R901
1
2 1
1
2
2 2 1 2 2
C846 C856 0.1UF/25V
3
1 2
0.01uF/25V
R897 2.7Ohm
5 1 2
1
10.2KOhm R908 12.7KOhm 11/26
1
VREF5
4
1
C845 Q65
C851 0.1UF/25V
GND 2 1
1
C908
5.6UF/25V
0.47U +
CE39
C853 0.1UF/25V TPC32tTPC32t (4A) T198 +1.5VS
2
0.1UF/25V 1 8
1
D1_1 G1
c0603 T384 T209 +1.5VO TPC32t
2
1
C855
C861
1
GND 2 7 JP15
1
D1_2 S1/D2_3 L71
+1.8VGND C837
2
3300P
1
VREF5 C850 0.1U +1.5VO 1
1
3 G2 S1/D2_2 6 1 2 2
10/11 +1.5VGND D32
2
5600P
2
4.7UH 3MM_OPEN_5MIL
2
1 2 4 5
1
S2 S1/D2_1
R902
2
48
47
46
45
44
43
42
41
40
39
38
37
52,53,57 SUSB#_PWR GND
1
100KOhm
1
R972
VREF5
100KOhm
FLT
INV1
LH1
OUT1_u
LL1
OUT1_d
OUTGND1
TRIP1
VIN_SENSE12
TRIP2
OUTGND2
OUT2_d
2
R973
470KOhm
D70 /* +1.5VGND
1
1 FB1 LL2 36 1 2
RB520S_30 ON_2.5 R490 1.8KOhm ON_1.8
2
2
2 SS_STBY1 OUT2_u 35
SHORT_PIN
1
0Ohm 3 INV2 LH2 34
1
6 PWM_SEL VREF5 31
/* 2 7 30
R974 CT TPS5130 REG5V_IN
8 GND LDO_IN 29 2 1 C836 0.1UF
3
47pF/50V
0Ohm Q190B /*
1
UM6K1N 1 2 10 27
STBY_VREF5 LDO_GATE
1
0.1U
VIN_SENSE3
0Ohm R484100KOhm 12 25
PG_DELAY
STBY_LDO INV_LDO
1
SS_STBY3
OUTGND3
C442
4.7uF/25V
4.7uF/25V
4
1
C450
C445
OUT3_u
OUT3_d
0.047U
1
PGOUT
8
TRIP3
AC_BAT_SYS
INV3
FB3
LH3
LL3
Q61
2
GND
09/23 D
2
ON_2.5 RSS090N03
GND GND GND
13
14
15
16
17
18
19
20
21
22
23
24
C446
C458
ON_1.05 +1.05VGND C834
49,54 1.8_2.5_1.5_1_PWRGD
2 1 G S T192
VREF5
2.7KOhm
/*
1
2 1 JP13
1
2
100KOhm
1
47,49 CPU_VRON
R454
C829 1 2 1 2 +2.5VO 1 2
1 2 +2.5VS
R874
4 R936 1 2 1SS355 4
2
GND
1
1
0.1UF
c06032
1
RB520S_30 11KOhm C873 c0603 AC_BAT_SYS 10UF/6.3V 0.1UF/25V
2
2
1
2200P
3
2
6.81KOhm
C417
UM6K1N 11/26
1
2
GND GND
5
6
7
8
1
5.6UF/25V
2
5 +
CE42
Q64 C909 01/03
2
D
GND
1
2
G
S
0.47U (5A)
2
L72
2
+1.05VO
4
3
2
1
1
GND 1 2 1 2
R876 0Ohm
T193 1.8UH
2
T212
5
6
7
8
1
TPC32t +5VALWAYS TPC32t 12/28 T38 T37 +
R444 R867 Q67 TPC32t TPC32t CE17
D
JP12
1
680Ohm 49.9KOhm
R875 SI4894DY-TI 330UF/2V
1
G
VREF5 1 2
S
1 2 12.4KOhm so8
1
2
T203 1MM_OPEN_5MIL GND
1
1 2
6800P
JP18 SHORT_PIN
2
GND
+1.05VO
1
VREF3 1 1 2 2
bom 1MM_OPEN_5MIL
REVISION DATE: Monday, January 24, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 51 OF 63 2.5V/1.5V/1.8V/1.05V RELEASE DATE : Amos Yu
A B C D E
5 4 3 2 1
+5VO
01/07
01/03
1
1844VCC
C81 C72 AC_BAT_SYS
0.1UF/25V 11/26
2
C0603 4.7UF/6.3V
2
R1001 R997 c0805
GND
0Ohm 0Ohm
1
5.6UF/25V
5.6UF/25V
/* + +
CE43
CE44
C39
1
1844_UVP 1 1844_OVP 0.1UF/25V
1
C80 c0603
2
2
2
2200P
2
D D
R999 R1000
2
0Ohm 0Ohm
1
+3VS GND
/* R84
1
20Ohm JP3
1
D13 VGAGND 1 2
8/30
GND
SS0540 MAX:15A
5
6
7
8
MAX1844EEP SHORT_PIN
2
GND
sod123
R128 Q10 1.2V
D
10KOhm 4.7UF/6.3V U9
2
+/-
IRF7413Z
c0805 C79
G
13 16
S
C95 VDD V+ R82
1844VCC 30mV
1
2 1 14 VCC BST 18 1 2 2 1
T273 T60 T52 T276 T414 +ATI_VCORE
4
3
2
1
GND
01/03 DH 0Ohm 0.1U T413 TPC32tTPC32tTPC32tTPC32t TPC32t
17 SKIP DH 20
12/28 R998 TPC32t 3MM_OPEN_5MIL
1 2 10 19 8/30
16,54 PWR_OK_VGA PGOOD LX JP4
L13
1
0Ohm CS
1
51,57 SUSC#_PWR 1 2 3 SHDN CS 1 1 2 1 1 2 2
CE4
/* 01/03 8/16 01/04
1
2 4 1844_OVP + + 3MM_OPEN_5MIL
51,53,57 SUSB#_PWR LATCH OVP
330UF/2V
R143 C75
JP33
5
6
7
8
CE2
REF 1844_UVP
220UF/2V
D14 1 2 8 9 0.1UF/25V
REF UVP
2
1SS355 R83 01/03 Q17 c0603
2
1 2
D
1 2
IRF7831
SOD323 100KOhm D12
2
1 2 15 TON OUT 6
/* 12/28
G
EC31QS04
S
C 1 2 0Ohm 11 5 GND GND GND C
GND FB
2
R1014 13KOhm C121
1
R121
200Ohm
1UF/10V
4
3
2
1
1
GND
2
2
1UF/10V T111 T113 T110 T135
1
c0603 TPC32tTPC32tTPC32tTPC32t
VGAGND
1
+5VO
2
01/07
1
GND
01/03 R133
1KOhm GND
2
+ATI_VCORE +3VS R114
1
100KOhm T412
2
TPC32t 3
D
2
R1004
1
R1007 100KOhm Q112
20KOhm /* PWR_OK_VGA
H:1.0V 1 C135
1
/* T411 L:1.2V G 2N7002 0.1UF/25V Option 1 : remove R54 LVDDR=2.5V
TPC32t 3 2 S c0603
1
2
D
3 /* Option 2 : remove R149 add R55 LVDDR=2.8V
1
D
3 Q113
C 1
1
1 B 1 16 ATI_PERF# 2N7002
G R102
G Q195 2 S 1 2
2 S 2N7002 +2.5VS
2
1
1 2 LVDDR
GND 10Ohm r0603 0Ohm
(100mA)
1
C900
1
1
1UF/16V T30 +3VS 11/26
REF +2.5VREF
127KOhm
C902 TPC32t
2
U3
R73
T410 GND 4.7U /*
11/26 TPC32t
2
1 VIN VOUT 5
12/28 U71 R52 100KOhm
1
2 VSS
2
SUSB#_PWR
2
1 VOUT1 VCC 8 GND 1 2 3 ON/OFF NC 4
5
6
7
8
R952 R955
1
2 VIN1- VOUT2 7
64.9KOhm 107KOhm 3 6 Q183 S_1111B28MC_NYN_TF
D
1
C53
G
1
LM358ADR T89 0.1UF/25V
1
1
100KOhm
T91 10/11 TPC32t c0603 T132
10UF/6.3V
10UF/6.3V
R58
C56
C55
TPC32t /* TPC32t
4
3
2
1
2
GND
+1.2VO +1.2VSP
JP7
1
2
1
1
1 1 2 2
2
12/28
1
/* R957
2
4.75KOhm C901
1
10/11 22UF/6.3V
2
+1.2VO GND
bom GND
REVISION DATE: Monday, January 24, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 52 OF 63 VGA VCORE RELEASE DATE : Amos Yu
5 4 3 2 1
A B C D E
1
U57 +1.5VAO
1
+1.05VO 1 1 2 2 +VCCP 2 2 1 1
1 IN OUT 5 POWER IN: +3VALWAYS
2
2MM_OPEN_5MIL 6/14 2 1MM_OPEN_5MIL +3V
GND
1
C421 3 4 R842 N/A +1.8V
EN ADJ
1 +VCC_GMCH_CORE 1
0.1UF/25V SI9183DT 2.4KOhm
1
/* /* C815
2
OUT: +0.9VS
1
GND 4.7u +1.5VSUS
2
/* +VCCP
2
R843
1
JP14
GND
1
+1.05VO 1 1 2 2 +VCC_GMCH_CORE
2MM_OPEN_5MIL
1
C470 6/14
0.1UF/25V
2
T150
GND TPC32t T164
+1.8V TPC32t +1.8V
+0.9VS
1
2 T6 T26 2
TPC32t TPC32t
R268
+ATI_MEM
+1.8VS +3V
3MM_OPEN_5MIL
3MM_OPEN_5MIL
JP26
1
T156
1
1 1 2 2
100KOhm
1
1
TPC32t
JP8
JP9
2
+3V
2
3MM_OPEN_5MIL
1
1
T163 R281
2
TPC32t Q45 100KOhm
U22
R262
1
3
1
1 VIN VCNTL2 6 D 2N7002
T2
2
2 GND VOUT 5
TPC32t 3 4
VCNTL1 REFEN 1
Q46
G
1
RT9173ACL5 S 2
+0.9VO
100KOhm
3
2
D 2N7002
R290
1
+ T64 1 2 1
1
CE15 C299 TPC32t C298 G
S 2
3 3
100U/2V 10UF/6.3V 10UF/6.3V 0Ohm
1
2
2
SUSB#_PWR 51,52,57
TPC32t
T387 GND
1
+5VALWAYS
2
R922
23.2KOhm 95 DEGREE C
TPC32t RT1 11/26 THERMAL PROTECTION
T140 100KOhm
PLACE UNDER CPU
1
2 2 1 1
+3VS
1
GND
4 +0.9VO 4
C871 +5VALWAYS
2
2 1
01/04 R12 R3
1
2
TPC32t R921
U68 T206 R2
10KOhm 20KOhm
1
1 NC VCC 5 VTT_PWRGD 54
2 SUB
1
1
D
PST9013 3
GND C
1 B 1
G Q3
E 2 S 2N7002
2
2 Q1
R6 PMBS3904
165KOhm
1
5 GND 5
bom
REVISION DATE: Monday, January 24, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 53 OF 63 0.9VS/1.05VS/1.5VSUS RELEASE DATE : Amos Yu
A B C D E
A B C D E
+5VLCM
U40
2
SOT23_S5_NB
5 VCC NC 1
1
SUB 2
T228 T230 T272 T223 T247 C535 R621 R620 4 3 TPC32t TPC32t
47KOhm 100KOhm VOUT GND
1U T225 T220 R551 0Ohm
2
TPC32t TPC32t TPC32t TPC32t TPC32t GND GND
PST9142 SMD_BAT_PW
1
1 1 2 1
U38
BAT_LOW R536 0Ohm
1
1 RA2 RA1 18
BAT_LLOW 2 17 1 2 SMC_BAT_PW
RA3 RA0
3 T0CKL OSC1/CLKIN 16 TPC32t TPC32t TPC32t TPC32t
4 MCLR#/Vpp OSC2/CLKOUT 15
5 14 T43 T259 T39 T35
Vss Vdd BAT_CTRL2
1
43,55,56 AC_APR_UC 6 RB0 RB7 13 BAT_CTRL2 56
7 12 BAT_CTRL1
43,55,56,58 TS1# RB1 RB6
43,55,56,58 TS2# 8 RB2 RB5 11 CHG_CTRL 55
55 BAT_1P 9 RB3 RB4 10 CHG_EN# 23,55
PIC16C54C R581 T257TPC32t
V0402MHS03
V0402MHS03
T242 T219
2
GND 1 2
1
TPC32t TPC32t
C536 C542 1MOhm
1
RST_BTN# 45
T417
100P 100P TPC32t
2
1
X6
BAT_LLOW#_OC 32
D44
D47
1
1
1 3
1
GND
CHG_EN_OC 43
1
4MHZ C530 3 T416
2
D
2 Q101 TPC32t 2
1U 2N7002 3
2
GND GND D
BAT_LLOW 1 Q100
GND G
2 S CHG_EN# 1 2N7002
GND G
T418 2 S
TPC32t GND
SMC_BAT_PW
1
PULL UP TO 3VA BAT_LOW#_OC 43
SMD_BAT_PW
32,58 SMDATA_BAT2
3
32,58 SMDATA_BAT1 D
Q87
32,58 SMCLK_BAT2 BAT_LOW 1 2N7002
G
32,58 SMCLK_BAT1 2 S
T1 +3VS
14
1
BAT_CTRL1 TPC32t U35A GND
GND 1 VCC
53 VTT_PWRGD
3
1
2
3
4
5
6
7
8
3 16,52 PWR_OK_VGA 2 3
U12 GND
14
S
I0A
I1A
YA
I0B
I1B
YB
GND
14
QS3257 1
TPC32t VCC U35C
7
4
6 9 VCC
VCC
I0D
I1D
I0C
I1C
+5VLCM POWERGD
YD
YC
5 8
E#
GND POWERGD 22
T214
14
1 10
TPC32t U35D LV08A GND
BAT1_OFF# 58
16
15
14
13
12
11
10
VCC LV08A
9
7
50 3V_5V_PWRGD 12
7
11
49,51 1.8_2.5_1.5_1_PWRGD 13 GND
1
3 GND
D
C125 1 LV08A T337 1
0.1uF/10V Q23 T194 TPC32t
7
1 2N7002 TPC32t
2
8/5 GND G
2 S 8,12,45,48,49 VRM_PWRGD
2
Q24 3 R86
R87 C
BAT_CTRL1 1 B 1MOhm
1 2
10KOhm E
1
2
4
3 PMBS3904 4
D
Q25
TS1# 1 22,33,34,40,43,47,57 PM_SUSB#
2N7002
G T216
2 S
2
TPC32t
R525
GND GND GND D1 1MOhm
1SS355
1
T419
TPC32t Q72A
6
UM6K1N
BAT2_OFF# 58
2
Q20 3 TPC32t Q72B
1
2
R57 C T3 UM6K1N R524
3
BAT_CTRL2 1 B
1
1 2 0Ohm
1
10KOhm E POWERGD C489
1
5
3 2 PMBS3904
1
D 4 1UF/10V
2
Q21
TS2# 1 VSUS_OFF# 47
2N7002 GND
G
5
2 S 6/14 5
GND GND
bom
REVISION DATE: Monday, January 24, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 54 OF 63 PIC16C54/BATCON/PWOK RELEASE DATE : Amos Yu
A B C D E
A B C D E
A/D_VIN
A/D_VIN_O
A/D_DOCK_IN
0.1UF/25V
0.1UF/25V
1 1
1
C492
C491
T44
2
GND GND
TPC32t
56 MAX1909_PDS AC_BAT_SYS
1
1
CHG_GND
1
C490
1U
11/26
5.6UF/25V
5.6UF/25V
+ +
1
CE46
CE45
MAX1909_LDO
43,54,56 AC_APR_UC
T236 C912
4
3
2
1
A/D_DOCK_IN TPC32t 0.1UF/25V T123 T48
2
GND MAX1909_LDO Q8 c0603 TPC32t TPC32t
2
S
A/D_VIN_O
G
R590
C493 0.1UF/25V
SI4835BDY
1
100KOhm JP2
D
CHG_GND
1
1 2
2
6/16 6/14 SHORT_PIN
5
6
7
8
AC_IN Threshold 2.089Vmax R526
PKPRES#
6/14 D38 33Ohm
29
28
27
26
25
24
23
22
2 A/D_DOCK_IN > 9.913V GND 2
2
100KOhm
CSSN
SRC
GND2
PDL
PDS
CSSP
DHIV
DHI
TPC32t C507 0.1UF/25V T33 T232 T15
1
1 21 1 2 TPC32t TPC32t TPC32t
DCIN DLOV
2 LDO DLO 20
L5 R26
1
3 ACIN PGND 19
1909_REF BAT
1
4 REF CSIP 18 1 2 1 2 BAT
5 PKPRES# CSIN 17
6 16 10UH 15mOhm
ACOK BATT
VCTL
7 15
ICTL
CCV
CCS
IINP
CLS
MODE GND1
2
5
6
7
8
CCI
1U
1U
1U
19.6KOhm
6/18
1
26.7KOhm
Q13
5750
7343
R569
R605
10
11
12
13
14
TPC32t MODE MAX1909 D9 15UF/25V
8
9
S
C497
C504
C517
2 EC31QS04
2
2
53.6KOhm
1
2
20KOhm
R591
T253
1
4
3
2
1
1
R603
TPC32t
IINP
GND GND GND GND
01/04
R566 6/14 CHG_GND
10KOhm
6/18
1
1
2 1
R589
3 T254 1 10.5KOhm 3
1
C528
TPC32t
0.01U
GND
0.047UF/16V
T255
1
2
CHG_CCV
C516
14.7KOhm
36.5KOhm
3 TPC32t
2
D
2
137KOhm
T224
R592
R619
R604
Q77
0.1UF/25V
2
1
20KOhm
1 2N7002
1
1
R598
C529
TPC32t G 8/16
2 S MAX1909_LDO
C524
6/14
0.1UF/25V
1
1
1
2
GND GND GND
2
54 BAT_1P
1
GND
GND
2
Hi = 1P (1.25A),
Low = 2P (2.5A) MAX1909_LDO R576
MAX1909_LDO 100KOhm
1
R577
R552 100KOhm
100KOhm
4 T234 4
Adapter Iin(max) = [0.075V/Rsense(ADin)]*[VCLS/VREF] TPC32t
Rsense(ADin)=0.02 ohm 3 3
D D
VCLS=3.685V 3
D
=> Iin(max)=3.27A Q78 Q74 PKPRES#
1
=> Constant Power = 19 * 3.27 = 62.13W 1 2N7002 Q94 1 2N7002
23,54 CHG_EN# 1 43,54,56,58 TS1#
G G
2 S 54 CHG_CTRL IRLML2402 2 S
Charge Current Ichg = [0.075V/Rsense(CHG)]*[ICTL/3.6V] G T420
2 S
6
Rsense(CHG)=0.015 ohm TPC32t
VICTL= 1.8Vor 0.9 GND
=> Ichg = 2.5A or 1.25A 2 Q79A
MODE UM6K1N
1
Vbatt = Cell * { Vref +[ (VCTL- 1.8V) / 9.52 ] } T217
1
VCTL= 1.576V TPC32t
0.1UF/25V
3
C510
=> Vbatt = 4.2V 3
D
Mode pin : Vmode > 2.8V (trie to LDO pin) ----> 4 Cells Q93 Q79B
1
43,54,56,58 TS2# 5
2.0 > Vmode > 1.6V (floating) ----> 3 Cells 1 2N7002 UM6K1N
2
32 BAT_LEARN
0.8 > Vmode (trie to GND) ----> Learning mode 11/26 G
4
2 S
2
R989
VICTL< 0.8V or DCIN < 7V -->Charger Disable 100KOhm GND
5
6/18 5
Pre_CHG_V = 3.1mV
1
bom
REVISION DATE: Monday, January 24, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 55 OF 63 CHARGER RELEASE DATE : Amos Yu
A B C D E
A B C D E
+5VO
R641
1KOhm
GND
A/D_VIN
1 2
+5VCHG
A/D_VIN_O
T31 T279
T16 TPC32t TPC32t
T25 T21 T20 T5 TPC32t 12/28 T11 T10 T9 D51 +5VLCM
TPC32t TPC32t TPC32t TPC32t Q11 D10 TPC32t TPC32t TPC32t A/D_VIN U42
1
46,55 A/D_DOCK_IN 1
S D R34 U45
1
1 8 1 3
+5VCHG +5VCHG
1
1 A/D_DOCK_IN 2 7 1 2 2 AC_BAT_SYS 1 OUT IN 3 2 IN OUT 1 2 1
3 6 3
GND
GND
2
4 G 5 20mOhm F02JK2E
T421 1 R662
TPC8107 6/14 EA60QC04_TE16F Q86 L78L05ACUTR TPC32t 4.7KOhm
2
C494 S D LM3480 T50
3
1 8 BAT
/* +2.5VREF
LM4040BIM3X
2 1 2 7
1U TPC32t
1
3 6
1
D39 1SS355 +2.5VREF
1
4 G 5
1
C594 C608
1
22KOhm
1 2 TPC8107 1U 1U C546
MAX1909_PDS 55
1
R642
2
1U
R523 10KOhm C560
2
3
U41
1UF/10V
2
+5V GND
2
R643
+5VCHG, +5VLCM, +2.5VREF
2
30KOhm
R663
10KOhm
1
2 2
6
AC_BAT_SYS A/D_DOCK_IN
1
2 Q99A
UM6K1N
100KOhm
T32 01/14
R50 68KOhm
TPC32t
1
AC_APR_UC 5 Q99B
1
UM6K1N
1
32 ACIN_OC
Q19
R74
3 2N7002
D
2
GND
1 TPC32t
2
G T28
S 2
1
AC_BAT_SYS, BATTERY LEARN CIRCUIT 47 ACIN#
T34
3 TPC32t
C R-1
B 1
1
3
MAIN BATTERY SHUNT 3
0.1UF/25V
47K
10KOhm
E
DOWN=11.53V R-2
1
AC_BAT_SYS 47K
SECOND BATTERY SHUNT
1
100KOhm
2
DOWN=8.575V
R49
C48
Q22
1
+5VLCM DTC144EK
2
470KOhm
R606
2
1
47KOhm
R585
TPC32t GND
R594
T213
BAT (11.6V)
2
1SS355
1
1
10KOhm
+5VCHG 2
1
D42 E 0923 3
2
D43
C
RB715F
R584
R565
243KOhm
1 B 1 B
+5VLCM 01/03
C
Q98 T59 +5VLCM
1
T72
2
3
PMBS3906 E TPC32t
R618 2 Q180
3
TPC32t
PMBS3904 +5VLCM
1
1
4 4.7KOhm BAT1_IN#_OC 32 4
3
D
100KOhm
1
BAT2_IN#_OC 32
5
1
47KOhm R597
R669 100KOhm
U37
1
1
R615
4.7u
+2.5VREF
100KOhm
100KOhm
1 V+ 1
R681
R687
R676 100KOhm
+ 4 G C543
2 S Q97
1
3 0.1UF/25V
1
C551
-
2
GND
2
3
2N7002 Q109A
2
2
D46 R599 LMV331 R1005
2
2
2 1 205KOhm 2 UM6K1N 5
15KOhm T96
2
0.1UF
0.1UF
4
1
1
100KOhm
D GND
3
R578
R624
100KOhm
1
GND
C511
C519
1
2
1
1 2 43,54,55,58 TS1# 2 43,54,55,58 TS2# 5
G Q111A
S AC_APR_UC 43,54,55
1000PF/16V
2 Q95 UM6K1N Q111B
2
4
1
1
1000PF/16V
UM6K1N
C590
C553 2N7002
C595
0.1UF/25V
2
2
2
5 5
GND
GND GND
54 BAT_CTRL2
BATTERY SHUT_DOWN
bom BATTERY IN CIRCUIT
REVISION DATE: Monday, January 24, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 56 OF 63 BATLOW#/SD# RELEASE DATE : Amos Yu
A B C D E
A B C D E
T19
01/03 T422 T290 TPC32t
TPC32t TPC32t +3VO +3VSUS
Q62 JP6
D S JP16
1
8 1 1 1 2 2
+1.8VO
1
7 2 1 1 2 2 +1.8VS
6 3 1MM_OPEN_5MIL
5 G 4 2MM_OPEN_5MIL
T188
1 SI4800BDY TPC32t 1
+5VO +5VSUS
JP10
1
12/28
2
12/28 C440
1
1 1 2 2
R462 0.022U
24KOhm 1MM_OPEN_5MIL
2
GND
01/03
TPC32tTPC32t T284
1
TPC32t TPC32t Q114 T277 T278 TPC32t
T84 T86 8 D S 1 JP24
7 2
1
6 3 1 1 2 2 +3VS
T120
1
1
+3VO 5 G 4
1
C636 3MM_OPEN_5MIL TPC32t
2
SI4800BDY 11/26 0.1UF/25V AC_BAT_SYS
R990 C913 TPC32t TPC32t T311
1
Q123 +12VO
TPC32t TPC32t 0Ohm 0.1UF/25V T306 T307 GND TPC32t
T121 T289 D S r0603 /* C191
1
8 1 JP30
2
7 2 GND 0.1U U14
R168
1
6 3 1 1 2 2 +5VS 1 2 1 IN OUT 5
+5VO 845KOhm
1
5 G 4
1
2 3MM_OPEN_5MIL 2 2
GND
1
12/28 C712 C185
SI4800BDY 1U
1
1 2 GND 3 EN LEAA ADJ 4
C705 0.1UF/25V 0.1UF/25V 01/03
2
2
/* MIC5233BM5
2
GND
D75 GND R1003 0Ohm /* R173
RB520S_30 SUSC#_PWR 2 1 95.3KOhm
TPC32t SUSB#_PWR_ON 1/* 2 TPC32t
T94 T235 R1002 0Ohm
Q39
1
2 1 47,50 VSUS_ON 2 1
UMC4N R167 GND
10KOhm 8/3
1
1
+12VO +12VS
T218
4
3
E
47K
TPC32t
2
B
1
22,33,34,40,43,47,54 PM_SUSB# 2 1
T92 R170 +3VALWAYS
47K
10K
2
B
2
47K
TPC32t R179 0Ohm
R175 100KOhm
100KOhm
1
6
51,52,53 SUSB#_PWR
/*
1
+3VALWAYS
1
2 1
2
3 3
R977 100KOhm GND GND GND R157 SUSB#_PWR_ON
/*
100KOhm
6
01/03
1
TPC32tTPC32t TPC32t 2
TPC32t TPC32t T81 T73 T82 Q31A
1
T90 T88 Q27 UM6K1N
1
JP5 C162
8 D S 1
1
7 2 1 1 2 2 +3V 0.47U
1
2
+3VO 6 3
1
5 G 4 C114 3MM_OPEN_5MIL
3
Q31B
0.1UF/25V UM6K1N
SI4800BDY TPC32tTPC32t TPC32t SUSB#_PWR
2
GND 5
TPC32t TPC32t Q119 T296 T292 T56
T134 T54 D S
4
8 1 JP27
7 2 GND
1
6 3 1 1 2 2 +5V
+5VO
1
5 G 4
01/14 3MM_OPEN_5MIL
1
C679 +3VALWAYS
4 SI4800BDY 1 2 4
C680 0.1UF/25V 0.1UF/25V
2
GND
SUSC#_PWR_ON GND
01/03 R177 0Ohm
2
TPC32t 2 1/* 2 1 TPC32t
T107 T282 R158 SUSC#_PWR_ON
Q29 8/16 R149 10KOhm
UMC4N 100KOhm
6
1
+12VO +12V
T4
1
C
4
3
01/04
47K
TPC32t 2
R155 0Ohm Q30A
2
1
B
UM6K1N C160
1
1
22,43,44,47,48 PM_SUSC# 2 1
T288 R146
47K
2
10K
B
2
47K
TPC32t 1UF/16V
100KOhm
2
R154
1
51,52 SUSC#_PWR
3
100KOhm Q30B
1
+3VALWAYS UM6K1N
SUSC#_PWR
1
2 1 5
R976 100KOhm
4
GND GND GND
5 /* GND 5
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REVISION DATE: Monday, January 24, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 57 OF 63 LOAD SWITCH RELEASE DATE : Amos Yu
A B C D E
A B C D E
T173
TPC32t
1
1 2 BAT2_OFF# 54
R546 0Ohm
1
1 2 BAT1_OFF# 54
1
C816
1
1 100P 1
C498 8/16
2
T221 T222 T227 T231 T338 T172 T340 T343 GND
100P TPC32tTPC32t TPC32tTPC32t
2
TPC32tTPC32tTPC32tTPC32t GND
L78
CN18 Change to new
1
1 2 BAT 1 2 BAT
1 CN31
1 TPC32t TPC32t
2 T14 150Ohm/100Mhz 6 T174 L110 150Ohm/100Mhz
2 R548 R848 0Ohm
3 3 5
1
4 4 1 2 SMCLK_BAT1 32,54 4 1 2 SMCLK_BAT2 32,54
5 5 TPC32t 3 TPC32t
6 T13 0Ohm 2 T179
6 R547 R851 0Ohm
7 7
1
8 8 1 2 SMDATA_BAT1 32,54 1 1 2 SMDATA_BAT2 32,54
1
1 2 TS1# 43,54,55,56 1 2 TS2# 43,54,55,56
0Ohm
2 2
1
1
C496 C502 T310 C351 C341
T116 T323 C500 C499 C501 C506 T321 T309 TPC32t T308 C817 C818 C819 C814
TPC32tTPC32t T322 0.1UF/25V 0.1UF/25V 100P TPC32t TPC32t TPC32t 0.1UF/25V 0.1UF/25V
T386 TPC32t 100P 100P 100P 100P 100P 100P 100P
2
2
TPC32t
1
1
GND GND GND
GND
3 3
4 4
5 5
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REVISION DATE: Monday, January 24, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 58 OF 63 PIC16C54/BATCON/PWOK RELEASE DATE : Amos Yu
A B C D E
A B C D E
A/D_DOCK_IN
L78L05 +5VCHG (20mA) +5VLCM
SWITCH
(Regulator)
(F02JK2E) LM4040BIM
+2.5VREF
1
(Regulator) 1
VSUSON
SI9183DP
+3VO (6A) +3VSUS +1.5VSUS
(Regulator)
AC_BAT_SYS LTC3728LX +12VO (100mA)
(Controllor)
+5VO (4.2A) +5VSUS
SUSC#_PWR
+12V
(UMC4N)
2 2
+5V
(SI4800DY)
+3V
SUSB#_PWR
SUSC#_PWR
+1.8VO (7A) +1.8V RT9173ACL5 +0.9VS
(Regulator)
SUSB#_PWR
+12VS
(UMC4N)
+5VS
4 4
+3VS
+1.5VS
(SI4800DY)
+2.5VS
CPU_VRON
+5VO
MAX1987 +VCORE
(27A)
(Controllor)
VRM_PWRGD, CLK_EN#
5 5
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Revision History
R1.1
1 1
SYSTEM
1. (p48) Modify CPU +VCCA
2. (p45,47) Fix auto power on when AC in in AC mode
3. (p45,57) Solve U56 easily damaged
4. (p8) Add R941 for BIOS internal VGA strapping
5. (p8) U48, D30 change from ICH6_PWROK to VRM_PWRGD (p12) R363 change to 10K, C893=0.47uF
6. (p20) Fix PID1 can't strapped low
7. (p45) Modify power sequence of +3VSUS -> PM_RSMRST#
8. (p47) Fix that +3VSUS/+5VSUS may be turned on for a while when the power comes in at the first time
9. (p16) Fix TV out can't work
10. Add Bluetooth support
11. (p24) DEL reserved V5REF_SUS circuit
12. (p12) ADD net "CPUSEL0/1" for layout
13. (p37) Change X7 part
14. (p23) Add R949 to reduce overshoot
15. (p34) Solve pop noise in Windows boot
2
16. (p47) Power button debounce 2
17. Tune X'tal freq. (p22) C353/C356 (p26) C350/C354 (p32) C78/C93 (p41) C355/C360
18. (p27) Change CN32 part
19. (p43) Change R924 to +5VLCM to solve +5V leakage in power off.
20. (p20) Tune LCD_VCC timing
21. (p44) Modify CN10 pin define for ID change
22. (p23,34) Add ALC861VS PC-Beep support
23. (p33) ADD T388, U61.3 ADD "AUD_GPIO0" (p34) DEL R482, ADD U72
24. (p34,35) DEL net "MIC_AGND_A"
25. (p39) ADD voltage divider for Mic VREF
26. (p34) for EMI request
27. (p47) VSUS_OFF#
28. (p45) Modify power on sequence
29. (p43,p32) Reserved for bluetooth LED
30. (p39) Reserved PCI_INTC# for MINI-PCI.
31. (p29) Solve USB power surge warning when USB HDD plug-in
32. (p28) Support CSEL+ ODD
3 33. (p6) GMCH_THRMTRIP# no function in high temperature 3
34. (p10) unstuff for W3V
35. (p17) Adjust ATI 27MHz Vhigh
36. (p23) Aviod logic output unstable
37. (p4) Fix BT_VCC unstable
38. (p40) Tune clock timing
39. (p43) Tune LED current for LED spec
40. (p46) Adjust for +5VS_FAN stable
41. (p47) Fix can't power on in batttery mode
POWER
1 (p49) Add R942, MCH_OK connect to 1.8_2.5_1.5_1_PWRGD, C248, R233 unstuff
R2.0
SYSTEM
4 1. (p20) Adjust BACK_EN Vhigh 4
2. (p48) Change MDC nut
3. (p22,38,43) DEL BT_ON#, control BT_VCC by BT_LED#
4. (p29) Adjust for USB-IF spec
5. (p32) Solve SMBus loss pull-high power in power-off.
6. (p23) Reduce PCI_RSTNS# overshoot
7. (p23) Reduce 2V step on PCI_RST#
8. (p12) Tune W3V clock
9. (p25) Update PCB_VID
10. (p47) Solve system can't power on in battery mode
11. (p48) Modify +1.8VS_VCCA gate ckt
12. (p20) Avoid U28 damage
13. (p34) Remove reserved Windows de-pop Ckt
14. (p16) Tune W3A HSYNC/VSYNC timing
15. (p21) Tune W3V HSYNC/VSYNC timing
16. (p28) Modify for swap bay detection.
17. (p34) For EMI
18. (p20) For EMI
5
19. (p48) For PD4 5
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REVISION DATE: Wednesday, January 26, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 60 OF 63 History RELEASE DATE : Alice Shih
A B C D E
5 4 3 2 1
D D
DC IN
C C
CONDC1
9 9 GND2 11
JDC1 HDC1
8 8
4 P_GND1 1 7 C197D87
7
5 NP_NC 2 6 6
6 P_GND 3 5 5
1
4 4
GND 3 3
DC_PWR_JACK_3P 2 2
1 1 GND1 10 GND
GND GND
WTOB_CON_9P
B B
A A
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REVISION DATE: Wednesday, January 26, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 61 OF 63 DC_IN CONNECTOR RELEASE DATE : Renyu Wang
5 4 3 2 1
A B C D E
Block Diagram
ODD CONN.
2 2
+5VDOCK_ODD CONODD1
IDE_PDD1_ODD 1 66
IDE_PDDREQ_ODD 1 NP_NC4
2 2 NP_NC3 65
CONODD2 IDE_PDD0_ODD 3 64
IDE_PDIOR#_ODD 3 NP_NC2
4 4 NP_NC1 63
61 63 IDE_PDIOW#_ODD 5 62
NP_NC1 SIDE1 IDE_PDDACK#_ODD 5 SIDE_L
6 6 SIDE_R 61
IDE_PDD1_ODD 1 31 IDE_PIORDY_ODD 7 60 CD_R_A_ODD
IDE_PDDREQ_ODD 1 31 SATA_DET_#2_ODD IDE_PDIAG_ODD 7 60 CD_L_A_ODD
2 2 32 32 8 8 59 59
3 IDE_PDD0_ODD 3 33 INT_IRQ14_ODD 9 58 CD_GND_A_ODD 3
IDE_PDIOR#_ODD 3 33 BAYDOCK_IN#_ODD IDE_PDA2_ODD 9 58 CD_GND_A_ODD
4 4 34 34 10 10 57 57
IDE_PDIOW#_ODD 5 35 11 56 IDE_PDD8_ODD
IDE_PDDACK#_ODD 5 35 SATA_SWAP_TXN2_ODD IDE_PDCS3#_ODD 11 56 IDERST#_5S_ODD
6 6 36 36 12 12 55 55
IDE_PIORDY_ODD 7 37 SATA_SWAP_TXP2_ODD IDE_PDA1_ODD 13 54 IDE_PDD9_ODD
IDE_PDIAG_ODD 7 37 13 54 IDE_PDD7_ODD
8 8 38 38 14 14 53 53
INT_IRQ14_ODD 9 39 SATA_SWAP_RXN2_ODD IDE_PDA0_ODD 15 52 IDE_PDD10_ODD
IDE_PDA2_ODD 9 39 SATA_SWAP_RXP2_ODD 15 52 IDE_PDD6_ODD
10 10 40 40 16 16 51 51
11 41 IDE_PDCS1#_ODD 17 50 IDE_PDD11_ODD
IDE_PDCS3#_ODD 11 41 IDE_PDD15_ODD 17 50 IDE_PDD5_ODD
12 12 42 42 18 18 49 49
IDE_PDA1_ODD 13 43 IDE_PDD2_ODD IDE_PDASP#_ODD 19 48 IDE_PDD12_ODD
13 43 IDE_PDD14_ODD BAY_IN0_ODD 19 48 IDE_PDD4_ODD
14 14 44 44 20 20 47 47
IDE_PDA0_ODD 15 45 IDE_PDD3_ODD IDE_PCSEL_ODD 21 46 IDE_PDD13_ODD
15 45 IDE_PDD13_ODD PIN22_+5V_PH_ODD 21 46 IDE_PDD3_ODD
16 16 46 46 22 22 45 45
IDE_PDCS1#_ODD 17 47 IDE_PDD4_ODD 23 44 IDE_PDD14_ODD
17 47 IDE_PDD12_ODD 23 44 IDE_PDD2_ODD
18 18 48 48 24 24 43 43
IDE_PDASP#_ODD 19 49 IDE_PDD5_ODD 25 42 IDE_PDD15_ODD
BAY_IN0_ODD 19 49 IDE_PDD11_ODD 25 42
20 20 50 50 26 26 41 41
IDE_PCSEL_ODD 21 51 IDE_PDD6_ODD 27 40 SATA_SWAP_RXP2_ODD
PIN22_+5V_PH_ODD 21 51 IDE_PDD10_ODD 27 40 SATA_SWAP_RXN2_ODD
22 22 52 52 28 28 39 39
23 53 IDE_PDD7_ODD 29 38
23 53 IDE_PDD9_ODD BAY_IN1_ODD 29 38 SATA_SWAP_TXP2_ODD
24 24 54 54 30 30 37 37
25 55 IDERST#_5S_ODD 31 36 SATA_SWAP_TXN2_ODD
25 55 IDE_PDD8_ODD SATA_DET_#2_ODD 31 36
4 26 26 56 56 32 32 35 35 4
27 57 CD_GND_A_ODD 33 34 BAYDOCK_IN#_ODD
27 57 CD_GND_A_ODD 33 34
28 28 58 58
29 59 CD_L_A_ODD
BAY_IN1_ODD 29 59 CD_R_A_ODD BtoB_60P
30 30 60 60
1
CODD4 CODD5 CODD2 CODD3 CODD1
62 NP_NC2 SIDE2 64
0.1U 0.1U 0.1U 0.1U 0.1U
/* /* /* /* /*
2
BtoB_CON_60P
5 5
bom
REVISION DATE: Wednesday, January 26, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 62 OF 63 ODD BOARD RELEASE DATE : Joe Wu
A B C D E
A B C D E
15 1 RIGHT_TP 1
GND1 1 1
2 2 2 2
3 INTCLK_5S_TP 3
3 INTDATA_5S_TP LEFT_TP 3
4 4 4 4
2 TP Board Connector 5 5
6 +5VS_TPD_TP
5
6
5 2
6 6
7 7 7 7
8 INTCLK_5S_TP 8
8 8
9 9 9 9
10 WIRELESS_LED_TP INTDATA_5S_TP 10
10 HDD_LED_TP 10
11 11 11 11
12 CHG_LED_TP +5VS_TPD_TP 12
12 PWR_LED_TP 12
13 13 13 NC1
16 GND2 14 14 14 NC2
TP CONN. TP Button
FPC_CON_12P
FPC_CON_14P_TP&LED
LED CONN.
3 3
1
8 SIDE2
3 4 LEFT_TP 3 4 RIGHT_TP
1
5 5
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REVISION DATE: Wednesday, January 26, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <OrgName> DESIGN ENGINEER :
PROJECT: W3V 2.1 SHEET 63 OF 63 TP&LED BOARD RELEASE DATE : Joe Wu
A B C D E