“Soft” processor Datasheet

This Datasheet describes the processor to be implemented for the Software and Systems assignment. This is based on a slimmed down version of the
ARMv2 processor. You may want to cut and paste this information into one of your ‘C’ source files while you are developing your simulator so you can easily
refer to the information from your code.

/*
* The processor has 16 registers (all 32 bits in length).
*
* R0 - General Purpose
* R1 - General Purpose
* R2 - General Purpose
* R3 - General Purpose
* R4 - General Purpose
* R5 - General Purpose
* R6 - General Purpose
* R7 - General Purpose
* R8 - General Purpose
* R9 - General Purpose
* R10 - General Purpose
* R11 - General Purpose
* R12 - General Purpose (but often used as the stack pointer).
* R14 - General Purpose / Link register (see BL instruction)
* R15 - The program counter (note: the bottom 2 bits of the PC are always 0 0 when memory is accessed.
* i.e. memory is implicitly accessed on a word aligned boundary.)
*
* It also has an 8 bit status register (SR), see schematic below.
*
* -----------------------------------
* | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
* -----------------------------------
* | N | Z | C | V | I | F | S1 | S0 |
* -----------------------------------
*
* Bits 7-4 Status flag that identify the result of the last operation.
*
* Bit 7 Negative flag
* Bit 6 Zero flag
* Bit 5 Carry flag
* Bit 4 Overflow flag
*
* Bits 3-2 Interrupt disable flags, when set prevent the specified type of interrupt from being serviced
*
* Bit 3 Interrupt disable flag
* bit 2 Fast interrupt disable flag
*
* Bits 1-0 Identify the processor operation mode (User mode is 0 0)
*
* bit 1 Processor mode bit
* bit 0 Processor mode bit
*
*
* -------------------------------------------------------------------------------------------------------------------------
* Instruction set.
*
* All instructions are 32 bits in length. Bit 31-28 of all instructions contain a condition code which is used to decide
* whether the instruction will
* execute. This condition code identifies the required state of the status register (SR) in order for execution to take place.
*
* The table below shows each condition code value (stored in top 4 bits of the instruction) and the status flags which are
* tested to see whether the condition is true. If a status flag is blank then that means its value doesn't matter for that
* condition to be true.
*
* -------------------------------------------------------------------------------
* Condition Status Reg Flags
* Code | N | Z | C | V |
* -------------------------------------------------------------------------------
* Equal 0000 | | 1 | | | Execute the instruction if the Z flag is set.
* Not Equal 0001 | | 0 | | | Execute the instruction is the Z flag is clear.
* Carry Set 0010 | | | 1 | | Execute the instruction if the C flag is set. Provides >= test (unsigned).
* Carry Clear 0011 | | | 0 | | Execute if the C flag is clear. Provides < test for unsigned comparison.
* Minus 0100 | 1 | | | | Execute if the N flag is set.
* Plus 0101 | 0 | | | | Execute if the N flag is clear.
* Overflow Set 0110 | | | | 1 | Execute if the V flag is set. Provides test (along with N/Z) for signed comparison.
* Overflow Clear 0111 | | | | 0 | Execute if the V flag is clear. Provides test (along with N/Z) for signed comparison
* Higher 1000 | | 0 | 1 | | Execute if the C flag is set and Z flag is clear. Provides > test (unsigned).
* Lower or Same 1001 | | 1 | 0 | | Execute if the C flag is clear and Z flag is set. Provides <= test (unsigned).
* Greater or Equal 1010 | 0 | | | 0 | Execute if the N flag is clear and V flag is clear,
* | 1 | | | 1 | or N flag is set and V flag is set. Provides >= test for signed comparison.
*
* Less Than 1011 | 0 | | | 1 | Execute if the N flag is clear and V flag is set,
* | 1 | | | 0 | or N flag is set and V flag is clear. Provides a < test for signed comparison.
*
* Greater Than 1100 | 0 | 0 | | 0 | Same as GE but Z flag must be clear. Provides > test for signed comparison.
* | 1 | 0 | | 1 |
* Less or Equal 1101 | 0 | | | 1 | Same as LT but also true if Z flag is set.
* | 1 | | | 0 |
* | | 1 | | |
* Always 1110 | | | | | Instruction always executes. Flags irrelevant.
* Never 1111 | | | | | Instruction never executes. Flags irrelevant.
*
*
*
* Data processing instructions
* ----------------------------
*
* -------------------------------------------------------------------------------
* | 31..........28 | 27 | 26 | 25 | 24.....21 | 20 | 19...16 | 15....12 | 11.......0 |
* -------------------------------------------------------------------------------
* | Condition code | 0 | 0 | I | OpCode | S | RegN | RegDest | Operand 2 |
* -------------------------------------------------------------------------------
*
* Bit 20 - Set status register bit. If this is set then result of the operation is reflected in the status register (SR).
*
* Bit 25 - Immediate bit. If this is set then operand 2 is an immediate value as follows -
*
* ----------------------------------
* | Operand 2 (when I = 1) |
* ----------------------------------
* | 11........8 | 0............7 |
* | Shift amount | Immediate Value |
* ----------------------------------
*
* otherwise it is a register, with the following format -
*
* -----------------------------
* | Operand 2 (when I = 0) |
* -----------------------------
* | 11........4 | 0.......3 |
* | Shift amount | Reg number |
* -----------------------------
*
* -------------------------------------------------------------------------------
* OpCode (21..24) - Identifies the specific Data Processing Instruction
* -------------------------------------------------------------------------------
* AND 0000 RegDest = RegN & Operand2
* EOR 0001 RegDest = RegN ^ Operand2
* SUB 0010 RegDest = RegN - Operand2
* RSB 0011 RegDest = Operand2 - RegN
* ADD 0100 RegDest = RegN + Operand2
* ADC 0101 RegDest = RegN + Operand2 + (carry_flag)
* SBC 0110 RegDest = RegN - Operand2 - !(carry_flag)
* RSC 0111 RegDest = Operand2 - RegN - !(carry_flag)
* TST 1000 (RegDest = 0000) flags set as result of RegN & Operand2
* TEQ 1001 (RegDest = 0000) flags set as result of RegN ^ Operand2
* CMP 1010 (RegDest = 0000) flags set as result of RegN - Operand2
* CMN 1011 (RegDest = 0000) flags set as result of RegN + Operand2
* ORR 1100 RegDest = RegN | Operand2
* MOV 1101 (RegN = 0000) RegDest = Operand2
* BIC 1110 RegDest = RegN & ~Operand2
* MVN 1111 (RegN = 0000) RegDest = ~Operand2 *
*
*
* Branch Instructions (B and BL)
* ------------------------------
*
* These instructions allow changing of the program counter relative to the current position.
*
* --------------------------------------------------------------------
* | 31..........28 | 27 | 26 | 25 | 24 | 23.......................0 |
* --------------------------------------------------------------------
* | Condition code | 1 | 0 | 1 | L | Offset (Two's Complement) |
* --------------------------------------------------------------------
*
* Bit 24 - Link bit. If this is set then Branch with Link (BL) is executed, i.e. return addr pushed into R14 before branch.
*
*
*
* Single Data Transfer Instructions
* ---------------------------------
*
* ----------------------------------------------------------------------------------------
* | 31..........28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19..16 | 15.....12 | 11......0 |
* ----------------------------------------------------------------------------------------
* | Condition code | 0 | 1 | I | P | U | B | W | L | RegN | RegDest | Offset |
* ----------------------------------------------------------------------------------------
*
* Bit 25 - Immediate bit. Same as data processing instruction. See previous information
* for how this effects the offset in bits 11......0
*
*
* Bit 24 - Pre/Post bit. 0 = post (offset added after transfer), 1 = pre (offset added before transfer)
* Bit 23 - Up/Down bit. 0 = down (offset subtracted from base), 1 = up (offset added to base)
* Bit 22 - Byte/Word bit. 0 = transfer words, 1 = transfer byte.
* Bit 21 - Writeback bit. 0 = no Writeback, 1 = write back into base register.
* Bit 20 - Load/Store bit. 0 = store, 1= load
*
* RegN - the base (index) register
* RegDest - The register from which to transfer the data.
* Offset - Offset added to base register (contents depend on Bit 25).
*
*
* Software Interrupt Instruction
* ---------------------------------
*
* --------------------------------------------------------------------
* | 31..........28 | 27 | 26 | 25 | 24 | 23.......................0 |
* --------------------------------------------------------------------
* | Condition code | 1 | 1 | 1 | 1 | Interrupt code (ignored) |
* --------------------------------------------------------------------
*
* The interrupt code needs to be examined by the SWI handler. This is extracted
* by pulling the SWI instruction from memory. The address of the SWI instruction
* can be determined by the handler using the return address which is loaded into
* R14. e.g.
*
*
* LDR R0, [R14, #-4] ; this will the load the SWI instruction into R0
* BIC R0, R0, #xFF000000 ; This will leave only the Interrupt code bits (0..23)
*
*
*
* Instruction Timings (cycles)
* ---------------------------------
*
* Data processing operations 1 (+ 2 if RegDest is PC)
* LDR 3 (+ 2 if RegDest is PC)
* STR 2
* B, BL 3
* SWI 5
*
*
* Any instruction which is not executed due to condition code takes 1 cycle.
*/