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 PBUS Access
 The PBUS access provides access to the TDM bus. The connection capacity of the 8 Pseudo Wires is 8 x P12
(2048 Kbit/s). The connection capacity of the 8 E1 front interfaces is 8 x P12 (2048 Kbit/s). The PBUS access of
the P12 signals from the Pseudo Wires and the E1 front interfaces is handled independently.
 The PBUS access block performs the following traffic functions:
 • Clock extraction from the received P12 signal (structured and unstructured)
 • Termination of the received and transmitted P12 signal (structured according ITU-T G.704)
 • Cross connection of all PBUS signals
 Line interface
 The line interface of each of the 8 E1 ports provides the following features:
 • Signal receiver and transmitter (The 120 Ω or 75 Ω line termination is determined by the wiring of the cable)
 • Galvanic isolation
 • Protection against over-voltage
 Maintenance
 This block provides Loops, Generation and analysis of test signals and Synchronization signal distribution
 TCXO
 The temperature compensated crystal oscillator (TCXO) is used as timing reference for the adaptive timing
recovery circuits of the Pseudo Wires.
 CESoP processor
 The CESoP processor has three main tasks:
 • Packetise/depacketise the P12 TDM data signal to/from SAToP/RTP/UDP/IP packets. The packet payload size is
configurable from 4 to 1408 bytes.
 • Timing recovery from each Pseudo Wire with the adaptive timing recovery method.. Adaptive timing recovery
uses the time stamp in the RTP overhead of the received packets. To guarantee the timing quality the CESoP
processor requires a stable clock oscillator (TCXO).
 • Implementation of the Ethernet 1 Gbit/s link interface.
 GbE star
 The IP traffic is transported over two GbE links to the working and the protecting COGE5 unit.
 Subrack internal communication
 This is the proprietary KEYMILE ICN protocol, allowing Software download and unit control functions.
 Backplane access
 This provides access to the backplane for the control signals, allowing the units to be managed and provides
access to the double power feed of the subrack.
 Host processor
 Runs the embedded software (ESW) and controls the functions of the SATP8 unit. The embedded software
(ESW) is stored directly in the flash memory of the unit
 Power
 The SATP8 unit is directly powered from battery (-48 VDC or -60 VD

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SAToP Header Bytes
The SATP8 unit only uses the L & R bits in the SAToP Header.
The L bit is used to indicate to the remote end that the TDM data in the payload is invalid due
to a fault in the incoming TDM signal. The L bit usage is similar to the well known alarm
indication signal (AIS).
The R bit is used to indicate to the remote end that the local interworking function has
detected a packet loss state. The R bit usage is similar to the well known remote defect
indication (RDI) signal.
The length bits (LEN) are not used by the SATP8 unit. The bits are all set to 0.
The 16 bit sequence number is not used by the SATP8 unit. The bits are all set to 0. The
SATP8 unit uses the sequence number of the RTP header instead.

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R bit handling
At the packet ingress side of the SATP8 unit the packet loss ratio is monitored.
When the packet loss ratio exceeds the threshold of 10-3 during one second, the
excessive packet loss (EPL) defect is activated. The active EPL defect sets the
R bit in the SAToP header which in turn activates the remote excessive packet
loss (REPL) defect at the remote end of the Pseudo Wire. The Pseudo Wire
status dialogue at the remote end counts the number of times the received R bit
has changed its state from „0“ to „1“ and accumulates also the duration of the
received R bit to be „1“.
L bit handling
The L bit is used to indicate to the remote end a failure state of an incoming P12
signal and insert the AIS at the outgoing P12 signal as a consequent action.
On the transmitting side the following conditions must be fulfilled that the L bit
can be set by the SATP8 unit:
 The P12 termination mode must be „Transparent“ or „Clock Master“.
 The Pseudo Wire configuration for the „Transmitted L Bit“ must be set to
„Controlled“.
 On the receiving side the L bit is only evaluated by the SATP8 unit when:
 The Pseudo Wire configuration for the „Received L Bit“ is set to „Controlled.
The received L bit inserts the alarm indication signal (AIS) in the P12 path and
activates the L bit (LBIT) defect of the Pseudo Wire. The Pseudo Wire status
dialogue counts the number of times the received L bit has changed its state
from „0“ to „1“ and accumulates also the duration of the received L bit to be „1“.

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The version (V) bits are fixed to 2.
The padding (P) bit, extension (X) bit, CSRC count (CC) bits and marker (M) bit are all set to
0.
The payload type (PT) bits are set to 96 as the SATP8 unit uses a dynamic payload type.
Sequence Number: The 16 bit sequence number is incremented by one with every packet
sent out towards the packet network by the SATP8 unit. It may be used by the receiver to
detect packet loss and to restore the packet sequence.
Time Stamp: The 32 bit time stamp reflects the sampling instant of the first octet in the RTP
data packet. From packet to packet the time stamp is incremented by the number of payload
bits per packet. The time stamp is used by the receiver to recover the timing information from
the original TDM signal.
Synchronization Source Identifier: The 32 bit synchronization source (SSRC) identifier
identifies the originator of the packet. The SATP8 unit sets the first three bytes to 02, 03 and
04. The fourth byte is set to the Pseudo Wire index minus one: „pw-x - 1“. E.g. the SSRC of
pw-7 is set to 02-03-04-06.
UDP, IP, Ethernet: The UDP port is used by the SATP8 unit to distinguish the different
Pseudo Wires multiplexed to the same network address.
The packet traffic is transported with UDP/IP. The IP traffic can be assigned a Differentiated
Services Code Point (DSCP) to give the CESoP packets a high priority in the packet network.
The Transparent LAN Service (TLS) is used to add a Service VLAN ID and a Service VLAN
priority to the CESoP packets.
The CESoP traffic is transported over the Ethernet traffic port of the core unit COGE5 towards
the IP network.

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The synchronization function of the XMC20 for TDM signals supports two main
applications:
 Synchronous timing
 Plesiochronous timing
Synchronous timing means that the TDM signals in receive and transmit
direction are synchronized to the XMC20 internal plesiochronous equipment
timing source (PETS). Received TDM signals not synchronous to the PETS will
suffer bit or frame slips.
In the synchronous timing mode the PETS must fulfil the timing requirements for
the traffic interfaces of ITU-T G.823.
The following sources can be used for the synchronization of the PETS:
 Local oscillator
 2048 kHz synchronization input signal (esi-1, esi-2)
 Gigabit Ethernet clock of a network interface (COGE5 port-1, port-2)
 Received clock from a service unit (e.g. SATP8 port-y, SATP8 pw-b).
The PETS clock is distributed via the XMC20 internal PBUS to all units requiring
this clock, i.e. all units accessing the PBUS.
Plesiochronous timing means that the TDM signals in receive and transmit
direction are not synchronized to the PETS. The timing of these signals are
transparent.
In the plesiochronous timing mode the clock recovery circuit of a received TDM
signal must fulfill the timing requirements for the traffic interfaces of ITU-T G.823
The SATP8 Pseudo Wire circuit emulation timing (CET) clock recovery mode
must be configured according to the XMC20 timing application mode,
i.e. the TDM signal termination mode.

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Adaptive Clock Recovery Modes
The SATP8 unit supports three timing recovery modes with the adaptive clock recovery mode.
Each mode uses a different algorithm to recover the timing information from the received
CESoP packets.
The examples below all use the filter type 4.
 Adaptive 1:
The adaptive 1 mode uses an averaging technique to remove network noise. This works
best in applications where the packet delay variation (PDV) is small, or there is no long
term change in PDV.
In mode 1 the DCO never goes to the holdover state and tracks any frequency changes
quickly.
Mode 1 should only be used if mode 2 is not working and higher maximum time interval
error (MTIE) variations are acceptable.
The time from the application of a 20 ppm frequency step to the TDM input signal until the
DCO is in the acquired state again is about 1000 s.
 Adaptive 2:
The adaptive 2 mode is the recommended algorithm for most applications, yielding the
best combination of frequency accuracy and phase wander under most conditions.
The time from the application of a 20 ppm frequency step to the TDM input signal until the
DCO is in the acquired state again is about 1000 s.
 Adaptive 3:
The adaptive 3 mode trades off phase wander for frequency accuracy. It corrects the
output frequency more slowly, allowing the phase to wander further in order to keep the
output frequency more stable.
This works better than mode 2 in some applications where frequency accuracy is more
important than phase.
It can take a very long time until the DCO goes to the acquired state.
Mode 3 shall only be used for frequency sensitive services and applications.
The time from the application of the 20 ppm frequency step to the TDM input signal until
the DCO is in the acquired state again is about 5000 s.

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CET Synchronous Clock Recovery
The circuit emulation timing synchronous clock recovery mode of the SATP8 unit can be
configured per Pseudo Wire.
In receive direction, i.e. from the packet switched network, the TDM bytes are read out from
the jitter buffer with a clock synchronous to the PETS. The P12 handling is also performed
with the PETS timing. Consequently the received TDM signal on the PBUS is synchronous to
the PETS.
If the received TDM signal is not synchronous to the PETS, the write and read addresses to
and from the jitter buffer are not synchronous either. The read address will wander through the
jitter buffer until it reaches the upper or lower limit. Then the read address is re-adjusted to the
middle of the jitter buffer. As a consequence half of the jitter buffer is read out a second
time or half of the jitter buffer is lost.
In transmit direction, i.e. towards the packet switched network, the TDM signal on the PBUS,
synchronous to the PETS, is processed and mapped into CESoP packets. The generated
CESoP packets are synchronous to the PETS. The timestamp, counting the number of TDM
bits per packet, is also incremented with the PETS timing.

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CET Adaptive Clock Recovery
The circuit emulation timing adaptive clock recovery mode of the SATP8 unit can be
configured per Pseudo Wire.
The adaptive clock recovery mode is applicable for the synchronous and the plesiochronous
timing application.
Plesiochronous Application
In receive direction, i.e. from the packet switched network, the packet processing block
evaluates the number of TDM bits received and forwards this information to the adaptive clock
recovery block. In parallel the digitally controlled oscillator (DCO) inside the adaptive clock
recovery block counts the number of bits it expects. If the expected number of bits is higher
than the effectively received bits, the DCO frequency is decreased. If the expected number of
bits is lower than the effectively received bits, the DCO frequency is increased.
TDM bytes are read out from the jitter buffer with the recovered clock. The P12 handling is
performed also with the recovered clock. Consequently the received TDM signal on the PBUS
is synchronous to the received signal.
In transmit direction, i.e. towards the packet switched network, the TDM transmit signal on the
PBUS, synchronous to the received signal at the TDM interface of the XMC20, is processed
and mapped into CESoP packets. The generated CESoP packets are synchronous to the
transmit signal. The timestamp, counting the number of TDM bits per packet, is also
incremented with the TDM transmit signal timing.

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Synchronous Application
In receive direction, i.e. from the packet switched network, the packet processing block
evaluates the number of TDM bits received and forwards this information to the adaptive clock
recovery block. In parallel the digitally controlled oscillator (DCO) inside the adaptive clock
recovery block counts the number of bits it expects. If the expected number of bits is higher
than the effectively received bits, the DCO frequency is decreased. If the expected number of
bits is lower than the effectively received bits, the DCO frequency is increased.
TDM bytes are read out from the jitter buffer with the recovered clock. In the P12 handling
block the TDM signal is then synchronized to the PETS timing in a FIFO. Consequently the
received TDM signal on the PBUS is synchronous to the PETS.
If the received TDM signal is not synchronous to the PETS, the write and read addresses to
and from the FIFO are not synchronous either. Frame slips will occur.
In transmit direction, i.e. towards the packet switched network, the TDM signal on the PBUS,
synchronous to the PETS, is processed and mapped into CESoP packets. The generated
CESoP packets are synchronous to the PETS. The timestamp, counting the number of TDM
bits per packet, is also incremented with the PETS timing.

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