VLSI DESIGN FLOW

STICK DIAGRAMS &

LAYOUTS

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VLSI DESIGN FLOW

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 STICK DIAGRAMS
• Cartoon of a layout.
• Shows all components.
• Does not show exact placement, transistor sizes,
wire lengths, wire widths, boundaries, or any
other form of compliance with layout or design rules.
• Useful for interconnect visualization, preliminary layout
layout compaction, power/ground routing, etc.

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 Stick Diagrams Color Representation
Metal

poly

ndiff

pdiff
Can also draw
in shades of
Buried Contact gray/line style.

Contact Cut

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5V 5v

Dep

Vout

Enh Vin

0V

0V
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 Alternate Layout Strategy

x
x

X X

A B
A B
X X

y y

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Parallel Connected MOS Patterning

x x
A B
A B

X X X

y
y

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 General Layout Geometry
Vp

Shared drain/
source

Individual Shared Gates

Transistors

Gnd

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 Designing MOS Arrays
A B C

x y

A B C

x
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CMOS STICK DIAGRAMS

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 Layer Types
• p-substrate
• n-well
• n+
• p+
• Gate oxide (thin oxide)
• Gate (polycilicon)
• Field Oxide
– Insulated glass
– Provide electrical isolation
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 Top view of the FET pattern
NMOS NMOS PMOS PMOS

n+ n+ n+ n+ p+ p+ p+ p+

n-well

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 The CMOS NOT Gate
Contact
Cut
Vp Vp
X n-well

X
x x
x x X

X
Gnd

Gnd

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 Alternate Layout of NOT Gate
Vp
Vp

X X

x x

X X

Gnd
x Gnd
x

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 Example - Stick Diagrams

Alternatives - Pull-up Network

Circuit Diagram. Pull-Down Network Complete Stick Diagram

(The easy part!)

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Example - Stick Diagrams
A
OUT
B

NOR Gate

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Example - Stick Diagrams

Power

A Out

Ground

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 NAND2 Layout
Vp Vp

X X X
a.b

Gnd a.b
a b
X X

a b
Gnd

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 NOR2 Layout
Vp
Vp

X X

a+b
a+b

a b X
Gnd X X
a b
Gnd

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 Dynamic latch stick diagram

VDD

in out

VSS
phi
phi’
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Stick Diagram XOR Gate Examples

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 Stick Diagrams
• Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers

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 Stick Diagrams
◼ Stick diagrams help plan layout quickly
◼ Need not be to scale
◼ Draw with color pencils or dry-erase markers

VDD

Vin
Vout

GND

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 Wiring Tracks
• A wiring track is the space required for a
wire
– 4  width, 4  spacing from neighbor = 8 
pitch
• Transistors also consume one wiring track

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 Well spacing
• Wells must surround transistors by 6 
– Implies 12  between opposite transistor flavors
– Leaves room for one wire track

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 Area Estimation
• Estimate area by counting wiring tracks
– Multiply by 8 to express in 

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 Example: O3AI
• Sketch a stick diagram for O3AI and estimate area
–
Y = ( A + B + C) • D

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 Example: O3AI
• Sketch a stick diagram for O3AI and estimate area
– Y = ( A + B + C) • D

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 Example: O3AI
• Sketch a stick diagram for O3AI and estimate area
– Y = ( A + B + C) • D

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Inverter stick diagram with colors

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CMOS Transmission Gate Stick Diagram

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STICK DIAGRAM AND TRANSISTOR LEVEL
DIAGRAM OF THE LATCH CIRCUIT

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Design Rules

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MODERN INTERCONNECT

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 Design Rules Description
• Design rules or layout rules provide strict guide lines
for preparing the geographic layouts, which will be
used to configure the actual masks used during
fabrication.

• Design rules are the effective interface between the

circuit/system engineer and fabrication engineer.

• The goal of any design rule set is to optimize yield

while keeping the geometry as small as possible
without compromising the reliability of the finished
circuit.
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 Micron Rules
• The layout constraints such as minimum
feature size and minimum allowable feature
separation are stated in terms of absolute
dimensions in micrometres.
 λ( lambda ) - based design rules
• Proposed by Mead and Conway.

• Single parameter (λ) and thus allow linear,

proportional scaling of all geometries constraints

• Provides a process and feature size independent

way of setting out mask dimensions to scale.

• These rules allows for scaling of the designs to a

limited extent, so that the designs are safe for a
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 λ( lambda ) - based design rules

• Design rules specify line widths, separations

and extensions in terms of λ.

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Design rules for wires (nMOS and CMOS)

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Design rules for Transistors

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 Design rules for contacts

The 2 λ X 2 λ contact cut indicates an area in which the oxide

is to be removed down to the underlying polysilicon or diffusion
Surface.
when deposition of the metal layer takes place, the metal
Is deposited through the contact cut areas onto the underlying area
So that contact is made between the layers.

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3 input NOR gate

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 λ (lambda) based design rules - CMOS
• Includes design rules for nMOS and few more
rules unique to well process.
– Ex : in case of N-well CMOS process, N-well, N+ mask and the
special substrate contacts

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P-well CMOS design rules

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P-well CMOS design rules

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CMOS INVERTER

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CMOS INVERTER

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 ORBIT 2 µm double metal double poly
CMOS / BiCMOS rules

• N – well : brown
• P – well : brown
• Poly 1 : red
• Poly 2 : orange
• n-diffusion or n-active : green
• p-diffusion or p-active : yellow or a
green outline to the yellow

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LAYOUTs FOR NAND NOR GATES

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Scaling of MOS Circuits

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 Scaling
• VLSI technology is constantly evolving towards
smaller line widths
• Reduced feature size generally leads to
– better / faster performance
– More gate / chip
• More accurate description of modern
technology is ULSI (ultra large scale integration

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 Scaling Factors
• In our discussions we will consider 2 scaling
factors, α and β
• 1/ β is the scaling factor for VDD and oxide
thickness D
• 1/ α is scaling factor for all other linear
dimensions
• We will assume electric field is kept constant

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 Scaling Factors for Device Parameters
• Simple derivations showing the effects of scaling are derived in Pucknell
and Eshraghian pages 125 - 129
• It is important that you understand how the following parameters are
effected by scaling
• Gate Area
• Gate Capacitance per unit area
• Gate Capacitance
• Charge in Channel
• Channel Resistance
• Transistor Delay
• Maximum Operating Frequency
• Transistor Current
• Switching Energy
• Power Dissipation Per Gate (Static and Dynamic)
• Power Dissipation Per Unit Area
• Power - Speed Product

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 Scaling of Interconnects

• Resistance of track R ~ L / wt A
• R (scaled) ~ (L / α) / ( (w/ α )* (t
/α))
t w
• R(scaled) = αR L

• therefore resistance increases with

scaling

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 Scaling - Time Constant
• Time constant of track connected to gate,
• T = R * Cg
• T(scaled) = α R * (β / α2) *Cg = (β / α) *R*Cg
• Let β = α, therefore T is unscaled!
• Therefore delays in tracks don’t reduce with scaling
• Therefore as tracks get proportionately larger, effect gets
worse
• Cross talk between connections gets worse because of
reduced spacing

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NAND3 (using Electric)

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 CMOS Layers
• n-well process
• p-well process
• Twin-tub process

Jhon P. U ECE
 n-well process
Gate NMOS NMOS PMOS PMOS

FOX

n+ n+ n+ n+ p+ p+ p+ p+

n-well
p-substrate

MOSFET Layers in an n-well process

Jhon P. U ECE
 Layer Types
• p-substrate
• n-well
• n+
• p+
• Gate oxide
• Gate (polycilicon)
• Field Oxide
– Insulated glass
– Provide electrical isolation

Jhon P. U ECE
 Top view of the FET pattern
NMOS NMOS PMOS PMOS

n+ n+ n+ n+ p+ p+ p+ p+

n-well

Jhon P. U ECE
 Metal Interconnect Layers
• Metal layers are electrically isolated from each
other
• Electrical contact between adjacent
conducting layers requires contact cuts and
vias

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 Metal Interconnect Layers
Ox3
Via
Metal2

Active Ox2
contact
Metal1

Ox1

n+ n+ n+ n+

p-substrate

Jhon P. U ECE
 Interconnect Layout Example
Gate contact

Metal1

Metal2

Metal1
MOS

Active contact

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 Designing MOS Arrays
A B C

x y

A B C

x
Jhon P. U ECE
Parallel Connected MOS Patterning

x x
A B
A B

X X X

y
y

Jhon P. U ECE
 Alternate Layout Strategy

x
x

X X

A B
A B
X X

y y

Jhon P. U ECE
 Basic Gate Design
• Both the power supply and ground are routed
using the Metal layer
• n+ and p+ regions are denoted using the same
fill pattern. The only difference is the n-well
• Contacts are needed from Metal to n+ or p+

Jhon P. U ECE
 The CMOS NOT Gate
Contact
Cut
Vp Vp
X n-well

X
x x
x x X

X
Gnd

Gnd

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 Alternate Layout of NOT Gate
Vp
Vp

X X

x x

X X

Gnd
x Gnd
x

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 NAND2 Layout
Vp Vp

X X X
a.b

Gnd a.b
a b
X X

a b
Gnd

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 NOR2 Layout
Vp
Vp

X X

a+b
a+b

a b X
Gnd X X
a b
Gnd

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 NAND2-NOR2 Comparison
Vp
X X
X

X
X
Gnd

Vp

X
X

MOS Layout X
Wiring X X
Gnd

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 General Layout Geometry
Vp

Shared drain/
source

Individual Shared Gates

Transistors

Gnd

Jhon P. U ECE
 Graph Theory: Euler Path
Vp

x Vertex b c
x

Edge a

Out

y
y c
Vertex a

Gnd
Jhon P. U ECE
 Topics
• Combinational logic functions.
• Static complementary logic gate structures.

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 Combinational logic expressions
• Combinational logic: function value is a
combination of function arguments.
• A logic gate implements a particular logic
function.
• Both specification (logic equations) and
implementation (logic gate networks) are
written in Boolean logic.

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 Gate design
Why designing gates for logic functions is non-
trivial:
– may not have logic gates in the libray for all logic
expressions;
– a logic expression may map into gates that
consume a lot of area, delay, or power.

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 Boolean algebra terminology
• Function:
f = a’b + ab’
• a is a variable; a and a’ are literals.
• ab’ is a term.
• A function is irredundant if no literal can be
removed without changing its truth value.

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 Completeness
• A set of functions f1, f2, ... is complete iff
every Boolean function can be generated by a
combination of the functions.
• NAND is a complete set; NOR is a complete
set; {AND, OR} is not complete.
• Transmission gates are not complete.
• If your set of logic gates is not complete, you
can’t design arbitrary logic.
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 Static complementary gates
• Complementary: have complementary pullup
(p-type) and pulldown (n-type) networks.
• Static: do not rely on stored charge.
• Simple, effective, reliable; hence ubiquitous.

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 Static complementary gate structure
Pullup and pulldown networks:

VDD

pullup
network

inputs out

pulldown
network

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 Inverter

a out

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 Inverter layout
VDD
+

tub ties
(tubs not
out transistors
a shown)
a out

GND

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 NAND gate

out
b
a

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 NAND layout
VDD
+

out

out
tub
b ties
a

a
GND

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 NOR gate

out

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 NOR layout

VDD
b

a tub ties
b
out
out

a
GND

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 AOI/OAI gates
• AOI = and/or/invert; OAI = or/and/invert.
• Implement larger functions.
• Pullup and pulldown networks are compact:
smaller area, higher speed than NAND/NOR
network equivalents.
• AOI312: and 3 inputs, and 1 input (dummy),
and 2 inputs; or together these terms; then
invert.
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 AOI example
out = [ab+c]’:

invert
symbol circuit

or

and

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 Pullup/pulldown network design
• Pullup and pulldown networks are duals.
• To design one gate, first design one network,
then compute dual to get other network.
• Example: design network which pulls down
when output should be 0, then find dual to
get pullup network.

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Dual network construction

a
a

dummy
b c
b c

dummy

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