What your final project report should have:

1) Names of teams members.

2) Schematic of the circuit you are designing.
3) Paper and pencil analysis showing calculation of transistors’ geometries and
bias voltages employed. (Provide sizes in a table. Name of transistors in the table
should match with your schematic).
4) Pre-layout simulation:
a. Provide an AC analysis of both the phase and gain such that the unity gain
frequency and DC gain are visible. Place markers at these points: DC gain,
unity gain frequency (where the gain curve intersects 0 dB), and in the
phase curve at the unity gain frequency. The purpose of these markers is to
show the numerical values of your DC gain, unity gain frequency, and
phase margin. To place a marker, once you have plotted your simulation
results, click on the menu Marker – Place – Trace Marker and then
click the point in your plot that you want to mark.
b. Provide also a TRANSIENT analysis simulation plot showing the output
and the input waveforms for input amplitude of 1 mV.
5) Provide a print out of your layout. Regarding the layout there are a couple of
issues:
a. Since the designs will be fabricated, you have to provide an error-free
layout. Check for errors using DRC.
b. Do not forget to bias the n-well and p-substrate. You can bias them by
placing the appropriate contacts (see Tutorial IV for how to do this)
c. Use metal1 layer for the VDD and GND connections.
d. Place the pins for the inputs or outputs on the sides of the layout so they
can be easily accessed when I route the whole chip.
e. For the VDD and GND pins use capital letters when naming the pins,
i.e., VDD! and GND! (see figure at the end of this document)
6) Email me the gds file of your layout and the Top Cell Name (see Tutorial IV for
how to generate this)
7) Extract circuit connectivity from layout (see Tutorial IV for how to do this)
8) Simulate the extracted circuit using hspiceS (do not use spectreS for the post-
layout simulation).
9) Plot AC and TRANSIENT results for the post-layout simulation.
Final report should not exceed 25 pages. You should be able to hand in a complete
yet concise report of your work.

VDD!

Vin1 out

Vin2 Rest of bias2

circuit
bias1

GND!