dce

2017

Digital Sytems
MSI Circuits

BK
TP.HCM
dce
Introduction
2017

• FFs and logic gates are combined to form

various counters and registers.
• Part 1 covers counter principles, various
counter circuits, and IC counters.
• Part 2 covers several types of IC registers and
shift register counter troubleshooting.
dce
2017

Decoders

• Define:
- A decoder is a logic circuit that accepts a set of inputs
that represents a binary number and activates only the
output that corresponds to that input number.
- Decoder circuit looks at its inputs, determines which
binary number is present there, and activates the one
output that corresponds to that number; all other
outputs remain inactive.
dce
2017

The diagram for a general decoder with N inputs

and M outputs. N inputs can be 0 or 1, there are 2n
possible input combinations . For each of these input
combinations, only one of the M outputs will be active
(HIGH); all the other outputs are LOW. (reverse).
dce
2017

In that application, the FFs in the counter provided

the binary code inputs for the decoder. The same basic
decoder circuitry is used no matter where the inputs come
from. The circuitry for a decoder with three inputs and 23 =
8 outputs. It uses all AND gates, and so the outputs are
active-HIGH.
dce
2017
ENABLE Inputs

• Some decoders have one or more ENABLE

inputs that are used to control the operation of
the decoder.
• With ENABLE held LOW, all of the outputs will
be forced to the LOW state regardless of the
levels at the A, B, C inputs.Thus,the decoder is
enabled only if ENABLE is HIGH.
dce
2017

(a) Which output will be activated for A4A3A2A1A0 = 01101 ?

(b) What range of input codes will activate the Z4 chip?
dce
2017

• (a) The five-bit code has two distinct parts.

- The A4 and A3 determine which one of the decoder chips
Z1 to Z4 will be enabled,
- A2 A1 A0 determine which output of the enabled chip will be
activated.
- With A4A3 = 01 only Z2 has all of its enable inputs activated.
- Thus, Z2 responds to the A2A1A0 = 101 code and activates
its -05 output, which has been renamed -O13.  input code
01101.
=> Output –O13 is LOW, all others stay HIGH.
dce
2017

• (b) To enable Z4 both A4 and A3 must be HIGH.

Thus, all input codes ranging from 11000 (2410 )
to 11111 (3110) will activate .This corresponds to
outputs to outputs -O24 to –O31
 BCD-to-Decimal Decoder
dce
2017

Those figures
below shows the
logic diagram for a
7442 BCD-to-
decimal decoder. It
is also available as a
74LS42 and a
74HC42.

(a) Logic diagram for the 7442 BCD-to-decimal

decoder
 (b) Logic symbol

 The logic symbol and the truth table

for the 7442 are also shown in the
figure. Note that this decoder does not
have an enable input.
(c) Truth table.
dce
2017 BCD-to-Decimal Decoder / Driver

• The TTL 7445 is a BCD-to-decimal

decoder/driver. The term “driver” is added to
its description because this IC has open-
collector outputs that can operate at higher
current and voltage limits than a normal
TTL output.
• This makes them suitable for directly driving
loads such as indicator LEDs or lamps,
relays, or DC motors.
dce
2017

Decoder Applications
Decoders are used whenever outputs are to be
activated with specific input levels provided by
the outputs of a counter or a register.
dce
2017

Counter/decoder combination used to provide

timing and sequencing operations .
dce
2017

7-Segment LED

• Form the decimal characters 0

through 9 and sometimes the hex
characters A through F.
• One common arrangement uses light-
emitting diodes (LEDs) for each
segment. By controlling the current
through each LED, some segments
will be light and others will be dark
so that the desired character pattern
will be generated
• The normal brightness is: 10mA,
FIGURE 9-7 (a) 7-segment 2.7V
arrangement; (b) active
segments for each digit.
dce
2017
BCD-to-7-segment Decoder/Driver

• A BCD-to-7-segment
decoder/driver is used to take a
four-bit BCD input and provide the
outputs that will pass current
through the appropriate segments
to display the decimal digit
• The logic for this decoder is more
complicated than the logic of
decoders that we have looked at
previously because each output is
activated for more than one
combination of inputs.

FIGURE 9-8 (a) BCD-to-7-

segment decoder/driver driving a
common-anode 7-segment LED
display; (b) segment patterns for
all possible input codes.
 Common-Anode Versus
dce
2017

Common-Cathode LED
Displays

• The LED display used in Figure 9-8

is a common-anode type because the
anodes of all of the segments are
tied together to Vcc
• Another type of 7-segment LED
display uses a common-cathode
arrangement where the cathodes of
all of the segments are tied together
and connected to ground. This type
of display must be driven by a BCD-
to-7-segment decoder/driver with
active HIGH outputs that apply a
HIGH voltage to the anodes of those
segments that are to be activated
dce
2017

9-3 LIQUID-CRYSTAL DISPLAYS

BK
TP.HCM
dce
2017

9-3 Liquid-Crystal Displays

A liquid-crystal display (LCD) controls the reflection of
available light.

Reflective LCDs use ambient light: The available light may

simply be ambient (surrounding) light such as sunlight or
normal room lighting.

Backlit LCDs : the available light might be provided by a small

light source that is part of the display unit.

LCDs operate from a low-voltage (typically 3 to 15 V rms),

low-frequency (25 to 60 Hz) ac signal and draw very little
current.
 9-3 Liquid-Crystal Displays
FIGURE 9-9 Liquid-crystal display: (a) basic
arrangement; (b) applying a voltage between the
segment and the backplane turns ON the
segment. Zero voltage turns the segment OFF.
- The Backplane is common to all
segments.
- Ac voltage is applied between the
segment and the backplane to turn
on this segment.
+ When there is no
difference in voltage between a
segment and the backplane, the
segment is said to be non-activated
(OFF) and will reflect incident light
so that they appear invisible against
their background.
+ When an appropriate
ac voltage is applied between a
segment and the backplane, the
segment is activated (ON) will not
reflect the incident light so that they
appear dark against their back.
 Driving an LCD
- An LCD segment will turn
ON when an ac voltage is
applied between the segment
and the backplane, and will
turn OFF when there is no
voltage between the two.
- It is common practice to
produce the required ac voltage
by applying out-of-phase
square waves to the segment
and the backplane.
- In Figure 9-10(a), A 40-Hz
square wave is applied to the
backplane and also to the input
of a CMOS 74HC86 XOR. The
other input to the XOR is a
CONTROL input that will
FIGURE 9-10 (a) Method for driving an LCD segment;
(b) driving a 7-segment display. control whether the segment is
ON or OFF.

FIGURE 9-10 (a) Method for driving an LCD segment;
(b) driving a 7-segment display.
Driving an LCD
- In Figure 9-10(b), using the
CMOS 74HC4511 BCD-to-7-
segment decoder/driver
supplies the CONTROL signals
to each of seven XOR for the
seven segments.
- The decoder/driver and XOR
gates of Figure 9-10(b) are
available on a single chip.
- CMOS devices are used to
drive LCDs for two reasons:
+ They require
much less power than TTL and
are more suited to the battery-
operated applications where
LCDs are used.
+ The TTL LOW-
state voltage is not exactly 0 V
and can be as much as 0.4 V
 Types of LCDs
- Liquid crystals are available as multidigit 7-segment decimal numeric displays. They
come in many sizes and with many special characters:
∙ Colons (:) for clock displays.
∙ + and - indicators for digital voltmeters.
∙ Decimal points for calculators.
∙ Battery-low indicators.

- The alphanumeric LCD module is a more complicated but readily available LCD
display.
These modules are available in numerous formats like 1-line-by-16-characters up to 4-
lines-by-40-characters.

- Other LCD modules allow the user to create a graphical display by controlling
individual dots on the screen called pixels. In these displays, the control lines are
arranged in a grid of rows and columns.

- Each pixel on a color display is actually made up of three subpixels which control the
light that passes through a red, green, or blue filter to produce the color of each pixel.
On a 640-by-480 LCD screen there would be connections for columns and 480
connections for rows, for a total of 2400 connections to the LCD
 Types of LCDs
We can separate LCDs into 2 types:
Passive Matrix LCD Active Matrix LCD

Allow high resolution Allow very high resolution

It is usually limited to about 50 It is not limited to about 50 rows

rows

Each sub-pixel is not individually Each sub-pixel is individually

controlled by an isolated thin film controlled by an isolated thin film
transistor (TFT) transistor (TFT)

Slow response time Fast response time

dce
2017
Introduction of Encoders
Introduction of Encoders

An octal-to-binary encoder (8-line-to-3-line encoder) accepts

eight input lines and produces a three-bit output code
depending on the active input.
dce
2017
Types of encoders
dce
2017
Priority encoders

 Priority Encoders is a modified version

which includes the necessary logic to
ensure that when two or more inputs are
activated, the output code will correspond
to the highest-numbered input.

 The 74148, 74LS148, and 74HC148 are

all octal-to-binary priority encoders.
74147 decimal-to-bcd priority encoder

 Having 9 active LOW

input representing the
decimal digit 1 through
9.

 Producing the
INVERTED BCD code
corresponding to the
highest order activated
inputs.
dce
2017

Truth Table Of IC 74147

dce
74147 decimal-to-bcd priority encoder
2017

 The 74147 is called the priority encoder because it

gives priority to the highest-ordered input.

 For example ,when input X3, X5, X7 are LOW and all
the input are HIGH, based on the truth table that when
X7 is low the level at X3, X5 dose not matter the output
will be 1000 (inverse of 0111).
dce
2017
Switch encoder
 Switch Encoder is Priority Encoder.

 It has 10 switches representing 10 digits from 0 to 9.

 The switches are normally open type.

 The inputs are usually HIGH.

 The BCD outputs is 0000.

dce
2017
Switch encoder

Decimal-to-BCD Switch Encoder

dce
2017

Circuit For Keyboard Entry Of

Three-digit Number Into Storage Registers
dce
2017

Multiplexers (Data Selectors)

Quad Two-Input
Basic Two-Input MUX
Multiplexer (74ALS157/HC157
)

Four-Input Eight-Input
Multiplexer Multiplexer
 dce2017

Basic Two-Input Multiplexer

The logic level
applied to
the S input
determines
which AND gate
is enabled
so that its data
input
passes through
the OR gate
The Boolean expression for the output is to output Z.
With S = 0 this expression becomes:

With S = 1 the expression becomes:

dce
2017

Basic Two-Input Multiplexer

• An example of where a two-input MUX could be used
is in a digital system that uses two different MASTER
CLOCK signals: a high-speed clock (say, 10 MHz) in
one mode and a slow-speed clock (say, 4.77 MHz) for
the other.
• Using the circuit above, the 10-MHz clock would be
tied to I0 and the 4.77-MHz clock would be tied to I1.
• A signal from the system’s control logic section would
drive the SELECT input to control which clock signal
appears at output Z for routing to the other parts of the
circuit.
dce
2017

Four-Input Multiplexer
• Four inputs are selectively
transmitted to the output
according to the four
possible combinations of
the S1S0 select inputs.
• Each data input is gated
with a different
combination of select
input levels.
• I0 is gated with S1S0 so
that I0 will pass through its
AND gate to output Z only
when S1 = 0 and S0 = 0.
dce
2017

Four-Input Multiplexer

• This approach uses

tristate buffers to select
one of the signals.
• The decoder ensures that
only one buffer can be
enabled at any time.
• S1 and S0 are used to
specify which of the input
signals is allowed to pass
through its buffer and
arrive at the output.
dce
2017

Eight-Input Multiplexer
• This multiplexer has an enable input and
provides both the normal and the inverted
outputs.
• When E’= 0, the select inputs S2S1S0 will
select one data input (from I0 through I7 )
for passage to output Z.
• When E’= 1, the multiplexer is disabled so
that Z = 0 regardless of the select input
code.
dce
2017

Eight-Input Multiplexer

The logic diagram for the 74ALS151 (74HC151) eight-input multiplexer.

dce
2017

Eight-Input Multiplexer

Two 74HC151s
combined to form
a 16-input multiplexer.
dce
2017

Eight-Input Multiplexer
• This circuit has a total of 16 data inputs, eight applied to
each multiplexer.
• The two multiplexer outputs are combined in the OR
gate to produce a single output X.
• The four select inputs S3S2S1S0 will select one of the 16
inputs to pass through to X.
• When S3 = 0, the top multiplexer is enabled, and the
inputs S2S1S0 determine which of its data inputs will
appear at its output and pass through the OR gate to X.
• When S3 = 1, the bottom multiplexer is enabled, and the
S2S1S0 inputs select one of its data inputs for passage to
output X.
dce
2017
Quad Two-Input MUX (74ALS157/HC157)

• The 74ALS157 is a very useful multiplexer

IC that contains four two-input multiplexers.

EXAMPL Determine the input conditions required for each Z

E output to take on the logic level of its
corresponding I0 input. Repeat for I1.
dce
2017
Quad Two-Input MUX (74ALS157/HC157)
dce
2017
dce
2017

Demultiplexer (DEMUX): reverse

operation of multiplexer

=> takes a single input and distributes

it over several outputs
dce
2017
dce
2017

IC
74ALS138
dce
2017

For example:
When S0S1S2=000
+ only AND gate 0 is
enabled.
+ data input I will appear
at output O0.
dce
2017

-E2’ and E3 are always

held in their active states.
=> The output follow the
signal on E1’.

-Case A1A2A3=000: Only

O0’ output is actived.
dce
2017

In An industrial plant:

BK
TP.HCM
dce
2017
dce
2017
dce
2017
dce
2017
dce
2017

MAGNITUDE COMPARATOR

BK
TP.HCM
dce
2017

DEFINITION
• A combination logic circuit that indicates
which of 2 binary quantity inputs is greater.
dce
2017

DATA INPUT & OUTPUT

• Input: The 74HC85 compares 2 unsigned
4-bit binary number.
• Output: The 74HC85 has 3 active-HIGH
outputs (for 3 states of result)
dce
2017

CASCADING INPUT
• Expand the comparison operation to
more than 4 bits
• The inputs are labeled the same as the
outputs.
• When 2 comparators are to be cascaded,
the output of the lower-order one is
connected to the input of higher-order one.
dce
2017

CASCADING INPUT
dce
2017

APPLICATION
• Useful in control applications where a
binary number represent the physical
variable.
dce
2017

Overview: Tri-state Register

_ Is 4-bit register

_ Allows 2 modes of operation:

+ load – the data at inputs D0 to D3 are transferred
into the FFs on the PGT of the clock pulse at CP.
+ hold – the data in the register do not change
when the PGT of CP occurs.
dce
2017
Tristate buffer

Enable Input Output

0 0 discornected
0 1 discornected
1 0 0
1 1 1
dce
2017
74ALS173 tristate register
dce
2017
74ALS173 tristate register
dce
2017
Data Bus Operation for register-to-register data
transfer:

In this arrangement:
•Corresponding outputs of each
register are connected to the same
data bus line (e.g., O3A, O3B, and
O3C are connected to DB3).
•The three registers have their
outputs connected together.
•Only one register have its outputs
enabled and that the other two
register outputs re-main in the Hi-
Z state.
•Corresponding register inputs are
also tied to the same bus line. the
levels on the bus will always be
ready to be transferred to one or
more of the registers depending on
the IE inputs.
dce
2017 Data transfer operation:

The contents of any one of the

three registers can be parallel-
transferred over the data bus to
one of the other registers through
the proper application of logic
levels to the register enable
inputs.
The control unit will generate the
signals that select which register
will put its data on the data bus
and which one will take the data
from the data bus.
dce Describe the input signal requirements for transferring
2017
[A] → [C]:

First of all, only register A should

have its outputs enabled:
•That is, we need OEA =0 OEB
=OEC =1

This will place the contents of

register A onto the data bus lines.
Next, only register C should have
its inputs enabled:
•For this, we want IEC =0 IEA
=IEB =1

This will allow only register C to

accept data from the data bus
when the PGT of the clock signal
occurs.
Finally, a clock pulse is required
to transfer the data from the bus
into the register C flip-flops.
dce
2017
Bus Signals
dce
2017
Simplified Bus Timing Diagram:

Use only a single timing waveform to represent the complete set of bus lines.
dce
Simplified Bus Representation:
2017

Use on block diagram and in some circuit

schematics

The connections to and from the data bus

are represented by wide arrows

The numbers in brackets([]) indicate the

number of bits of register and number of
lines of data bus

Figure 9-48
Simplified representation of bus arrangement.
dce
2017
Simplified Bus Representation:
Bundle method:

A single line denotes the data bus

“/8” denotes an eight-line data bus

Figure 9-49
Bundle method for simplified representation of data bus connections. The “/8” denotes an eight-line data bus.
dce
2017
Bidirectional Busing:

• Some devices have both inputs and outputs connected to the data bus.
 Inputs and outputs are connected together internal to the chip

Reduce the number of IC pins

Reduce number of connections to the bus
• Input lines (I0 /D0 to I3 /D3 ) and output lines (O0 to O3 ) have been replaced by input/output lines
(I/O0 to I/O3 )
• I/O line will function as either an input or an output depending on the state of the enable inputs.
Thus, they are called bidirectional data lines.
dce
2017
Bidirectional Busing:

Bidirectional register connected to data bus