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Ripple suppression
Isolation
Low noise
Stability
Summary
Performance Metrics
Load regulation
Line regulation
Static/dynamic
PSR
Regulation Efficiency
LDO
Quiescent current Noise
Dropout voltage
VOUT
IIN RON IOUT Dropout
IN OUT
CO
+
VIN LDO VOUT RL Regulation
ESR
- Off
Vdropout VIN
Quiescent Current
Efficiency
VOUT
VIN
Load Regulation
Measure of LDO’s ability to maintain desired VOUT with
varying IOUT
VOUT
Ideal LDO
VDesired
Practical
LDO
VIN VIN
VOUT VOUT
t
ILOAD LOAD
VLR1
VOUT
VLR2
t t
Accuracy
Includes all non-ideal effects:
1. Line/load regulation
2. Reference voltage drift
3. Error amplifier offset drift
4. Feedback resistor tolerance
VREF VREF
EA EA
VOUT VOUT
RF1 RF1
RF2 RF2
VREF
EA
VOUT
RF1 CO
RL
RF2 ESR
+ 1/rdsp
Load
VIN (RF1+RF2) ZL VOUT
+ gmp
Feedback
RF2
HEA(s) +
RF2+RF2
EA
VREF
M j j
H
j
in A B C out
M j j
H
j
• M1 = ABC
• Δ1 = 1
• Δ = 1 – (L1+ L2+ L3) + (L1 L2 + L2 L3 + L3 L1) – (L1L2L3)
= 1 – (AX+BY+CZ) + (AXBY+BYCZ+CZAX) – (AXBYCZ)
ABC
H
1 AX BY CZ AXBY BYCZ CZAX ( AXBYCZ )
+ 1/rdsp
Load
VIN (RF1+RF2) ZL VOUT
+ gmp
Feedback
RF2
HEA(s) +
RF2+RF2
EA
VREF
+ 1/rdsp
Load
VIN (RF1+RF2) ZL VOUT
+ gmp
Feedback
RF2
HEA(s) +
RF2+RF2
EA
VREF
Load Regulation
VIN
EA
VOUT
RF1
IOUT
RF2
VREF
EA
VOUT
RF1
CO RL
RF2
Loop Gain
VIN
VREF
EA
VOUT
RF1 CO
+ RL
VX VY RF2 ESR
-
VOUT
RF1
CO RL ugf
RF2
PL PH Z log()
-180°
-90°
0°
T
vx GMEA gmp vy
CO
ROEA C'1 ROUT RC
|T|
ugf
log()
PL PH Z
VREF
EA
VOUT
RF1 CO
RL
RF2 RC=ESR
VREF
EA
VOUT
RF1 CF1
VX CO RL
RF2
VOUT
RF1 ICF
VX
ICF RF2
VOUT
RF1 CF VX sCF
VOUT
RF1 ICF
VX VX
ICF RF2 RF2 CF VOUT sCF
VOUT
RF1 CF VX sCF
VOUT
RF1 ICF
VX VX
ICF RF2 RF2 CF VOUT sCF
VOUT
RF1 CF
VX
RF2 CF VOUT sCF
VREF
EA
VOUT
RF1 CF+CO
RL
RF2 VOUT sCF
VCCS Implementation
VIN
VREF
EA
VOUT
RF1 CF+CO
RL
RF2 VOUT sCF
1:1
VOUT
RF1
RF2
IB sCF IB
Z log()
PL PH
Reducing C1 is difficult
C1 is set by ILOAD and VDSAT of pass device
VREF C1
EA
VOUT
ROEA RB
RF1
CO RL
RF2
IB
VREF
EA MB VOUT
RF1
CO RL
RF2
Improved Buffer
VG
VEA MB
RB
VX
MS
Low power
VREF
EA VOUT
RF1
CO RL
RF2
Miller Compensation
VIN
VREF
EA
CC
VOUT
RF1
CO RL
RF2
R2
R1 CC
M3 vout
M1 C1 M2 C2
vin
R2
CC
M3
M2
R1
Z2in
R2
CC
M3
M2
R1
Z2in
R2
M3 Z2out
M2
R1
VREF MP
EA MB VOUT
CC RF1 CO RL
RF2
VREF MP
EA MB VOUT
CC RF1 CO RL
RF2
For small CO
Cascode Compensation[5]
VIN
VREF MP
EA MB VOUT
CC RF1 CO RL
RF2
For large CO
90
85
80
Phase Margin [Degrees]
75
70
65
60
55
90
85
Phase Margin [Degrees]
80
75
70
65
60 -3 -2 -1 0 1 2 3
10 10 10 10 10 10 10
Load Current [mA]
P. Hanumolu CICC 2015 Low Dropout Regulators Page 56
Power Supply Rejection
VIN
VREF
EA
VOUT
RF1
CO RL
RF2
PSR Calculation
+ 1/rdsp
VIN (RF1+RF2) ZL VOUT
+ gmp
RF2
HEA(s) +
RF2+RF2
PSREA VREF
PSRREF
+ 1/rdsp
VIN (RF1+RF2) ZL VOUT
+ gmp
RF2
HEA(s) +
RF2+RF2
PSREA VREF
PSRREF
VREF
EA
VOUT
RF1
LPF
RF2
vdd M3 M4
vout
M1 M2
M5
vdd M3 M4
vout
M1 M2
M5
vdd M3 M4
vout
M1 M2
M5
vdd M5
M1 M2
vout
M3 M4
vdd
vout VDD
M1 vdd M1 vdd
M1 vdd M1 vdd
Case 1 Case 4
VREF
VREF
RL
RL
Regulator PSR2/2
VDD
CC
VREF ωa
VOUT
ωo
CD RL
3. Cascaded regulators
4. Replica regulators
CF VOUT
RL
VDD
Voltage RF
Booster
CF VOUT
RL
VDD
CC
VREF ωa
VOUT
ωo
CD RL
Cascaded LDOs
VDD
REGULATOR1
VREF1 PSR1
VDO1
VOUT1
REGULATOR2
VREF2 PSR2
VDO2
VOUT
VIN MR
MM
VREP VOUT
RREP RL CD
Replica Output
output stage stage
vrep
Conventional (d = )
RB-LDO
References
1. ESR, Stability, and the LDO Regulator, 2002 :Texas Instruments.
2. C. Chava and J. Silva-Martinez "A robust frequency compensation scheme
for LDO voltage regulators", IEEE Trans. Circuits Syst. I, Reg. Papers, vol.
51, no. 6, pp. 1041-1050 2004.
3. M. Al-Shyoukh, H. Lee, R. Perez, "A transient-enhanced low-quiescent
current low-dropout regulator with buffer impedance attenuation", IEEE J.
Solid-State Circuits, pp. 1732-1742 vol. 42, Aug. 2007.
4. B. K. Ahuja, "An improved frequency compensation technique for CMOS
operational amplifiers", IEEE J. Solid-State Circuits, vol. SC-18, no.
6, pp.629 -633 1983.
5. R. Reay and G. Kovas, "An unconditionally stable two-stage CMOS
amplifier", IEEE J. Solid-State Circuits, vol. 30, pp.591 -594 1995
6. V. Gupta , G. Rincon-Mora and P. Raha "Analysis and design of monolithic,
high PSR, linear regulators for SoC applications", Proc. IEEE Int. Syst. Chip
Conf., pp.311 -315 2004.
7. G. W. den Besten and B. Nauta, "Embedded 5-V-to-3.3-V voltage regulator
for supplying digital ICs in 3.3 V technology", IEEE J. Solid-State
Circuits, vol. 33, no. 7, pp.956 -962 1998.
8. A. Arakali, S. Gondi, and P. Hanumolu, “Low-power supply-regulation
techniques for ring oscillators in phase-locked loops using a split-tuned
architecture,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2169-2181,
Aug. 2009.