JULY 1997 INSTRUCTION MANUAL

40-201.81

REL 350 VERSION 2.50

NUMERICAL SEGREGATED PHASE COMPARISON

TRANSMISSION LINE PROTECTION SYSTEM

ABB POWER T&D COMPANY INC.

POWER AUTOMATION AND PROTECTION DIVISION
4300 CORAL RIDGE DRIVE
CORAL SPRINGS, FL 33065
Version 2.50 I.L. 40-201.81

1.1 INTRODUCTION
Section 1. PRODUCT DESCRIPTION
1
The REL 350 relay assembly is a numerical (fully digital) segregated phase comparison trans-
mission line protection system, with optional distance back-up protection and oscillographic ca-
pability. The following communication options are provided:

• 9600 bps Audio tone

• 56/64 kbps Digital communication

1.2 REL 350 CONSTRUCTION

The standard nomenclature for ABB relay protection equipment is as follows:

• Cabinet – contains fixed-racks, swing-racks, or open racks

• Rack – contains one or more chassis (e.g., the REL 350)
• Chassis – contains several modules (e.g., Microprocessor or Power Supply)
• Module – contains a number of functional circuits (on printed circuit board)
• Circuit – a complete function on a printed circuit board (e.g., analog-to-digital conversion)
• The REL 350 relay assembly consists of an outer-chassis and an inner-chassis which slides
into the outer-chassis. The REL 350 conforms to the following dimensions and weight (also
see Section 2, begining on page 11):
• Height 7" (requires 4 rack units @ 1.75" each); 177 mm
• Width 19"; 483 mm
• Depth 13.6"; 345 mm
• Weight 38 Lbs; 17.5 kg

All of the relay circuitry, with the exception of the input isolation transformers and first-line surge
protection, are mounted on the inner chassis, to which the front panel is attached. The outer
chassis has a Backplate, which is a receptacle for all external connections, including Digital
Communication Interface. Two optional FT-14 switches are mounted in the two peripheral ar-
eas of the outer chassis (see Figure 4-1, on page 70). The FT-14 switches permit convenient and
safe disconnection of trip, ac and dc input circuits, and provide for injection of test signals.

1.3 REL 350 MODULES

The inner and outer chassis, together, contain standard modules, plus the optional relay output
for single pole trip applications (see Figure 1-2, on page 7). The Backplane module and Digital
Communication Interface (DCI) are connected to the Backplate (outer chassis). The remaining
modules are attached to the inner chassis:

• Interconnect module
• Relay Output module
• Contact Input module
• Microprocessor module

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• Display module
• Power Supply module
• Analog Input module
• Modem module for a 9600 bps Audio Tone Channel only
• CODEC module for 56/64 kbps Digital Communication only

Circuit descriptions for each module, may be found in Appendices A thru I, in accordance with
the list in the Preface to this document (see “Contents of Relay System”, page ii).

1.3.1 Backplane Module

The Backplane Assembly includes three voltage transformers, three current transformers, four
filter chokes and surge protection capacitors.

The Backplane Module (see Appendix A, begining on page 107) receives all external connections
and connects directly to the Interconnect module, thru plug-in connectors (J11, J12, J13); and
to the Relay Output and Contact Input modules, mounted on the Interconnect module (via con-
nectors JA1, JA2, JA3, JA4), which provide the connections between the inner and outer chas-
sis.

Backplane Module provides connection to DCI module used for 56/64 kbps Digital Communi-
cations.

The INCOM/PONI®* is mounted on the Backplate of the outer chassis and is connected to the
Backplane module (via connector J4).

1.3.2 Interconnect Module

The Interconnect module (see Appendix B, on page 111) becomes the floor of the REL 350 inner
chassis; it provides electrical connections from and to all other modules: from the Backplane
(at the rear), to the Analog Input and Power Supply modules (at left and right, respectively), to
the Relay Output and Contact Input modules in the center, and to the Modem, Microprocessor
and Display modules at the front of the inner chassis.

The Interconnect module receives inputs VA G , VB G , VC G , IA, IB, IC from the Backplane module
and feeds them to the Analog Input module.

1.3.3 Relay Output Module

There are three versions of this module (they are installed on the Interconnect module):

• Option
• Base 1
• Base 2
(See Appendix C, on page 115, for contact output functions)

*. “INCOM” stands for INtegrated COMmunications, a product of The Westinghouse Electric Corporation. The “PONI”
acronym stands for Product Operated Network Interface.

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1.3.4
The Option version is used for Single Pole Tripping (SPT) requirements.

Contact Input Module 1

This module provides an opto-isolated interface between:

• Contact inputs contaminated by external noise, and

• Logic level inputs to the Microprocessor module
(See Appendix D, begining on page 121, for more details)

1.3.5 Microprocessor Module

This module contains two processor systems (connected via the Dual Port RAM), which per-
form two main functions:

• Processor 1 samples the analog inputs and provides the operator interface
• Processor 2 is the protection processor

Each processor system (P1 and P2) contains the following elements:

• Microprocessor — 16 bit microcontroller (Intel 80C196) operating at 12 MHz.

• EPROM — an ultraviolet erasable read-only memory for program storage.
• RAM — a read-write, static, random access volatile memory for per-
forming data storage.

Processor 1 (P1) has access to:

• EEPROM — electrically erasable, read-write non-volatile memory for set-

tings and fault-data storage.
• Real-Time Clock — is accessed by Processor 1, to time-stamp the events.
1.3.6 Display Module

The Display module interfaces with the Processor 1 system of the Microprocessor module. The
Display module contains:

• 2 blue-vacuum fluorescent alphanumeric displays for value and function fields (each
field has 4 characters)
• 7 LEDs (with 7 corresponding keys for selection purposes) provide function interpreta-
tion capabilities
(See Section 4, on page 51, and Appendix F, on page 141, for further details)

1.3.7 Power Supply Module

Three different styles of power supply boards are required to accommodate the input voltage
ranges listed below. The REL 350 relay is capable of continued operation during a 200 msec
voltage dip from the dc battery input; the magnitude of this voltage dip is also shown on the next
page:

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Nominal Input Voltage

Battery (Vdc) Range (Vdc) Dip (Vdc)
48/60 38-70 28
110/125 88-145 73
220/250 176-280 146

As an option this module contains two independent power supplies, with diode-auctioneered
outputs for reliability purposes; both supplies are powered from a dc battery voltage.

The switching power supply, operating at 25 kHz, generates transformer-isolated voltages as

follows:

System System System

Circuitry Supplied Circuitry Supplied Circuitry Supplied
Voltage Voltage Voltage

Channel Modem
Processor Board
8.5 Vdc -12 Vdc Analog circuitry -24 Vdc VF Display COPS
+5 Vdc Supply
Chips

Channel Modem, Vacuum Fluorescent

+12 Vdc Analog Circuitry +24 Vdc 6.5 Vac
PONI Module Display Filament

See Appendix G, begining on page 145, for further details

1.3.8 Analog Input Module

This module (see Appendix H, on page 149) interfaces with the voltage and current transformers
that are mounted on the Backplane module. These transformers provide the following ac val-
ues: VA, VB, VC, IA, IB, IC. These values are applied to active third-order Butterworth antialiasing
filters, with a cut-off frequency determined by the Nyquist criterion and the system sampling
rate. Values IA, IB, IC are summed to produce 3I0.

All 7 inputs (VA, VB, VC, IA, IB, IC, 3I0) are connected to the multiplexer and to the A/D converter.
The A/D converter is a self-calibrating 12-bit (plus sign), with an internal track-and-hold ampli-
fier. Additionally, the autoranging circuitry provides 16 bits of dynamic range needed to mea-
sure high fault current values.

1.3.9 Modem Module (9600 bps Audio Tone Option)

This module (see Appendix I, begining on page 157) interconnects two REL 350 systems, located
at each end of the protected line. A 4-wire communication channel of sufficient quality to pro-
vide reliable data interchange is required. The modem, operating at a carrier frequency of 1700
Hz, conforms to ITU V.29 standards, and provides a communication speed of 9600 bps.

The modem is under the control of an on-board digital signal processor and interfaces, via a
parallel bus, with the Microprocessor module.

The analog signals (transmit and receive levels), and digitally-encoded S/N ratio, are also avail-
able to the Microprocessor module. The modem transmit level is controlled by the Microproces-
sor module via the above-mentioned parallel bus.

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1.3.10 CODEC (56/64 kbps Digital Communication Option)

This module (see Appendix J, begining on page 169) interconnects two REL 350 systems, located
at each end of the protected line.
1
CODEC (Coder/Decoder) provides digital communication capability at 56 or 64 kbps.

The CODEC is under the control of an on-board digital signal processor and interfaces via a
parallel bus with the Microprocessor module.

1.3.11 Digital Communication Interface DCI (56/64 kbps Digital Communication Option)

This module converts 5V logic level serial input and output data lines to/from CODEC module
into one of the optional interfaces:

• Fiber Optic, 820 nm Multi Mode cable with ST connectors

• Fiber Optic, 1300 nm, Single Mode cable with ST connectors
• Direct Digital conforming to RS 422/RS 530 communication standards
1.3.12 Contact Outputs

• 4 make contacts (2 trip, 2 BFI); 8 additional optional contacts when single pole trip option is
used
• Single pole reclose initiate (2 Form A)
• Three pole reclose initiate (2 Form A)
• Reclose block (2 Form A)
• General start (1 Form A)
• System failure alarm (1 Form B)
• Trip alarm (2 Form A).
• Channel alarm (1 Form A)

1.4 SELF-CHECKING SOFTWARE

a. Digital Front-end A/D Converter Check

REL 350 continually monitors its ac input subsystems using multiple A/D converter calibration-
check inputs. Failures of the converter trigger alarms.

b. Program Memory Check Sum

Immediately upon power-up, the relay does a complete ROM (EPROM) checksum of program
memory.

c. Power Up RAM Check

Immediately upon power-up, the relay does a complete RAM memory read/write tests.

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d. Nonvolatile RAM Check

All settings and targets are stored in nonvolatile RAM in three identical arrays. These arrays are
continuously checked by the program. If all three array copies disagree, a nonvolatile RAM fail-
ure is detected.

1.5 UNIQUE REMOTE COMMUNICATION (WRELCOM) PROGRAM

Two optional types of remote interface can be ordered.

• RS232C for single point computer communication.

• INCOM for local network communication.

A special PC software (WRELCOM RCP and OSCAR) program are available for obtaining or
sending the setting information to the REL 350. The REL 350 front panel shows two fault
events (last and previous faults), but the remote communication, 16 fault events and 3 records
of oscillographic data can be obtained and stored. Each record of the oscillographic data con-
tains 8-cycle information (1-prefault and 7-post-fault), with 7 analog inputs and 24 digital data
(at the sampling rate of 12 per cycle).

(Refer to Appendix M, begining on page 205, for more detailed information.)

1.6 PROGRAM FLOW

A top level diagram of the program flow for Processor 1 is shown in Figure 1-5, on page 9; the
program flow for Processor 2 is shown in Figure 1-6, on page 10.

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∆ Digital Comm Interface

PONI BACKPLANE BD.

ANALOG INPUT BD.

XFMR

POWER SUPPLY
CONTACT INPUT BD. RELAY OUTPUT BDS.

FT-14
FT-14

SPT

INTERCONNECT BD.
∆ CODEC ❊ Modem

PROCESSOR BD.

DISPLAY BD.

∆ 56/64 bps Digital Comm. Option Only

❊ 9600 bps audio Tone Channel Option Only

I.L. 40-201.81
Figure 1-1-: Layout of REL 350 Modules within Inner and Outer Chassis
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Figure 1-2 Block Diagram of REL 350 Relay

Version 2.50
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Initialization (INIT_REL 350)

Dual Port Ram Settings (SETTINGS)

1
Synchronization (SYNTWO)

Sample analog inputs (INPUT)

Fourier computation (FOURIER)
Write new sample values (SENDSAMPLE)
Check IE, IL, IH (RMS_PICKUP)
Faulted phase selection (SELECT_PHASE)

Utilities (*)

Data bank control (DBANK_CTRL)

Read oscillographic data (READDATA)

(*) Display Driver (DISP_DRV)

Front Panel Control (FP_CNTRL)
Setting Conversion (PROCON)
Nonvolatile Setting Voting (NVOTE)
INCOM® Communications (INCOM)
Metering (METERING)
Target Data Collection (TARGET)
Target Data Processing (ITB_UPDATE, TF1_UPDATE, TF2_UPDATE)
Nonvolatile Target Data Storage(NVTARGET)
Full Cycle Data Storage (FULL_CYCLE)
Self Check
Incident Log Recording

ESK00050

Figure 1-3: Processor 1 Program Flow

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Initialization (INIT_REL 350)

Synchronization (SYNCTONE)

Open Breaker Output Logic (OPENBKR)

Read new sample data (INPUTDATA)

Calculate:
IKEY-A,B,C,G
SWP-A,B,C,G SWN-A,B,C,G Interrupt for
LP-A,B,C,G LN-A,B,C,G channel inputs
TP-A,B,C,G TN-A,B,C,G (CHINPUT) up to 4 times
Do phase protection
Phase Comparison Logic (PC_LOGIC)

Interrupt for
channel outputs
(CHOUTPUT) up to 4 times

Check for new target data (TARGETS)

Utilities (**)
Write oscillographic data (OUTOSCDATA)
Check Channel integrity (CHANNEL)

Sample Frame Control (SAMPLE_CTRL)

(**) Read Opto Inputs (INPUT)

Output Relay Driver (OUTPUT)
Unblock Trip Logic (UNBLKTRP)
Check for breaker current (DOBKRIL)
Reclose Logic (PT_52B)
System Integrity Check (INTEGRITY)
Self Check

ESK00051

Figure 1-4: Processor 2 Program Flow

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2.1 TECHNICAL
Section 2. SPECIFICATIONS
2
Operating Speed
(from fault detection 24 ms (typical) *
to trip contact close -60 Hz) 15 ms (typical) * *

Nominal ac Voltage(VLN) at 60 Hz 69.3 V rms

Nominal ac Current (In) 1 or 5 A rms

Rated Frequency 50 or 60 Hz

Maximum Permissible ac Voltage:

• Continuous 160 V rms

— (limited by maximum Input to A/D converter)

• 10 Second 240 V rms

— (limited by input transformer flux density)

Maximum Permissible ac Current:

• Continuous 3 x Nominal Current

— (limited by thermal characteristics)

• 1 Second

Operational 160 A rms - 5A nominal

32 A rms - 1A nominal
— (limited by maximum input
to the A/D converter)

Thermal 100 x Nominal Current

dc Battery Voltages:

Nominal Input Range

60/48 Vdc 38 - 70 Vdc

110/125 Vdc 88 - 140 Vdc

220/250 Vdc 176 - 280 Vdc

NOTES:
dc Burdens:
* Phase Comparison
Operation with Audio Tone Mo-
Battery 15 W normal dem, excluding Absolute Delay of
40 W tripping the Communication Channel.

ac Burdens: ** Phase Comparison

Operation with 56/64 kbps digital
Volts per Phase 0.02VA at 70 Vac communication, excluding Abso-
lute Delay of the Communication
Channel
Current per Phase 0.45VA at 5 A

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I.L. 40-201.81 Version 2.50

2.2 EXTERNAL CONNECTIONS

Terminal blocks located on the rear of the chassis suitable for #14 square tongue lugs.

Wiring to FT-14 switches suitable for #12 wire lugs.

2.3 CONTACT DATA

Trip Contacts — make & carry 30 A for 1 second, 10 A continuous capability, break 50 watts
resistive or 25 watts with L/R = .045 seconds.

• Non-Trip Contacts
1 A Continuous
0.1A Resistive Interrupt Capability
Contacts also meet IEC - 255-6A, IEC - 255-12, IEC -255-16, BS142-1982.

2.4 9600 bps AUDIO TONE COMMUNICATION CHANNEL

Operating Speed:
Standard Compliance:
Carrier Frequency:
Modulation:
Transmit Level:
Receiver Sensitivity:
Audio Tone Channel
Requirement:
9600 Bits per second
ITU V.29
1,700 Hz
QAM - Quadrature
Amplitude modulation
-1 dBm to -15 dBm
Adjustable in 2 dBm steps
-33 dBm
4 wire, AT&T 3002,
C2 conditioning or better

2.5 56/64 kbs DIGITAL COMMUNICATION

Operating Speed: 56 or 64 kbits/sec

2.5.1 Direct Digital Option

RS422/RS485 (electrical)
RS 530 (mechanical)
Standards Compliant

2.5.2 Fiber Optic Options

2.5.2.1
Wave Length 820 nm
Fiber Optic Connector: ST
Cable: MultiMode
Transmitter Output: -18 dBm minimum (into 50/125 µm cable)
Receiver Input: -28 dBm minimum

2.5.2.2
Wave Length: 1300 nm
Fiber Optic Connector: ST
Cable: Single Mode

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Transmitter Output:
— Short Reach Option:
— Medium Reach Option:
— Long Reach Option:
Receiver Input:
(into 9/125 µm cable)
-20 dBm minimum
-10 dBm minimum
0 dBm minimum
2
- 32 dBm minimum
- 11 dBm maximum
(MAXIMUM INPUT POWER, NOT TO BE EXCEEDED,
DETERMINED BY RECEIVER SATURATION)

2.6 Optional G.703 Interface

The external G.703 interface adapter complies with CCITT (ITU) G.703 co-directional, 64 kbps
specification.

For details refer to I.L. 40-201.7

2.7 OPTIONAL COMPUTER/NETWORK INTERFACE

• RS232C/PONI — for single point computer communications
• INCOM/PONI — for local network communications using INCOM network

2.8 CHASSIS DIMENSIONS AND WEIGHT

Height 7" (177.8 mm) 4 Rack Units (See Figure 2-1, page 14)

Width 19" (482.6 mm)

Depth 14" (356 mm) including terminal blocks

Weight 38 lb. (17.5 kg)

2.9 ENVIRONMENTAL DATA

Ambient Temperature Range

• For Operation — 20°C to +60°C

• For Storage — 40°C to +80°C
Insulation Test Voltage 2.8 kV, dc, 1 minute (3.2 kV dc, 1 sec) ANSI, C37.90 IEC-255-5

Open contacts 1400 Vdc continuous

Impulse Voltage Withstand 5 kV Peak, 1.2/50 microseconds, 0.5 Joule, (IEC-225-5)

Surge Withstand Voltage 3 kV, 1 MHz (ANSI C37.90.1, IEC-255-22-1)

Fast Transient Voltage 4 kV, 10/100 ns Withstand (ANSI C37.90.1, IEC 255-22-4)

EMI Field Strength Withstand 25 MHz-1GHz, 10V/m Withstand (ANSI C37.90.2)

Emission Tests (EN 50081-1)

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I.L. 40-201.81
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2427F04

Figure 2-1: REL 350 Outline Drawing

Version 2.50 I.L. 40-201.81

3.1
Section 3. APPLICATIONS AND ORDERING INFORMATION

INTRODUCTION
3
The REL 350 is a dual-microprocessor based, segregated phase comparison relay system.
REL 350 operates on the principle of offset keying; it is essentially a current-only system suit-
able for any application that may require single pole trip (e.g., critical EHV applications and se-
ries compensated lines).

Although the REL 350 system is applicable to any transmission line, it is ideally suited for re-
laying problems introduced by series capacitor compensated lines, e.g.:

• Voltage reversals caused by negative reactance.

• Phase unbalance caused by protective gaps flashing and reinserting unsymetrically.
• Abnormal frequencies from 20 to 400 Hz during fault and post-fault intervals.

The REL 350 system will operate correctly regardless of capacitor locations or the amount of
compensation. REL 350 is also suitable for lines requiring single-pole tripping.

The offset keying technique allows the REL 350 relay to TRIP for internal faults even with con-
siderable outfeed at one terminal. Outfeed, for other relaying systems and principles is a very
severe problem.

For extremely severe cases of outfeed and weakfeed applications, the relay may be set using
a modified “Skewed” offset keying technique.

An optional distance-type relaying system has been included to provide back-up for a loss of
channel situation. This back-up system is similar to Zone 2 and Zone 3 distance units and logic
for a distance non-pilot relaying system. Phase and ground distance units are included. Ground
protection can be chosen via a relay setting. Either ground-distance and/or ground overcurrent
unit can be chosen.

Since the primary protection is insensitive to systems’ swings, blinders have been provided for
detecting the condition. OST (Out of Step Trip) is included in the back-up system.

Trip under OST conditions may be selected via a relay setting even when the channel is sound
and the system is performing only segregated phase comparison.

The REL 350 requires the use of Voltage Transformers (vts) for distance protection, fault loca-
tor and loss of potential and loss of current detection.

The REL 350 relay has the capability, through its channel modem, to accurately measure, the
communication channel-delay. A continuous channel delay measurement with optional delay
compensation is provided. The user, however, can choose fixed channel delay via relay system
settings.

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3.2 SEGREGATED PHASE COMPARISON PROTECTION

The offset keying concept permits the REL 350 to recognize an internal fault, even if there is
significant outfeed from one terminal (see Figure 3-1, on page 30). Phase comparison logic is
shown in Figure 3-2a, on page 31. Equal logic is provided for each phase and ground. The sep-
arate current units and current detectors are provided in each subsystem.

The current units and level detectors are processed on a per-phase basis, which allows for sin-
gle-pole tripping. The different current units are as follows:

• IE – Very low set overcurrent function provides output for additional logic in the relay.
• IL – Low set overcurrent function is used as a fault detector to supervise the phase
comparison logic.
• IH – High set overcurrent function provides high-speed trip. When the optional backup
function is included in the system, it is supervised by a directional unit.
• ICD – Rate of change current detector is used to initiate keying to the other terminal, to
allow phase comparison, and to supervise tripping when the phase comparison
has operated. The relay will always start with the operation of either phase or
ground change detectors.
• VCD – Voltage-rate of change detector is used to start the relaying system. It can be se-
lected to be either in or out. If it is selected, it works in parallel to the current change
detectors.
• IKEY – Detects a positive current level in the current waveform. Its output is “one” when
the instantaneous value is above a positive current level setting.
• ISWP – It is set to detect a positive current value. Its output is “one” if the current is more
positive than that negative current setting. Otherwise, its output is “zero”.
• ISWN – It is set to detect a negative current value. Its output is “one” if the current is more
negative than the negative current setting. Otherwise, its output is “zero”.
NOTE: ISWP and ISWN are implicitly defined:

ISWP = -(RIKEY - IDIFF)

ISWN = -(RIKEY + IDIFF)

where RIKEY is the remote terminal IKEY.

NOTE: Phase and Ground units are differentiated using P and G prefixes.

For Example:
PKEY, IPSWP vs. GKEY, IGSWP

PKEY and PDIFF correspond to the phase IKEY and IDIFF. Similarly GKEY and GDIFF are the
ground IKEY and IDIFF.

The offset keying technique can accommodate and detect internal faults with outfeed.

The keying waveform referred to as IKEY, is derived from a positive threshold: above this
level is called Trip-Positive (TP), and below this level is Trip-Negative (TN). Local wave-

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forms are derived by negative thresholds. The positive local, ISWP, becomes logic “0”; and
the negative local, ISWN, becomes logic “1” at their respective negative thresholds (as shown
in Figure 3-3, on page 34).
3
The threshold settings are defined as the rms magnitude of current that will produce 3* msec
of output. For example, with the REL 350 keyer, IKEY set at +3, this means that a 3.0 A, 60 Hz
rms current will produce 3* msec pulses of trip-positive (logic “1”) during the positive half cycle
of current, while the current is above an instantaneous level of 3 x 1.194 = 3.582 A. (3* msec
represents 64.8 electrical degrees.) Current levels of IKEY are based on expected maximum
outfeed current, while IDIFF is generally a function of line charging error current. In most appli-
cations, the REL 350 threshold settings are as shown in Figure 3-3, on page 34, and are iden-
tical at each line terminal.

Returning to Figure 3-2a, 3-2b, 3-2c, begining on page 31, the different current levels are com-
pared. Remote TP (Trip Positive) is ANDed with the local ISWP and the remote TN (Trip Nega-
tive) is ANDed with the local ISWN. A trip condition exists if either of these two conditions is true
and the channel is sound and the overcurrent unit IL has operated.

NOTE: The local values ISWP and ISWN are delayed by an adjustment timer (LDT), to
compensate for the delay of the remote values (TP and TN), introduced by the
communication channel.

It is suggested that the reader studies Figures 3-2 a, b, c, begining on page 31, for a better un-
derstanding of the offset keying technique.

Refer to Figure 3-4, on page 35. The logic output of Comp-AND is a successful alignment for a
TRIP condition. To compensate for channel errors and/or phase angle errors caused by the
charging current of the line, a 3* millisecond minimum alignment is required for a successful
Pilot Trip (PLT).

If the user selects the 2 count (2 CNT) mode for increased security, the logic output of Comp-
AND is required to provide at least two 3* to 5* msec pulses within 25 msec for a successful
Pilot Trip (PLT). If the first pulse is longer than 5* msec, a bypass timer assures a faster Pilot
Trip output.

NOTE: For the Ground Subsystem, a 4* msec alignment is required for increased se-
curity.

Once a pilot trip signal is obtained, it is pulse stretched by 30 msec to insure indication and trip.

The trip logic is shown in Figure 3-5, on page 36. All trip outputs are supervised by IL, the low
set overcurrent unit.The high set overcurrent unit IH is Nondirectional for units with no back-up.
For units with back-up, this unit is supervised by a forward directional unit FDOP for phase and
FDOG for Ground.

* These values are 20% longer for 50 Hz operation

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The trip output seals in through TRIP-OR and TRIP AND. The trip signal to the trip relays, PT,
is stretched 30 msec before dropout.

The local TP (Trip Positive) is generated by IKEY for phase comparison. When a trip occurs in
the local end, the remote end should be informed.

The output of SQ- AND “Stretches” a 75 msec TP (Trip Positive) to the other end to assure the
remote end will trip. This feature is important for outfeed conditions and weak-infeed terminal
applications.

REL 350 logic includes additional security. When the remote breaker is open, the remote side
will key a different signal code indicating an open breaker condition. This is recognized in the
local side. The Remote Open Breaker (ROBR) signal is generated through remote signal de-
coding. This signal, supervised by IL to prevent tripping of the local breaker under normal con-
ditions, does have an intentional delay of the local time delay plus an extra 8 msec before
generating a trip signal.

The REL 350 relaying system incorporates Stub Bus Protection (SBP). An externally generated
signal (SBP), supervised by IL, the low set overcurrent unit, is another input to the trip logic.

In most applications, the SBP input decodes the position of any disconnect switch in the line.

3.2.1 Skewed Offset Keying

Some rare applications require different keyer levels at both ends.The principles covered above
still hold.

In general, skewed offset keying techniques are used when the amount of outfeed is large
enough to operate the IKEY level of the terminal with outfeed. Otherwise, it is always recom-
mended to use offset keying.

3.3 PHASE COMPARISON UNDER FAULT CONDITIONS

3.3.1 Phase Subsystem Fault Conditions

Under normal fault conditions, either internal or external, the current change detector (ICD) and
the low set overcurrent unit (IL) will operate (IL may already be picked up by load flow) at both
terminals. Transmission of trip-positive (TP) key information is sent from both ends. Since both
ICD and IL have operated, and if the channel is good (no noise or low signal), then the trip AND
will be satisfied.

For an external fault, the received trip-positive (TP) will be “1” when the local ISWP is “0”. Like-
wise, trip-negative will be “1” when the local ISWN is “0”.

Since the AND-P sees a “1” and a “0” as its inputs, it is never satisfied. For this external fault
condition, neither AND-P nor AND-N are satisfied; no tripping will occur.

18
Version 2.50 I.L. 40-201.81

On the other hand, for an internal fault, the polarity of trip-positive (TP) and of trip-negative
(TN) will be reversed. Therefore, AND-P will be satisfied when ISWP = ”1”, and AND-N sat-
isfied when ISWN = ”1”. As a result, a comparison signal is obtained and tripping will occur. 3
NOTE: Opposite polarity is caused by current flow into CT polarity at one terminal and
into CT non-polarity at the other terminal.
3.3.2 Ground Subsystem Fault Conditions

The Ground Sub-system operates the same way as the Phase Sub-systems. IL for the ground
system is normally not picked up since, with normal load flow in a balanced system, the ground
current is negligible.

The ground system acts as a backup for some phase-to-ground faults and allows tripping for
higher resistance ground faults. In the event that the phase subsystems do not recognize a
ground fault, the logic allows the ground system and the faulted phase algorithm (to be de-
scribed later) to select the faulted phase.

3.3.3 Heavy Current Faults

For heavy current faults which exceed the settings of the high-set IH overcurrent unit, the IH unit
will produce a trip output. This unit may be supervised with a forward directional unit when the
optional back-up system is included in the system. This is a direct trip path that causes a trip
output and sets up the continuous transmitter trip-positive. IH is used for rapid clearing for close-
in current faults.

3.3.4 Outfeed Current Conditions

Normal internal faults cause faulted phase currents to flow inwardly at both terminals, while out-
feed conditions have current out (thus, outfeed) at one terminal. This outfeed condition, al-
though rare, may be caused by conditions such as weakfeed sources, high resistance ground
faults with heavy load current, some series capacitor line configurations, etc.

The REL 350 offset keying technique allows tripping under outfeed conditions.

Assume offset settings as IKEY = 3.0A, ISWP = –2.0 A, ISWN = – 4.0 A. Also, assume that the
outfeed current is 2.5 A or less due to a weakfeed type source. With current of 2.5 A at the weak
terminal, the 3.0 A keyer threshold is never reached, therefore, causing this terminal to transmit
a steady trip negative (TP=0 and TN=1). The other terminal, presumably strong in relation to
the weak source, generally will see current in excess of 4.0 A. This exceeds the ISWN threshold,
in which case local negative (local ISWN) becomes “1” during a portion of the negative half cycle,
permitting trip, since the received signal is trip-negative. Once tripped, the strong terminal shifts
to a steady trip-positive (TPK=”1”), allowing the weak source to trip with local positive.

Tripping will occur, provided the outfeed current is slightly less than the IKEY setting at the out-
feed terminal, and the current at the infeed end exceeds the ISWN setting.

If outfeed current is greater than the IKEY level of the terminal with outfeed, the user has two
options: To use “Skewed” offset keying or to increase the IKEY level at both terminals.

19
I.L. 40-201.81 Version 2.50

Normally, outfeed conditions will not be that severe. It is therefore recommended that the usual
offset keying levels be used.

3.4 COMMUNICATION LOGIC

The REL 350 segregated phase comparison principle is dependent on the relaying communi-
cations channel. The use of digital communications principles allows the system to transmit in-
formation required for phase comparison over a single channel. Information for phase
comparison is encoded into six bits that represent the keying of either phase subsystem or
ground.

The data encoding is described in Appendix E, Table E-1, on page 128.

3.4.1 Transmitter Keying

The normal state of operation for the transmitter is the sending of a GUARD signal. Under this
condition, no phase comparison is performed.

Under fault conditions, signal KE (Key Enable) starts the transmission of the segregated phase
comparison algorithm (refer to Figure 3-9, on page 40). The KE signal is started under fault condi-
tions when the ICD or VCD detectors are activated.

The encoding of the keying signal will depend on the Trip Positive (TPAK, TPBK, TPCK and TPGK)
signals of the phase and ground units. Moreover, an Open Breaker (OPBKR) signal is also in-
put to the channel encoding logic for the appropriate transmission of a remote open breaker
condition to the other end.

3.4.2 Receiver Decoding

The received signal from the other end is decoded for the phase comparison logic.

Under normal conditions, the received signal is the same string of GUARD bits. A GUARD sig-
nal is derived (GD) for the sound channel logic.

Under fault conditions, the Trip Negative (TNA, TNB, TNC and TNG) and the Trip Positive (TPA,
TPB, TPC and TPG) signals are decoded for the Segregated Phase comparison algorithm for the
phase and ground systems. Realize that Trip Negative and Trip Positive (TN and (TP) are com-
plementary signals, i.e., TP = not (TN).

The decoding logic in REL 350 also derives the Channel Trouble signal (CT). This signal is
used to enable the back-up relaying algorithms to start after 150 msec of channel trouble. More-
over, it is used for the Unblock logic (to be described later), and in conjunction with the guard
(GD) signal; forms the good channel signal that enables the phase comparison system.

The REL 350 channel decoding logic also derives the Remote Open Breaker (ROBR) signal
allowing, in the local terminal, a Remote Open Breaker high speed trip under fault conditions.

20
Version 2.50 I.L. 40-201.81

3.4.3 Unblock Logic

This logic is used in power line carrier applications. Refer to Figure 3-10, on page 41. 3
NOTE: ABB suggests this option always be set to BLK.

CT (Channel Trouble Signal) goes low for an unsound channel. It provides a 150 msec time
window for the relay system to make a decision to trip when the channel is unsound.

The REL 350 uses a phase selector algorithm (see Section 3.7.5, on page 24) to decide which
pole to open when the single Pole Trip (SPT) option has been selected and no phase unit has
operated.

The phase selection algorithm will also determine if a 3Ø or Ø-Ø fault has occurred. This acti-
vates the Ø-unblock signal that trips the 3 poles of the breaker and blocks reclosing.

The additional logic included considers a loss of channel under reclosing conditions; if a trip
has occurred in the last 2.5 seconds, allowing a 150 msec time window for fault determina-
tion.

3.5 TRIPPING AND RECLOSE INITIATE LOGIC

3.5.1 Tripping Options

REL 350 is a relaying system that easily identifies the faulted phases during a fault in the power
system. The operation of the different subsystems (øA, øB, øC and Ground) back-up each oth-
er. For any type of fault, there will be more than one subsystem that will operate, demonstrating
the inherent redundancy of the Segregated Phase Comparison concept.

The relay system offers the capability of providing a Single-Pole-Trip function. The single pole
trip logic is implemented (as shown in Figures 3-11, 3-12, begining on page 42). The user may
choose (via a relay setting) single pole trip or three pole trip options.

For the situation when a Single-Line-to-Ground Fault (SLGF) occurs, and there is not adequate
fault current to allow one of the phase subsystems to operate, then single pole to trip cannot be
identified, using the phase comparison algorithm. Therefore, if the ground subsystem operates
and a concurrent operation of a phase subsystem does not occur, then REL 350 will use a
phase selector algorithm (see section 3.7.5, on page 24).

Single-Pole tripping is defined as the tripping of only the faulted phase for single line-to-ground
faults (SLGF), while tripping all three phases for all other types of faults. The logic for single
pole trip is shown in Figure 3-11, on page 42. Signal 3PT (three pole trip) enables tripping of
the unfaulted phases when the 3PT option has been selected. The system will trip the three
phases for multiphase faults or, when the optional back-up is operative, and it detects a fault.
Moreover, the optional OST (Out of Step Trip) logic will only trip the three phases.

3.5.2 Reclosing Logic

REL 350 provides 3-phase Reclose Initiate (3RI) and Single pole Reclose Initiate (SRI) contact
outputs to be used with an external reclosing relay. A Reclose Block (RB) contact output is also

21
I.L. 40-201.81 Version 2.50

provided. The relaying system will block the reclosing relay if reclosing into a permanent fault
(OR-3), or a “Sound Phase” fault has been detected (OR-2) or the reclosing action has taken
too long (AND-1).

The logic for reclosing is shown in Figure 3-12, on page 43. Selection of the Reclose Block En-
able (RBEN) setting is done through the front panel of the relay. The options are:

• 3øRB – Block reclosing on three phase faults only.

• NORB – No reclosing block.
• MøRB – Multi-phase reclose block.
• ALRB – Reclose block for all types of faults.
NOTE: If SPT has been selected with ALRB, intentionally, RB is not activated for sin-
gle line to ground faults.
With 52b contact open (closed breaker) the sequence of operation is:
Fault applied >>Pilot Trip>>Reclose initiate (SRI or 3RI).
With 52b closed (open breaker) the sequence becomes:
52b closed >>Fault applied>>Pilot Trip>>RIFT>>Reclose Block.
Explanation:
Closing of 52b before applying fault enables the RIFT logic after 250 msec. The Pilot Trip ap-
pears to the relay to be on a first reclose rather than on initial trip, the RIFT prevents a “second”
reclose.
Initial trip is always without 52b (breaker closed), thus a reclose is initiated. When the breaker
opens on the initial trip, 52b closes and RIFT is armed in 250 msec.
When the breaker is closed on the first reclose 52b opens, but is held “on” logically for 500 msec
to the RIFT logic.
A Pilot Trip within that 500 msec is interpreted as having reclosed onto the same fault, and fur-
ther reclosing is blocked.

3.6 RELAY FUNCTIONS

3.6.1 Open Breaker Function

When the IE (Very Low Set Overcurrent unit, all IEA, IEB, IEC) is not operating or the 52b contact
signal (all 52bA, 52bB and 52bC) is operated, the relay system will place a special code in the
8 bit latch to the channel logic.

This will tell the remote terminal hat the local terminal has the breaker open and any overcurrent
detection signifies a fault in the line. The processor will check the incoming data byte and, if it
receives an open breaker code, it will trip if the IL function operates. The open breaker trip is
delayed by an amount equal to the Local Delay Timer (LDT) setting, plus an extra 8 msec delay
for security purposes.

The sending of the open breaker keying can be disabled or be activated by the 52b signal.

The user may choose to activate the open breaker logic through the absence of IE (any
IEA, IEB or IEC). This is the very low set overcurrent unit for which it should be set below

22
Version 2.50 I.L. 40-201.81

the transmission line charging current. The user must be aware that the minimum IE set-
ting is 0.04 x In (0.2A for 5A ct and 0.04 A for 1 A ct), therefore for lines with low charging
current the above requirement may not be satisfied. For this application the open break-
er function must be detected by 52b contacts. The user may also select both 52b and IE
3
as inputs to the open breaker logic.

NOTE: When using 52b inputs, the reset time of the breaker contacts should be care-
fully considered. If the contact reset time is too slow (greater than the channel
delay), reclosing will be unsuccessful. The reason is as follows: after a trip,
with both breakers open, one end closes back into the line successfully; the
second end closes in, but has slow-resetting 52b contacts; when the second
closes, load current is established in the line while at the same time the slow
52b reset is causing an OPBR (OPen BReaker) signal to continue to be sent to
the first end; the first end, which had closed earlier, sees load current above
the IPL level and also receives the OPBR signal; if this condition persists for
more than eight msec, the first end will trip out, interrupting the load flow; thus,
the second end reclose will have been unsuccessful. In order to avoid the
problem, the 52b reset time must be less than the sum of LDT (Local Delay
Time) plus eight msec. A similar situation could occur if the first end’s 52b’s
were also sluggish. In that case, as soon as the second end closed in (while
the first end’s 52b’s were still causing OPBR to be sent) it would be seeing load
and the OPBR signal from the first end, and would immediately trip back out (if
the condition lasts eight msec).
3.6.2 Stub Bus Logic

The system has provisions for an external input for Stub Bus Protection (SBP). If this input is
activated and the IL (Low set overcurrent unit) operates, the local breaker will be tripped. Stub
Bus Trip is delayed by an amount equal to the Local Delay Timer setting plus an extra 8 msec
delay for security purposes.

The system will immediately use the SBP input to key an open breaker condition to the other
end.

3.6.3 Loss of Potential (LOPB)

This logic is implemented in the relay when the optional back-up distance protection is included.
Loss of Potential Block (LOPB) is used to supervise the distance measurements in the backup
system. When this condition exists, all impedance measuring units will have their outputs
blocked.

The simple logic is shown in Figure 3-13, on page 44. This logic will detect one or two blown
fuses, but will fail to detect the unlikely failure of all three phase fuses. The output of this logic will
also energize the failure alarm relay.

3.6.4 Loss of Current (LOI)

This logic is provided when the backup system is included in the relaying system.

The simple logic (shown in Figure 3-13, on page 44) will detect the loss of one or two current
inputs. The output of this logic is only used to energize the failure alarm relay of REL 350.

23
I.L. 40-201.81 Version 2.50

3.6.5 Faulted Phase Selection

REL 350 uses a field proven algorithm to determine the faulted phase and the type of fault
cleared. In REL 350, this algorithm is used to supplement the inherent phase selection of the
Segregated Phase Comparison algorithm.

As mentioned previously, when the fault current is not large enough for single line to ground
faults, the phase subsystems may not be able to detect such a high resistance fault. The ground
system, being the most sensitive of all, will not have problems determining the fault. However,
there is not enough information to determine the faulted phase. The phase selector algorithm
is, therefore, used to determine the type of fault. This algorithm is crucial for single pole tripping.

The algorithm removes the zero sequence component of the fault current and also the prefault
load current. The resulting fault current is the sum of the positive and negative sequence cur-
rents of the fault. These currents are:

∆IA = (IA - I0) - IAL

∆IB = (IB - I0) - IBL

∆IC = (IC - I0) - ICL

The magnitudes of the above equations are compared (in Table 3-3, on page 50) and the fault
type is determined. Logic signals IA3I0, IB3I0 and IC3I0 are, therefore, derived to select the
faulted phase and allow single pole trip.

3.6.6 Fault Locator

The REL 350 fault locator feature computes the magnitude and phase angle of the fault imped-
ance and the distance to the fault in both miles and kilometers. The fault impedance is calcu-
lated from the voltage and current phasors of the faulted phase(s). Thus, proper faulted phase
selection is essential for good fault locator results. The distance to the fault is computed by mul-
tiplying the imaginary part of the fault impedance times (VTR/CTR), the voltage transformer and
current transformer ratios, and dividing by the distance multiplier setting (XPUD). The imped-
ance calculations for the various fault types are:

ZXG = VXG / (IX + KI0)

for single line to ground faults,

ZXY = (VXG - VYG) / (IX - IY)

for line to line faults, and

ZABC = VA / IA

for three phase faults.

(X, Y = Any A, B, C phase)

24
Version 2.50 I.L. 40-201.81

The algorithm has limitations, especially when REL 350 is being applied to lines with series ca-
pacitors. The above equations represent the apparent impedance to the relay and do not ac-
count for the presence of the series negative reactance. The user should account for this in the
final estimate.
3
This function is included in REL 350 when the optional distance back-up system is included.

3.6.7 SPT By-Pass (External)

An opto-isolated input has been provided in the relaying system to by-pass single pole tripping
when the input is energized by dc. The relaying system will trip 3-pole and block reclosing when
the input is activated and a single pole has been selected for tripping.

3.6.8 Direct Transfer Trip (56/64 kb/s option only)

An Opto-Isolated contact input is provided to transmit DTT Function (if enabled by setting) to
the distant unit.

Reception of DTT code at the distant unit for at least 10 msec will result in 3 pole tripping oper-
ation.

3.7 OPTIONAL BACK-UP

3.7.1 DISTANCE RELAYING

The Distance units in the REL 350 relay system are only operative when the communications
channel is unsound. The back-up distance relaying system only includes Zone 2 and Zone 3 of
a conventional non-pilot distance relaying system.

Line measurement techniques applied to each zone include:

• Single Phase-to-Ground fault detection

• 3-Phase fault detection
• Phase-to-Phase fault detection
• Phase-to-Phase-to-Ground fault detection
3.7.1.1 Single Phase-to-Ground

Single Phase-to-Ground fault detection (see Figure 3-6, on page 37) is accomplished by 3 non-
directional phase units (A, B, C). Expressions 1 and 2 (below) are for the operating and refer-
ence quantity, respectively. The unit will produce output when the operating quantity leads the
reference quantity.

Z 0L – Z 1L
V XG – I X + ----------------------- I 0 Z FG equ. (1)
Z 1L

and

25
I.L. 40-201.81 Version 2.50

Z OL – Z 1L
j V XG + I X + ------------------------ I 0 Z RG equ. (2)
 ZL 

where

VXG = VAG, VBG or VCG

IX = IA, IB or IC

1
I0 = zero sequence relay current --- ( I A + I B + I C )
3
Z1L, Z0L = Positive and zero sequence line impedance in relay ohms.

ZFG = Forward zone reach setting in secondary ohms for SLGF.

ZRG = Reverse reach setting in secondary ohms for SLGF.

3.7.1.2 Three Phase

Three phase fault detection (see Figure 3-7, on page 38) is accomplished by the logic op-
eration of one of the three ground units, plus the 3øF output signal from the phase selector
unit.

However, for a 3-phase fault condition, the computation of the distance units will be:

VXG - IXZP equ. (3)

and

VQ equ. (4)

VQ = Quadrature Phase Voltages

VCB for phase A
VAC for phase B
VBA for phase C

where

VXG = VAG, VBG, VCG

IX = IA, IB or IC

ZP = Zone Reach Settings (Z2P, Z3P) in secondary ohms

3.7.1.3 Phase-to-Phase

The Phase-to-Phase unit (see Figure 3-8, on page 39) responds to all forward Phase-to-Phase
faults, and some Phase-Phase-to-Ground faults. Expressions 5 and 6 are for operating and ref-

26
Version 2.50 I.L. 40-201.81

erence quantity, respectively. They will produce output when the operating quantity leads the
reference quantity.

(VAB - IABZP) equ. (5)

3
(VCB - ICBZP) equ. (6)

NOTE: Phase-to-Phase-to-Ground faults will be detected by the operation of either

Phase-to-Ground or Phase-to-Phase units.
3.7.2 Zone 2 and Zone 3 Distance Relaying

The optional back-up system in REL 350 consists of two zones of distance protection for both
phase and ground faults.

Each zone consists of four distance units that are able to detect all fault types. The impedance
units are three Phase-to- Ground units (ag, bg and cg) and a Phase-to-Phase unit.

The Phase-to-Ground units detect all Single Line-to- Ground Faults (SLGF), three phase faults
and some Phase-to-Phase-to-Ground faults within its operating characteristic. The ZGF and
ZGR (forward and reverse) settings apply to ground faults and the Zp settings apply to 3 Phase
faults.

The Phase-to-phase unit detects all Phase-to-Phase faults and some Phase-to-Phase-to-
Ground faults. Since this unit is inherently directional only the forward reach is used. ZP (for-
ward phase setting) applies to Phase-to-Phase faults.

NOTE: All Phase-to-Phase-to-Ground faults are covered by the operation of the de-
scribed units.

For the indication of a phase distance trip the following conditions have to occur:

1. For a Three phase fault, the RT blinder (if the system has OST logic included) and no OSB
and the 3Ph output of the phase selector and any of the Phase-to-Ground units have to
have operated to indicate a three phase fault.
2. For a Phase-to-Phase fault only the Phase-to-Phase unit needs to operate to indicate a
Phase-to-Phase fault.
3. For a Phase-to-Phase-to-Ground fault either the Phase-to-Phase unit or the Phase-to-
Ground units have to operate to indicate a Phase-to-Phase-to-Ground fault.
4. For a single line to ground fault, any of the Phase-to-Ground fault units have to operate to
indicate a Phase-to-Ground fault.

The phase fault detection is supervised by IL, the low set overcurrent unit.

The phase to ground fault detection is supervised by I0m.

Each zone has its own timer to time coordinate with relays further away for step distance relay-
ing. Separate phase and ground timers are provided.

The impedance back-up logic is shown in Figure 3-14, on page 45.

27
I.L. 40-201.81 Version 2.50

3.7.3 Directional Overcurrent Units

Phase and ground directional units (FDOP and FDOG) may be either in or out. When they are
in, the high-set overcurrent units (IAH, IBH, ICH and IGH) are directional. The ground directional
unit may either be zero sequence polarized or negative sequence polarized.

Zero sequence polarization utilizes the zero sequence components of the currents and voltag-
es into the relay, and the unit operates when 3Io leads 3V0 by more than 30° or lags by more
than 150°. For the operation of these units, it is required that 3I0 > 0.5 amp and 3V0 > 1 Volt.

Negative sequence polarization utilizes the negative sequence components of the currents and
voltages into the relay and the unit has its maximum torque line when I2 leads V2 by 98˚ with
the current 3I2 > 0.5 amp and 3V2 > 3 Volts.

FDOG may be used for detecting high ground resistance faults that may not be detected by any
of the ground distance units. TOG may be blocked or given a definite time for operation once
FDOG has operated and Iom has picked up.

The phase directional unit (FDOP) is based on the angular relationship of a single-phase cur-
rent and the corresponding pre-fault phase-to-phase voltage phasors. The forward direction is
identified if the current phasor leads the voltage phasor. The pair of current and voltage phasors
which are compared are IA and VBA (FDOPA, IB and VCB (FDOPB), IC and VAC (FDOPC). The
three-phase fault detection of Zone 2 and 3t are supervised by FDOPA and FDOPB and
FDOPC. The high set currents IAH, IBH, ICH are supervised by FDOPA, FDOPB and FDOPC,
respectively.

The logic for FDOG and FDOP xzis shown in Figure 3-15, on page 46.

3.7.4 Out of Step Trip (OST) and Out of Step Block (OSB) Logic

Out of step detection in REL 350 is achieved by the use of blinders. Only units with optional
back-up have this logic since for the blinder implementation voltage inputs are required.

A two blinder scheme is used for detecting Out of step conditions. The two blinders are called
21 BO (Outer Blinder) and 21 BI (Inner Blinder) and are parallel to the line impedance setting,
i.e., they are tilted by the PANG setting.

The RU and RT settings are the distance perpendicular to the line impedance that the blinders
are displaced from the latter. This is illustrated in Figure 3-16, on page 47. The RT setting is
also for load restriction and if any three phase fault occurs, the inner blinder, 21 BI has to be
activated for tripping and the impedance be in either Zone 2 or Zone 3 reach.

Figure 3-17, on page 48, shows the OST and OSB logic. This logic is being executed constantly
in the relay regardless whether the relaying channel is sound or not. OST logic applies in both
the phase comparison system or in the distance back-up system.

The duration of time it takes 21 BI to operate after 21 BO operates is the indication of an Out
of Step condition. Timer OST1 controls this time. When the timer times out, an Out of Step con-

28
Version 2.50 I.L. 40-201.81

dition has been detected. An OSB signal is immediately sent to block the operation of Zone 2
and Zone 3 distance units.

Timer OST2 times the trip after an OST condition has been detected and the trajectory moves
3
from point 2 to point 3 in Figure 3-16. When OST 2 times out a trip signal is sent if the REL 350
has been set to trip on the way in under out of step conditions.

Timer OST3 starts timing after the inner blinder operates. If the timer has timed out then
tripping will be allowed immediately (with a 20 millisecond time delay) once the outer blinder
(21 BO) resets. Other wise, OST has to time out first. OST3 controls the trip for an OST
condition on the way out, as illustrated by the points 4 and 5 in Figure 3-16.

The OSOT timer is an Out of Step Over-ride Timer that bypasses OSB after it has timed
out and lets the relay trip.

29
30

I.L. 40-201.81
1) “Normal Internal Fault”

2) “External Fault”

3) “Internal Fault with Outfeed”

Version 2.50
Sub 2
ESK00035

Figure 3-1: REL 350 Segregated Phase Comparison, Fault Recognition

 Version 2.50
TP AND COMP
–P
TN
AND OR
–N
LDT
ISWP
TRIP TRIP
ISWN LDT
AND
IH OUT AND
FDO IN
IL

ICD
0
OTHER PHASES OR
IE 150 GOOD CHANNEL

IKEY

I.L. 40-201.81
Sub 1
ESK00036

Figure 3-2a: REL 350 Phase-Comparison Logic

31

3
I.L. 40-201.81 Version 2.50

Sub 2
3519A78

Figure 3-2b: Offset Keying, Typical Internal Fault

32
Version 2.50 I.L. 40-201.81

Sub 3
3519A96
Figure 3-2c: Offset Keying, Typical External Fault

33
I.L. 40-201.81 Version 2.50

IKEY TP (1)
TN (0)

ISWP 1
0 (– IKEY)
IDIFF
ISWN 0
1

1
IKEY
0

1
ISWP

1
ISWN
0

IKEY = LOGIC “1” FOR 3 MS @ + AMPS BASED ON OUTFEED

ISWP = LOGIC “0” FOR 3 MS @ – IKEY + IDIFF

ISWN = LOGIC “1” FOR 3 MS @ – IKEY – IDIFF

WHERE IDIFF = ERROR CURRENT DIFFERENTIAL

EXAMPLE: (NORMAL SETTINGS – PHASE)

MAXIMUM OUTFEED < 3 AMPS

ERROR CURRENT DIFFERENTIAL = 1 AMP

THEREFORE, I KEY = + 3 AMPS

ISWP = – IKEY + IDIFF = – 3 + 1 = – 2 AMPS

ISWN = – IKEY - IDIFF = – 3 –1 = – 4 AMPS

NOTE: IKEY AT ONE TERMINAL MUST COORDINATE WITH ISWP AND ISWN AT
OTHER TERMINAL.
ESK00040

Figure 3-3: REL 350 Offset Keyer and Locals

34
 Version 2.50
IL

GOOD CHANNEL IPLT

0
150 150

AND
–P

COMP COMP 3
0 0
25
PT
AND PLT
OR
OR AND

AND 2
–N
1 CNT

5
0
VCD
CD
OR

ICD

I.L. 40-201.81
Sub 1
ESK00041

Figure 3-4: REL 350 Two-Count Mode Selection

35

3
36

I.L. 40-201.81
SBP

OR
ROBR
LDT 3-POLE TRIP
AND +
IL 8MSEC

TRIP
PT
PT
PLT
OR
OUT
OR IN
OR

TRIP 0
30

IL
0
AND
150

IPLT 150

IH
75
0 SQ
AND
AND
FDO TEST
T-P
TPK

OR

Version 2.50
IKEY

Sub 1
ESK00037
Figure 3-5: REL 350 Trip Logic
Version 2.50 I.L. 40-201.81

3
j X

ZGF

ϒ
R
α
ZGR

FDOG

ZGF: Forward Reach Setting

ZGR: Reverse Reach Setting

ϒ: Maximum Torque Angle

B: Balance Point

α: 30˚ w/DIRV set to ZSEQ

α: 8˚ w/DIRV set to NSEQ

*Sub 5
ESK00042

Figure 3-6: Mho Characteristics for Single Phase-to-Ground Fault Detection

37
I.L. 40-201.81 Version 2.50

jX
B

ZP

ϒ
R

ZP: Forward Phase Reach Setting

ϒ: Maximum Torque Angle (PANG)

B: Balance Point

Sub 5
ESK00043

Figure 3-7: Mho Characteristics for Three-Phase Fault Detection

38
Version 2.50 I.L. 40-201.81

Sub 1
9654A15

Figure 3-8: Mho Characteristics for Phase-to-Phase Fault Detection

39
40

I.L. 40-201.81
KE
TPAK
CHANNEL TPBK
Ch. In
6
TPCK

ENCODING
MODEM/CODEC

CHANNEL
TPGK
XDTT
IEA
SBP IEB
Ch. Out OPBKR
IEC
OR
OR 40
6 0 IE
OR

ROBR
CHANNEL DECODING
RDTT 10 52b
DTT
0
(DIRECT TRANSFER TRIP)

TNG TPG TNA TPA TNB TPB TNC TPC GUARD CHANNEL TROUBLE Sub 4
ESK00044

Version 2.50
Figure 3-9: Communication Channel Interface
 IAL

Version 2.50
IBL
ICL OR
150
IGL 0
AND

PTA
PTB
OR 0
PTC
2500 OUT
PTG

150 OR AND 8 IN
CT
150 30
UNBLOCK
0
16

PTA
PTB AND SELECT POLE (SPT ONLY)
PTC AND
AND
X2
X2
Ø - UNBLOCK
3Ø AND
32
Ø-Ø OR 32
Sub 3

I.L. 40-201.81
X2 ESK00045

Figure 3-10: Unblock Logic

41

3
I.L. 40-201.81 Version 2.50

PSE

PTA TRIP A

OR AND

BFIA
L
SEAL IN

TRIP B
PTB
OR AND

BFIB
L
SEAL IN

PTC TRIP C

OR AND
BFIC

L
SEAL IN

3PT

Sub 1
ESK00046

Figure 3-11: Single-Pole Trip Function

42
Version 2.50 I.L. 40-201.81

AND
RBEN
3φRB
3
PTC
PTA
PTB
N0RB 0
OR RB
MφRB 300
ALRB
AND
AND

OR OR 0 3RI
AND 200
AND OR
1
AND
TTYP 3PT
AND
SLGF
PTG SPT OR 3PT
X2 100 AND Mφ
0
AND
OR
SPF
AND OR 0
OR 2 SRI
200
16
62T
AND
OR

AND
250 AND
500 SPFT
(Sound Phase
OR RIFT
AND OR Fault Trip)
3
250
500 BK-UP
OST
250 AND φ-UNBK
500
5BT-OBKT
DTT
62T
OR
AND TTYP SPT
0.5-5.0
1 0
3PT
OR A
Z2T
A N
N D
SPT
52bA
52b SEBR D BY-PASS
52bB AND
52bC
X2 (Pole Disagreement) Sub 7
ESK00038

Figure 3-12: Reclosing Logic

43
I.L. 40-201.81 Version 2.50

IO VO X2

N LOPB

N
LOI
D

Sub 2
ESK00047
Figure 3-13: Loss of Potential Block Logic

44
 Version 2.50
IL3φ
FDOP 16

OSB

Load Restriction
3φ
Zone 2

3φ

O A
R N
D

φφ

FDOG

FDOG
φG

FDOP
3φ IL3φ
ZONE 3

A
O N
R D

φφ

FDOG

FDOG

φG
Sub 2

I.L. 40-201.81
2420F06
Sheet 2 (in part)
45

Figure 3-14: Zone 2 and Zone 3 Back-up System

3
46

I.L. 40-201.81
A
N FDOP
D

LOW LEVEL CURREN

SUPERVISION

IAL A
FROM
IBL N IL3φ
SHEET 1
ICL D

O IL
FDOG R

O
φG
R

φA

OPERATING
φφ
ELEMENTS Sub 2
3φ 2420F06

Version 2.50
Sheet 2 (in part)

Figure 3-15: Optional Directional Overcurrent Units

 Version 2.50
ESK000257

I.L. 40-201.81
Figure 3-16: Blinders for the Out-of-Step Logic
47

3
48

I.L. 40-201.81
φ

Sub 2

Version 2.50
2420F06
Sheet 2 (in part)

Figure 3-17: OST and OSB Logic Diagram

Version 2.50 I.L. 40-201.81

REL 350 NUMERICAL

TABLE 3-1. REL 350 CATALOG NUMBERS

MS 3 A
Typical Catalog Number

1 P T F R G
3
COMPARISON SYSTEM (50/60 Hz)

TRIP

Three Pole Trip 3

Single Pole Trip 1

CURRENT INPUT

1A A
5A B
MOCT Inputs (Future) C

BATTERY SUPPLY VOLTAGE

48/60 Vdc  1
110/125 Vdc  Single Power Supply 2
220/250 Vdc
 3

48/60 Vdc  4
110/125 Vdc  Dual Power Supplies 5

220/250 Vdc 6

DISTANCE BACKUP RELAYING

Backup Protection P
No Backup Protection N

COMMUNICATION
CHANNEL INTERFACE

9600 bps Audio Tone Channel T

9600 bps Audio Tone Channel (British Telcom) B
56/64 kbs Direct Digital Channel * D
56/64 kbs Fiber Optic, 820 nm, Multimode, ST Connector * H
56/64 kbps 1300 nm, Single Mode Fiber, ST * See Section 2.5 for details
Connector, Short Reach * E
56/64 kbps 1300 nm, Single Mode Fiber, ST
Connector, Medium Reach * M
56/64 kbps 1300 nm, Single Mode Fiber, ST
Connector, Long Reach * L

TEST SWITCHES

FT-14 Test Switches F

No FT-14 Test Switches N

COMMUNICATION DEVICE

RS-232C R
INCOM® C

ADDITIONAL FEATURES

Oscillographic Data Storage G

49
I.L. 40-201.81 Version 2.50

TABLE 3-2. REL 350 ACCESSORIES

FT-14 TEST PLUG

• Right-Side Style # 1355D32G01

• Left-Side Style # 1355D32G03

TABLE 3-3. FAULTED PHASE SELECTION

FAULT TYPE

AG BG CG AB BC CA ABG BCG CAG

| ∆IA | > 1.5 ∗ | ∆IB | X X X

| ∆IA | > 1.5 ∗ | ∆IC | X X X
| ∆IB | > 1.5 ∗ | ∆IA | X X X
| ∆IB | > 1.5 ∗ | ∆IC | X X X
| ∆IC | > 1.5 ∗ | ∆IA | X X X
| ∆IC | > 1.5 ∗ | ∆IB | X X X

If none of the nine fault types in the table are identified, then a three-phase condition exists. The
comparisons do not differentiate between Phase-to-Phase and Phase-to-Phase-to-Ground faults,
but a simple check for the presence of I0 is employed to make this determination.

| ∆Ix | = | IX - IO - IXL |

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Version 2.50 I.L. 40-201.81

4.1
Section 4. INSTALLATION, OPERATION AND MAINTENANCE

SEPARATING THE INNER AND OUTERCHASSIS

4
! CAUTION

It is recommended that the user of this equipment become acquainted with the
information in these instructions before energizing the REL 350 and associated
assemblies. Failure to observe this precaution may result in damage to the
equipment.

All integrated circuits used on the modules are sensitive to and can be dam-
aged by the discharge of static electricity. Electrostatic discharge precautions
should be observed when operating or testing the REL 350.

! CAUTION

Use the following procedure when separating the inner chassis from the outer
chassis; failure to observe this precaution can cause personal injury, or undes-
ired tripping of outputs and component damage.
a. Unscrew the front panel screws.
b. Remove the (optional) FT-14 covers if supplied (one on each side of the
REL 350).
c. Open all FT-14 switches.

Do Not Touch the outer contacts of any FT-14 switch; they may be
energized.
d. Slide out the inner chassis.
e. Close all FT-14 switches.
f. Replace the FT-14 covers.
g. Reverse procedures above when replacing the inner chassis into the outer
chassis.

4.2 TEST PLUGS AND FT-14 SWITCHES

• Test Plugs are available as accessories (see Table 3-2 , on page 50); they are inserted into the
FT-14 switches for the purpose of System Function Tests.

4.3 EXTERNAL WIRING

All external electrical connections pass thru the Backplate (Figure 4-1, on page 70) on the outer
chassis. Seven DIN connectors (J11, J12, J13, JA1, JA2, JA3, JA4) allow for the removal of the
inner chassis from the outer chassis.

51
I.L. 40-201.81 Version 2.50

Electrical inputs to the Backplane module, which are routed either directly thru the Backplate or
thru the FT-14 switch to the Backplate include (see Figure 4-1, on page 70):

• VA, VB, VC and VN

• IA/IAR, IB/IBR, IC/ICR
• Power Supply (Battery) Inputs
Primary (IBP, IBN)
Backup (2BP, 2BN)

Analog input circuitry consists of three current transformers (IA, IB, IC) three voltage transform-
ers, (VA, VB and VC), and low-pass filters. The six transformers are located on the Backplane
PC Board (see Appendix A). The primary winding of all six transformers are directly-connected
to the input terminal TB6/1 thru 12 (see Functional Block Diagram, (System Diagrams Section), Figure
S-1 , on page 215); the secondary windings are connected thru the Interconnect module to the
Analog Input module.

As shown in Figure 4-1, dry contact outputs for breaker failure initiation (BFI), reclosing initiation
(RI), reclosing block (RB), failure alarm and trip alarm are located on the Backplane PC Board.

As shown in Figure 4-2, on page 71, the power system ac quantities (Va, Vb, Vc, Vn, Ia, Ib, Ic),
as well as the dc sources are connected to the left side 1FT-14 switch (front view). All the trip
contact outputs are connected to the right-side 2FT-14 switch (front view). Switches 13 and 14
on 2FT-14 may be used for disabling the Breaker Failure Initiation/Reclosing Initiation (BFI/RI)
control logic. (See also external connections, Block Diagram, System Diagrams Section , Figure S-1, on
page 215.)

The INCOM/PONI communication box is mounted thru the Backplate of the outer chassis and
connected to the Backplane module. An RS-232C serial port is provided for remote transmis-
sion of target data. The serial port is also available for networking, data communications, and
remote settings (see section 4.7, NETWORK INTERFACE, on page 60).

4.4 REL 350 FRONT PANEL DISPLAY

The front panel display consists of a vacuum fluorescent display set of seven LED indicators,
seven key switches.

4.4.1 Vacuum Fluorescent Display

The vacuum fluorescent display (blue color) contains four alphanumeric characters for both the
function field and the value field. All the letters or numbers are fourteen segment form (7.88mm
x 13mm in size). The display is blocked momentarily every minute for the purpose of self-check;
this will not affect the relay protection function.

A “DISPLAY SAVER” feature turns-off the display if no key activity for 3 minutes is detected.

4.4.2 Indicators

There are 7 LED indicators on the front panel display:

52
Version 2.50 I.L. 40-201.81

• 1 “relay-in-service” indicator
• 1 “value accepted” indicator
• 5 display-select indicators
4
When the “Relay-in-Service” LED illuminates, the REL 350 Relay is in service, there is dc
power to the relay and the relay has passed the self-check and self-test. The LED is turned
“OFF” if the Relay-in-service relay has at least one of the internal failures shown in the “Test”
mode.

The “Value Accepted” LED flashes only once, to indicate that a value has been entered suc-
cessfully.

The 5 indicators used for the display selection are:

• Settings
• Volts/Amps/Angle
• LAST FAULT
• PREVIOUS FAULT
• Test

One of these indicators is always illuminated, indicating the mode selected.

4.4.3 Key Switches

The front panel contains 7 keys:

• Display Select
• Reset Targets
• Function Raise
• Function Lower
• Value Raise
• Value Lower
• Enter (recessed for security purposes)

The “Display Select” key is used to select one of the five display modes, which is indicated when
the proper LED illuminates. When a fault is detected, the “LAST FAULT” flashes once per sec-
ond. If two faults are recorded, the “LAST FAULT” flashes twice per second, and the prior fault
will be moved from “LAST FAULT” to “PREVIOUS FAULT”. The new fault data will be stored in
the “LAST FAULT” register. By depressing the “Reset Targets” key, the flashing LED indicators
are cleared, and the LED will revert back to the Metering mode. The information in the “PRE-
VIOUS FAULT” and “LAST FAULT” will not be reset from the front panel key switch, but will be
reset from External Reset (TB5-7 and TB5-8) and the remote reset through the Communication
Interface.

The “Function Raise” and “Function Lower” keys are used to scroll thru the information for the
selected display mode. The “Value Raise” and “Value Lower” keys are used to scroll thru the
different values available for each of the five functions. The “Enter” key is used to enter (in mem-
ory) a new value for settings.

53
I.L. 40-201.81 Version 2.50

4.5 FRONT PANEL OPERATION

The front (operator) panel provides a convenient means of checking or changing settings, and
for checking relay unit operations after a fault. Information on fault location, trip types, phase,
operating units, and breakers which tripped become available by using the keys to step thru the
information. Targets (fault data) from the last two faults are retained, even if the relay is deen-
ergized. The operator is notified that targets are available by red flashing LEDs on the front pan-
el; in addition, alarm output-relay contacts are provided for the external annunciators.

The operator can identify nonfault voltage, current and phase angle on the front panel display.
Settings can be checked easily, however, any change to the settings requires the use of the
keys. When relay is in the normal operating mode, it is good practice to set the LED on the
Volts/Amps/Angle mode.

4.5.1 Settings Mode

In order to determine the REL 350 settings that have been entered into the system, continually
depress the “DISPLAY SELECT” key until the “SETTINGS” LED is illuminated. Then depress
the “FUNCTION RAISE” or “FUNCTION LOWER” key, in order to scroll thru the REL 350 SET-
TINGS functions (see Table 4-3, begining on page 63). For each settings function displayed, de-
press the “VALUE RAISE” or “VALUE LOWER” key in order to scroll thru the REL 350 values
available for the particular function. (Each value that appears, as each different function ap-
pears in the function field, is considered to be the “current value” used for that particular func-
tion.)

In order to change the “current value” of a particular settings function, “RAISE” or “LOWER” the
FUNCTION field until the desired function appears (e.g., “RP”). Then “RAISE” or “LOWER” the
values in the VALUE field until the desired value appears. If the “ENTER” key (recessed for se-
curity purposes) is depressed, the value which appears in the VALUE field will replace the “cur-
rent value” in memory; but only if the “VALUE ACCEPTED” LED flashes once to indicate that
the value has been successfully entered into the system.

For reasons of security, a plastic screw is used to cover the ENTER key. A wire can be used to
lock the plastic screw and to prevent any unauthorized personnel from changing the settings.

4.5.2 Metering (Volts/Amps/Angle) Mode

When the Volts/Amps/Angle LED is selected by the “Display Select” key, the phase A, B, C volt-
ages, currents and phase angles are available for on-line display during normal operation. All
measured values can be shown by scrolling the “Raise” or “Lower” key in the FUNCTION field.
The values on the display are dependent on the settings of RP (read primary); RP= YES for the
primary side values and RP = NO for the secondary values. Conditions such as channel re-
ceive, channel transmit and loss-of-potential can also be monitored. The function names and
values are shown in Table 4-5, on page 67.

NOTE: All displayed Phase Angles use VA as reference.

54
Version 2.50 I.L. 40-201.81

4.5.3 Target (LAST and PREVIOUS FAULT) Mode

The last two Fault records are acessible at the Front panel. The “LAST FAULT” information
is of the most recent fault, the “PREVIOUS FAULT” information is of the fault prior to the
4
“LAST FAULT”. These displays contain the target information along with the “Frozen” data at
the time of trip. The “LAST FAULT” register shows one or two records stored by flashing the
LED once or twice per second, respectively.

Different types of faults with related descriptions are shown in Table 4-6. As soon as a fault
event is detected, the most recent two sets of target data are available for display. The “LAST
FAULT” is the data associated with the most recent trip event. The “PREVIOUS FAULT” con-
tains the data from the prior trip event. If a single fault occurs, the “LAST FAULT” LED flashes.
If a reclosing is applied and the system trips, the original “LAST FAULT” information will be
transferred to the “PREVIOUS FAULT” memory. The latest trip information will be stored in the
“LAST FAULT” memory, and its LED flashes twice per second. To reset the flashing LEDs, de-
press the “Reset Targets” key once. To reset the target information in “LAST FAULT” and
“PREVIOUS FAULT”, see the foregoing procedure (in Section 4.4.3, Key Switches, begining on
page 53).

There are 2 ways to reset the targets: Table 4-1:

Test Mode Functions
• Using the “Target Reset” Contact Function Description
Input.
• With the INCOM command, using STAT Relay Self-Check Status
the communication channel. TEST Phase comparison TEST ENABLE Signal
TLDT Test Mode Computation of Local Delay Time
4.5.4 Test Mode Function SRT Monitor Standing Relay Trip Signal
OPTI Display Opto Input Status
The test display mode provides diag- TRIP Relay Test: Trip Relays
BFI Relay Test: BFI Relays
nostic and testing capabilities for SRI Relay Test: SRI Relay (RI1)
REL 350. Relay status display, local 3RI Relay Test: 3RI Relay (RI2)
delay time computation, and relay RB Relay Test: Reclose Block Relay
testing are among the functions pro- GS Relay Test: General Start Relay
vided. The test mode functions are FALM Relay Test: Failure Alarm Relay
TALM Relay Test: Trip Alarm Relay
listed in Table 4-1.
CALM Relay Test: Channel Alarm Relay
4.5.4.1 Contact Input Test

The Contact Input module (Appendix D) can be conveniently tested, using the Contact Input
Test Function.

To activate this function, continually depress the DISPLAY key until the “TEST” LED is illumi-
nated. Then depress the “FUNCTION RAISE’ or “FUNCTION LOWER” key until the word “OP-
TI” appears in the FUNCTION field.

The “VALUE” field will display the status of the contact inputs, using two hexadecimal digits, as
explained below.

When the contacts close (voltage is applied across two input terminals), the corresponding bit
is set to binary “1”; an open set of contacts results in a binary “0”. The following correspondence
exists:

55
I.L. 40-201.81 Version 2.50

FUNCTION BIT NUMBER

Direct Transfer Trip 0

Stub Bus 1
Single-Pole Trip Override 2
Target Reset 3
52b A 4
52b B 5
52b C 6
Not Used 7

For Example:
The functions listed below,
• DTT (closed)
• Single-Pole Trip Override (closed)
• Target Reset (closed)
• 52b B contacts (closed)
• Remaining contacts (open)

will result in the following binary pattern:

Bit Pattern 0010 1101

Bit Number 7654 3210






HEX “Value”
Field Display 2 D

For reference, refer to Table 4-2 for the binary-to-hexadecimal conversion.

4.5.4.2 Relay Output Test Table 4-2:

Binary-to-Hexadecimal Conversion

All relay outputs can be tested using the procedure BIT NUMBER
described below: 3/7 2/6 1/5 0/4 HEX DIGIT
0 0 0 0 0
0 0 0 1 1
(1) Open the FT switch, using the red handles of the
0 0 1 0 2
breaker trip circuits, making sure that the follow-
0 0 1 1 3
ing jumper is not disturbed:
0 1 0 0 4
0 1 0 1 5
BFI/RECLOSE ENABLE 0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
(2) Install jumper JMI in position 1-2 on the Micropro-
1 0 0 1 9
cessor module.
1 0 1 0 A
(3) Continually depress the “DISPLAY” key until the 1 0 1 1 B
“TEST” LED is illuminated; then depress the 1 1 0 0 C
“FUNCTION RAISE” or “FUNCTION LOWER” 1 1 0 1 D
key until the words “TRIP” and “RELY” appear in 1 1 1 0 E
the FUNCTION and VALUE fields, respectively. 1 1 1 1 F

56
Version 2.50 I.L. 40-201.81

(4) Activate the “ENTER” key for the desired duration of the output relays operation.
(5) Depress the “FUNCTION RAISE” key to select the following parameters, as desired:
FUNCTION
FIELD
VALUE
FIELD DESCRIPTION
4
TRIP RELY TRIP (A, B, C)
* BFI RELY Breaker Failure Initiate
* SRI (RI1-1,2) RELY Single Pole Reclose Initiate
* 3RI (RI2-1,2) RELY 3 Pole Reclose Initiate
RB RELY Recloser Blocking
GS RELY General Start
FALM RELY Failure Alarm
TALM RELY Trip Alarm
CALM RELY Channel Alarm
(6) Activate the “ENTER” key to operate selected output relays.
Note: * These outputs are enabled only if a connection is made from TB1-13 to TB1-14.
(7) After completion of this test, restore the system to its operating state by moving JM1 to po-
sition 2-3 on the Microprocessor module, and closing the FT switch red handles.

4.5.4.3 Self Check

The results of the system self-check routines are accessible using the following procedure:

a. Continually depress the “DISPLAY” key until the “TEST” LED is illuminated; then depress
the “FUNCTION RAISE” or “FUNCTION LOWER” key until the word “STAT” appears in the
FUNCTION FIELD.
b. The VALUE FIELD will display the status of the relay in hexadecimal Format:
RELAY STATUS
DESCRIPTION BIT NUMBER
External RAM Failure 0 Least Significant Right-Most Position
EEPROM Failure 1
ROM Checksum Failure 2
Dual-Port RAM Failure 3
Analog Input Failure 4
Processor Failure 5
± 12V P.S.Fail 6
Modem Failure 7
EEPROM Warning 8
Power Supply 1 Failure 9
Power Supply 2 Failure 10
Dual Port RAM
Com Status Warning 11
Failure Detected by Processor 1 12
Failure Detected by Processor 2 13
0 14
0 15 Most Significant Left-Most Position

57
I.L. 40-201.81 Version 2.50

A bit set to “1” signifies that the corresponding failure has been detected. For example, the fol-
lowing failures will result in a bit pattern:

ROM CHECKSUM (Bit 2)

Analog Input (Bit 4)
Processor 1 (Bit 12)

The bit pattern which results is shown below:

Bit Pattern 0 0 0 1 0 0 00 0 0 0 1 0 1 0 0
Bit Number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Hex “VALUE” 1 0 1 4
Display
For normal error-free system performance, the “VALUE” field display is “0”.

The status display is generated by “OR”ing, the self-test status from Processor 1 and Processor
2. A zero value indicates that no self-test failure has occurred. A non-zero value in the low byte
(bits 0 to 7) represents an REL 350 failure condition which enables the failure alarm, and dis-
ables tripping. A non-zero value in the third character from the right (bits 8 to 11) indicate a self-
test-warning which enables the failure alarm, but does not disable tripping. The left-most char-
acter (bits 12 to 15) indicates which processor(s) detected the failure.

4.5.4.4 Test Enable

The TEST ENABLE signal on the REL 350 channel logic diagram is provided through the front
panel TEST mode. When the TEST mode TEST or TLDT functions are selected, the TEST EN-
ABLE signal on the REL 350 phase comparison logic diagram is active, otherwise it is disabled.
Oscillographic data storage is triggered, when the ENTER key is depressed, while the TEST
mode TEST function is selected on the front panel.

4.5.4.5 Channel Delay Time (TEST)

The channel delay time is computed when the TEST mode TLDT function is selected. The cus-
tomer must set the LPKY setting the same at both ends of the line, and the load current greater
than LPKY must be present. When the TEST mode TLDT function is selected, tripping is dis-
abled. The TEST ENABLE signal on the REL 350 phase comparison logic diagram is enabled.
The REL 350 computes the channel delay time for each phase as: the time from the IKEY rising
edge to the TP rising edge. The average LDT of the 3 phases is displayed in the value field.
The computed local delay time is between 0 and 1 cycle in milliseconds. The user must know
if the delay time is greater than one cycle, and add that time to the displayed value.

58
Version 2.50 I.L. 40-201.81

NOTE: All three phase currents must be present to compute average delay.
Absence of any current is returned as an ERRx in the VALUE FIELD, where
“x” is a hexadecimal number with absent phase assignment:
4
Bit Number Absent Phase

2 A
1 B
0 C

Thus all three absent phases will produce:

Bit 2=1
Bit 1=1
Bit 0=1

to give 7hex

NOTE: The Channel Delay Time measurement described here is implemented for ver-
ification only. The delay time measurement performed by Modem/CODEC and
used by the system is described elsewhere in this document.

4.5.4.6 Standing Relay Trip

A real-time status monitor of the Standing Relay Trip (SRT) logic signal is provided as a test
mode function. The value of the SRT function is YES if any of the trip relays is enabled, other-
wise, the value is “NO”.

! CAUTION

The user should verify that SRT = “NO” prior to putting the REL 350 in service
after testing.

4.6 JUMPER CONTROL

The following jumpers are set at the factory; the customer normally does not need to move the
jumpers.

4.6.1 Backplane Module

An external jumper is permanently-wired to terminals 13/14 of switch 2FT-14.

When switch 2FT-14/13 or 2FT-14/14 is opened, the BFI and RI output relays are deenergized
to prevent BFI and RI contact closures during system function test.

4.6.2 Contact Input Module

The factory sets jumpers (JMP1 thru JMP7) for 48 Vdc or 125 Vdc input source.

59
I.L. 40-201.81 Version 2.50

! CAUTION

If the customer intends to use a voltage other than 48 Vdc or 125 Vdc, see Con-
tact Input Module Schematic, Appendix D.

4.7 NETWORK INTERFACE

Two options are available for interfacing between REL 350 and a variety of local and remote
communication devices.

• RS-232C/PONI - for single point computer communication

• INCOM/PONI - for local network communication

An IBM PC or compatible computer, with software provided (WRELCOM), can be used to mon-
itor the settings, 16 fault data records, 3 oscillographic records, and metering information. For
a remote setting, SETR should be set to “YES”; then the settings can be changed (remotely)
with a user-defined password. If a user loses his assigned password, a new password can be
installed by turning the REL 350 relay’s dc power supply “OFF” and then “ON”. REL 350 allows
a change of password within the next 15 minutes, by using a default “PASSWORD”.

When in the remote mode, the computer can disable the local setting by showing SET = REM
(in the Metering mode). Then, the setting cannot be changed locally. In this situation, the only
way to change a setting locally would be to turn the dc power “OFF” and then “ON”. The com-
puter will allow for a local setting change within 15 minutes. Refer to the IL 40-603 (Remote
Communication Program) for detailed information.

4.8 OSCILLOGRAPHIC DATA

Refer to ABB Publications:

• IL 40-603 Remote Communication Program

• IL 40-606 Oscillographic and Recording Program

See appendix “M” for Oscillographic Data Definitions.

4.9 REL 350 SETTINGS

The REL 350 setting mnemonics are in Table 4-3; the appropriate setting information is in Table
4-4,, on page 65, i.e., setting name, format, setting range (min, max, step), units and related
notes.

4.10 MONITORING FUNCTIONS

The REL 350 monitoring functions display on-line system information (see Table 4-5, on page 67;
monitoring values and conditions are listed in Table 4-6, on page 68). All angles are computed using
VAG as the reference angle.

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4.11 TARGET (FAULT DATA) INFORMATION

The REL 350 stores 16 sets of targets (fault data). All 16 sets are accessible through INCOM®,
but only the two most recent sets of data are accessible from the front panel (see Table 4-5, on
4
page 67).

The first part of the fault data contains “Yes/No” targets (see Table 4-6), which identify the cause
of the trip and the status of certain system inputs and outputs; the second part of the fault data
contains values, including currents, voltages, fault impedance, and distance to the fault.

4.12 COMMUNICATION CHANNEL TESTING

Monitoring functions (see section 4.10, MONITORING FUNCTIONS, begining on page 60) display the
following communication channel information:

4.12.1 9600 bps Audio Tone Option Only

• XMTR — provides transmitter output level (in dBm)

• RCVR — provides receiver input level (in dBm)
• SNR — provides signal-to-noise-ratio (in dB)
4.12.2 56/64 kbps Option Only

BERR Bit Error

DISPLAY VALUE # of Frames in Error in 512 frames
SYER Synch Error
CTER Channel Trouble
IDER Unit ID Error

4.13 ROUTINE VISUAL INSPECTION

With the exception of Routine Visual Inspection, the REL 350 relay assembly should be main-
tenance-free. A program of Routine Visual Inspection should include:

• Condition of cabinet or other housing

• Tightness of mounting hardware and fuses
• Proper seating of plug-in relays and subassemblies
• Condition of external wiring
• Appearance of printed circuit boards and components
• Signs of overheating in equipment

4.14 ACCEPTANCE TESTING

The customer should perform the REL 350 Acceptance Tests (see Appendix L, begining on page
183) on receipt of shipment.

4.15 NORMAL PRECAUTIONS

Troubleshooting is not recommended due to the sophistication of the Microprocessor unit.

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I.L. 40-201.81 Version 2.50

! CAUTION

With the exception of checking to insure proper mating of connectors, or setting

jumpers, the following procedures are normally not recommended. (If there is a
problem with the REL 350, it should be returned to the factory. See PREFACE.)

4.16 DISASSEMBLY PROCEDURES

a. Remove the inner chassis from the outer chassis, by unscrewing the lockscrew (on the front
panel), and unsnapping the two covers from the FT-14 switches.
NOTE: The inner-chassis (sub-assembly) slides in and out of the outer chassis from
the front. Mating connectors inside the case eliminate the need to disconnect
external wiring when the inner chassis is removed.
b. Remove the FT-14 switches, mounted by two screws on the side walls.
c. Remove the front panel (with the Display module) from the inner chassis, by unscrewing
four screws behind the front panel.
d. Remove the Microprocessor module, by loosening six mounting screws, and unplugging
the module from the Interconnect module.
e. Remove the Modem, Relay Output and Contact Input modules by unscrewing 2 mounting
screws from the brackets and unplugging these modules from the Interconnect module.
f. Remove the Power Supply and Analog Input modules, by first removing the Microprocessor
module and the support cross bar.
g. Remove the Backplate, by unscrewing the mounting hardware from the rear of the
Backplate.

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Table 4-3: REL 350 SETTINGS (Sheet 1 of 2)

4
VERS . . . . . Software version
FREQ . . . . . Rated frequency setting selection
RP . . . . . . Enable readouts in primary values
CTYP . . . . . Current transformer type: 1A or 5A ct
CTR . . . . . . Current transformer ratio
VTR . . . . . . Voltage transformer ratio
OSC . . . . . . Trigger for storing oscillographic data
FDAT . . . . . Trigger for storing Fault Target Data
TRGG . . . . . Ground current pickup level trigger for OSC and FDAT
TRGP . . . . . Phase current pickup level trigger of OSC and FDAT
CD . . . . . . Change Detector Option
TTYP . . . . . Selection of single-pole or 3-pole trip type
62T . . . . . . Single pole trip limit timer
RBEN . . . . . Reclose block enable
UNBK . . . . . Unblock logic enable
CNT . . . . . . Pilot logic 1-count/2-count trip selection
IPLT . . . . . . Select memory timer for IPL
OPBR . . . . . Open Breaker selection
IE . . . . . . . Very low set phase current pickup value in amps
IPL . . . . . . Low set phase current pickup value in amps
IPH . . . . . . High set phase trip current setting in amps
IGL . . . . . . Low set ground current pickup value in amps
IGH . . . . . . High set ground trip current setting in amps
LPKY . . . . . Local phase pickup for enabling the transmitter keying circuit
RPKY . . . . . Remote phase pickup for enabling the transmitter keying circuit
PDIF . . . . . . Difference from PKEY for computing |SWP and |SWN
LGKY . . . . . Local ground pickup for enabling the transmitter keying circuit
RGKY . . . . . Remote ground pickup for enabling the transmitter keying circuit
GDIF . . . . . . Difference from GKEY for computing |SWP and |SWN
ALDT . . . . . Enable automatic LDT adjustment
LDFL. . . . . . Select LDT leader/follower mode
LDT . . . . . . Local delay timer setting
* XMTR . . . . . Modem transmitter level setting
* RLSD . . . . . Receiver level signal detect setting
** UNID. . . . . . Unit ID
** KBPS . . . . . Communication speed (56 or 64 kbps)
** TTRP . . . . . Transfer Trip
** XCLK . . . . . Source of Transmit Clock
** LPBK . . . . . Loopback Test
XPUD . . . . . Ohms per unit distance multiplier for fault locator
DTYP . . . . . Selection of distance units for XPUD setting
PANG . . . . . Positive sequence line impedance angle
GANG . . . . . Zero sequence line impedance angle

NOTES:

* 9600 bps Audio Tone Option

** 56/64 kbps Digital Comm Option

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I.L. 40-201.81 Version 2.50

Table 4-3: REL 350 SETTINGS (Sheet 2 of 2)

ZR . . . . . . Line impedance ratio (Z0L/Z1L)

BKUP . . . . . Backup Protection Enable
LOPB . . . . . Loss-of-potential blocking selection
FDOP . . . . . Directional Overcurrent Phase
FDOG . . . . . Directional Overcurrent Ground
DIRU . . . . . . Directional Unit selection
IOM . . . . . . Medium set ground current pickup value in amps
TOG . . . . . . Timer for Ground Overcurrent Unit
Z2P . . . . . . Zone 2 phase distance setting in ohms
T2P . . . . . . Zone 2 phase time delay in seconds
Z2GF. . . . . . Zone 2 ground forward distance setting in ohms
Z2GR . . . . . Zone 2 ground reverse distance setting in ohms
T2G . . . . . . Zone 2 ground time delay in seconds
Z3P . . . . . . Zone 3 phase distance setting in ohms
T3P . . . . . . Zone 3 phase time delay in seconds
Z3GF. . . . . . Zone 3 ground forward distance setting in ohms
Z3GR . . . . . Zone 3 ground reverse distance setting in ohms
T3G . . . . . . Zone 3 ground time delay in seconds
OST . . . . . . Out-of-step trip enable
OSB . . . . . . Enable out-of-step blocking for backup protection
RT . . . . . . Inside blinder setting in ohms
RU . . . . . . Outside blinder setting in ohms
OST1 . . . . . Out-of-step block timer
OST2 . . . . . Out-of-step trip on-the-way-in timer
OST3 . . . . . Out-of-step trip on-the-way-out-timer
OSOT . . . . . Out-of-step override timer in milliseconds
SETR . . . . . Enable INCOM remote setting feature
TIME . . . . . . Enable setting of real time clock
YEAR . . . . . RTC setting year
MNTH . . . . . RTC setting month
DAY . . . . . . RTC setting day
WDAY . . . . . RTC setting day of week
HOUR . . . . . RTC setting hours
MIN . . . . . . RTC setting minutes

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Table 4-4: SETTING INFORMATION

Setting

VERS
Format

XX.XX
Min

0.01
Max

99.99
Step Units Notes
4
FREQ 50/60 Hz
RP YES/NO
CTYP XXXX 1 5 4 Amp CTYP = In
CTR XX.XX 30 5000 5
VTR XXXX 300 7000 10
OSC TRIP/ITRG/∆V∆I
FDAT TRIP/ITRG
TRGG XX.XX 0.1X In 2.0 X In 0.1 X In Amps 1
TRGP XX.XX 0.1X In 2.0 X In 0.1 X In Amps 1
CD ∆I/∆V ∆I
TTYP SPT/3PT
62T XX.XX 0.30 5.00 0.05 sec
RBEN NORB/3PRB/MPRB/ALRB
UNBK IN/OUT
CNT 1CNT/2CNT
IPLT XXXX 0 150 150 msec
OPBR IE/52B/BOTH
IE X.XXX 0.04 X In 0.1X In 0.002 X In Amps 1
IPL XX.XX 0.1 X In 0.8 X In 0.02 X In Amps 1
IPH XX.XX 0.8 X In 16.0 X In 0.02 X In Amps 1, 4
IGL XX.XX 0.1 X In 0.8 X In 0.02 X In Amps 1
IGH XX.XX 0.8 x In 16.0 X In 0.02 X In Amps 1, 4
LPKY XX.XX 0.2 X In 4.0 X In 0.02 X In Amps 1
RPKY XX.XX 0.2 X In 4.0 X In 0.02 X In Amps 1, 2
PDIF XX.XX 0.10 X In 3.9 X In 0.02 X In Amps 1, 2
LGKY XX.XX 0.2 x In 4.0 X In 0.02 X In Amps 1
RGKY XX.XX 0.2 x In 4.0 X In 0.02 X In Amps 1, 2, 3
GDIF XX.XX 0.10 X In 3.9 X In 0.02 X In Amps 1, 2
ALDT YES/NO
LDFL LEAD/FOLO
LDT XXX.X 8 32.0 0.1 msec 6
LDT XXX.X 0 24.0 0.1 msec 7
XMTR XXXX -15 -1 2 dBm 6
RLSD -43/-33/-26/-16 dBm 6
UNID XXXX 0 15 1 7
KBPS 64/56 7
TTRP IN/OUT 7
XCLK INT/EXT 7
LPBK YES/NO 7
XPUD X.XXX 0.300 1.500 0.001 ohms/DTYP
DTYP MI/KM
PANG XXXX 40 90 1 deg
GANG XXXX 40 90 1 deg
ZR XXX.X 0.1 7.0 0.1
BKUP IN/OUT
LOPB YES/NO
FDOP IN/OUT
FDOG IN/OUT
DIRU ZSEQ/NSEQ
IOM XX.XX 0.1 X In 2.0 X In 0.02 X In Amps 1
TOG XX.XX 0.10 9.99 0.01 sec 3

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Table 4-4: SETTING INFORMATION (SHEET 2 OF 2)

Setting Format Min Max Step Units Notes

Z2P XX.XX 0.01 50.00 0.01 ohms 5

T2P XX.XX 0.10 2.99 0.01 sec 3
Z2GF XX.XX 0.01 50.00 0.01 ohms 5
Z2GR XX.XX 0.01 50.00 0.01 ohms 5
T2G XX.XX 0.10 2.99 0.01 sec 3
Z3P XX.XX 0.01 50.00 0.01 ohms 5
T3P XX.XX 0.10 2.99 0.01 sec 3
Z3GF XX.XX 0.01 50.00 0.01 ohms 5
Z3GR XX.XX 0.01 50.00 0.01 ohms 5
T3G XX.XX 0.10 2.99 0.01 sec 3
OST NO/IWAYI/WAYO
OSB NONE/Z2/Z3/BOTH
RT XX.XX 1.00 15.00 0.10 ohms 5
RU XX.XX 3.00 15.00 0.10 ohms 5
OST1 XX.XX 0.50 5.00 0.05 cycles
OST2 XX.XX 0.50 5.00 0.05 cycles
OST3 XX.XX 0.50 5.00 0.05 cycles
OSOT XXXX 24 240 1 cycles 4
SETR YES/NO
TIME YES/NO
YEAR XXXX 1980 2079 1 year
MNTH XX 1 12 1 month
DAY XX 1 31 1 day
WDAY SUN/MON/TUES/WED/THUR/FRI/SAT
HOUR XX 0 23 1 hour
MIN XX 0 59 1 minute

NOTE 1: Current settings are per-unit quantities. The setting range is multiplied by the CTYP setting
(In = 1 or 5) for display purposes.

NOTE 2: The PDIF, GDIF setting must be less than the remote RPKY,RGKY settings. The maximum allow-
able PDIF, GDIF settings are the remote RPKY, RGKY setting -0.1 per unit. The minimum allowable
remote RPKY, RGKY setting is the PDIF, GDIF setting +0.1 per unit.

NOTE 3: These settings have a “BLK” option for disabling a corresponding function.

NOTE 4: These settings have an “OUT” option for disabling the protection.

NOTE 5: The impedance settings are dependent upon the CTYP setting. The setting ranges shown are for
a 5 A ct. The displayed setting range is multiplied by 5 if a 1 A ct is used (CTYP = 1).

NOTE 6: 9600 bps Audio Tone option

NOTE 7: 56/64 kbps Digital Communication option.

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FUNCTION

CHRX
CHTX.
.
.
.
.
DESCRIPTION

.
.
Table 4-5: MONITORING FUNCTIONS

. REL 350 channel receive status GARD/OPBR/ARM/CHTB

. REL 350 channel transmit status GARD/OPBR/KEY
FORMAT UNITS
4
IA . . . . . . IA metered current magnitude . . . . . . . . XXX.X . . . Amps
∠IA . . . . . IA metered current angle . . . . . . . . . XXXX. . . . deg
VAG . . . . . VAG metered voltage magnitude . . . . . . . XXX.X . . . Volts
∠VAG . . . . VAG metered voltage angle . . . . . . . . XXXX. . . . deg
IB . . . . . . IB metered current magnitude . . . . . . . . XXX.X . . . Amp
∠IB . . . . . IB metered current angle . . . . . . . . . XXXX. . . . deg
VBG . . . . . VBG metered voltage magnitude . . . . . . . XXX.X . . . Volts
∠VBG . . . . VBG metered voltage angle . . . . . . . . XXXX. . . . deg
IC . . . . . . IC metered current magnitude. . . . . . . . XXX.X . . . Amps
∠IC . . . . . IC metered current angle . . . . . . . . . XXXX. . . . deg
VCG . . . . . VCG metered voltage magnitude . . . . . . . XXX.X . . . Volts
∠VCG . . . . VCG metered voltage angle . . . . . . . . XXXX. . . . deg
3I0 . . . . . 3I0 metered Current Magnitude . . . . . . . XXX.X . . . Amps
3I0 . . . . . 3I0 metered Current Angle. . . . . . . . . XXXX. . . . deg
DATE . . . . . Date (Month, Day) . . . . . . . . . . . MM/DD
TIME . . . . . Time (Hours, Minutes) . . . . . . . . . . HH/MM . . . .
SET . . . . . Setting access status . . . . . . . . . . BOTH/LOC/REM
LOP . . . . . Loss-of-potential indication . . . . . . . . YES/NO
LOI . . . . . Loss-of-current indication . . . . . . . . . YES/NO
OSB . . . . . Out-of-step blocking indication . . . . . . . YES/NO
MLDT. . . . . Measured local delay time from Modem/CODEC . XXX.X . . . msec
* XMTR . . . . Channel transmit level . . . . . . . . . . XXXX. . . . dBm
* RCVR . . . . Channel receive level . . . . . . . . . . XXXX. . . . dBm
* SNR . . . . . Channel signal-to-noise ratio . . . . . . . . XXXX. . . . dB
** BERR . . . . Channel Error. . . . . . . . . . . . . Value/SYER/CTER/IDER
NOTE: All angles are computed using VAG as the reference angle.
* 9600 bps Audio Tone option
** 56/64 kbps Digital Communication option

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Table 4-6: TARGET (FAULT DATA) INFORMATION (SHEET 1 OF 2)

TARGET DESCRIPTION FORMAT UNITS

FTYP Fault Type AB/BG/CG/AB/BC/CA/ABC

BK1 Breaker current flowed YES/NO
BK1A Phase A breaker current flowed YES/NO
BK1B Phase B breaker current flowed YES/NO
BK1C Phase C breaker current flowed YES/NO
BK2 Breaker current flowed YES/NO
BK2A Phase A breaker current flowed YES/NO
BK2B Phase B breaker current flowed YES/NO
BK2C Phase C breaker current flowed YES/NO
IAH High set phase A fault YES/NO
IBH High set phase B fault YES/NO
ICH High set phase C fault YES/NO
IGH High set ground fault YES/NO
PLTA Pilot trip Phase A YES/NO
PLTB Pilot trip Phase B YES/NO
PLTC Pilot trip Phase C YES/NO
PLTG Pilot trip ground YES/NO
PTOG Pilot overcurrent ground trip YES/NO
SPFT Sound phase fault trip YES/NO
RIFT Reclose-into-fault trip YES/NO
62T Single-phase time-out trip YES/NO
SBT Stub-bus trip YES/NO
OBKT Open breaker trip YES/NO
OST Out-of-step trip YES/NO
UNBK Unblock trip YES/NO
TG Time overcurrent ground trip YES/NO
Z2P Zone 2 phase fault YES/NO
Z2G Zone 2 ground fault YES/NO
Z3P Zone 3 phase fault YES/NO
Z3G Zone 3 ground fault YES/NO
Z Fault impedance XX.XX ohms
FANG Fault impedance angle XXX.X deg
DMI Fault distance in miles XXX.X mi
DKM Fault distance in kilometers XXX.X km
PFLC Pre-fault load current XXX.X Amps
PFLV Pre-fault voltage XXX.X Volts
LP Pre-fault load angle XXX.X deg
VAG VAG fault voltage magnitude XXX.X Volts
∠VAG VAG fault voltage angle XXX.X deg
VBG VBG fault voltage magnitude XXX.X Volts
∠VBG VBG fault voltage angle XXX.X deg
VCG VCG fault voltage magnitude XXX.X Volts
∠VCG VCG fault voltage angle XXX.X deg
3V0 3V0 fault voltage magnitude XXX.X Volts
∠3V 0 3V0 fault voltage angle XXX.X deg
Z2T Pole Disagreement Trip, 3 Pole Tripping in Backup mode YES/NO

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TARGET
Table 4-6: TARGET (FAULT DATA) INFORMATION (SHEET 2 OF 2)

DESCRIPTION FORMAT UNITS 4

IA IA fault current magnitude XXX.X Amps
∠IA IA fault current angle XXX.X deg
IB IB fault current magnitude XXX.X Amps
∠IB IB fault current angle XXX.X deg
IC IC fault current magnitude XXX.X Amps
∠IC IC fault current angle XXX.X deg
3IO 3I0 fault current magnitude XXX.X Amps
∠3I 0 3I0 fault current angle XXX.X deg
DATE Date of fault (Month.Day) MM.DD
YEAR Year of fault YYYY
TIME Time of fault (Hours.Minutes) HH.MM
SEC Time of fault (Seconds) XXXX sec
MSEC Time of fault (Milliseconds) XXXX msec
LDT LDT used at time of trip XXX.X msec
* XMTR Channel transmit level XXXX dBm
* RCVR Channel receive level XXXX dBm
* SNR Channel signal-to-noise ratio XXXX dB
** BERR Channel error XXXX
** TTRP Direct Transfer Trip YES/NO

NOTES: The “YES/NO” targets are displayed only if they are “YES”.

The angles are not displayed if the magnitude of the value or the reference is less than 0.5 A
or 0.7 V rms.

The impedance is dependent upon the CTYP setting. The internal impedance values are for a
5 A ct. The impedance value is multiplied by 5 if a 1 A ct is used (CTYP = 1).

* 9600 bps Audio Tone Channel

** 56/64 kbps Digital Communication

69
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I.L. 40-201.81
Sub 10
1354D22
Sheet 5 of 7

Version 2.50
Figure 4-1: REL 350 Backplate
 NOTES

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5.1 INTRODUCTION
Section 5. SETTING CALCULATIONS
5
REL 350 can be set through the front panel Man-Machine Interface (MMI) or through Remote
Communication Computer Software (WRELCOM Local Area Network).

This section will follow the sequence of settings displayed in the front panel display when the
relay system is in the settings mode.

! CAUTION

Reference will be made to current levels based on 5A secondary line ct’s. For
1A secondary line ct’s multiply the current levels by 0.2.

5.2 RELAY SYSTEM SET UP

5.2.1 SOFTWARE VERSION (VERS)

Indicates the software version in the REL 350.

5.2.2 System Frequency (FREQ)

Select either 60 or 50 Hz, depending on the power system frequency.

NOTE: It is imperative that the proper selection of frequency is made prior to applica-
tion of power system currents and voltage.
5.2.3 Readout in Primary Values (RP)

A “YES” setting enables the REL 350 system to display all the monitored voltages and currents
in primary kAmperes and kVolts.

5.2.4 Current Transformer Type (CTYP)

This setting is used for load current monitoring, if the selection is to be displayed in primary kA-
mperes or secondary amperes.

For Example:
Enter CTYP = 5 if 1200/5 line ct’s are being used.

5.2.5 Current Transformer Ratio (CTR)

This setting is used for load current monitoring, if it is selected to be displayed in primary kAm-
peres. It has no effect on the protective relaying system.

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I.L. 40-201.81 Version 2.50

For Example:
Set CTR = 240 if 1200/5 line ct’s are being used.

5.2.6 Voltage Transformer Ratio (VTR)

This setting is used for the system voltage monitoring, if it is selected to be displayed in primary
kVolts. It has no effect on the protective relaying system.

For Example:
Set VTR = 575 if 69000 V to 120 V vt’s are being used.

5.3 OSCILLOGRAPHIC INFORMATION

5.3.1 Trigger for Storing Oscillographic Data (OSC)

Indicates trigger for oscillographic data gathering. The user can select the trigger of oscillo-
graphic data when:

• TRIP — The REL 350 system tripped

• ITRG — The REL 350 system detected the operation of either the TRGP or
TRGG, phase or ground current trigger respectively (see below).
• ∆V, ∆I — The REL 350 system has detected a fault in the system that may not
even be within the protective zone of the relay

The change detector occurs (CD) when current or voltage change between the corresponding
data samples, spaced one power line cycle apart, exceeds 12.5%.

Using of CD as a trigger of oscillographic data is of little practical value when a relay is connect-
ed to a “live” power system.

Numerous changes due to sudden load changes, remote switching, distant faults, etc., make
the resulting oscillographic records difficult to relate to events of importance.

5.3.2 Ground Trigger Pick UP Level (TRGG)

This setting controls the level of current magnitude on the ground current,which when exceeded
triggers oscillographic data storage.

5.3.3 Phase Trigger Pick Up Level (TRGP)

This setting controls the level of current magnitude, on the phase currents which when exceed-
ed triggers oscillographic data storage.

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5.4

5.4.1
PHASE COMPARISON - LOGIC SETTINGS

Change detector option (CD) 5

The relaying system is generally in the “background” mode processing secondary functions
such as metering and display until a disturbance is detected and the relay is put in Fault Pro-
cessing mode.

This can be achieved either by using the current change detectors (∆Ι) or the current and volt-
age change detectors (∆Ι and ∆V).

The user can select the Fault Processing mode of the relay on:

• ∆Ι — Current change detectors only. This setting provides more security.

• ∆Ι ∆V — Current and voltage change detectors if the system has voltage inputs.
This setting provides more sensitivity and should always be used for
weak-feed applications, where the change in current may not be signifi-
cant to start the relaying system.

5.4.2 Selection Trip Type (TTYP)

This setting determines whether single pole trip or 3 pole trip will be used for single line to
ground faults. The REL 350 will always trip the three poles for multi-phase faults.

NOTE: An optional board is required for single pole trip. If not provided in the hard-
ware, SPT is not possible at all.
5.4.3 SINGLE PHASING TIMER (62T)

This setting applies when single pole tripping is being used. It specifies the maximum allowable
time for the breaker to have one pole open. If 62T timer expires, the other 2 poles will be tripped
and Reclose Block (RB) will be activated.

5.4.4 Reclose Block Enable (RBEN)

The following settings are provided for system flexibility:

• NORB — No Reclose Block for the system. This logic may be provided by external
devices.
• 3PRB — Reclose block will be activated only if the fault is a three phase fault.
• MPRB — Reclose block will be activated only if the fault is a phase fault (L-L or 3
phase).
• ALRB — Reclose block will be activated for all types of faults.
5.4.5 Unblock Logic Enable (UNBK)

This setting is primarily for Power Line Carrier (PLC) applications. The logic is described in Sec-
tion 3.5.3, begining on page 21.

NOTE: For channels other than Power Line Carrier (i.e., Audio Tone or Digital Commu-
nication) this setting should be set to OUT.

Power Line Carrier at this moment is not an approved communications media for REL 350.

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5.4.6 Phase Comparison Count Logic (CNT)

This setting provides a choice between sensitivity and increased security. The options are:

• 1CNT — Only one 3 msec, trip comparison (output of COMP-AND) is required to

trip the system.
• 2 CNT — If the coincidence at the output of COMP-AND (Figure 3-4(on page 35))
is only 3 to 5 milliseconds long a second coincidence greater than 3 mil-
liseconds is required within 25 msec. If this output is longer than 5 milli-
seconds, no second comparison is required.
For more security set CNT = 2 CNT.

5.4.7 Phase unit stretch timer (IPLT)

For terminals in which the fault current disappears too fast, for example close to an AC-DC in-
terconnection, it is necessary to stretch the duration of IPL to ensure the tripping of the other
terminal.

The IPL signal timer may be chosen to be:

• 0 — No pulse stretch
• 150 — IPL will be stretched 150 milliseconds.

Notice that stretching IPL implies that the trip output will be energized longer.

NOTE: For most of the applications this setting should be “0”.

5.4.8 Open Breaker (OPBR)

The following settings are available for open breaker keying:

(See Section 3.7.1(on page 22), for recommendations)

• IE — The keying is initiated when the line current is lower than IE setting.
• 52B — The keying is initiated when the 52b contact at the local end is closed.
• BOTH — The keying is initiated when either IE is absent or the 52b contact is
closed.
NOTE: When using 52b inputs, the reset time of the breaker contacts should be
carefully considered. If the contact reset time is too slow (greater than the
channel delay), reclosing will be unsuccessful. The reason is as follows:
after a trip, with both breakers open, one end closes back into the line suc-
cessfully; the second end closes in, but has slow-resetting 52b contacts;
when the second closes, load current is established in the line while at the
same time the slow 52b reset is causing an OPBR (OPen BReaker) signal
to continue to be sent to the first end; the first end, which had closed ear-
lier, sees load current above the IPL level and also receives the OPBR sig-
nal; if this condition persists for more than eight msec, the first end will trip
out, interrupting the load flow; thus, the second end reclose will have been
unsuccessful. In order to avoid the problem, the 52b reset time must be
less than the sum of LDT (Local Delay Time) plus eight msec. A similar sit-
uation could occur if the first end’s 52b’s were also sluggish. In that case,
as soon as the second end closed in (while the first end’s 52b’s were still
causing OPBR to be sent) it would be seeing load and the OPBR signal

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5.5
from the first end, and would immediately trip back out (if the condition
lasts eight msec).

PHASE COMPARISON ALGORITHM

5
5.5.1 SETTINGS

5.5.1.1 Outfeed Current

REL 350 is a relaying system that can successfully identify internal faults with outfeed. Although
outfeed is rare, the following conditions or the combination of them are most likely to produce
outfeed:

• Series Compensated Parallel Lines

• Weak-Feed or Zero-Feed Applications
• Series Compensated Lines with line end capacitors.
• Simultaneous Open Conductor and Single Line-to-Ground Fault.
• High Resistance Single Line-to-Ground Fault.

The situation of outfeed is a function of various factors, which may be highly variable:

• Load Flow
• Source Impedance
• Maximum Expected Fault Impedance
• Capacitor Gap flashover

Outfeed, even at the worst conditions, rarely is over 2.5A. Under these conditions, “Offset Key-
ing” is recommended.

• When the worst outfeed condition is met, the terminal with more than 2.5A of outfeed
reaches the IKey threshold if normal settings are used. This situation is identified as
an external fault by the system. Therefore, the relaying system settings should be
changed by:
• Increasing LPKY, LGKY at both ends

or

• Using “Skewed” offset keying.

5.5.2 Estimating Line Charging Current

The net line charging current (ICH) has been defined as the total line charging current minus
any shunt reactor current, providing the shunt reactors are connected within the zone of pro-
tection. The magnitude of ICH is very important to the phase comparison system. ICH is a dif-
ferential “error” current which actually appears as a low grade internal fault to any phase
comparison (or current differential) relay system. ICH is superimposed on the through current
during external disturbances (external faults, load switching, etc.) and affects the ideal current-
in equals current-out relationship. The phase comparison must be secure regardless of this er-
ror current. The REL 350 system achieves this security by separating the local square wave
thresholds (ISWP, and ISWN) by a small amount, to provide “nesting” during external fault con-

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ditions. Therefore, the local square wave thresholds are based, in part, on the net line charging
current.

If the shunt reactors are connected outside the zone of protection, then they do not benefit the
phase comparison, and the REL 350 settings must be based on the uncompensated charging
current.

If the shunt reactors are connected within the zone of protection, but may at times be switched
out, totally or partially, then the REL 350 settings must be based on the worst case (i.e., mini-
mum compensation).

The determination of ICH can be made by measurement or calculation. The measurement can
be made at either terminal, by reading local phase currents with the local breaker closed and
the remote breaker open. The calculation is made by computing the total distributed capaci-
tance, converting to equivalent phase current at rated voltage, and then subtracting shunt com-
pensation current, if any. Of course, the current transformer ratio must be known, or assumed,
in order to express the ICH in secondary Amperes. A safety factor is incorporated in the setting
rules of the REL 350 so a high degree of precision in these calculations is not necessary.

5.5.3 Recommended Keyer Settings

The current values referred to are secondary Amperes, based on 5 A cts and 5A (secondary)
maximum load current. If low-current cts (e.g., 1A) are used, then the currents stated here
should be multiplied by the appropriate factor (0.2 for 1A cts). If 5 A cts are used, but the max-
imum load current is significantly different than 5 A, then the recommended “Keyer” (LPKY and
LGKY) value should be adjusted. For example, if maximum load current is 4A, then multiply the
“Keyer” (LPKY and LGKY) setting by 0.8. If the maximum load current is 7A, then multiply the
“Keyer” setting by 1.4. The local (ISWP and ISWN) thresholds are also changed, since these
thresholds are derived from the remote “Keyer” setting (see next section).

NOTE: If the load current is less than 4.A, it is recommended to use ILOAD 4.0A as the
setting criteria. This is only done for security.
5.5.4 Current Units

5.5.4.1 Very Low Set Phase Current Unit (IE)

This unit is used with the Open Breaker (OPBKR) keying logic. It should be set sensitive
enough to pick-up when the local breaker is closed.

NOTE: There is 20% hysteresis associated with this setting. The open breaker keying
will start when line current drops below .8 x IE and will remain so until it in-
creases above1.2 x IE.

5.5.4.2 Low Set Phase Unit (IPL)

The low set overcurrent units perform the function of supervision of fault detectors and also to
prevent the REL 350 system from tripping undesirably under line energization.

The phase (IPL) unit should be set at 1.5 times the net line charging current, but must be at
least .5 A. Net line charging current is herein defined as: the steady state net single-end line
charging phase current, as measured under balanced conditions (all local poles closed and all
remote poles open).

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“Net” line charging indicates the distributed capacitive current minus the line-connected
shunt reactor current (if any), since line-connected shunt reactors are within the zone of pro-
tection of the phase comparison and tend to cancel the capacitive current. 5
5.5.4.3 High Set Phase Overcurrent Unit (IPH)

This unit is provided in the REL 350 system to supplement the phase comparison protection by
providing a non-pilot direct trip capability for high current internal faults. The IPH unit should be
set above the maximum expected external fault current with a security margin.

On lines which do not contain series capacitors, the IPH unit should be set for 1.25 times the
maximum through current for an external three phase fault.

On series compensated lines, the phase IPH unit should be set for the higher of the following
two calculated values:

1. 1.25 times the gap flashover setting.

2. 1.25 times the maximum thru current for an external three-phase fault, with the line
compensated.

For Example:
Consider a long line with maximum thru current (line compensated) equal to 8A, and the gap
flashover setting equal to 12A. Set the phase IPH unit at 15A.

Next, consider a short line application with maximum thru current (line compensated) equal to
14A and the gap flashover setting equal to 12A. In this case, set the phase IPH equal to 17.5A.

These high set overcurrent units are only directional when the distance back-up function is in-
cluded in the REL 350 system. IPH is supervised by FDOP for all phase subsystems.

5.5.4.4 Low Set Ground Unit (IGL)

The ground unit supervises the phase comparison logic for the ground subsystem. Since the
effect of charging current is minimum for the ground subsystem, the setting should only allow
for inherent unbalance under normal operation. A minimum setting of 0.5 A is recommended.

5.5.4.5 High Set Ground Overcurrent Unit (IGH)

The high set ground unit should follow the same guidelines as the high set phase units.

The IGH unit is directional only when the optional distance back-up is included. IGH is super-
vised by FDOG.

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5.5.5 Square Wave Generators

5.5.5.1 Phase Units Settings

5.5.5.1.1 “Offset Keying”

“Offset Keying”, both the local (LPKY) Keyer and the remote (RPKY) Keyer should be set the
same.

For outfeed current less than 2.5 A, the recommended keyer levels are:

LPKY = 3.0
RPKY = 3.0

5.5.5.1.2 “Skewed Offset Keying”

“Skewed Offset Keying” the local LPKY and remote RPKY are different.

For outfeed currents greater than 2.5A the recommended settings are:

LPKY = 7.0
RPKY = 2.0

in the higher-outfeed terminal, and

LPKY = 2.0
RPKY = 7.0

in the lower-outfeed terminal.

5.5.5.1.3 Phase Differential Current (PDIF)

This setting is a security margin for the calculation of the local ISWP an ISWN that depends on
the charging current. The local square wave thresholds ought to be symmetrical to the RPKY
level. The following are the threshold relationships:

IPSWP = RPKY -PDIF

IPSWN = RPKY + PDIF

The above thresholds are negative thresholds.

The following settings are recommended for PDIFF:

a. Lines with Net Charging Current of 0.75A or Less

This category includes short lines (less than approximately 50 miles), medium length lines
(approximately 50 miles to 150 miles), and long lines (above approximately 150 miles), if
the compensating shunt reactors are within the zone of protection.
For these cases, PDIFF = 1.0A.

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b. Lines with Net Charging Current Greater than 0.75A

This category consists of long EHV lines which require a high security margin to pre-
vent false tripping, due to the high line charging current which appears to the relays as
error current (simulating a low current internal fault). The differential (PDIFF and
5
GDIFF) value, which determines the square wave threshold, must be increased in or-
der to provide the necessary security.
For these cases, PDIFF = 1.2 x ICH (PDIFF should be > 1.0A).

5.5.5.2 Ground Unit Settings

5.5.5.2.1 Keyer Settings (LGKY, RGKY)

For offset keying, both the local LGKY and remote RGKY keyer levels should be the same. Out-
feed in the ground subsystem is seldom significant. Therefore, “Offset Keying” should always
be used.

The recommended keyer levels for the ground sub-system are:

LGKY = 2.0
RGKY = 2.0
NOTE: In RGKY a setting of “BLK” (Block) has been provided. This setting is to be
used with ABB’s Recommendation. Otherwise, ignore its presence.

5.5.5.2.2 Ground Differential Current (GDIF)

Similar to the phase settings, GDIF depends on the charging current of the line. The relation-
ship of the ground thresholds are:

IGSWP = RGKY – GDIF

IGSWN = RGKY + GDIF

The above are negative thresholds. The recommended setting is:

GDIF = 1.0 For net changing current < 0.75

and GDIF = 0.8 x ICh

(But not less than 1.0A for net charging current >.75 A.)

5.5.5.3 Summary of Recommended Settings

5.5.5.3.1 Offset Keying

For ICH <.75 A.
Both Terminals
LPKY = 3.0
RPKY = 3.0
PDIF = 1.0
LGKY = 2.0

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RGKY = 2.0
PDIF = 1.0
For ICH >.75 A

Both Terminals

LPKY = 3.0
RPKY = 3.0
PDIF = ICH x 1.2
LGKY = 2.0
RGKY = 2.0
GDIF = ICH x .8

5.5.5.3.2 “Skewed” Offset Keying

For ICH <.75 A

Terminal Second
with Outfeed Terminal

LPKY = 7.0 2.0

RPKY = 2.0 7.0

PDIF = 1.0 1.0

LGKY = 2.0 2.0

RGKY = 2.0 2.0

GDIF = 1.0 1.0

For ICH >.75 A

Terminal Second
with Outfeed Terminal

LPKY = 7.0 2.0

RPKY = 2.0 7.0

PDIF = ICH x 1.2 ICH x 1.2

LGKY = 2.0 2.0

RGKY = 2.0 2.0

GDIF = ICH x 0.8 ICH x .8

(but not < 1.0)

NOTE: The above are recommended settings that have been used in thousands of
model power system tests in REL 350’s product development and in years of
experience in the field.
NOTE: For examples of practical applications of the above phase comparison settings
refer to Section 5.11 (on page 91).

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5.5.6

5.5.6.1
Channel - Modem settings

Automatic Use of the Channel Delay Measurement

The relay logic continuously performs the communication Channel Delay measurement. To use
5
this feature set ALDT to YES. If fixed Channel Delay value is to be used set ALDT to NO.

5.5.6.2 Lead/Follow Mode (LDFL)

One terminal should be set to LDFL = LEAD and the other to LDFL = FOLO.

NOTE: Never set both terminals the same. I.e., both to LDFL = LEAD nor both to
LDFL = FOLO.

5.5.6.3 Local Delay Timer (LDT)

REL 350 uses the LDT setting when no automatic channel delay measurement is being used
(ALDT = NO).

LDT should be equal to the total channel delay including the inherent modem delay.

For Example:
Modem (9600 Baud) = 8.6 msec
Channel (micro-wave) = 4.0 msec
LDT = 12.6 msec.
Set LDT = 12.6

5.5.6.4 Transmitter level (XMTR)

(9600 bps Audio Tone option)

This setting defines the output power from the unit’s transmitter in [-dBm].

5.5.6.5 Receiver Level Signal Detector (RLSD)

(9600 bps Audio Tone option)

This setting defines the minimum threshold for declaring channel trouble (CHTB) in [-dBm].

5.5.6.6 Unit Identification (UNID)

(56/64 kbs option)

This setting eliminates the possibility of connecting two wrong units to each other due to cross
connection in the communication channel matrix.

• The UNID numbers in both units should be adjacent.

For Example:
0 in one and 1 in the other
2 “ 3 “
10 “ 11 “

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• The lower number of the pair should be an even number

For Example:
0 and 1 is legal and 1 and 2 is illegal

5.5.6.7 Communication Speed Selection (KBPS) (56/64 kbps option)

This setting allows 56 kbps or 64 kbps communication speed selection.

This speed should be coordinated with the external communication multiplexer used in the sys-
tem.

A vast majority of applications are 64 kbps.

5.5.6.8 Transfer Trip (TTRP) (56/64 kbps option)

Transfer Trip function as initiated by a contact closure (TB5 9 to 10) can be enabled or disabled
(IN or OUT).

If enabled (TTRP = IN) contact closure, as described above will result in transmission of TTRIP
code to the remote unit, the reception for at least 10 msec will result in 3-pole tripping at the
remote unit.

5.5.6.9 Transmit Clock Source (XCLK) (56/64 kbps option)

This setting establishes source of the transmit Data clock.

If XCLK = EXT is set, the transmit data clock is extracted from the received data stream. XCLK
set to INT causes transmit clock origination from the internal crystal oscillator.

NOTE: For systems utilizing External Communication Multiplexers (T1 or E1 type) this
setting should be EXT.
For Systems where REL 350 units are connected directly (no multiplexers) this
setting should be INT.

5.5.6.10 Loopback (LPBK) (56/64 kbps option)

For Loopback configuration used in test when transmitter to receiver connection is made set
LPBK = YES.

NOTE: This setting is set to NO for normal system operation.

5.6 FAULT LOCATOR, BLINDERS AND DISTANCE PROTECTION COMMON

SETTINGS

5.6.1 Ohms per Unit Distance (XPUD)

This setting is used by the fault locator algorithm to estimate a calculated distance to the fault.
The units of XPUD will be in primary ohms per mile or ohms per kilometer, depending on the
setting of DTYP.

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For Example:
Set XPUD = 0.8 if DTYP = miles and the line reactance is 0.8 Primary Ohms/mile.
5
5.6.2 Distance Unit Type for XPUD (DTYP)

Either miles (MI) or kilometers (km) should be selected. This setting should match the units
used in XPUD.

5.6.3 Line Positive sequence impedance setting angle (PANG)

This setting relates directly to the assumed positive sequence impedance angle of the line. It
defines the Zone 2 and Zone 3 phase impedance unit maximum torque angle in degrees. This
setting is also the complement of ZP (Phase reach) and is also used for defining the slope of
the blinders for OST and OSB and for the fault locator algorithm.

For example, if the assumed positive sequence impedance of the line is Z1 = 3.0 ohms at 75°,
then set PANG = 5.

5.6.4 Line zero sequence impedance angle setting (GANG)

This setting defines the assumed impedance angle of the zero sequence (Zl0) impedance of
the transmission line. Zone 2 and Zone 3 ground impedance units use this parameter for their
operation.

For Example:
If the assumed zero sequence impedance of the line is Zl0 = 15 ohms at 80° then set
GANG = 80.

5.6.5 Zero sequence impedance to Positive sequence impedance ratio (ZR)

This setting is used for all ground fault measurements. It reflects the magnitude ratio of the as-
sumed zero sequence impedance to the positive sequence impedance of the line.

For Example:
If Zl0 = 65 ohms at 60°, and Zl1 = 19 ohms at 75°, then set ZR = 65/19 = 3.42.

5.7 BACK - UP SYSTEM SETTINGS

5.7.1 Loss of Potential Block enable (LOPB)

This setting enables the loss of potential logic (Vo and not Io) to block all Zone 2 and Zone 3
impedance units if the logic is satisfied.

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For Example:
Set LOPB = YES to enable the logic.

5.7.2 Forward Directional Phase Unit (FDOP)

If the system has voltage inputs, then the high set overcurrent units (IPH) can be made direc-
tional if FDOP is in. Set FDOP = IN to make the IPH units directional.

NOTE: In a series capacitor environment the directional units are not reliable. Set
FDOP = OUT when using IPH in a series capacitor environment. This makes
the IPH units non-directional.

5.7.3 Forward directional ground unit (FDOG)

If the system has voltage inputs, then the high set overcurrent unit (IGH) and the time delayed
ground back-up unit (TOG) can be made directional if FDOG is in. Set FDOG = N to the make
the IGH and TOG units directional.

NOTE: In a series capacitor environment the directional unit is not reliable. Set
FDOG = OUT when using IGH and TOG in a series capacitor environment. This
makes the IGH and TOG units non-directional.

5.7.4 Ground directional unit polarization

options (DIRU)

The ground directional unit can be zero sequence or negative sequence polarized. When zero
sequence polarized it uses all zero sequence quantities to determine the power flow direction
and it is very sensitive to zero sequence mutuals between parallel lines. When negative se-
quence polarized it uses all negative sequence quantities to determine the power flow direction
and its operation is negligibly affected by the presence of mutual effects. Set DIR = ZSEQ if mu-
tuals are not a consideration and DIR = NSEQ if strong zero sequence mutuals are present in
the neighborhood of the transmission line.

5.7.5 Medium set zero sequence overcurrent unit (IOM)

This overcurrent unit supervises the ground trips of the ground units in the impedance back-up
system. If TOG is being used it is also used for tripping after a time delay, TOG. It is measuring
the ground return current or 3I0. It should be set above the maximum expected unbalance in
the normal load current flow in the line.

The recommended setting is IOM = 0.5 amps.

5.7.6 Time Overcurrent Ground back - up timer (TOG)

This timer starts timing after IOM has operated. The relay system will trip if this TOG timer has
operated. It is used for back-up to the ground distance units for high ground fault resistance
faults that do not cause system instability and may not be detected otherwise. This unit needs
to be coordinated with down stream devices.

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5.8 ZONE 2 AND ZONE 3 SETTINGS

Settings for Zone 2 and Zone 3 protective systems are similar. Application of the distance units
follow the standard application for a conventional step distance, non-pilot relaying system.
5
When REL 350 is applied in a series capacitor environment, the impedance units provided to
it are always to be used as time delayed Zone 2 and Zone 3 protective zones with the series
capacitor shorted.

Following the traditional step distance, Zone 2 is set to under-reach any Zone 1 covering the
adjacent lines coming out of the remote terminal, if possible. It is also expected that Zone 2 will
always cover at least 100 percent of the protected line plus 10 percent of the shortest adjacent
line under all operating conditions. The maximum apparent impedance that the line can have
is when the protective gaps and/or MOV’s are shorting the series capacitors totally and effec-
tively removing the series capacitors from the apparent impedance to the relay. Therefore, this
condition should be the basis for calculating the reach of Zone 2.

Zone 2 timers, for phase and ground, should be set to coordinate with the forward and reverse
adjacent high speed trips. Moreover, the timer should include the breaking time of the slowest
adjacent breaker and a tolerance of two to three cycles. Typical Zone 2 timers range between
0.2 to 0.3 seconds.

For Zone 3, it is recommended to be set under-reaching any Zone 2 from the remote terminal,
if possible. Zone 3 should include at least 100 percent of the protected line plus 100 percent
of the adjacent shortest line plus 10 percent of the next shortest line.

Zone 3 timers, for phase and ground, should be set to coordinate with the forward and reverse
adjacent Zone 2 trips. Generally two times the Zone 2 timer may be chosen for the Zone 3 timer
setting. Zone 3 timer ranges between 0.4 and 0.6 seconds.

Applicable parameters and settings for the characteristics of the zones have been discussed
already. These are the PANG, GANG and ZR settings discussed in previous paragraphs since
they are commonly used in other parts of the relay algorithms, for example the fault locator.

Ground units in both zones are self-polarized and have a forward (ZGf) and a reverse (ZGr)
reach. Therefore, phase to ground has a forward and a reverse reach in order to have better
performance when applied to resistance grounded system. The FDOG is used to supervise the
forward direction while the “reverse” reach is used primarily to define the overall size of the
characteristic and the amount of reach along the R-axis.

The phase to phase and 3-phase units in REL 350 have only a forward reach (ZP). These units
are inherently directional. This implies that all phase to phase and some phase to phase to
ground and 3 phase faults have a forward reach only.

Examples of Zone 2 and Zone 3 reach settings will be provided in Section 5.11, begining on
page 91.

5.8.1 Zone 2 phase unit reach (Z2P)

This setting controls the Zone 2 reach for phase to phase faults in secondary ohms. It is always
forward looking.

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For Example:
If Z2 reach is 30 ohms at 75°, set Z2P = 30.

5.8.2 ZONE-2 PHASE TIMER (T2P)

Selects the time delay for Zone 2 Phase fault detection in seconds. Set T2P = 0.15 if the min-
imum time delay for step distance coordination is 150 milliseconds.

5.8.3 Forward Zone 2 ground unit reach (Z2GF)

This setting is equivalent to the phase unit setting since it defines the forward reach of the Zone
2 ground unit in secondary ohms.

For Example:
Set Z2GF = 30 if the Zone 2 reach is 30 ohms at 75°.

5.8.4 Reverse Zone 2 ground unit reach (Z2GR)

Phase to ground units in REL 350 have been designed to have three self-polarized phase-
ground units (ph-A, ph-B, ph-C). The Z2GR setting is determined by the amount of reach along
the R-axis as shown in figure 3-6(on page 37).

For Example:
If the reverse reach has been determined to be 15 ohms at 75°, set Z2GR = 15.

5.8.5 Zone 2 ground unit timer (T2G)

Selects the time delay for Zone 2 Ground fault detection in seconds. Set T2G = 0.15 if the min-
imum time delay for step distance coordination is 150 milliseconds.

5.8.6 Zone 3 phase unit reach (Z3P)

This setting controls the Zone 3 reach for phase to phase faults in secondary ohms. It is always
forward looking.

For Example:
If Z3 reach is 45 ohms at 75°, set Z3P = 45.

5.8.7 ZONE-3 PHASE TIMER (T3P)

Selects the time delay for Zone 3 Phase fault detection in seconds. Set T3P = 0.30 if the min-
imum time delay for step distance coordination is 300 milliseconds.

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5.8.8 Forward Zone 3 ground unit reach (Z3GF)

This setting is equivalent to the phase unit setting since it defines the forward reach of the
Zone 3 ground unit in secondary ohms.
5
For Example:
Set Z3GF = 45 if the Zone 3 reach is 45 ohms at 75°.

5.8.9 Reverse Zone 3 ground unit reach (Z3GR)

Phase to ground units in REL 350 have been designed to have three self-polarized phase-
ground units (ph-A, ph-B, ph-C). The Z3GR setting is determined by the amount of reach along
the R-axis as shown in figure 3-6(on page 37).

For Example:
If the reverse reach has been determined to be 15 ohms at 75°, set Z3GR = 15.

5.8.10 Zone 3 ground unit timer (T3G)

Selects the time delay for Zone 3 Ground fault detection in seconds. Set T3G = 0.30 if the min-
imum time delay for step distance coordination is 300 milliseconds.

5.9 OUT-OF-STEP LOGIC SETTINGS

Segregated phase comparison is immune to system swings. When voltage inputs are part of
the REL 350, blinders are provided for power swing detection. The Out of Step Trip (OST) logic
is executed all the time regardless of the status of the channel. This means that OST is possible
when the system is operating the segregated phase comparison algorithm only. The Out of
Step Block (OSB) logic is only applicable to the back-up system, i.e., Zone 2 and Zone 3.

5.9.1 Out of Step Trip (0ST)

This setting enables the Out of Step Trip logic. Set the relay to:

OUT: If there is no need for an Out of Step Trip.

WAYI: If the controlled Out of Step Trip is in the Way in to the operating characteristics of
the relay.

WAYO: If the controlled Out of Step Trip is in the Way out of the operating characteristics
of the relay.

5.9.2 Out of Step Block (OSB)

This setting enables the Out of Step Block logic that blocks the Zone 2 and/or Zone 3 distance
units under Out of Step Conditions.

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Chose:

OUT: If no OSB is required

Z2: If only Zone 2 units are to be blocked by the OSB logic on Out of Step conditions.

Z3: If only Zone 3 units are to be blocked by the OSB logic on Out of Step conditions.

BOTH: If both Zone 2 and Zone 3 are to be blocked by the OSB logic on Out of Step con-
ditions.

5.9.3 Inner blinder, 21 BI, setting. (RT)

This setting is the offset in the perpendicular direction to the line impedance on the R-X diagram
in Ohms.

For Example:
Set RT = 4.0 ohms for an inner blinder 4 ohms away from the line impedance.
NOTE: RT restricts tripping inside its operating characteristics. It may be used for
load restriction purposes to avoid tripping under load.
5.9.4 Outer blinder, 21 B0, setting (RU)

Similar to RT. It does not restrict tripping. Used mainly to detect out of step conditions.

For Example:
Set RU = 8.0 ohms for a blinder 8.0 ohms away from the line impedance.
5.9.5 Out of Step detection timer. (OST1)

This timer is started when the outer blinder, 21 B0, has operated but the inner blinder, 21 BI,
has not operated. If the timer times out, an out of step condition has been detected and OSB is
active.

For Example:
Set OST1 = 1.5 cycles.
5.9.6 Out of Step Trip on the Way in timer (OST2)

This timer is started when an Out of Step condition has been detected and the two blinders have
operated. Once it times out, a trip signal is issued for OST.

For Example:
Set OST2 = 2 cycle.

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5.9.7 Out of Step Trip on the Way out timer (OST3)

This timer is started when an Out of Step condition has been detected and the OST2 timer
has timed out and both 21 BI are NOT operated. This permits controlling the time that the
breaker opens.
5
OST3 = 0.5 cycles

5.9.8 Out of Step Over-ride timer. (OSOT)

This timer is started once an Out of Step condition is identified (output of OST1). An OST signal
is generated if OSOT times out and the apparent impedance seen by the relay is inside Zone
2 or Zone 3 reach plus the RT blinde

For Example:
OSOT = 1600 msec

5.10 TIME SETTINGS

REL 350 has an internal clock for event time tagging purposes. Even if the unit has lost its pow-
er supply the internal clock will continue running.

5.10.1 Setting the clock

To set the clock in the relay, set TIME = YES.

The next fields are self explanatory:

- Year YEAR
- Month MNTH
- Day DAY
- Day of the week WDAY
- Hour HOUR
- Minutes MIN

Enter the correct values as appropriate.

5.11 SETTING EXAMPLES

The purpose of this section is to discuss typical applications of REL 350 and recommended set-
tings for the protective functions.

5.11.1 Example 1

Refer to Figure 5-1(on page 101). REL 350 will be used as the protective relaying system for a
500 KV series-capacitor compensated line. The maximum line loading, line impedances and
charging current of the line are shown in the Figure in primary quantities. The vt and ct ratios
are Rv = 4167 and Rc = 400, respectively.

The series capacitor banks provide a total of 66.7% compensation and are located at both line
terminals. The series capacitors are protected from over-voltages by gaps.

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Outfeed currents that could be generated in the line due to different power system conditions
will never be greater than 500 amps primary. Also, the maximum expected residual unbalance
in the load current is 100 amps primary.

5.11.1.1 Segregated Phase Comparison Settings.

Using the specified ct ratio, the secondary currents that determine the thresholds of the termi-
nals are:

ICH = ICH primary/Rc

= 0.575 sec amps

Max. Load = Imax/Rc

= 4.33 sec amps

Max. Outfeed = 500/Rc

= 1.25 sec amp

Max. Unbalance = 100/Rc

= 0.25 amps

Since the maximum outfeed is less than 2.5 (4.33/5.0) or 2.17 amps, Offset Keying will be used.

For the Phase systems the local and remote keying levels are the same at both terminals and
referring to Section 5.5.5.3 the keyer level should be:
RPKY = 3.0 (4.33/5) = 2.6

LPKY = 2.6

Also since ICH is less than 0.75 (4.33/5.0) = 0.65 then the differential should be:
PDIF = 1 (4.33/5.0) = 0.87

The low set overcurrent, IPL, should be set at 1.5xICH or 0.5 amps, which ever is maximum. In
this case
IPL = 1.5 x (0.575) = 0.86 amp

For the ground subsystem, for both terminals, the keyer levels are:
RGKY = 2.0 (4.33/5.0) = 1.7

LGKY = 1.7

Since ICH < 0.75 (4.33/5.0) the differential current is:

GDIF = 1.0 (4.33/5.0) = 0.87

The low set overcurrent unit should be set at

IGL = 0.5

since it is above the maximum expected unbalance of 0.25.

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5.11.1.2 Back-up distance settings

Only settings for the left or local relaying system will be provided since the right or remote
relaying system should follow the same guidelines.
5
Using the ct and vt ratios of 400 and 4167 respectively, the secondary impedances required for
the proper setting of the impedance units are:

Zl1 = 100/(Rv/Rc)

= 9.6 ohms at 80 deg.

Zl0 = 33.6 ohms at 70 deg.

Xcl = -j 3.17 ohms

Xcr = -j 3.17 ohms

Zsl1 = 3.17 ohms at 80 deg.

Zadj = 4.8 ohms at 80 deg.

Min

Zadj = 0.96 ohms at 80 deg.

2nd

To set the forward reach of the distance units, (the series capacitor should be shorted).

Under this conditions, the settings of the positive and zero impedance angles and ratio should
be:
PANG = 80
GANG = 70
ZR = (Z0l/Z1l)
= 3.5

The forward reach is obtained using the guidelines of Section 5.8. Therefore:

Z2P = 9.6 + 0.7(4.8)

= 12.96 sec. Ohms

Z2GF = 12.96 sec. Ohms

Z3P = 9.6 + 1.0(4.8) + 0.7(0.96)

= 15.07 sec ohms

Z3GF = 15.07 sec ohms

NOTE: Zone 2 and Zone 3 reach settings should include at least 10% of the next adja-
cent line, as shown in the example above.

The above assumption ensures that the whole line will be covered by Zone 2 and Zone 3 dis-
tance units when the gaps have been shorted.

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I.L. 40-201.81 Version 2.50

The phase to phase unit is inherently directional. Please refer to Figure 3-8(on page 39) for de-
termining the characteristic of the unit and Figure 5-1(on page 101) for the applicable charac-
teristic for this example.

The phase to ground units have a reverse reach setting which is determined by the amount of
reach along the R-axis as shown in figure 3-6 (on page 37). Assume 25% of the forward reach.
Therefore, the reverse ground settings should be:

Z2GR = 0.25 (12.96) = 3.24 sec ohms

Z3GR = 0.25 (15.07) = 3.77 sec ohms

The phase to ground units are directional with FDOG supervision and the reverse reach should
be considered for coordinating step distance zones.

The forward directional units supervising IPH and IGH should be set 1.15 times the maximum
fault on the remote bus, where the factor of 1.15 is to allow for the transient overreach.:

5.11.2 Example 2

Refer to Figure 5-2(on page 102). REL 350 will be used as the protective relaying system for a
345 KV series-capacitor compensated line. Other lines of different voltages run parallel to it and
introduce a zero sequence mutual impedance of about 60% of the zero sequence impedance
of the 345Kv line to be protected. The maximum line loading, line impedances and charging
current of the line are shown in the figure in primary quantities. The vt and ct ratios are
Rv = 2875 and Rc = 600, respectively.

The series capacitor banks provide 50% of compensation and are located at both line terminals.
The series capacitors are protected from over-voltages by gaps and Metal Oxide Varistors.

Outfeed currents that could be generated in the line due to different power system conditions
will never be greater than 800 amps primary. Also, the maximum expected residual unbalance
in the load current is 150 amps primary.

5.11.2.1 Segregated Phase Comparison Settings

Using the specified ct ratio, the secondary currents that determine the thresholds of the termi-
nals are:

ICH = 0.5 sec amps

Max. Load = 5.0 sec amps

Max. Outfeed = 1.33 sec amp

Max. Unbalance = 0.25 amps

Since the maximum outfeed is less than 2.5, Offset Keying will be used.

For the Phase systems the local and remote keying levels are the same at both terminals and
referring to Section 5.5.5.3(on page 81), the keyer level should be:

RPKY = 3.0

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Version 2.50 I.L. 40-201.81

LPKY = 3.0

Also since ICH is less than 0.75 then the differential should be: 5
PDIF = 1.0

The low set overcurrent, IPL, should be set at 1.5 x CH or 0.5 amps, which ever is maximum.
In this case

IPL = 1.5x0.5 = 0.75 amp

For the ground subsystem, for both terminals, the keyer levels are:

RGKY = 2.0

LGKY = 2.0

Since ICH < 0.75 the differential current is:

GDIF = 1.0

The low set overcurrent unit should be set at

IGL = 0.5

Since it is above the maximum expected unbalance of 0.25.

5.11.2.2 Back-up Distance Settings

Only settings for the left or local relaying system will be provided since the right or remote re-
laying system should follow the same guidelines.

Using the ct and vt ratios of 600 and 2875 respectively, the secondary impedances required for
the proper setting of the impedance units are:

Zl1 = 30 (600/2875 = 6.26 ohms at 85 deg.

Zl0 = 86 (600/2875) = 17.95 ohms at 70 deg.

Xcr = -j 1.57 ohms

Zsl1 = 10.43 ohms at 85 deg.

Zadj = 3.13 ohms at 85 deg.

Min

Zadj = 2.09 ohms at 85 deg.

2nd

To set the forward reach of the distance units, consider the worst condition, which is with all the
gaps flashed (shorted), therefore ignoring the presence of the capacitors in the line.

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I.L. 40-201.81 Version 2.50

Under this condition, the settings of the positive and zero impedance angles and ratio should
be:

PANG = 85
GANG = 70
ZR = 2.87

The forward reach is obtained using the guidelines of Section 5.8(on page 87). Therefore:

Z2P = 6.26 + 0.1(3.13)

= 6.57sec. ohms
Z2GF = 6.57 sec. Ohms
Z3P = 6.26+ 3.13 + 0.1(2.09)
= 9.60 sec ohms
Z3GF = 9.60 sec ohms
NOTE: Zone 2 and Zone 3 reach settings should include at least 10% of the next adja-
cent line, as shown in the example above.

The above assumption ensures that the whole line will be covered by Zone 2 and Zone 3 dis-
tance units when the gaps have flashed.

The phase to phase unit is inherently directional and will always see the capacitor. Please refer
to Figure 3-8(on page 39) for determining the characteristic of the unit and Figure 5-2(on page
102) for the applicable characteristic for this example.

The phase to ground units have a reverse reach as well and the purpose of this reverse reach
is to extend the reach along the R-axis as shown in figure 3-6 (on page 37). Assume to set at
25% of the forward reach. Therefore, the reverse ground setting should be:

Z2GR = 0.25 (6.57) = 1.64 sec ohms

Z3GR = 0.25 (9.60) = 2.40 sec ohms

The phase to ground units are non-directional and the reverse reach should be considered for
coordinating step distance zones.

The forward directional units supervising IPH and IGH should be set 1.15 times the maximum
fault on the remote bus, where the factor of 1.15 is to allow for the transient overreach.

5.11.3 OST Settings – Example

5.11.3.1 The Problem

Refer to the example of Figure 5-3(on page 103). Two neighboring utilities are tied together by
two series compensated parallel lines. These lines are the only ties to the system and are de-
signed to transfer 3000 MW in either direction. MOV’s and protective gaps are part of the series
capacitor banks which provide 66.67% compensation.

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Version 2.50 I.L. 40-201.81

The two utilities have agreed that if either power system becomes unstable, separation is nec-
essary to prevent the stronger utility from having to shed load. The impedances for the two pow-
er systems are equivalent, and it is evident that the electrical center for the overall system is in
the parallel lines.
5
Stability studies performed by the two utilities did not consider the unsymmetrical behavior of
the protective gaps and non-linear MOVs. The stability studies performed considered the ca-
pacitors either in or out. Experience of the system departments indicated that these were the
two extremes and that the real behavior would be in between these two conditions.

Table 5-1: Table 5-2:

Overall System From REL 350 (L)

Zec Sec Zms Sec Zec Sec Zms Sec

CASE CASE
Ohms Ohms Ohms Ohms

5 - 4a 6.49 ∠81.92˚ 7.50 ∠51.92˚ 5a 3.04 ∠71.70˚ 8.51 ∠12.04˚

4 - 4b 11.49 ∠81.08˚ 13.27 ∠51.08˚ 5b 13.03 ∠78.8˚ 19.07 ∠34.08˚

REL 350 relays, with optional back-up distance logic, will be used for the protective relaying of
the transmission lines. Segregated phase comparison has been chosen due to the presence of
series capacitors. This relaying scheme, however, is immune to power swings that occur when
the phase difference between two systems is increasing and the apparent three phase imped-
ance falls somewhere in the protected line. The optional backup system; however, is affected
by the power swing and will operate if the apparent impedance falls in the three phase imped-
ance characteristics that may even include a reverse reach.

The stability studies and the experience of the system engineers in both utilities estimated that
for the overall system (both parallel lines in), the impedance trajectory on the R-X diagram will
travel with a maximum rate of 0.75 sec. ohms/cycle. This is the worst case and their experience
indicated that it is an extremely fast rate.

5.11.3.2 General Comments

The above discussion may not be a real life situation, but does illustrate several points to be
considered.

Segregated phase comparison is immune to power swings, therefore, the additional OST logic
is necessary for controlled tripping of the transmission line.

The optional impedance back-up is not immune to power swings; through it is in service only
on channel failure, and the OSB option should be used when controlled tripping (OST) on pow-
er swings is required.

The OST logic is operative all the time, regardless of the channel status and provides controlled
tripping of the circuit breaker. Large angle differences between the voltages of the two terminals
make interruption of the current more difficult for the circuit breaker. Therefore, the time for
energizing the trip coil of the circuit breaker should be controlled. The OST options of the trip-
ping of the breaker “On the Way Out (WAYO)” and “On the Way In (WAYI)” provide this flexi-
bility. Tripping “On the Way In” is required if the swing rate is slow. Tripping “On the Way Out”
is required if the swing is relatively fast.

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I.L. 40-201.81 Version 2.50

Although the above example illustrates a case in which two parallel lines connect two power
systems; it is by no means the rule. Any two power systems can be reduced to two source im-
pedances and two lines connecting the two. One of the lines is the line under consideration for
the OST settings and the other is the equivalent connection between the power systems.

The OS detection in REL 350 is done by the use of two blinders. The time spent by the apparent
impedance in between blinders is an indication of an out-of-step condition. The requirements
for setting the inner (21 BI) and outer (21 BO) blinders are:

• The inner blinder (21 BI) must be set to accommodate reasonable amounts of phase-fault-
impedance. Generally this is not a limitation.
• The inner blinder (21 BI) should not operate for stable swings. It is a rule of thumb that the
most severe stale swing occurs when the phase difference between the source voltages is
120°. If the phase difference between sources is greater, the swing may be considered un-
stable.
• The outer blinder (21 BO) must have adequate separation from the inner blinder to identify
the fastest power swing as an out-of-step condition.
• The outer blinder (21 BO) must not operate on maximum load (minimum apparent imped-
ance). Generally this will be the limiting case.

It is especially true in selecting settings for the out-of-step logic that experience and good judge-
ment are important. There are no strict rules to follow; except a few guidelines.

5.11.3.3 Settings Procedure

All impedances in Figure 5-3(on page 103), are in secondary ohms, and they correspond to the
positive sequence impedances of the systems and lines.

The following settings calculation will consider the relay at bus a, REL 350 (L).

The maximum load flow into the line is 1500MW. This translates to a primary current of 2510
amp. Taking into consideration ct and vt ratios, the minimum apparent load impedance corre-
sponds to 16.56 ohms.

When the gaps are not flashed the equivalent combination of the two lines considers the neg-
ative reactance of the reactors also. In this example when the gaps are not flashed the equiv-
alent impedance of both lines is around 5∠80°.

Calculating the electrical center for the system when the gaps are not flashed:

Zec = (5∠85˚+ 5∠80˚ + 3∠80˚) / 2 = 6.49∠81.92 sec ohms

The maximum stable angular separation is a phasor with an angle that is 30° lower than the
angle of the electrical center impedance (Zec) and a magnitude of Zec/Cos(30°). This corre-
sponds to a phase difference of 120° between the sources.

Therefore:

Zms = (6.49 / 0.866) ∠81.92° - 30° = 7.5 ∠51.92° sec ohms

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These points are plotted in Figure 5-4(on page 104). The diagrams are not to scale, but do help
in the illustration.

The same procedure could be followed for all the gaps conducting case. Therefore:
5
Zec = (5∠85° + 15∠80° + 3∠80°) /2 = 11.49 ∠81.086° sec ohms

and
Zms = (11.49/Cos 30°) ∠81.086° -30° = 13.27 ∠51.086° sec ohms

These last two points are shown in Figure 5-4 (b)(on page 104). Table 5-1(on page 97), is a
summary of the previous calculations:

The above apparent impedances shown in Figure 5-4(on page 104), do not correspond by any
means to the apparent impedance that the relay REL 350 (L) will “see”. They are offset by the
source impedance behind bus A. Moreover, the influence of the other parallel transmission line
should be taken into account. This is done by multiplying any of the above impedances by the
factor (Z1+Z2) / Zp, where Z1 is the line under consideration and Zp is the line parallel to the
line under consideration. In the present case, this factor is equal to 2.

The electrical center when the gaps are conducting referenced to REL 350 (L) is therefore:

Zec A = 2 (Zec - 5∠85°) = 3.04 ∠71.7° sec ohms

Figure 5-5(on page 105) illustrates the calculated values for the gaps conducting and not con-
ducting with the impedances referenced to REL 350 (L). The figures shown are not to scale.
Table 5-2 can be calculated with the above procedure:

The same is true for the swing rate estimate. An estimate of 0.75 ohms/cycle rate, for REL 350
(L) is equivalent to 0.75 (2) = 1.5 sec ohms per cycle.

The inner blinder setting is to be determined by the maximum stable phase separation when
the gaps are not conducting. RT = 8.5 is a reasonable setting for the inner blinder.

It is recommended that for severe fast swing rates the outer blinder be set as far apart from the
inner blinder as possible. Since the limitation for the inner blinder is the minimum apparent im-
pedance for load flow, and this limit is 16.56 sec ohms a setting of RU = 14 sec ohms is rea-
sonable.

The difference in secondary ohmic impedance between the two blinders is 14 - 8.5 = 5.5
ohms. For the fastest swing of 1.5 ohms per cycle, this indicates that the apparent impedance
trajectory will be a minimum of 3.66 cycles in between blinders. This indicates that OST1 can
be set to 3 cycles and be sure that any power swing will be detected.

When controlled out-of-step trip is desired it is necessary to block the operation of the imped-
ance units in the back-up system for loss of channel. Therefore OSB = BOTH should be select-
ed to block the operation of Zone 2 and Zone 3 units.

Due to the fast swing rate expected it will be safe to avoid the tripping “On the Way In” since
this could produce the opening of the breaker contacts when the phase difference between the

99
I.L. 40-201.81 Version 2.50

generator voltages is almost 180° out-of-phase, i.e., the apparent impedance being close to the
electrical center of the system.

Therefore, to control the tripping of the breaker OST = WAYO is used and the breaker trip coil
will be energized when the apparent impedance of the swing is coming out of the operating
characteristics of the blinders.

OST2 setting is for tripping “on the Way In” and maybe set to 0.5 cycles to minimize its influence
in the above.

OS3 is a security timer. It is the minimum time inside the two blinders (21 BI and 21 BO) to de-
clare an unstable swing and trip “On the Way Out”. If the fastest travel between inner blinders
is 2(85) / 1.5 = 113.33 cycles, then the maximum setting of 3 cycles will provide enough secu-
rity.

OSOT is the out-of-step block Override timer. This timer should reflect the maximum permissi-
ble time that the impedance trajectory can stay in between outer blinders (21 BO). Using a width
of 2 (14) = 28 ohms between outer blinders and a swing rate of 1.5 ohms per cycle, a total un-
stable swing, traveling from right, to left will take 18.67 cycles. Allowing the logic for OST on the
WAYO to trip takes another 1.5 cycles (refer to logic diagram, Figure 3-17(on page 48)). Allow-
ing 5 cycles of tolerance OSOT cold be set for 400 msec.

In summary, the settings for the proceeding example are:

OS = WAYO
OSB = BOTH
RT = 8.5
RU = 14.0
OST1 = 3.0
OST2 = 0.5
OST3 = 3.0
OSOT = 400
NOTE: The above settings example has been provided for demonstration purposes to
illustrate the function of the different settings. It should be mentioned again
that OST logic settings are based on good judgement as well as experience.

100
 Version 2.50
REL 350(L) REL 350(R)

Z3G Z3P
Gaps flashed Gaps flashed

Z2G

Normal Normal
R

Phase-to-Ground units Phase-to-Phase units

I.L. 40-201.81
Sub 2
ESK000253
101

Figure 5-1:

5
102

I.L. 40-201.81
REL 350(L) REL 350(R)

Z3G
Gaps Flashed Z3P
Gaps Flashed

Normal Z3P
Z3G

Normal

Phase to Phase Unit

Phase to Ground Units

Version 2.50
Sub 2
ESK000254

Figure 5-2:
 Version 2.50
REL 350(L) REL 350(R)

I.L. 40-201.81
Sub 2
ESK00347
103

Figure 5-3:

5
I.L. 40-201.81 Version 2.50

a) Gaps not conducting

b) All gaps conducting

ESK00348

Figure 5-4:

104
Version 2.50 I.L. 40-201.81

5
Maximum stable
Angular Separation

a) Gaps not conducting

Maximum stable
Angular separation

b) All gaps conducting

ESK00349

Figure 5-5:

105
 Notes

106
Version 2.50 I.L. 40-201.81

BACKPLANE MODULE

Schematic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1612C22
A
Component Location Diagrams - - - - - - - - - -1611C26, 1502B38

All external electrical connections pass thru the Backplane module (see Figure 4-1, on page
70) of the outer chassis. Seven DIN connectors (J11, J12, J13, JA1, JA2, JA3 and JA4) allow
for the removal of the outer chassis (Backplane module) from the inner chassis (Interconnect
module, Contact Input and Relay Output modules).

Electrical inputs to the Backplane module, which are routed through the FT-14 switch to the
Backplate, include:

• VA, VB, VC, and VN

• IA/IAR, IB/IBR, IC/ICR
• BP(48, 125 or 250 Vdc) and BN (common) for primary and backup power inputs.

The Backplane module, (see Figure A-1, on page 108 and Schematic) contains three voltage-
type transformers, for VA/VN (VAN), VB/VN (VBN), VC/VN (VCN) inputs.

A Transformer module (see Figure A-2 and Schematic, on page 109) is piggybacked onto the
Backplane module, consisting of three current-type transformers (IA, IB, IC) with three 0.1% re-
sistors. The primary windings of all six transformers are directly-connected to the input terminal
(TB6/1 thru 10); the secondary windings are connected thru the Interconnect module to the
Analog Input module. The current transformers (IA, IB, IC) are not gapped; dc offset attenuation
is done with a digital filtering algorithm. Surge suppression is included where the signals enter
the module.

The Backplane module also includes:

• 4 chokes (L1 thru L4) for dc power supply filter

• surge-suppressor capacitors

INCOM/PONI is supplied in two versions:

• INCOM/PONI to RS232 computer interface (supplied as standard).

• INCOM/PONI to INCOM network interface (supplied as option).

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I.L. 40-201.81
Sub 7

Version 2.50
1611C26

Figure A-1: REL 350 Backplane Module Component Location Diagram

Version 2.50 I.L. 40-201.81

Sub 1
1502B38

Figure A-2: REL 350 Backplane/Transformer Module PC Board

109
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I.L. 40-201.81
Version 2.50
Sub 4
1612C22

Figure A-3: REL 350 Backplane/Transformer Module Schematic

Version 2.50 I.L. 40-201.81

INTERCONNECT MODULE

Schematic - - - - - - - - - - - - - - - - - - - - 1612C21
B
Component Location Diagram - - - - - - 1611C25

The Interconnect module (see Figure B-1 and Schematic, on page 112) becomes the floor of
the inner chassis and provides electrical connectors for all other modules; it connects from the
Backplane module (at the rear), to the Analog Input and Power Supply modules (at the left and
right sides, respectively), to the Relay Output and Contact Input modules, in the center, and to
the Microprocessor, Modem (CODEC) and Display modules at the front of the chassis. The
components on the Interconnect module include:

• 2 audio transformers for 9600 bps Audio Tone communication channel

• channel alarm relay

Related connections are shown below:

Module
Connector Destination

J11, J12, J13 Backplane

J7 Power Supply
J9 Analog Input
J5 Microprocessor
J10 Modem for 9600 bps option or
CODEC for 56/64 kbps option
JB1 Relay Output (Single Pole Trip)
JB2 Relay Output (Base 1)
JB3 Relay Output (Base 2)
JB4 Contact Input

111
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I.L. 40-201.81
Sub 3
1611C25

Version 2.50
Sheet 3 of 3

Figure B-1: REL 350 Interconnect Module Component Location Diagram

 113

BACKPLATE

Figure B-2: REL 350 Interconnect Module Schematic

(INCOM) (POWER INPUT)
ANALOG INPUT J2 MICROPROCESSOR J6 POWER SUPPLY J7

MICROPROCESSOR J6 MODEM P3
Sub 4
1612C21

CHANNEL CHANNEL
INPUT OUTPUT
J8
J8
J8
J8

INPUTS
OUTPUT
OUTPUT
OUTPUT

CONTACT
CONTACT

CONTROL
CONTROL

B
I.L. 40-201.81 Version 2.50
 Notes

114
Version 2.50 I.L. 40-201.81

RELAY OUTPUT MODULE

Schematic - - - - - - - - - - - - - - - - - - - - 1611C36
C
Component Location Diagram - - - - - - 1611C27

There are 3 versions of the Relay Output module for each operating voltage (48, 125 and 250
Vac), as follows:

VersionFunction

• Option Phase B and C Trip, Breaker Failure

• Base 1 Phase A (3ø) Trip, Breaker Failure, General Start, Reclose Blocking
• Base 2 Trip Alarm, Failure Alarm, Reclose Initiate

The option version provides phase B and C control functions for Single Pole Trip (SPT).

All 9 version/voltage variants share components of the same PC Board; the slight differences
are shown on 1611C27 (sheet 1, on page 117). The 3 versions are plugged-in and permanently
secured (via brackets) to the following connectors on the Interconnect module.

VersionInterconnect Module Connector

• Option JB1
• Base 1 JB2
• Base 2 JB3

Connector JB connects (via the Interconnect module) to the Microprocessor module’s digital
I/0 interface.

Connector JA connects relay contacts through the Backplane module to the outside world.

Opto-isolators U1, U2, U3 and U4 interface logic level output signals from the Microprocessor
module to relay driver transistors (Q1 through Q4, respectively).

Output relays K1, K2, K5, K6, K9, K10 provide desired control operations. Reed relays K3, K4,
K7, K8 monitor the breaker trip control circuit current.

Connector terminals are assigned the following functions (see Table C-1 on the following page):

115
I.L. 40-201.81 Version 2.50

Table C-1:

Option Base 1 Base 2

Terminal Version Version Version

JB-8A Reed B2 Reed A2 —

JB-6A Reed B1 Reed A1 —
JB-2A Trip B Trip A (3Ø) Trip Alarm
JB-6C Reed C2 — —
JB-8C Reed C1 — —
JB-2C Trip C GS (Gen. Start) Failure Alarm
JB-4A BFIB BFIA RI1
JB-4C BFIC RB RI2

JA-30AC/28AC Trip B1 Trip A(3Ø) - 1 Trip Alarm -1

JA-26AC/24AC Trip B2 Trip A(3Ø) - 2 Trip Alarm -2
JA-22AC/20AC Trip C1 — —
JA-18AC/16AC Trip C2 GS Failure Alarm
JA-14AC/12AC BFIB-1 BFIA-1 RI1-1
JA-10AC/8AC BFIB-2 BFIA-2 Ri1-2
JA-6AC/4AC BFIC-1 RB-1 RI2-1
JA-2A/2C BFIC-2 RB-2 RI2-2

116
Version 2.50 I.L. 40-201.81

Sub 3
1611C27

Figure C-1: REL 350 Relay Output Module Component Location Diagram

117
I.L. 40-201.81 Version 2.50

OPTION

* = See Chart Below

Component 48V, G01 125V, G04 250V, G07

R3, 4, 7, 8, 11, 14 750Ω, 5 W 4, 0K 5 W 15, 0K 5W

K1, 2, 5, 6 12V Relay 24V Relay 48V Relay
K9, 10 12V Relay 24V Relay 48V Relay Sub 3
C1, 2, 3, 4 2.0 µF 1.0 µF 0.47 µF 1611C36
Q1, 2, 3, 4 VN2410M VN2410M ZVN0535R Sheet 1 of 3

Figure C-2a: REL 350 Relay Output Module Schematic

118
Version 2.50 I.L. 40-201.81

BASE 1
* = See Chart Below

Component 48V, G02 125V, G05 250V, G08

R3, 4, 8, 11, 14 750Ω, 5 W 4, 0K 5 W 15, 0K 5W Sub 3

K1, 2, 6 12V Relay 24V Relay 48V Relay
1611C36
K9, 10 12V Relay 24V Relay 48V Relay Sheet 2 of 3
C1, 2, 4 2.0 µF 1.0 µF 0.47 µF
Q1, 2, 3, 4 VN2410M VN2410M ZVN0535R

Figure C-2b: REL 350 Relay Output Module Schematic

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I.L. 40-201.81 Version 2.50

sφ
sφ
3φ
3φ

BASE 2

* = See Chart Below

Component 48V, G03 125V, G06 250V, G09

R3, 4, 8, 11, 14 750Ω, 5 W 4, 0K 5 W 15, 0K 5W

K1, 2, 6 12V Relay 24V Relay 48V Relay Sub 3
K9, 10 12V Relay 24V Relay 48V Relay 1611C36
C1, 2, 4 2.0 µF 1.0 µF 0.47 µF Sheet 3 of 3
Q1, 2, 3, 4 VN2410M VN2410M ZVN0535R

Figure C-2c: REL 350 Relay Output Module Schematic

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Version 2.50 I.L. 40-201.81

CONTACT INPUT MODULE

Schematic - - - - - - - - - - - - - - - - - - - - 1611C37
D
Component Location Diagram - - - - - - 1611C28

The Contact Input module provides an opto-isolated interface:

• from the external noise-contaminated contact inputs

• to logic level inputs on the Microprocessor module

This module contains 7 identical circuits; one of these circuits is described below:

• Resistors (R1, R2, R3 and R4) limit the input current to the approximate values of:
3.9 mA for 15V input
2.9 mA for 48V input
8.2 mA for 125V input
3.7 mA for 250V input
• Zener Diode (Z1) provides overvoltage and reverse voltage protection
• Zener Diode (Z2) and shunt resistor (R5) set an approximate 0.6 mA current threshold which
turns-on opto-isolator U1
• Jumper positions JMP3 to JMP9:
(1-2) are for 15/20V
(3-4) are for 48/125V
(5-6) are for 220/250V

NOTE: Position 3-4 is the factory setting.

• Connector JA connects to the Backplane module and, via Terminal Block TB-5, to the exter-
nal contacts
• Connector JB interfaces to the Microprocessor module via connector JB-4 (on the Intercon-
nect module)

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I.L. 40-201.81 Version 2.50

Sub 7
1611C28
Sheet 2 of 2

Figure D-1: REL 350 Contact Input Module Component Location Diagram

122
Version 2.50 I.L. 40-201.81

Sub 3
1611C37

Figure D-2: REL 350 Contact Input Module Schematic

123
 Notes

124
Version 2.50 I.L. 40-201.81

MICROPROCESSOR MODULE

Schematic - - - - - - - - - - - - - - - - - - - - 1612C18
E
Component Location Diagram - - - - - - 1611C22

1.1 ARCHITECTURE

The block diagram of this module is shown in Figure E-1, on page 130. Each block in the figure
has a location designator with the following convention (for example, 2/U16):

Schematic Page # IC Number

2 U16

NOTE: For clarity, the supporting components, e.g., transparent latches, address de-
code PALs, buffers, drivers, etc., are not shown on the block diagram.

Each Processor (P1 and P2) contains the following elements:

• Microprocessor – 16 bit microcontroller (Intel 80C196), operating at a clock frequency

of 12 MHz.
• EPROM – an ultraviolet, erasable read-only memory for program storage.
• RAM – a read-write, static, volatile memory for temporary data storage.
• EEPROM – electrically erasable, read-write memory for settings and fault-data
storage.
• I/O Interface – for power system control (relay outputs and contact inputs); also, in-
terfaces with a communication Modem and analog/digital sub-
system.

Additionally, Processor P1 accesses real-time clock (U16), which contains a battery for non-
volatile operation in the absence of power.

Both processor systems are interconnected via the dual port RAM 2k x 16 (U32). This device
has 2 separate ports; each port permits independent asynchronous access for reads and writes
to any memory location. The chip arbitration logic resolves any contentions for memory access.

1.2 MEMORY MAPS

Memory maps for Processors P1 and P2 are shown in Figures E-2 and E-3, begining on page
131, respectively.

The 80C196 microcontroller supports 64K bytes of address space directly. This is adequate for
Processor 2, but Processor 1 requires more than 64K of address space because of the large
RAM requirement for oscillographic data collection. The INST output of the microcontroller is
used to decode 64K of program memory and 64K of data memory separately.

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I.L. 40-201.81 Version 2.50

1.3 TASK ASSIGNMENT

The processors perform the following major tasks:

Processor 1

• Analog input sampling and Fourier computations

• Operator interface
• INCOM communications
• Non-volatile data storage with 2-out-of-3 memory sampling (voting)

Processor 2

• Protection functions
• Contact input interface
• Control output interface
• Communication Modem interface

1.4 COMMUNICATION CHANNEL INTERFACE

The phase comparison system is based on the data exchanged over the communication chan-
nel. Four current input samples (IO, IA, IB, IC) are examined, each sample period, to determine
if they have crossed the thresholds set by the IKEY and IDIF settings. Linear interpolation of the
sampled data effectively increases the sampling rate by a factor of 16. The resolution of the in-
terpolated samples is 86.8 µs, for a 60 Hz system, operating at 12 samples per cycle. The out-
put of the threshold detection process is a separate pulse train for IKEY, ISWP, and ISWN for each
input current. The ISWP and ISWN pulse trains are then delayed by the local delay time to gen-
erate Local Positive and Local Negative signals. The IKEY pulse trains provide the channel out-
put when keying is enabled. Trip Positive and Trip Negative signals are received from the
remote REL 350 through the channel interface. These signals are compared with the Local pos-
itive and Local Negative signals to determine if proper signal alignment exists for a trip condi-
tion. (See also Section 3, begining on page 15.)

The 12 inputs to the Microprocessor board from the Modem are shown in Table E-2, on page
129. They include 8 digital data inputs (ID0 - ID7); channel interrupt, a 2 to 5 µs signal indicating
a change on the Modem input or S/N out-of-range; Modem reset, indicating the need for Modem
initialization.

The 11 outputs from the Microprocessor board to the Modem are shown in Table E-3, page 5.
They include 8 digital data outputs (OD0 - OD7); two digital control outputs for selecting the Mo-
dem operating mode; and data valid, a 150 ns low-level-true signal indicating an update of the
Modem output data.

The 6 bit code, shown in Figure E-1, on page 130, defines the data output field to the modem
(CODEC) transmitter and the data input field from the modem (CODEC) receiver.

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Version 2.50 I.L. 40-201.81

1.5 JUMPER SETTINGS

Jumper functions are listed below: E

Jumper Position Description

JM1 1-2 Enable Relay Output Test

JM1 2-3* Disable Relay Output Test
(Normal Operation)

JM2 1-2 Disable Display Saver

JM2 2-3* Enable Display Saver
JM3 2-3 Spare, not used at this time“
JM4 2-3 “
JM7 2-3 “
JM8 2-3 “
JM9 2-3 “

JM5 1-2 P2 RAM 2kx8

JM5 2-3* P2 RAM 8kx8 or 32kx8

JM6 1-2* P2RAM 32kx8

JM6 2-3 P2 RAM 8kx8 or 2kx8

* Factory Setting

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I.L. 40-201.81 Version 2.50

Table E-1:
CODING FOR REL 350 CHANNEL DATA

U V W X Y Z
S0 1 0 0 0 0 0

S1 0 0 0 0 0 1

S2 0 0 0 0 1 0

S3 1 0 0 0 1 1

S4 0 0 0 1 0 0

S5 1 0 0 1 0 1

S6 1 0 0 1 1 0

S7 0 0 0 1 1 1

S8 0 0 1 0 0 0

S9 1 0 1 0 0 1

S10 1 0 1 0 1 0

S11 0 0 1 0 1 1

S12 1 0 1 1 0 0

S13 0 0 1 1 0 1

S14 0 0 1 1 1 0

S15 1 0 1 1 1 1

GUARD1 1 1 0 0 0 1

GUARD2 0 1 0 0 0 0

OPBKR 0 1 1 0 0 1

TTRIP* 1 1 0 1 1 1

U Parity (ODD)

V Special Code (Guard, Open BKR, Transfer Trip)

W Phase A

X Phase B

Y Phase C

Z Ground

* 56/64 kb/s option only

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Version 2.50 I.L. 40-201.81

J6 Pin Signal Name

Table E-2:
INPUTS FROM Modem TO MICROPROCESSOR BOARD

Destination Function
E
28c ID0 U25-2 Z (Ground)

28a ID1 U25-3 Y (Phase C)

27c ID2 U25-4 X (Phase B)

27a ID3 U25-5 W (Phase A)

26c ID4 U25-6 V (Guard or Open Breaker)

26a ID5 U25-7 U (Parity)

25c ID6 U25-8 Input Data

25a ID7 U25-9 CT (Channel Trouble)*

24c PINT U41-24 (HSI0) Channel Interrupt

24a MRESET U41-15 (EXTINT) Modem Reset*

18a RECCHL U41-10 (P0.5) Analog Channel Receive Level

18c TXMCHL U41-8 (P0.6) Analog Channel Transmit Level

* Low rue Signal

Table E-3:
OUTPUTS FROM MICROPROCESSOR TO Modem BOARD

J6 Pin Signal Name Destination Function

23c OD0 U38-2 UO (Parity)

23a OD1 U38-5 VO (Guard or Open Breaker)

22c OD2 U38-6 WO (Phase A)

22a OD3 U38-9 XO (Phase B)

21c OD4 U38-12 YO (Phase C)

21a OD5 U38-15 ZO (Ground)

20c OD6 U38-16 Digital output

20a OD7 U38-19 Digital output

19c OC0 U29-12 Modem mode control

17c OC1 U29-15 Modem mode control

19a DATAVAL U35-21 Channel Output Data Valid

129
 I.L. 40-201.81 Version 2.50

INCOM
Operator Network Communication
Interface PONI Interface Modem Interface

φ
φ
J1, J2 J6 J6

A/D Sub-
System
Interface Relay Outputs
φ φ
J5 Processor Processor
J6
P1 P2 Reed Relay Inputs
1/U2 3/U41 φ
J6

Dual Port
RAM
2k x 16
4/U32

EPROM EPROM
32k x 16 32k x 16
1/U1,U14 3/U31, U46

RAM RAM
32k x 16 8k x 16
2/U7, U23 4/U39, U47
Contact
Input
Interface EEPROM
φ 8k x 8
J6 2/U26

Real-Time 5 V Regulator Power Supply

Clock φ
2/U16 U36 J3 +8.5V

ESK00052

Figure E-1: Microprocessor Module Block Diagram

130
Version 2.50 I.L. 40-201.81

FFFFH

F000H
4k Memory Mapped I/0
4k Dual Port RAM (2k x 16)
E
E000H 8k DB2 8k DB5
(4k x 16) (4k x 16)
8k DB1 8k DB4

DATA MEMORY
C000H
(4k x 16) (4k x 16)
8k DB0 8k DB3
A000H
(4k x 16) (4k x 16)

8000H 8k Permanent RAM (4k x 16)

6000H 8k EEPROM (8k x 8)

4000H
64k EPROM Program Memory
(32k x 16)
100H
80C196 special Function Registers
0H ESK00053

Figure E-2: REL 350 Processor 1 Memory Map

FFFFH

4k Memory Mapped I/0

F000H

Dual Port RAM

(2k x 16)
4k
E000H
RAM
(4k x 16)
8k
C000H
Program Memory (EPROM)
48k
100H
80C196 Internal
Register File
0H

ESK00054

Figure E-3: REL 350 Processor 2 Memory Map

131
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I.L. 40-201.81
Sub 6
1611C22

Version 2.50
Sheet 3 of 3

Figure E-4: REL 350 Microprocessor Module Component Location Diagram

Version 2.50 I.L. 40-201.81

Sub 1
1612C18
Sheet 1 of 7

Figure E-5a: REL 350 Microprocessor Module Schematic

133
134

I.L. 40-201.81
Sub 1

Version 2.50
1612C18
Sheet 2 of 7

Figure E-5b: REL 350 Microprocessor Module Schematic

Version 2.50 I.L. 40-201.81

Sub 1
1612C18
Sheet 3 of 7

Figure E-5c: REL 350 Microprocessor Module Schematic

135
136

I.L. 40-201.81
Version 2.50
Sub 1
1612C18
Sheet 4 of 7
Figure E-5d: REL 350 Microprocessor Module Schematic
 Version 2.50
Sub 1

I.L. 40-201.81
1612C18
Sheet 5 of 7
137

Figure E-5e: REL 350 Microprocessor Module Schematic

E
138

I.L. 40-201.81
Sub 1
1612C18

Version 2.50
Sheet 6 of 7

Figure E-5f: REL 350 Microprocessor Module Schematic

 Version 2.50
Sub 1

I.L. 40-201.81
1612C18
Sheet 7 of 7

Figure E-5g: REL 350 Microprocessor Module Schematic

139

E
 Notes

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Version 2.50 I.L. 40-201.81

DISPLAY MODULE

Schematic - - - - - - - - - - - - - - - - - - - - 1608C93
F
Component Location Diagram - - - - - - 1498B40

The Display module contains a blue vacuum fluorescent alphanumeric display, with 4 charac-
ters in the function field and 4 characters in the value field; it also includes 7 LEDs, 7 push-but-
ton switches and 5 test points (See Figure, F-1, on page 142, and Schematic). The 7 push-button
switches (SW1 thru SW7) are used to activate the following functions on the front panel:

• Display Select (the LEDs, to the right of this push-button, indicate the selected function)
• Reset (the targets selected)
• Function Raise (move to the following function)
• Function Lower (move to the previous function)
• Value Raise (move to the next higher value)
• Value Lower (move to the next lower value)
• Enter (the value that has been selected for upper contact testing)

The Microprocessor module scans these switches once every cycle while in the “background”
mode, where it looks for phase current or phase voltage disturbances. When a phase distur-
bance is detected, the relay enters the “fault” mode. While scanning, the Microprocessor mod-
ule updates the Display module via the ICs (U1, U2, U3 and U4). The display will be blocked
momentarily once every minute due to the self-check function. This is for readout check and
will not interrupt the relay protection function. The Microprocessor also illuminates some LEDs
when the Display Select Switch is depressed. IC (U5) controls the LEDs, which are as follows
(See Section 1.3.6 , on page 3):

• Relay In Service (DS2)

• Settings (DS3)
• V/I/Angle (DS4)
• Last Fault (DS5)
• Previous Fault (DS6)
• Value Accepted (DS7)
• Test (DS8)

Test points (TP1 thru TP5) are used to monitor dc voltages:

• -24V (TP1)
• + 5V (TP2)
• -12V (TP3)
• +12V (TP4)
• Common (TP5)

141
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I.L. 40-201.81
Version 2.50
Sub 4
1498B40
Sheet 7 of 7

Figure F-1: REL350 Display Module Component Location Diagram

 Version 2.50
I.L. 40-201.81
Sub 3
1608C93
143

Figure F-2: REL350 Display Module Schematic

F
 Notes

144
Version 2.50 I.L. 40-201.81

POWER SUPPLY MODULE

Schematic - - - - - - - - - - - - - - - - - - - - 1356D56
G
Component Location Diagram - - - - - - 1611C24

The Power Supply Module consists of two identical power supplies whose outputs are auction-
eered through diodes to provide an uninterrupted power source, in the event one of the supplies
fails. The following description is provided for one supply (both supplies are identical).

The input power from terminals J7/26AC and 28AC is applied to fuses F1 and F2, rectifier
bridge BR1 and filter network R1, C1. Therefore, both dc and ac operation are possible.

Switching transistor Q2 is turned on and off to provide current for the flywheel inductors L1 and
L2 which feed the charge capacitor C11. When transistor Q2 is turned off, the flywheel current
continues through diode D5.

The dc voltage, developed across C11, is applied through resistor divider R7, R17 and R14 to
the pulse width modulator U1, pin 1. In U1, this voltage is compared with the voltage on pin 2,
which is derived from an internal Zener reference voltage on pin 16. The voltage difference be-
tween pins 1 and 2 controls the high or low duty cycle (or pulse width) of the ac waveform on
pins 12 and 13. The frequency of this ac signal is determined by R13 and C7. This ac signal is
amplified by transistor Q4 which controls the gate of switching transistor Q2 thru driver Q3; thus
completing the feedback loop which controls the voltage on capacitor C11.

Chip U1 is powered from internal element VC1 (12 volt). On powerup, VC1, is initially generated
from voltage across Zener diode Z2, driving the emitter follower Q1. VC1 also initially powers
transistors Q3 and Q4 thru diode D1. When the voltage across C11 gradually builds up, and
overtakes VC1, transistors Q3 and Q4 will be powered through R16 and D2. When the voltage
across C11 reaches about 75% of its final value, the current through R3 will back bias Q1
through diode D4, turning off Q1 and supplying VC1 through R3 from the voltage across C11.
This arrangement minimizes the power dissipation on Q1. For the same reason, it is extremely
important to limit the current from P12V (Terminal J7 14AC) to 10mA. Otherwise, the turn off of
Q1 may be hampered, and serious overheating will result. The gradual buildup of voltage
across C11 is controlled by capacitor C3.

Overload protection is provided by sense resistors R18, R19 and R20 through filter R5 and C6
to control input (pin 5) of chip, U1.

The primary dc voltage (PRDC 1) across C11 is converted to a regulated ac voltage, with the
aid of U2 and U3 devices that alternately control switching transistors Q5 and Q6, thereby pro-
viding power to the primary winding of transformer T1. Protection against accidental shorts is
provided by sensing resistors R28, R29 and R30, through filter R27 and C12, to control pin 4
of U2.

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I.L. 40-201.81 Version 2.50

The secondary winding of transformer T1, on terminals 6, 7 and 10 provides:

• +12 Vdc thru full wave rectifier D17 and D18 and auctioneering diode D21 (to terminal J2/
28A, 28C)
• -12 Vdc thru full wave rectifier D15 and D11 and auctioneering diode D14 (to terminal J2/
30A, 30C)
• +24 Vdc thru voltage doubler circuit C16, C19, D23, C18 and auctioneering diode D24 (to
terminal J7/8A, 8C)
• -24 Vdc thru voltage doubler circuit C17, D20, D25, C19 and auctioneering diode D22 (to ter-
minal J7/6A, 6C)

The secondary winding of transformer T1, on terminals 8 and 9 provides:

• +8.5 Vdc thru full wave bridge rectifier D10, D11, D12, D13 and auctioneering diode D9 (to
terminal J2/20A, 20C, 22A and 22C) (also to terminal J7/10A, 10C)

The secondary winding of transformer T1, on terminals 4 and 5 provides:

• 6.5 VacREL 350 for the electroluminescent display (to terminals J2/4A, 4C and 6A, 6C)

The 6.5 Vac is switched by relay K1, since it is impossible to auctioneer two nonsynchronized
ac voltages. Relay K1 is controlled by status monitor U7. The 6.5 Vac output is biased at -20
Vdc to satisfy the requirements of the electroluminescent display.

The status monitor U7 checks the health of each power supply by monitoring the +8.5 Vdc out-
puts of each supply. The status outputs are normally low, thus, a high output means a failed
power supply (Terminal J2/12A, 12C).

Each power supply is capable of delivering a total output of 35 W power, distributed among its
six load outputs.

Due to the maximum diode rating of 1A, no individual load should exceed a current drain of 1A.

ADJUSTMENTS
To achieve optimum performance, the following adjustments are required

Adjust Power Supply To Achieve On Comments

R17 1 26.00Vdc PRDC1 (Term. J7/16AC) G01

R17 1 70.00Vdc PRDC1 (Term. J7/16AC) G02 and G03

R50 2 26.00Vdc PRDC2 (Term. J7/18AC) G01

R50 2 70.00Vdc PRDC2 (Term. J7/18AC) G02 and G03

NOTE: For proper operation of the auctioneered outputs, PRDC1 and PRDC2 shoud
have identical vaues.

146
 Version 2.50
I.L. 40-201.81
Sub 1
1612C63
Sheet 12
147

Figure G-1: REL 350 Power Supply PC Board

G
Version 2.50 I.L. 40-201.81

ANALOG INPUT MODULE

Schematic - - - - - - - - - - - - - - - - - - - - 1612C20
H
Component Location diagram - - - - - - 1611C23

The block diagram of this module is shown in Figure H-1, on page 150. The module interfaces
with the voltage and current transformers that are mounted on the Backplane module. These
transformers provide the following ac values: VA, VB, VC, IA, IB, IC. The values are applied to
active third-order Butterworth antialiasing filters (U8 thru U13), with a cut-off frequency deter-
mined by the Nyquist criterion and the system sampling rate. Values IA, IB, IC are summed to
produce 3I0 in U5. All seven values (VA, VB, VC, IA, IB, IC, 3I0) are applied to the multiplexer
(U5), whose output connects to the A/D converter (U15) via autoranging circuitry.

The A/D converter is a 12 bit plus sign with an internal sample-and-hold amplifier. Additionally,
on request, the A/D converter executes a self-calibrating routine that corrects zero errors and,
also, full-scale and linearity errors. Device U16 provides stable, precision 5.000 V reference to
the A/D converter. The autoranging circuitry provides 16 bits of dynamic range needed to mea-
sure high current values during power system faults.

The 13 bit output is available from the A/D converter (12 bit plus sign). To achieve a 16-bit range
requires a multiplication of the A/D converter output (or gain) by eight.

If the input value satisfies the expression:

+ 0.5 V < VIN < - 0.5 V

then the comparators (U3.1 and U3.2) select the Y0 - Y) switch of U4, and multiplication by 8
takes place in the Microprocessor software.

For the range:

- 0.5 V < IIN < + 0.5 V

the (Y1 - Y) path of U4 is selected (by U3.1 and U3.2), connecting the output of U2 (analog input
with a gain of 8) to the A/D converter, performing a multiplication by 8 in the analog domain.

NOTE: Adjust potentiometer (R59) for 5.000V at the test point (TP2) to ground.

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I.L. 40-201.51 Version 2.50

MUX.
J2 J1
Select
VA F
1/U13

VB F
1/U12

µP Module
VC F
1/U11
MUX Control
Yo 3/U4
IA F

To
2/U10 Y

A/D
IB Y1
F Data
2/U9

IC 4/U15
F X8
2/U8 3/U2
Antialiasing
- 3I0
Filters
2/U7 REF
To Voltage and Current
Transformers via > + .5 V 4/U16
Interconnect Module Range Select
Comp

3/U5 3/U3.2

< - .5 V
Comp
3/U3.1

Autoranging Circuits

ESK00055

Figure H-1: Analog Input Module Block Diagram

150
 Version 2.50
Sub 4

I.L. 40-201.81
1611C23
Sheet 3 of 3

Figure H-2: Analog Input Module Component Location Diagram

151

H
I.L. 40-201.51 Version 2.50

Sub 2
1612C20
Sheet 1 of 4

Figure H-3a: Analog Input Module Schematic

152
Version 2.50 I.L. 40-201.81

Sub 2
1612C20
Sheet 2 of 4

Figure H-3b: Analog Input Module Schematic

153
I.L. 40-201.51 Version 2.50

Sub 2
1612C20
Sheet 3 of 4
Figure H-3c: Analog Input Module Schematic

154
Version 2.50 I.L. 40-201.81

Sub 2
1612C20
Sheet 4 of 4

Figure H-3d: Analog Input Module Schematic

155
 Notes

156
Version 2.50 I.L. 40-201.81

MODEM MODULE

Schematic - - - - - - - - - - - - - - - - - - - - 1612C73
I
Component Location Drawing - - - - - - 1612C01

1.1 ARCHITECTURE

The block diagram of this module is shown in Figure I-1, page 162.

1.2 CPU, I/O AND PROGRAM MEMORY

The CPU is a TMS320C25 Digital Signal Processor (U24). It functions as a high speed control
microprocessor. Its purpose is to control all functions of the Modem module via software instruc-
tions. The clock is a crystal (Y1) which operates at 18 MHz, but the CPU internally divides this
by four, so its instruction cycle clock is 4.5 MHz (single cycle instructions execute in 222 nano-
seconds).

U1 and U2 are high-speed EPROMS that contain the program for the CPU. Each EPROM is 8
bits wide, but the two together supply 16 bit instructions, which are needed by the 16 bit CPU.
U1 supplies the least significant 8 bits (D0 thru D7); U2 supplies the most significant 8 bits (D8
thru D15). These EPROMS are addressed by CPU A0 through A11, which map program code
into the first 4K of CPU program memory.

When the CPU fetches an instruction from the EPROMS, it drives PS* and STRB* low and it
drives R/W* high; OR gates then enable the EPROM CE* inputs, and EPROM drive the CPU
data bus.

The CPU has three address mapping modes. All RAM is within the CPU IC and this RAM has
its own address map separate from program and I/O memory maps. As mentioned above, pro-
gram memory is in external EPROMS which are mapped to the lowest 4K addresses. I/O and
program memory share the lowest eight address lines.

The CPU communicates with the Modem, the inputs and outputs from/to the Microprocessor
module, and various on-card functions via I/O operations. An I/O bus operation takes place
when IS* goes low; R/W* controls the direction of data flow and the STRB* strobes the data at
the appropriate time of the I/O instruction cycle. Some I/O devices (that the CPU communicates
with) are too slow to operate at full CPU speed. Therefore, one wait state is generated during
each I/O operation. This is done by ORing IS* and MISC* to the READY input.

The 24 line-programmable peripheral interface I/O devices need a separate RD* and WR* line;
U20.1 thru U20.4 and U21.1 decode the CPU IS*, STRB* and R/W* lines so that an RD* will be
asserted when the CPU wants to strobe input data. WR* will be asserted when the CPU wants
to strobe output data.

I/O port addressing is accomplished by decoder U19. When IS* is low, then the CPU address
lines (A0 thru A2) are decoded to one out of eight I/O device select lines. I/O ports 0 and 7 are
used to strobe the watchdog timer (covered later). I/O port 1 communicates with 24 line-

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I.L. 40-201.81 Version 2.50

programmable peripheral interface U6; I / 0 port 0 communicates with 24 line-programma-

ble peripheral interface U5, and I/O ports 2,3 and 4 communicate with the 9600 bps Modem.

NOTE: * This is a “Low True Signal”

1.3 WATCHDOG TIMER

The purpose of the watchdog timer is to reset the CPU and the 9600 bps Modem if the micro-
processor program crashes. It does this within 1 millisecond of a program crash. At least once
each 500 microseconds, a properly running program will first access I/O port 0 then port 7.The
port 0 access will clock dual D flip-flop U16.1 thru U18.1. This will cause Q of U16.1 and D of
U16.2 to go high. A port 7 access will clock U16.2 through U18.2; Q of U16.2 will then go high.
After a non-critical couple of microseconds, controlled by R1 and C1, the output of U17.1 will
go low, which will reset both flip-flops of U16; Q of U16.2 will go low; then, after a couple of mi-
croseconds, the output of U17.1 will return to the normal high state.

When 17.1 goes low, it resets counter U22 thru U17.4; U22 is a 14 stage ripple counter driven
from the CPU at 4.5 MHz clock output. If the port 0/port 7 access sequence takes place fre-
quently enough, then U22 will be reset before its Q output can go high. If the program crashes
and the port access sequence stops, then Q12 will go high in 455 microseconds, Q13 in 910
microseconds and Q14 in 1820 microseconds. P4 is factory set to one of these Q outputs.

A Q output from U22 will cause inverter U18.3 to rapidly discharge C2. Prior to that, one input
of U17.2 was low, so U17.2 was not resetting the CPU or resetting U22. Also, one input of
U17.2 is low when the U22Q output is high, which allows enough time for full discharge of C2.
When the Q output of U22 returns low, the output of U17.2 will go low. This will reset the CPU,
the Modem and U22 through U17. It will also apply a MRESET* to pin 22C of P3 to notify the
Microprocessor module of a reset.

1.4 ADDRESSING THE I/O DEVICES

CPU data busses are buffered from I/O data and address busses, by U23 and U15, respective-
ly. The lower 8 data bits are bi-directionally buffered by U23 (U23 is only active during an I/O
operation). Its OE* line is driven by CPU IS*. The CPU R/W* line connects to U23 DIR to control
the direction in which I/O data moves.

The CPU communicates with three I/O devices:

• Modem (Rockwell R96DP)

• Programmable Peripheral Interface U5 (82C55) that controls the Rockwell Modem
• PIP U6 (82C55) that sends/receives data to/from the Microprocessor

The CPU must first set the address lines of the I/O device that it will access. U15 latches data
on CPU data lines D8 through D11 when CPU output is sent to I/O port 5. This sets 82C55 ad-
dress lines A0 and A1 as well as Modem module address lines RS0 thru RS3. The I/O device
address remains at the Q outputs of U15 until changed by another port 5 output instruction.
Therefore, to communicate with one of the three I/O devices, the CPU must first set an address
via an output port 5 instruction (D8 thru D11 is the address), then do a port input or port output
operation to the device (D0 thru D7) to transfer the data.

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1.5 MODEM INTERFACE

A detailed description of the Modem (Rockwell R96DP) may be found in the following docu-
ments:
I
• “Communications Products Data Book”
• “Quality of Received Data for Signal Processor-Based Modems”
• “Modem Interface Specifications”
• “Interface Guide, R96 DP Modem Functional Characteristics”

The Modem operates in the 9600 bps, ITU V.29 mode, summarized as follows:

• Carrier Frequency is 1700 Hz

• The data stream to be transmitted, in 6 bit frames (as shown in 8. Serial Data Protocol) at
9600 bps, is divided into groups of four consecutive data bits (quadbits). The first bit (Q1) is
used to determine the signal element amplitude to be transmitted. The second (Q2), third
(Q3) and fourth (Q4) bits are encoded as a phase change relative to the phase of the imme-
diately preceding element (see Table I-1, page 161). The relative amplitude of the transmit-
ted signal is determined by the first bit (Q1) of the quad bit, and by the absolute phase of the
signal element (see Table I-2, page 161). The absolute phase diagram of transmitted signal
elements, at 9600 bps, is shown in Figure I-2, page 163. The quad bits are decoded, at the
receiver, and the data bits are reassembled in the correct order.

The Modem is controlled and read through a number of addressable registers. The CPU sends
data to the Modem registers to execute commands from the Microprocessor module. The CPU
also monitors Modem registers to determine the quality of the received signal.

In order to communicate with the Modem registers, the CPU first sets the RS0 thru RS3 ad-
dresses by doing an output to port 5. The CPU then does an input or an output to port 2, 3 or
4 to activate Modem chip select line CS0*, CS1* or CS2*, respectively. An RD* at the output
of U20.3 is inverted by U3.2 to be compatible with the Modem READ line.

The Modem’s request RTS* input is controlled by U5 PB3. This turns the transmitted signal on/
off. The Modem RLSD* output is active if the received signal is detected. It is monitored by U5
PA3. The Modem is supplied by +5V, +12V and -12V.

A small test socket (PO2) on the PC board will accept a cable from the eye pattern generator
board. The eye pattern generator is only needed for factory testing.

Modem TXA and RXA are transmitter tone output and receiver tone input lines, respectively.
TXA is 600 ohms, but RXA is high impedance and is terminated by R6. These lines appear at
the REL 350 interface connector.

The R96DP serial input and output lines (RXD and TXD) transfer data from/to the CPU via U5.
Port A of U5 is configured for input to the CPU and port B is output from the CPU. Port A reads
Modem RXD, transmit and receive bit and baud clocks, CTS* and RLSD*. Port B drives Modem
TXD, RTS* and POR (Modem reset line). Port B also resets the Modem interrupt flip-flops and
forces a MRESET* to the REL 350 through U18.4.

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I.L. 40-201.81 Version 2.50

The Modem transmit clock (TDCLK) interrupts the CPU when it is time to load a new bit to TXD.
It does this by clocking D flip-flop U26.1 through inverter U3.4. The Q* output of U26.1 then in-
terrupts CPU INT1*. The transmit clock interrupt handler (software) will then reset U26.1. The
Modem receive clock (RDCLK) interrupts the CPU when it is time to read a new bit at RXD. It
does this by clocking D flip-flop U26.2. The Q* output of U26.2 then interrupts CPU INTO*. The
receive clock interrupt handler (software) will then reset U26.2.

1.6 DIGITAL INTERFACE TO MICROPROCESSOR MODULE

The Digital Interface (82C55, U6) feeds data to the Microprocessor module and receives data
from the Microprocessor module. The device is programmed for output on port A and input on
port B. The lower nibble of port C is input and the upper nibble of port C is output. Data OD0
through OD7, coming from the microprocessor, drives port B of U6. The CPU can read the data
anytime by inputting from that port. However, the microprocessor can force a read by pulsing
the DATAVAL line. This clocks D flip-flop U9.1. The Q* output goes low and activates CPU in-
terrupt INT2*. After the CPU recognizes the interrupt, it will pulse U6, PC4 low which will reset
U9.1 and remove the interrupt.

OC0 and OC1 are control lines from the microprocessor. They are read by the CPU when it
inputs from the lower four bits of U13, port C. OC0 indicates if OD0 through OD7 is relay data
or setting up information. OC0 will be checked by the CPU whenever a DATAVAL strobe is de-
tected. OC1 controls the output latch (U7 or U8) that will drive data lines ID0 through ID7 going
to the microprocessor. The eight output bits come from U6, port A. This octet can either be relay
data or can be signal-to-noise ratio. Relay data is latched into U8 by pulsing U6, PC7. S / N
data is latched into U7 by pulsing U6, PC6. If OC1 is low, then U8 outputs are enabled. If OC1
is high, then U7 outputs are instead enabled. In this way, the microprocessor can select which
type of data to read without interrupting the DSP CPU.

PINT will be pulsed high when appropriate (controlled by software). This is done by the CPU
pulsing U6, PC5 high. MRESET* is pulled low when the CPU reset line is forced low or when
software drives U5 port B5 high.

1.7 TONE SIGNAL LEVEL DETECTORS

The Modem transmitter output is amplified by U10.1 and rectified by the linear operational rec-
tifier consisting of U10.2, U10.3 and associated components. This amplifier/rectifier will output
+5.0 Vdc at TXCHL for a 0 dBm Modem output. The dc output is approximately proportional to
Modem tone output voltage level below 0 dBm. The rectified output is filtered by C37.

Modem receive input is amplified by U11.2 and rectified by the linear operational rectifier, con-
sisting of U11.1, U10.4 and associated components. This amplifier/rectifier will output +5.0 Vdc
at RXCHL for a 0 dBm Modem input. The dc output is approximately proportional to Modem
tone input voltage level below 0 dBm.

1.7.1 Serial Data Protocol

The serial data format is shown in Table I-3, on page 161.

The six bits (U, V, W, X, Y and Z) define data frame as follows:

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Bit

V
Definition

Odd Parity

1 for special codes

I
0 for phase comparison codes

W,X,Y,Z IF V = 0
Phase comparison code
W - Phase A current above IPKY if 1
X - Phase B current above IPKY if 1
Y - Phase C current above IPKY if 1
Z - Ground current above IGKY if 1
IF V = 1
Guard 1, Guard 2, Open BKR as shown in Table I-3

Table I-1 Tab le I-3

SECOND, THIRD AND FOURTH DATA BITS SERIAL DATA FORMAT
DETERMINE PHASE CHANGE
U V W X Y Z
Phase Change * S0 1 0 0 0 0 0
Q2 Q3 Q4 (Degrees) S1 0 0 0 0 0 1
S2 0 0 0 0 1 0
0 0 1 0
S3 1 0 0 0 1 1
0 0 0 45
S4 0 0 0 1 0 0
0 1 0 90
S5 1 0 0 1 0 1
0 1 1 135
S6 1 0 0 1 1 0
1 1 1 180
S7 0 0 0 1 1 1
1 1 0 225
S8 0 0 1 0 0 0
1 0 0 270
S9 1 0 1 0 0 1
1 0 1 315
S10 1 0 1 0 1 0
* The phase change is the actual on-line S11 0 0 1 0 1 1
phase shift in the transition region from S12 1 0 1 1 0 0
the center of one signaling element to the S13 0 0 1 1 0 1
center of the following signalling element. S14 0 0 1 1 1 0
S15 1 0 1 1 1 1
GUARD1 1 1 0 0 0 1
Table I-2 GUARD2 0 1 0 0 0 0
FIRST DATA BIT DETERMINES AMPLITUDE OPBKR 0 1 1 0 0 1

U Parity (Odd)
Absolute Phase Relative Signal V Special Code (Guard, Open Breaker)
(Degrees) Q1 Element Amplitude W Phase A
X Phase B
0 3 Y Phase c
Z Ground
0, 90, 180, 270 1 5
0 √2

45, 135, 225, 315 1 3√2

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I/O
ADDR 80C55
& PPI
DATA
DSP BUFFER
EPROM
U15,23
CPU U1, 2 U6

To Microprocessor Module
U24
80C55 R96D
PPI Modem
Watchdog Timer

U16, 17, 18, 22 U5 U25

U10.1, 10.2, 10.3

0-5V
TX Level

U11.1, U11.2, U10.4

0-5V

To Communication Channel
RX Level

TX Interconnect Module
via

RX

ESK00056

Figure I-1: REL 350 Modem Block Diagram

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Version 2.50 I.L. 40-201.81

I
90°

135° 45°

3
3√ 2

1 √2

180° 0° Absolute
1 3 5

225° 315°

270°

ESK00057

Figure I-2: Modulation Diagram at 9600 bps

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1612C01

Figure I-3: REL 350 Modem Component Location Diagram

 Version 2.50
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1612C73
Page 1 of 3

I.L. 40-201.81
Figure I-4a: REL 350 Modem Schematic
165

I
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Page 2 of 3

Version 2.50
Figure I-4b: REL 350 Modem Schematic
 Version 2.50
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1612C73
167

Page 3 of 3

Figure I-4c: REL 350 Modem Schematic

I
 Notes

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CODEC MODULE

Schematic - - - - - - - - - - - - - - - - - - - - 1615C34
J
Component Location diagram - - - - - - 1615C33

1.8 Architecture

The block diagram is shown in Figure J-1 below.

1.9 Circuit Description

1.9.1 CPU, Program Memory and I/O

U2 is the TMS320C25 DSP CPU. It functions as a high speed control microprocessor. Clock is
crystal Y1 which operates at 20 MHz, but the CPU internally divides this by four so its instruction
cycle clock is 5.0 MHz (single cycle instructions execute in 200 nanoseconds).

U3 and U4 are high-speed EPROMS that contain the program for the CPU. Each EPROM is 8
bits wide, but the two together supply 16 bit instructions which are needed by the 16 bit CPU.
U4 supplies the least significant 8 bits of an instruction (D0 through D7) and U3 the most sig-
nificant 8 bits (D8 through D15). These EPROMS are addressed by CPU A0 through A11 which
map program code into the first 4K of CPU program memory.

The CPU has three address mapping modes. All RAM is within the CPU IC and this RAM has
its own address map separate from program and I/O memory maps. I/O and program memory
share the lowest sixteen addresses.



Parallel
COUNTER/ 80C55 Interface
DSP EPROM TIMER PPI to
Microprocessor


CPU U3,4 Module
U6 U7

U2

WATCHDOG
TIMER EPLD
U5 Serial
TX  Data
RX  To/From
U1  DCI Module
Figure J-1: Block Diagram

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I.L. 40-201.81 Version 2.50

The CPU uses I/O operations to communicate data from/to the REL 350, EPDL functions and
a programmable counter/timer. an I/O bus operation takes place when IS* goes low. R/W* con-
trols direction of data flow and STRB* strobes the data at the appropriate time of the I/O in-
struction cycle. Some I/O devices that the CPU communicates with are too slow to operate
at full CPU speed. Therefore, one wait state is generated during each I/O operation. This is
done by the EPLD ORing IS* and REL 350* to the READY input.

The 24 line programmable peripheral interface I/O device U7 and Programmable counter/timer
U6 provide parallel interface to microprocessor module.

1.9.2 Watchdog Timer

Purpose of the watchdog timer is to reset the CPU if the microprocessor program crashes. It
does this within 1 millisecond. At least once each 500 microseconds, a properly running pro-
gram will first activate I/O address 0 then I/O address 12. This order will be decoded in the
EPLD which will in turn apply a reset pulse to ripple counter U5. If after approximately 1 ms the
reset pulse is not applied (program has crashed), then Q13 output of U5 will go high which will
reset the CPU and also apply MRESET* to the REL 350 via the EPLD (U1).

1.9.3 Interface to Microprocessor Module

82C55, U7 feeds data and receives data from the µP module.

1.9.4 56/64 kbps Serial Data Section

Parallel to serial data conversion, serial data encoding and decoding, clock recovery from the
received serial data and all other aspects of serial data transmission and reception are handled
in U1.

U1 is a programmable logic device (EPLD).

The two signals TX (Transmit Data) and RX (Receive Data) interface to Digital Communication
Interface module (DCI).

1.10 Serial Data Protocol

1.10.1 Data Rate

64 or 56 kb/sec (64,000 or 56,000 bits per second) selectable via REL 350 relay setting.

1.10.2 Data Encoding

Non-return to ZERO Inverted (NRZI). Binary “I” is encoded as a transition on the beginning of
a bit frame,. Binary “0” is encoded as no transition.

1.10.2.1 Message Structure (Data Frame)

Data Frame consists of 32 bits defined as follows:

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Bit 0

Bit 1
Sync bit. Toggles every frame. Is not protected by CRC. The alternating 101010 –
pattern will be detected as sync. J
Defines two purposes for bits 2 through 15. Only one purpose is defined at this time,
with bit 1 = 1.
Bits 2 - 5
Unit ID code.
Bits 6 - 11
This is the 6 bit REL 350 data code as shown in Table J-1, page 172.
Bits 12 - 14
These carry time delay information needed to calculate communication channel delay.
A delay calculation is performed once every 128 frames (64 msec at 64 kbs). Bit values
are:
111B = No “Leader” or “Follower” delay measurement action.
110B = “Leader” requests delay measurement.

Leader or follower replies:

000B = Internal delay < 100 us

001B = Internal delay between 100 and 200 µs
010B = Internal delay between 200 and 300 µs
011B = Internal delay between 300 and 400 µs
100B = Internal delay between 400 and 500 µs
101B = Internal delay between 500 and 600 µs
Bit 15
Unassigned. It is 0 for now.
Bit 16 - 31
A 16 bit Cyclic Redundancy Check (CRC) field using the CCITT polynomial:
X 16 + X12 + X5 + 1

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Table J-1
REL 350 DATA CODE FIELD (Bits 6 - 11 of Data Frame)

U V W X Y Z

S0 1 0 0 0 0 0
S1 0 0 0 0 0 1
S2 0 0 0 0 1 0
S3 1 0 0 0 1 1
S4 0 0 0 1 0 0
S5 1 0 0 1 0 1
S6 1 0 0 1 1 0
S7 0 0 0 1 1 1
S8 0 0 1 0 0 0
S9 1 0 1 0 0 1
S10 1 0 1 0 1 0
S11 0 0 1 0 1 1
S12 1 0 1 1 0 0
S13 0 0 1 1 0 1
S14 0 0 1 1 1 0
S15 1 0 1 1 1 1
GUARD1 1 1 0 0 0 1
GUARD2 0 1 0 0 0 0
OPBKR 0 1 1 0 0 1
TTRIP 1 1 0 1 1 1

U Parity (Odd)
V Special Code (Guard, Open Breaker, Transfer Trip)
W Phase A
X Phase B
Y Phase c
Z Ground

DATA FRAME

0 1 2 5 6 11 12 14 15 16 31

Unit ID Data Time 16 bit CRC

uvwxyz Delay
(See Table J-1) Info

Always 1
Always 0

Sync (alternates 101010……)

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Version 2.50
Figure J-3: REL 350 CODEC Module
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DIGITAL COMMUNICATION INTERFACE MODULE

Schematic - - - - - - - - - - - 1615C44, 1618C52, 1618C55

K
Component Location - - - - 1615C43, 1615C53, 1618C56

1.1 CIRCUIT DESCRIPTION

There are several options of the REL 350 Digital Communications interface.

• DCI Assy. 1614C98G01 - Fiber Optic option, 820 nm, ST connector, multi-mode cable*
• DCI Module assembly- - - - - - - - - - - - - - - - - - - - - - - - - - - - -1615C43G01
• DCI Module schematic diagram - - - - - - - - - - - - - - - - - - - - - - - - -1615C44
• DCI Assy. 1614C98G02 - 56/64 Kbps Direct Digital Option, Electrical STD RS422/RS485
Mechanical STD RS530. Connector J1 is a male DB-25 plug as required for Data Terminal
Equipment (DTE).
• DCI Module assembly- - - - - - - - - - - - - - - - - - - - - - - - - - - - -1615C43G02
• DCI Module schematic diagram - - - - - - - - - - - - - - - - - - - - - - - - -1615C44
• DCI Assy. 1614C98G06 - fiber Optic option, 1300nm, ST connector, single-mode cable,
short reach*
• Single-mode module assembly - - - - - - - - - - - - - - - - - - - - - -1618C53G01
• Single-mode module schematic diagram - - - - - - - - - - - - - - - - - -1618C52
• Optical module assembly - - - - - - - - - - - - - - - - - - - - - - - - - - 1618C5G01
• Optical module schematic diagram - - - - - - - - - - - - - - - - - - - - - 16118C55
• DCI Assy. 1614C98G07 - Fiber Optic option, 1300nm, ST connector, single-mode cable, me-
dium reach*
• Single-mode module assembly - - - - - - - - - - - - - - - - - - - - - -1618C53G02
• Single-mode module schematic diagram - - - - - - - - - - - - - - - - - -1618C52
• Optical module assembly - - - - - - - - - - - - - - - - - - - - - - - - - - 1618C5G02
• Optical module schematic diagram - - - - - - - - - - - - - - - - - - - - - 16118C55
• DCI Assy. 1614C98G08 - Fiber Optic option, 1300nm, ST connector, single-mode cable, me-
dium reach*
• Single-mode module assembly - - - - - - - - - - - - - - - - - - - - - -1618C53G03
• Single-mode module schematic diagram - - - - - - - - - - - - - - - - - -1618C52
• Optical module assembly - - - - - - - - - - - - - - - - - - - - - - - - - - 1618C5G03
• Optical module schematic diagram - - - - - - - - - - - - - - - - - - - - - 16118C55

These DCI Assemblies connect to the rear of the REL 350 relay system via 4 pin header P1.
The TX (P1.3) & RX (P1.4) signals, routed to the Codec module are TTL level output & input
signals respectively.

* See section 2.5, on page 12 for details

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Sub 2
Figure K-1: Internal Schematic 1615C44
(Direct Digital, Fiber Optic Multi-mode, 820 nm)

176
Version 2.50 I.L. 40-201.81

Sub 2
1615C43

Figure K-2: Component Location

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Version 2.50
1618C52

Figure K-3: Internal Schematic

(Direct Digital, Fiber Optic, Single-mode)
Version 2.50 I.L. 40-201.81

P2 P3

R2
R3
L3

R14
R15
U1
L2
C1

+
P1 B
C5

C E
R1

Q4

C10
R16

D1

C9

Sub 1
1615C53

Figure K-4: Component Location

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Figure K-5: Internal Schematic

(Direct Digital, Fiber Optic, Single-mode)
Version 2.50 I.L. 40-201.81

C2

LE1
LE2

C4

C1
C3

L2

C5
+
+ L1

P2 P3

Sub 1
1615C56

Figure K-6: Component Location

181
 Notes

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1.2 INTRODUCTION
ACCEPTANCE TESTS

L
The acceptance test of the relay verifies the operation of four subsystems.

• Analog Input
• Contact Input
• Relay Output
• Communication

Additionally, Phase Comparison functional tests (simulating internal faults) are performed.

1.3 EQUIPMENT NEEDED

Qty. Description

1 REL 350 Relay

1 Doble, Multi-amp or equivalent 3-Phase Test System

1.4 TEST SETUP

1.4.1 Current and voltage Inputs

Connect the Relay Test System to REL 350 Relay, per application diagram 2693F87 (see SYS-
TEM DIAGRAMS section, on page 213). Please note that the Relay Test System Simulates
Power System shown on 2693F87.

Do not leave fault currents with trip relays energized for long periods of time.
1.4.2 Power

Connect the primary and secondary dc power as shown on 2693F87. Consult the relay name-
plate for rated voltage.

NOTE: Before turning on dc power check jumper positions on the Contact Input and
Microprocessor modules. (See page 121 and page 125)

1.5 ANALOG INPUT AND FRONT PANEL METERING TEST

STEP 1
Turn on the primary and optional secondary dc input power if used. Make sure that the FREQ
setting matches the line frequency, and the RP setting is set to “NO” (Readout in secondary
values). The “Relay in Service” LED on the front panel should be lit.

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I.L. 40-201.81 Version 2.50

STEP 2
NOTE: All ac voltage & current phase angles in this document are referenced to
VA-G voltage (0 degrees). Positive angles LEAD VA-G, negative angles
LAG VA-G.
Fault impedance angles (FANG) are displayed as positive for inductive faults
and negative for capacitive.

Apply the following ac quantities to the relay:

V (volts) / Angle I (amps) / Angle

Va = 70 ∠0° Ia = 10 ∠-45°
Vb = 70 ∠-120° Ib = 10 ∠-165°
Vc = 70 ∠+120° Ic = 10 ∠+75°

Using the procedure described in Section 4.5.2, on page 54, read the following parameters:

VAG = 70 (VOLTS)
∠VAG = 0 (DEG.)
VBG = 70 (VOLTS)
∠VBG = -120 (DEG.)
VCG = 70 (VOLTS)
∠VCG = +120 (DEG.)
IA = 10.0 (AMPS)
∠IA = -45 (DEG.)
IB = 10.0 (AMPS)
∠IB = -165 (DEG.)
IC = 10.0 (AMPS)
∠IC = +75 (DEG.)

Verify all metered values to be ± 5% on magnitude and ± 2 degrees on phase angle.

1.6 CONTACT INPUT SUBSYSTEM TEST

Make sure that the input voltage selection jumpers on the contact input module 1611C28 (See
Figure 1-2, on page 7 in Section 1, for Module Placement and Figure D-1, on page 122, in
Appendix D for jumper location) correspond to the desired contact “wetting” voltage.

Apply the rated voltage across the terminals shown in the table below:

Using procedure described in Section 4.5.4.1, on page 55, verify proper response of the front
panel display to contact input status changes.

1.7 RELAY OUTPUT SUBSYSTEM TEST

Using the procedure described in Section 4.5.4.2, on page 56, verify operation of relay output
subsystem. The relay contact wiring is shown on Block Diagram 1617C46 and application di-
agram 2693F87 found in System Diagrams section of this I.L. Please note that the Failure
Alarm Relay (TB4, 5-6) has a normally closed contact.

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DTT Key
Description

STUB BUS
Terminal
Block

TB5
TB5
9
Terminal
+

11
-

10
12
HEX
Digit

1
2
L
Single-Pole Trip Override TB5 13 14 4
Target RESET TB5 7 8 8
52b A/52b (3PT) TB5 1 2 10
52b B / 52b (3PT) TB5 3 4 20
52b C / 52b (3PT) TB5 5 6 40

1.7 COMMUNICATION SUBSYSTEM TEST

1.7.1 9600 bps Audio Tone Option

Make the following test connection on the rear of the relay:

TB4-11 to TB4-13
TB4-12 to TB4-14

This connects the Communication XMT pair to RCV pair.

STEP 1
Make sure that 52b-A, 52-B, 52b-C contact inputs (TB-5 terminals 1-2, 3-4, & 5-6 respectively)
are de-energized.

Change the “OPBR” setting to “52B” to disable the open breaker code transmission. Change
the “ALDT” setting to “NO” since automatic delay time measurement is not possible with com-
munication channel in a “Loopback” configuration. Turn the dc supply connected to the
REL 350’s dc (Battery) inputs “off” for 1 second & then back “on” again to re-initialize the mo-
dem’s “ALDT” setting on power-up sequence.

Change the “XMTR” setting to “-1” dBm. Press the “DISPLAY SELECT” key on REL 350 front
panel several times to select the “VOLTS/AMPS/ANGLE” mode. Use the FUNCTION RAISE/
LOWER keys to display the “XMTR” monitoring function. The transmitter output level is mea-
sured via the “XMTR” monitoring function should read between +2 an -5 dBm.

Change the “XMTR” setting to “-11” dBm. The transmitter output level as measured via the
“XMTR” monitoring function should read between -8 and -15 dBm.

Change the “XMTR” setting back to “-1” dBm. Use the “CHRX” monitoring function for indication
of the Channel receiver line status, “CHRX” should read “GARD”.

STEP 2
Temporarily disconnect the XMT to RCV jumper TB4-11 to TB4-13. The display CHRX should
change to CHTB (Channel Trouble).

STEP 3
Reconnect TB4-11 to TB4-13. The display CHRX should return to GARD after a short time de-
lay.

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1.7.2 56/64 KPBS Digital Communication Option

Make following Loopback connections on digital Communication Interface on the rear of the
relay.

• Fiber Optic Version (820 nm)

Using 50/100 µm or larger Multi Mode Cable with ST connectors at each end, connect Fiber
Optic Transmitter to Fiber Optic Receiver.
• Fiber Optic Version (1300 nm)
Using 9/125 µm, Single Mode Cable with ST connectors at each end, connect Fiber Optic
Transmitter to Fiber Optic Receiver.
NOTE: For Medium and Long Reach Options (DCI assemblies G04 and G05) the Opti-
cal Power Attenuator must be used to limit the Receiver Input Power to maxi-
mum of -11 dBm to prevent receiver saturation.
• Direct Digital Version (RS422/RS530)
Connect Pin 2 to Pin 3 (TXA to RXA)
Connect Pin 14 to Pin 16 (TXB to RXB)

Pin placement on DB-25 connector used is as follows:

1
14 2
15
3
16
4

25
13

Step 1

Set: UNID = 0
KBPS = 64
XCLK = INT
LPBK = YES

Make sure that 52b-A, 52-B, 52b-C contact inputs (TB-5 terminals 1-2, 3-4, & 5-6 respectively
are de-energized.

Change the “OPBR” setting to “52B” to disable the open breaker code transmission. Change
the “ALDT” setting to “NO” since automatic delay time measurement is not possible with com-
munication channel in a “Loopback” configuration. Turn the dc supply connected to the
REL 350’s dc (Battery) inputs “off” for 1 second & then back “on” again to re-initialize the mo-
dem’s “ALDT” setting on power-up sequence.

The Monitoring Function CHRX (Received Line Status) should read GARD.

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STEP 2.
Disconnect above described Loopback Connections. The display CHRX should read CHTB
(Channel Trouble).

STEP 3.
Reconnect the Loopback Connection. The display CHRX should return to GARD after a short
time delay.

1.8 FUNCTIONAL TESTS – PHASE COMPARISON SYSTEM

1.8.1 9600 bps Audio Tone Option

The purpose of these tests is to test the proper operation of the segregated phase comparison
logic in the REL 350. Having followed all the steps in section 1. 7.1, on page 185, make sure
that the following test connections on the rear of the relay are made:

TB4-11 to TB4-13
TB4-12 to TB4-14

The REL 350 modem interface has nominal time delay of approximately 8.9 milliseconds. The
LDT can be set to 8.9 msec to simulate internal faults (local and remote currents in phase).

Make sure that GARD is the received signal and the following settings are made in addition to
settings specified in section 1.7.1:

1 FDAT = TRIP 9 RPKY = 3.0

2 TTYP = 3PT 10 PDIF = 1.0

3 IE = 0.20 11 LGKY = 2.0

4 IPL = 0.5 12 RGKY = 2.0

5 IPH = OUT 13 GDIF = 1.0

6 IGL = 0.5 14 ALDT = NO

7 IGH = OUT 15 LDT = 8.9

8 LPKY = 3.0

1.8.1.1 Internal Faults

The system should be using a channel delay time of 8.9 milliseconds.

Set LDT = 8.9

Apply all types of faults with currents greater than 4.0 amps to be sure the system trips. The
system should trip for all currents applied. For example, to simulate an AG fault, apply:

Ia = 4.0 amps
Ib = 0.0 amps
Ic = 0.0 amps

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NOTE: If the system has provisions for single pole tripping set TTYP = SPT and make
sure that the relaying system operates the corresponding trip relays (trip con-
tacts) for the different line to ground faults (AG, BG, and CG).

WARNING

The user should verify that Standing Relay Trip SRT = NO in the Test Mode Function (see
4.5.4) prior to putting the REL 350 in service.

1.8.2 56/64 kbs Digital Comm Option

The purpose of these tests is to test the proper operation of the segregated phase comparison
logic in the REL 350. Having followed all the steps in section 1. 7.2, on page 186, make sure
that the Loopback Connections are made.

The REL 350 CODEC interface has nominal time delay of approximately 1.6 milliseconds. The
LDT can be set to 1.6 msec to simulate internal faults (local and remote currents in phase).

Make sure that GARD is the received signal and the following settings are made in addition to
settings specified in section 1.7.2.

1 FDAT = TRIP 9 RPKY = 3.0

2 TTYP = 3PT 10 PDIF = 1.0

3 IE = 0.20 11 LGKY = 2.0

4 IPL = 0.5 12 RGKY = 2.0

5 IPH = OUT 13 GDIF = 1.0

6 IGL = 0.5 14 ALDT = NO

7 IGH = OUT 15 LDT = 1.6

8 LPKY = 3.0

1.8.2.1 Internal Faults

The system should be using a channel delay time of 1.6 milliseconds. Set LDT = 1.6.

Apply all types of faults with currents greater than 4.0 amps to be sure the system trips. The
system should trip for all currents applied. For example, to simulate an AG fault, apply:

Ia = 4.0 amps
Ib = 0.0 amps
Ic = 0.0 amps

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NOTE: If the system has provisions for single pole tripping set TTYP = SPT and
make sure that the relaying system operates the right trip relays (trip con-
tacts) for the different line to ground faults (AG, BG, and CG).

WARNING

The user should verify that Standing Relay Trip SRT = NO in the Test Mode Function (see
section 4.5.4, on page 55) prior to putting the REL 350 in service.

1.9 FUNCTIONAL TESTS – OPTIONAL BACKUP SYSTEM

For units that include the stepped distance backup system the following tests will functionally
test all the distance units provided.

Be sure that the connections recommended in section 8 are not in and the display shows CHTB
as the signal received. A channel trouble enables the backup system.

The following settings should be used:

PANG = 75 Z2P = 4.5

GANG = 75 T2P = 0.1

ZR = 3.0 Z2GF = 4.5

BKUP = IN Z2GR = 0.01

LOPB = NO T2G = 0.1

FDOP = IN Z3P = 7.0

FDOG = IN T3P = 1.0

DIRU = ZSEQ Z3GF = 7.0

IOM = 0.5 Z3GR = 0.01

TOG = BLK T3G = 1.0

1.9.1 Phase-to-ground Units

To calculate the apparent impedance seen by the relay the following formula applies:

Vxg
Zapp = ------------------------------------------------------------------
+ ZR ∠GANG-PANG
I X 2-------------------------------------------------------- -
3

where x is either phase a, b or c.

The above formula is rigorous and general. However, if a quick approximation of the current
required at different angles (Ø) is desired, the following formula applies:

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I.L. 40-201.81 Version 2.50

V XG
I = --------------------------------------------------------------------------------------
-
ZR – 1
Z 2GF cos ( PANG – φ ) 1 + ----------------
3

For forward Zone 2 trips follow the following table for currents and voltages applied and com-
pare the calculated impedance in the relay target data to the provided impedance in the table.
The displayed value should fall within ±5%. Also make sure that the trip times are within 100 to
132 milliseconds.

V I Z I Z

AG OR
Va = 30 ∠0˚ Ia = 4 ∠-75˚ Ia = 5.65 ∠-30˚
4.5 3.18
Vb = 69 ∠-120˚ Ib = 0˚ or 5.65 ∠ -120˚
Vc = 69 ∠+120˚ Ic = 0˚

BG OR
Va = 69 ∠0˚ Ia = 0˚ Ib = 5.65 ∠+120˚
4.5 3.18
Vb = 30 ∠-120˚ Ib = 4∠+165˚ or 5.65 ∠ +210˚
Vc = 69 ∠+120˚ Ic = 0˚

CG OR
Va = 69 ∠0˚ Ia = 0˚ Ic = 5.65 ∠0˚
4.5 3.18
Vb = 69 ∠-120˚ Ib = 0˚ or 5.65 ∠ 90˚
Vc = 30 ∠+120˚ Ic = 4∠+45˚

Zone 2 ground (Z2G) should operate in all of the above.

For reverse Zone 2 faults follow the next table:

V I Z

AG
Va = 30 ∠0˚ Ia = 8 ∠+105˚
No Trip
Vb = 69 ∠-120˚ Ib = 0˚
Vc = 69 ∠+120˚ Ic = 0˚

BG
Va = 69 ∠0˚ Ia = 0˚
No Trip
Vb = 30 ∠-120˚ Ib = 8∠-15˚
Vc = 69 ∠+120˚ Ic = 0˚

CG
Va = 69 ∠0˚ Ia = 0˚
No Trip
Vb = 69 ∠-120˚ Ib = 0˚
Vc = 30 ∠+120˚ Ic = 8∠-135˚

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Change the setting Z2RG = 4.5 and repeat the Z2 test:

V I Z
AG
Va = 30 ∠0˚ Ia = 4.0 ∠-30˚
4.5
Vb = 69 ∠-120˚ or 4.0 ∠-75˚
Vc = 69 ∠+120˚ or 4.0 ∠-120˚
BG
Va = 69 ∠0˚ Ib = 4.0 ∠+120˚
4.5
Vb = 30 ∠-120˚ or 4.0 ∠+165˚
Vc = 69 ∠+120˚ or 4.0 ∠+210˚
CG
Va = 69 ∠0˚ Ic = 4.0 ∠0˚
4.5
Vb = 69 ∠-120˚ or 4.0 ∠+45˚
Vc = 30 ∠+120˚ or 4.0 ∠-120˚

Zone 2 (Z2G) should operate for all the above faults.

For forward Zone 3 trips outside of Zone 2 trips, apply the following quantities. Check the
apparent impedance as well as the trip time. The trip time should be 1.0 ±5% seconds.

V I Z app
AG
Va = 25 ∠0 Ia = 3 ∠-75
Vb = 69 ∠-120 Ib = 0
Vc = 69 ∠+120 Ic = 0 5.0 ∠75
BG
Va = 69 ∠0 Ia = 0
Vb = 25 ∠-120 Ib = 3∠+165
Vc = 69 ∠+120 Ic = 0 5.0 ∠75
CG
Va = 69 ∠0 Ia = 0
Vb = 69 ∠-120 Ib = 0
Vc = 25 ∠+120 Ic = 3∠+45 5.0 ∠75

The following table tests external forward faults outside Zone 3 reach.

V I
AG
Va = 25 ∠0 Ia = 2 ∠-75
Vb = 69 ∠-120 Ib = 0
Vc = 69 ∠+120 Ic = 0
BG
Va = 69 ∠0 Ia = 0
Vb = 25 ∠-120 Ib = 2∠+165
Vc = 69 ∠+120 Ic = 0
CG
Va = 69 ∠0 Ia = 0
Vb = 69 ∠-120 Ib = 0
Vc = 25 ∠+120 Ic = 2∠+45

The system should not trip.

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The following are external reverse faults.

V I

AG
Va = 25 ∠0 Ia = 3.75 ∠+105
Vb = 69 ∠-120 Ib = 0
Vc = 69 ∠+120 Ic = 0

BG
Va = 69 ∠0 Ia = 0
Vb = 25 ∠-120 Ib = 3.75∠-15
Vc = 69 ∠+120 Ic = 0

CG
Va = 69 ∠0 Ia = 0
Vb = 69 ∠-120 Ib = 0
Vc = 25 ∠+120 Ic = 3.75∠-135

The system should not trip.

1.9.2 Phase-to-phase Unit

To calculate the apparent impedance seen by the relay for phase-to-phase faults the following
formula applies:

Vxy
Zapp = --------------
Ix – Iy

where x is phase a, b or c and y is the next lagging phase.

The above formula is rigorous and general. However, if a quick approximation of the current
required at different angles (Ø) is desired, the following formula applies:

V XY
I = --------------------------------------------------------
2 Z 2P ( cos ( Pang – φ

The phase-to-phase unit is totally directional. For forward Zone 2 trips the following quantities
should be applied:.

V I Z app

AB
Va = 17.3 ∠0 Ia = 3.7 ∠-45
4.05 ∠75
Vb = 17.3 ∠-120 Ib = 3.7 ∠+135
Vc = 69 ∠+120 Ic = 0

BC
Va = 69 ∠0 Ia = 0
4.05 ∠75
Vb = 17.3 ∠-120 Ib = 3.7 ∠-165
Vc = 17.3 ∠+120 Ic = 3.7 ∠+15

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CA
V

Va = 17.3 ∠0
Vb = 69 ∠-120
I

Ia = 3.7∠-105
Ib = 0
Z app

4.05 ∠75
L
Vc = 17.3 ∠+120 Ic = 3.7∠+75

Zone 2 Phase (Z2P) unit should operate for all of the above tests. The trip times should be
greater than 100 milliseconds.

For Zone 3 trips outside Zone 2 reach, the following quantities should be applied:

V I Z app

AB
Va = 35 ∠0 Ia = 5 ∠-45
6.12∠75
Vb = 35 ∠-120 Ib = 5∠+135
Vc = 69 ∠+120 Ic = 0

BC
Va = 69 ∠0 Ia = 0
6.12∠75
Vb = 35 ∠-120 Ib = 5∠-165
Vc = 35 ∠+120 Ic = 5∠+15

CA
Va = 35 ∠0 Ia = 5 ∠-105
6.16∠75
Vb = 69 ∠-120 Ib = 0
Vc = 35 ∠+120 Ic = 5∠+75

The REL 350 should trip and the tripping time should be 1.0 ±5% seconds. Zone 3 phase (Z3P)
unit should operate for all of the above tests.

For forward external faults apply the following quantities:

V I

AB
Va = 35 ∠0 Ia = 4 ∠-45
Vb = 35 ∠-120 Ib = 4∠+135
Vc = 69 ∠+120 Ic = 0

BC
Va = 69 ∠0 Ia = 0
Vb = 35 ∠-120 Ib = 4∠-165
Vc = 35 ∠+120 Ic = 4∠+15

CA
Va = 35 ∠0 Ia = 4∠-105
Vb = 69 ∠-120 Ib = 0
Vc = 35 ∠+120 Ic = 4∠+75

The REL 350 should not trip.

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The following quantities simulate reverse phase-to-phase faults:

V I

AB
Va = 35 ∠0 Ia = 4 ∠+135
Vb = 35 ∠-120 Ib = 4∠-45
Vc = 69 ∠+120 Ic = 0

BC
Va = 69 ∠0 Ia = 0
Vb = 35 ∠-120 Ib = 4∠+15
Vc = 35 ∠+120 Ic = 4∠-165

CA
Va = 35 ∠0 Ia = 4 ∠+75
Vb = 69 ∠-120 Ib = 0
Vc = 35 ∠+120 Ic = 4∠-105

The REL 350 should not trip.

WARNING

The user should verify that Standing Relay Trip SRT = NO in the Test Mode Function (See
Section 4.5.4, on page 55) prior to putting the REL 350 in service.

1.10 OUT OF STEP SYSTEM FUNCTIONAL TESTS

For systems equipped with OST logic the following settings may be used to check the OST logic
in REL 350:

PANG = 65 T2G = 0.1

GANG = 65 Z3P = 11.0
ZR = 3.0 T3P = .2
BKUP = OUT Z3GF = 11.0
LOPB = NO Z3GR = 0.01
FDOP = IN T3G = .2
FDOG = IN OST = WAYO
DIRU = ZSEQ OSB = BOTH
IOM = 0.5 RT = 2.0
TOG = BLK RU = 4.0
Z2P = 8.5 OST1 = 2
T2P = 0.1 OST2 = 3
Z2GF = 6.5 OST3 = 3
Z2GR = 0.01 OSOT = 100

The situation is described more accurately in the sketch of Figure 3-16, on page 47.

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NOTE: These tests are optional and require programing Computer Aided, Multi-
amp or Doble test equipment.

In the R-X diagram, the positions shown in Figure 3-16, on page 47, correspond to the fol-
lowing quantities:

V (Volts) I (Amps)

Va = 69 ∠0 Ia = 5 ∠-5
Vb = 69 ∠-120 Ib = 5∠-125
1 Vc = 69 ∠+120 Ic = 5∠+115

Va = 20 ∠0 Ia = 4.5 ∠-25
Vb = 20 ∠-120 Ib = 4.5∠-145
2 Vc = 20 ∠+120 Ic = 4.5∠+95

Va = 20 ∠0 Ia = 6 ∠-65
Vb = 20 ∠-120 Ib = 6∠+175
3 Vc = 20 ∠+120 Ic = 6∠+55

Va = 20 ∠0 Ia = 4 ∠-100
Vb = 20 ∠-120 Ib = 4∠+140
4 Vc = 20 ∠+120 Ic = 4∠+20

Va = 69 ∠0 Ia = 6.5 ∠-105
Vb = 69 ∠-120 Ib = 6.5∠+135
5 Vc = 69 ∠+120 Ic = 6.5∠+15

The apparent impedances seen by the relay in each of the above positions and the expected
operation of the inner (21 BI) and outer (21 BO) blinders are the following:

POS Z app 21 BI 41 BO

1 13.8 ∠5 No No

2 4.47 ∠25 No Yes

3 3.33 ∠65 Yes Yes

4 5.00 ∠100 No Yes

5 10.6 ∠105 No No

The following tests make sure that the transmitter and receiver are connected in the unit.

NOTE: Make sure that the loopback connections described in 1.7.1, page 185 and 1.7.2
on page 186 are made. Also, the metered value CHRX displayed should be
GARD.

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Test #1 indicates the sequence of positions in the RX diagram to be applied and the time in
cycles to hold the position and the action of the relay.

TEST #1
Trip OST on the Way Out

Pos Time Trip Action

1 60
2 5
3 20
4 5
5 60 50-67 ms after 2

The fault impedance measured should be 10.6 ∠105 ohms.

WARNING

The user should verify that Standing Relay Trip SRT = NO in the Test Mode Function (See
Section 4.5.4, on page 55) prior to putting the REL 350 in service.

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1.11 FUNCTIONAL TESTS - “ON-LOAD” PHASE COMPARISON SYSTEM

The object of the following procedure is to carry out “on load” end to end tests in order to dem-
onstrate that the protection system has been correctly installed. The minimum requirement for
load current is 0.2 x ct ratio. This procedure will provide a positive and negative check by sim-
ulating both internal and external primary fault conditions, using normal load current. Table L-
1 states the test sequence to be followed, where references to end “L” or “R” are shown fill in
the names of the substations concerned.

This test schedule has to be done at both ends of the circuit in turn.

As explained in Sections 3.4 and 5, the phase comparison process and transmission of phase
comparison information are activated by the Change Detector (CD).

During the normal load condition the CD is deasserted and both REL 350 relays are transmit-
ting (and receiving) the GUARD code over communication channel. Remember also that the
load current resembles external fault i.e. out of phase relationship of currents at both ends of
protected line. Therefore the following elements need to be simulated:

• Transmission of phase comparison information from the remote “R” relay.

This is accomplished by setting the relay in TEST mode (see step 6).

• Generation of Change Detector (CD) in the local “L” relay. This is performed
by application of voltage (step 8).

Please note that the setting CD = ∆V∆I must be used.

For the systems with no voltage inputs connected the steps 3 and 8 must be
disregarded and steps 3A and 8A must be used.

• Simulation of internal fault must be done by reversing the ct wiring (step 4).

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Table L-1:

Completed
Item On Load End to End Test Procedure
( ✓ )

The circuit should be on load with the ABB Type REL 350 protection
1 system normal but trip outputs disconnected to prevent circuit breaker
tripping.

Ensure that the circuit load current exceeds the applied “KEYER” settings
2 (LPKY, RPKY, LGKY & RGKY). If this is not the case, apply identical lower
settings to each relay, as appropriate for the actual load current.

At circuit end “L”:

Remove the A (red) phase VT input to the relay by withdrawing the appro-
3
priate isolating link.

Remove the B (yellow) phase ct input by opening the appropriate test

3a
switch.

Reverse wiring to A (red) phase ct input. Take care not to open circuit any
4
ct secondary circuits while on load.

At circuit end “R”:

5 Set the relay to “Test” mode and confirm the LED indication.

From the displayed sub-menu, select “TEST” to initiate the Phase Compar-
6 ison Test Enable signal thus causing the remote relay to transmit phase
comparison data.

At circuit end “L”:

By utilizing the relay “Volts/Amps/Angle” mode confirm that the status of

7
“CHRX” has changed from guard (GARD) to armed (ARM).

Replace the removed VT isolation link. This will cause the relay Voltage
8
Change Detector to pickup thus resulting in relay operation/trip output.

Replace the removed ct test switch. This will cause the change detector to
8a
pickup thus resulting in relay trip output operation.

Confirm that the relay operates and that the relay indications are correct.
9 Reset trip indications. Power down the relay and reenergize to clear SRT
(Standing Relay Trip). Check SRT = NO

At circuit end “R”:

Select the relay to normal by selecting from “TEST” mode to “Volts/Amps/

10
Angle” mode.

At circuit end “L”:

By utilizing the relay “Volts/Amps/Angle” mode confirm that the status of

11
“CHRX” has changed from armed (ARM) to guard (GARD).

Return the A (red) phase ct wiring to normal. Take care not to open circuit
12
any ct secondary circuits while on load.

Remove the A (red) phase VT input to the relay by withdrawing the appro-
13
priate isolating link.

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Table L-1: (Continued)

Completed
Item On Load End to End Test Procedure
( ✓ )

Remove the B (yellow) phase ct input by opening the appropriate test

13a
switch.

At circuit end “R”:

14 Set the relay to “Test” mode and confirm the LED indication.

From the displayed sub-menu, select “TEST” to initiate the Phase Compar-
15
ison Test Enable signal thus causing the remote relay to be “Armed”.

At circuit end “L”:

By utilizing the relay “Volts/Amps/Angle” mode confirm that the status of

16
“CHRX” has changed from guard (GARD) to armed (ARM).

Replace the removed VT isolation link and confirm that the relay does not
17
operate.

At circuit end “R”:

Select the relay to normal by re-selecting from “Test” mode to “Volts/Amps/

18
Angle” mode.

At circuit end “L”:

By utilizing the relay “Volts/Amps/Angle” mode confirm that the status of

19
“CHRX” has changed from armed (ARM) to guard (GARD).

Remove the B (yellow) phase VT input to the relay by withdrawing the

20
appropriate isolating link.

20a Remove the C (blue) phase ct input by opening the appropriate test switch.

Reverse wiring to B (yellow) phase ct input. Take care not to open circuit
21
any secondary circuits while on load.

At circuit end “R”:

22 Set the relay to “Test” mode and confirm the LED indication.

From the displayed sub-menu, select “TEST” to initiate the Phase Compar-
23
ison Test Enable signal thus causing the remote relay to be “armed”.

At circuit end “L”:

By utilizing the relay “Volts/Amps/Angle” mode confirm that the status of

24
“CHRX” has changed from guard (GARD) to armed (ARM).

Replace the removed VT isolation link. This will cause the relay Voltage
25
Change Detector to pickup thus resulting in relay operation/trip output.

Replace the removed ct test switch. This will cause the change detector to
25a
pickup thus resulting in relay trip output operation.

Confirm that the relay operates and that the relay indications are correct.
26 Then reset trip indications. Power down the relay and reenergize to clear
SRT (Standing Relay Trip). Check SRT = NO.

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Table L-1: (Continued)

Completed
Item On Load End to End Test Procedure
( ✓ )

At circuit end “R”:

Select the relay to normal by re-selecting from “Test” mode to “Volts/Amps/

27
Angle” mode.

At circuit end “L”:

By utilizing the relay “Volts/amps/Angle” mode confirm that the status of

28
“CHRX” has changed from armed (ARM) to guard (GARD).

Return B (yellow) phase ct wiring to normal. Take care not to open circuit
29
any ct secondary circuits while on load.

Remove the B (yellow) phase VT input to the relay by withdrawing the

30
appropriate isolating link.

30a Remove the C (blue) phase ct input by opening the appropriate test switch.

At circuit end “R”:

31 Set the relay to “Test” mode and confirm the LED indication.

From the displayed sub-menu, select “Test” to initiate the Phase Compari-
32
son Test Enable signal thus causing the remote relay to be “armed”.

At circuit end “L”:

By utilizing the relay “Metering Mode” confirm that the status of “CHRX”
33
has changed from guard (GARD) to armed (ARM).

Replace the removed VT isolation link and confirm that the relay does not
34
operate.

Replace the removed ct test switch. This will cause the change detector to
34a
pickup thus resulting in relay trip output operation.

At Circuit end “R”:

Select the relay to normal by re-selecting from “Test” mode to “Volts/Amps/

35
Angle” mode.

At circuit end “L”:

By utilizing the relay “Volts/Amps/Angle” mode confirm that the status of

36
“CHRX” has changed from armed (ARM) to guard (GARD).

Remove the C (blue) phase VT input to the relay by withdrawing the appro-
37
priate isolating link.

37a Remove the A (red) phase ct input by opening the appropriate test switch.

Reverse wiring to C (blue) phase ct input. Take care not to open circuit any
38
ct secondary circuits while on load.

At circuit end “R”:

39 Set the relay to “Test” mode and confirm the LED indication.

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Table L-1: (Continued)

Completed
Item On Load End to End Test Procedure
( ✓ )

From the displayed sub-menu, select “TEST” to initiate the Phase Compar-
40
ison Test Enable signal thus causing the remote relay to be “armed”.

At circuit end “L”:

By utilizing the relay “Volts/Amps/Angle” mode confirm that the status of

41
“CHRX” has changed from guard (GARD) to armed (ARM).

Replace the removed VT isolation link. This will cause the relay Voltage
42
Change Detector to pickup thus resulting in relay operation/trip output.

Replace the removed ct test switch. This will cause the change detector to
42a
pickup thus resulting in relay trip output operation.

Confirm that the relay operates and that the relay indications are correct.
43 Then reset trip indications. Power down the relay and reenergize to clear
SRT (Standing Relay Trip). Check SRT = NO.

At circuit end “R”:

Select the relay to normal by re-selecting from “Test” mode to “Volts/Amps/

44
Angle” mode.

At circuit end “L”:

By utilizing the relay “Volts/Amps/Angle” mode confirm that the status of

45
“CHRX” has changed from armed (ARM) to guard (GARD).

Return the C (blue) phase ct wiring to normal. Take care not to open circuit
46
any ct secondary circuits while on load.

Remove the C (blue) phase VT input to the relay by withdrawing the appro-
47
priate isolating link.

47a Remove the A (red) phase ct input by opening the appropriate test switch.

At circuit end “R”:

48 Set the relay to “Test” mode and confirm the LED indication.

From the displayed sub-menu, select “TEST” to initiate the Phase Compar-
49
ison Test Enable signal thus causing the remote relay to be “armed”.

At circuit and “L”:

By utilizing the relay “Volts/Amps/Angle” mode confirm that the status of

50
“CHRX” has changed from guard (GARD) to armed (ARM).

Replace the removed VT isolation link and confirm that the relay does not
51
operate.

Replace the removed ct test switch. This will cause the change detector to
51a
pickup thus resulting in relay trip output operation.

At circuit end “R”:

Select the relay to normal by re-selecting from “Test” mode to “Volts/Amps/

52
Angle” mode.

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Version 2.50 I.L. 40-201.81

L
Table L-1: (Continued)

Completed
Item On Load End to End Test Procedure
( ✓ )

By utilizing the relay “Volts/Amps/Angle” mode confirm that the status of

53
“CHRX” has changed from armed (ARM) to guard (GARD).

Select the relay to normal by selecting to “Volts/Amps/Angle” mode and

54
confirm that the relay display of system volts and load current is correct.

55 Reset any relay alarms or indications

The above sequence of on load tests should be repeated from both circuit ends. PLEASE
CONFIRM by a tick ( ✓ ) when this is completed.

Both ends tested ( )

Table L-2:

Name Representing

Date of Testing: ...................../....................../..........................

1.11.1 Putting The Relay Into Service

All on load testing is now completed. The relays at BOTH ends of the circuit should be powered
down and re-energized before putting the relays into service. This ensures the SRT function
has been cancelled and the trip contacts have been released after testing. PLESE CONFIRM
the SRT indication is NO by ticking ( ✓ ) box.

SRT = NO at both ends ( )

203
I.L. 40-201.81 Version 2.50

WARNING

The user should verify that Standing Relay Trip SRT = NO in the Test Mode Function (See
Section 4.5.4, on page 55) prior to putting the REL 350 in service.

1.11.2 Reinstate The Relay To Normal

The protection at each end should be switched back into service having first verified that all ct
connections and relay settings are reinstated to normal. PLEASE CONFIRM by a tick ( ✓ ).

Both ends fully reinstated and switched into service ( )

204
Version 2.50 I.L. 40-201.81

1.1
COMPUTER COMMUNICATIONS

COMMUNICATION PORT(S) USE M

1.1.1 Introduction

REL 350 can be communicated with for target data, settings, etc., through the man-machine
interface (MMI), The relay can also be communicated with via the communication (comm.)
ports. Comm port communications, provides the user with more information than is available
with the MMI. For example, all 16 targets are available and a more friendly user interface for
settings can be accessed (all settings are displayed on a single screen on the user’s PC). This
section will provide the details of the comm port options, personal computer requirements, con-
necting cables and all information necessary to communicate with and extract data from the
relay. Additional communications details are contained in IL 40-603, (RCP) Remote Commu-
nication Program.

NOTE: Earlier versions of RCP program refer to REL 350 as MSPC.

1.1.2 Communication Port Options

REL 350 is supplied with a rear communications port. If the network interface is not specified,
a RS-232C (hardware standard) communications port is supplied. Network interface comm.
port option allows the connection of the relay with many other devices to a 2-wire network. A
detailed discussion of networking capabilities can be found in AD 40-600, Substation Control
and Communications Application Guide.

RS-232C, rear comm. port is of the removable, Product Operated Network Interface (PONI)
type and is available in two styles. One is identified by a 25 pin (DB-25S) female connector, it
is usually black and has a single data comm. rate of 1200 bps. The second style is identified
by a 9 pin (DB-9P) male connector and externally accessible dip switches (next to the connec-
tor) for setting the communication data rate. This port option is always black in color, can be
set for speeds of 300, 1200, 2400, 4800, or 9600 bps (see Table M-2, on page 208) and offers an
option for IRIG-B time clock, synchronization input.

1.1.3 Personal Computer Requirements

Communication with the relay requires the use of Remote Communication Program (RCP) re-
gardless of the comm. port option. RCP is supplied by ABB Relay Division and is run on a per-
sonal computer (PC).

To run the program requires an IBM AT, PC/2 PC or true compatible with a minimum of 640
kilobytes of RAM, 1 hard disk drive, a RS-232C comm. port and a video graphics adapter card.
The PC must be running Version 3.3, or higher, MS-DOS.

1.1.4 Connecting Cables

With each comm. port option the connecting cable requirement can be different. Also, connect-
ing directly to a PC or connecting to a modem, for remote communication, affects the connect-
ing cable requirements. Table M-1, on page 208, provides a summary of a plug pin
assignments, pins required and cable connectors.

205
I.L. 40-201.81 Version 2.50

Some terminology will be defined to aid the user in understanding cable requirements in Table
M-1 (page 208). Reference, is often made to the “RS-232C” standard, for data communication.
The RS-232C standard describes mechanical, electrical, and functional characteristics. This
standard is published by the Electronics Industry Association (EIA) and use of the standard is
voluntary but widely accepted for electronic data transfer. ABB relay communications follows
the RS-232C standard for non-network data communication.

Although the RS-232C standard does not specify a connector shape, the most commonly used
is the “D” shape connector. As stated in Section 1.1.2 , on page 205, all ABB relay communi-
cation connectors are of the “D” shape (such as DB-25S).

Data communication devices are categorized as either Data Terminal Equipment (DTE) or Data
Communication Equipment (DCE). A DTE is any digital device that transmits and/or receives
data and uses communications equipment for the data transfer. DCE’s are connected to a com-
munication line (usually a telephone line) for the purpose of transferring data from one point to
another. In addition to transferring the data, DCE devices are designed to establish, maintain,
and terminate the connection. As examples, a computer is a DTE device and a modem is a
DCE device.

By definition the connector of a DCE is always female (usually DB-9S or 25S). Similarly, DTEs
are always male (usually DB-9P or 25P). These definitions apply to the equipment being con-
nected and to the connectors on the interconnecting cables.

One additional piece of hardware that is required, in some applications, is a “null” modem. Null
modem’s function is to connect the transmit line (TXD), pin 2 by RS-232C standard, to the re-
ceive line (RXD), pin 3. A null modem is required when connecting like devices. That is DTE to
DTE or DCE to DCE. A DCE to DCE, example, where a null modem is required, is the connec-
tion of a 25 pin, PONI to a modem.

A null modem function can be accomplished in the connecting cable or by separate null modem
package. That is, by using a conventional RS-232C cable plus a null modem. One type of null
modem, available from electronics suppliers, is B & B Electronics Type 232MFNM.

1.1.5 Setting Change Permission and Relay Password

To gain access to certain communication port functions, the REL 350 must have the remote
setting capability permission SETR set to YES and knowledge of the relay password is re-
quired. All communications port functions listed below require SETR set to YES before the ac-
tions can be performed:

Update/Change Settings
Enable Local Settings (capability)
Disable Local Settings (capability)
Activate Output Relays (contact testing function)

Access control, both setting permission and password knowledge is required for all communi-
cation port options.

206
Version 2.50 I.L. 40-201.81

Before attempting any of the above functions, the setting of SETR must be verified via the
front panel MMI. Using the setting change procedure in Section 4.5, on page 54, verify or
change SETR such that it is set to YES.
M
Using comm. port communications, the ability to change settings from the MMI can be dis-
abled.The RCP, Password Menu Choice “Disable Local Settings” when selected, will block set-
ting changes via the MMI. Blocking the front panel setting changes, may be useful for situations
in which the access to the relay cannot be secured from tampering by unauthorized persons.

Password:

When the REL 350 is received from the factory or if the user loses the relay password, a new
password can be assigned with the following procedure:

Turn off the relay dc supply voltage for a few seconds,

Restore the dc supply voltage and wait for the relay to complete the self check/start-up
routine, Using RCP, perform the Password Menu choice “Set Relay Password”,
Use the word “password” when prompted for the “current relay password” and
Then enter a new password.

Password setting change procedure must be completed within 15 minutes of energizing relay
or “password” will not be accepted as the “current” password.

1.1.6 Troubleshooting

In the event the communication remains unsuccessful, first make sure that the relay is powered,
proper communication cable is used (Table M-1, on page 208), and the connection is good.

For further testing, check that the bit rate (Baud) on the RS-PONI (Table M-2, on page 208) is set
to correspond to the one displayed at the bottom right of the RCP display.

If after these verifications the problem remains, try to remove the power from the relay and ap-
ply it again. If the communication still fails (several attempts), the communication equipment
needs to be serviced.

1.1.7 SIXTEEN FAULT TARGET DATA

The REL 350 saves the latest 16 fault records, but only the latest two fault records can be ac-
cessed from the front panel. For complete 16 fault data, the computer communication is nec-
essary.

1.1.8 OSCILLOGRAPHIC DATA

Three sets of oscillographic data are stored in REL 350. Each set includes seven analog traces
(Va, Vb, Vc, Ia, Ib, Ic and In), with one cycle pre-fault and 7-cycle fault information, and 20 sets
of digital data based on 12 samples per cycle. Refer to Section 1.2, on page 209, for detailed
information.

207
I.L. 40-201.81 Version 2.50

NOTE: IF POWER IS INTERRUPTED TO RELAY ALL “OSCILLOGRAPHIC DATA” WILL

BE LOST.

Table M-1
Communications Cable Requirements
Cable Pins Req’d.
Connection Type (Straight = no (All pins Cable Connectors Data Rate
null modem) not required)
To port: 25 pin DTE
DB-25S, RS-232C connected to PC* Straight 2, 3, 7 1200 bps only
To PC: 9 or 25 pin DCE
To port: 25 pin DTE
DB-25S, RS-232C connected to modem Null Modem 2, 3, 7 1200 bps only
to Modem: 25 pin DTE
To port: 9 pin DCE See Table M-2
DB-9P, RS-232C connected to PC* Null Modem 2, 3, 5
To PC: 9 or 25 pin DCE For settings
Straight To port: 9 pin DCE See Table M-2
DB-9P, RS-232C connected to modem* 2, 3, 5
To Modem: 25 pin DTE For settings

* Note: A communications cable kit (item identification number 1504B78G01) that will
accommodate most connection combinations is available through your local
ABB representative.

Table M-2
RS-PONI Dip Switch Settings
Dip Switch Pole
1 2
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Dip Switch Pole
4 5
Port Data
Rate
3 bps
0 300
1 1200
0 2400
1 4800
0 9600
1 19200
0 1200
1 1200
Auto Answer
Rings

0 0 none
0 1 4
1 0 8
1 1 12
NOTE: Turn the power OFF and ON, anytime
Dip Switch changes are made.

208
Version 2.50 I.L. 40-201.81

M
1.2 OSCILLOGRAPHIC DATA DEFINITIONS

The Oscillographic and Recording Program (OSCAR) under selection: “Load Screen
Layout File” of the main menu offers the following display files for REL 350.

NOTE: Earlier versions of OSCAR Program refer to REL 350 as MSPC.

PHAMSP.MSP Phase comparison Phase A

PHBMSP.MSP Phase comparison Phase B
PHCMSP.MSP Phase comparison Phase C
GNDMSP.MSP Phase comparison GROUND
PHSECMP.MSP Phase comparison Phases A, B, C, GND
BKUPMSP.MSP Distance Backup Subsystem Phases A, B, C, GND

The signals associated with the above files are described in sections 1.2.1 thru 1.2.5, begining
on page 209:

1.2.1 PHAMSP.MSP

In PHAMSP.MSP the following signals are shown:

Ia, Ib, Ic, -3IO, Vag, Vbg, Vcg and 3V0: Self Explanatory.

TPA: Remote Trip Positive (Received signal)

LPA: Local Positive
LNA: Local Negative
COTA: Coincidence AND output
PTA: Pilot Trip
IKA: Transmitted signal
IAL: Low set overcurrent supervision
IAH: High set overcurrent supervision
52bA: Axillary Breaker contact for phase A
IE: Very Low set current for open breaker detection
CDIV: Change detector of current and/or voltage
AGF: Phase selector (On if an Ag fault)
KE: Keying Enable signal
CT: Channel Trouble signal
SCT: Soft Channel Trouble: If no delay time measurement
ROBR: Remote Open breaker signal received
TGD: Transmit Guard signal
RGD: Receive Guard Signal
CARM: Channel Arm (Enables Phase Comp)
TRSL: Trip Seal (Breaker trip current detected)

1.2.2 PHBMSP.MSP

In PHBMSP.MSP and PHCMSP.MSP with the respective change of phase.

Files in the above definitions apply with the respective phase (B or C) changes.

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I.L. 40-201.81 Version 2.50

1.2.3 GNDMSP.MSP

For GNDMSP.MSP the signals are:

Ia, Ib, Ic, 3I0, Vag, Vcg, 3V0: Self explanatory.

TPG: Trip Positive

LPG: Local Positive
LNG: Local Negative
COTG: Coincidence AND Output
PTG: Pilot trip
IKG: Transmitter signal
IGL: Low set overcurrent supervision unit
IGH: High set overcurrent direct trip
PTOG: Pilot trip through the phase selector (Only when the ground subsystem
operates and none of the other subsystems operate. Will select the proper
pole in signal pole trip systems.)
AGF: An AG fault detected
BGF: A BG fault detected
CGF: A CG fault detected
MPF: A multiphase fault detected
KE: Keyer Enable
CT: Channel Trouble
SCT: Soft Channel Trouble
ROBR: Remote open breaker signal received
TGD: Transmit guard signal
RGD: Receive Guard Signal
TRSL: Breaker Trip coil current detected

1.2.4 PHSECMP.MSP

For PHSECMP.MSP the following is the definition of the signals:

Vag, Ia: Self explanatory

IKA: Keying signal for phase A

TPA: Trip positive for phase A
LPA: Local positive for phase A
LNA: Local negative for phase A
PTA: Pilot Trip (Trip) for phase A

Vbg, Ib: Self explanatory

IKB: Keying signal for phase B

TPB: Trip positive for phase B
LPB: Local positive for phase B
LNB: Local negative for phase B
PTB: Pilot Trip (TRIP) for phase B

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Version 2.50 I.L. 40-201.81

M
Vcg, Ic: Self explanatory

IKC: Keying signal for phase C

TPC: Trip positive for phase C
LPC: Local positive for phase C
LNC: Local negative for phase C
PTC: Pilot Trip (TRIP) for phase C

3V0, -3I0 Self explanatory

IKG: Keying signal for GROUND

TPG: Trip positive for GROUND
LPG: Local positive for GROUND
LNG: Local negative for GROUND
PTG: Pilot Trip (TRIP) for GROUND

1.2.5 BKUPMSP.MSP

For BKUPMSP.MSP the following signals are defined:

Ia, Ib, Ic, -3I0, Vag, Vbg, Vcg and 3V0: Self Explanatory.

SPFT: Sound phase fault trip (for single pole trip systems)
RIFT: Reclose into a fault trip
UNBK: Unblock logic trip
62T: Pole disagreement timer trip (for single pole trip systems)
SRI: Reclose Initiate for single line to ground faults
3RI: Reclose Initiate for multiphase faults
RB: Reclose Block
21BO: Outer blinder for OST
21BI: Inner blinder for OST
OSB: Out-of-step bock signal (Disables Z2 and Z3 three-phase fault detection)
OST: Out-of-step trip
Z2P: Zone 2 phase unit operated
Z2G: Zone 2 ground unit operated
Z3P: zone 3 phase unit operated
Z3G: Zone 3 ground unit operated
Z2T: Zone 2 trip (phase or ground after T2)
Z3T: Zone 3 trip (phase or ground after T3)
TOG: Ground Overcurrent trip
IOM: Medium set ground overcurrent unit operated
LOP: Loss of potential detected (V0 and not IO)

211
 Notes

212
Version 2.50 I.L. 40-201.81

Figure No.
SYSTEM DIAGRAMS

Description
S
S-1 REL 350 Block Diagram - - - - - - - - - - - - - - - - - (1617C46) sheet 1 of 1 - - - - - - - - - - - page 215
S-2a REL 350 System Logic Diagram- - - - - - - - - - - - (2420F06) sheet 1 - - - - - - - - - - - - - - page 217
S-2b REL 350 System Logic Diagram- - - - - - - - - - - - (DTP2420F06) - - - - - - - - - - - - - - - - - page 219
S-3 REL 350 Application Diagram - - - - - - - - - - - - - (2693F87) sheet 1 of 1 - - - - - - - - - - - page 221

213
 Notes

214
 Version 2.50
Sub 2
1617c46

I.L. 40-201.81
Sheet 1 of 1
215

Figure S-1: REL 350 System Block Diagram

S
 Notes

216
 Notes

218
 Version 2.50
IL3φ
FDOP 16

3φ
Zone 2
3φ

φ O A
N
φ R
D
φφ

FDOG

A
N FDOP
D

FDOG
φG
LOW LEVEL CURREN
SUPERVISION
FDOP
IAL A
FROM I N IL3φ 3φ IL3φ
SHEET 1 IBL
CL D ZONE 3

O IL
FDOG R
A
O N
R D
φφ

O φG FDOG
R

FDOG
φA φG
OPERATING
φφ ELEMENTS
3φ

I.L. 40-201.81
DTP2420F06
219

Figure S-2b: REL 350 System Logic Drawig

S
 Notes

220
 Notes

222
INSTRUCTION MANUAL
REL350
Version 2.50
Version 2.50 Instruction Manual 201.81

!
CAUTION
It is recommended that the user of REL 350 equipment become ac-
quainted with the information in this instruction manual before energizing the
system. Failure to do so may result in injury to personnel or damage to the
equipment, and may affect the equipment warranty. If the REL 350 relay sys-
tem is mounted in a cabinet, the cabinet must be bolted to the floor, or other-
wise secured before REL 350 installation, to prevent the system from tipping
over.

All integrated circuits used on the modules are sensitive to and can be
damaged by the discharge of static electricity. Electrostatic discharge precau-
tions should be observed when handling modules or individual components.

ABB does not assume liability arising out of the application or use of
any product or circuit described herein. ABB reserves the right to make chang-
es to any products herein to improve reliability, function or design. Specifica-
tions and information herein are subject to change without notice. All possible
contingencies which may arise during installation, operation, or maintenance,
and all details and variations of this equipment do not purport to be covered by
these instructions. If further information is desired by purchaser regarding a
particular installation, operation or maintenance of equipment, the local ABB
representative should be contacted.
© Copyright
ABB Power T&D Company Inc.
Published 1994, 1995, 1996,
1997
All Rights reserved

ABB does not convey any

license under its patent rights
nor the rights of others.

i
Instruction Manual 201.81 Version 2.50

Equipment Identification
The REL 350 equipment is identified by the Catalog Number on the REL
350 chassis nameplate. The Catalog Number can be decoded by using
Catalog Number Table 3-1 (see Section 3, page 49 ).

Production Changes
When engineering and production changes are made to the REL 350
equipment, a revision notation (Sub #) is reflected on the appropriate sche-
matic diagram, and associated parts information. A summary of all Sub #s
for the particular release is shown below.

Equipment Repair
Repair work is done most satisfactorily at the factory. When returning
equipment, carefully pack modules and other units, etc. All equipment
should be returned in the original packing containers if possible. Any dam-
age due to improperly packed items will be charged to the customer.

Document Overview
Section 1 (page 1) provides the Product Description, which includes soft-
ware functions. Section 2 (page 11) provides Specifications and External
Connections. Section 3 (page 15) presents applications with related Cata-
log Numbers for ordering purposes. REL 350 Installation, Operation and
Maintenance are described in Section 4 (page 51) with related Setting Cal-
culations in Section 5 (page 73). Appendices A thru K (beginning on page
107) include related module circuit descriptions. Acceptance Tests are de-
scribed in Appendix L. Oscillographic Data Definitions are defined in Ap-
pendix M and System Diagrams are included at the back of the book.

Contents of Relay System

The REL 350 Relay System includes the style numbers, listed below, for
each module. Addenda pages may be included (representing future revi-
sions).

Module Style
• Backplane - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C26
• Microprocessor - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C22
• (Sub-Backplane Xfmr)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1502B28
• Display - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1609C01

• Interconnect - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C25
• Power Supply- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C24

• Relay Output - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C27

• Analog Input - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C23

• Contact Input - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1611C28

• Modem - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1612C01

• CODEC - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1615C33
• Digital Comm. Interface- - - - - - - - - - - - - - - - - - - - - - - - - - - - 1615C43

ii
 CONTENTS

PART I: BASICS
1 PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . .1
1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . .1
1.2 REL 350 CONSTRUCTION . . . . . . . . . . . . . . . . .1
1.3 REL 350 MODULES . . . . . . . . . . . . . . . . . . . . .1
1.4 SELF-CHECKING SOFTWARE . . . . . . . . . . . . . . . .5
1.5 UNIQUE REMOTE COMMUNICATION . . . . . . . . . . . .6
1.6 PROGRAM FLOW . . . . . . . . . . . . . . . . . . . . .6
2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 TECHNICAL . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 EXTERNAL CONNECTIONS . . . . . . . . . . . . . . . . 12
2.3 CONTACT DATA . . . . . . . . . . . . . . . . . . . . . 12
2.4 9600 bps AUDIO TONE COMMUNICATION CHANNEL . . . . 12
2.5 56/64 kbs DIGITAL COMMUNICAITON . . . . . . . . . . . 12
2.6 Optional G.703 Interface . . . . . . . . . . . . . . . . . . 13
2.7 OPTIONAL COMPUTER/NETWORK INTERFACE. . . . . . 13
2.8 CHASSIS DIMENSIONS AND WEIGHT . . . . . . . . . . . 13
2.9 ENVIRONMENTAL DATA . . . . . . . . . . . . . . . . . 13
3 APPLICATIONS AND ORDERING INFORMATION . . . . . . . . 15
3.1 INTRODUCITON . . . . . . . . . . . . . . . . . . . . . 15
3.2 SEGRAGETED PHASE COMPARISON PROTECTION . . . . 16
3.3 PHASE COMPARISON UNDER
FAULT CONDITIONS . . . . . . . . . . . . . . . . . . . 18
3.4 DISTANCE RELAYING. . . . . . . . . . . . . . . . . . . 25
3.5 COMMUNICATION LOGIC. . . . . . . . . . . . . . . . . 20
3.6 TRIPPING AND RECLOSE INITIATE LOGIC . . . . . . . . 21
3.7 RELAY FUNCTIONS . . . . . . . . . . . . . . . . . . . 22
3.8 OPTIONAL BACK-UP . . . . . . . . . . . . . . . . . . . 25
4 INSTALLATION, OPERATION AND MAINTENANCE . . . . . . . 51
4.1 SEPARATING THE INNER AND
OUTERCHASSIS . . . . . . . . . . . . . . . . . . . . . 51
4.2 TEST PLUGS AND FT-14 SWTICHES. . . . . . . . . . . . 51
4.3 EXTERNAL WIRING. . . . . . . . . . . . . . . . . . . . 51
4.4 REL 350 FRONT PANEL DISPLAY . . . . . . . . . . . . . 52
4.5 FRONT PANEL OPERATION. . . . . . . . . . . . . . . . 54
4.6 JUMPER CONTROL. . . . . . . . . . . . . . . . . . . . 59

iii
CONTENTS

4.7 NETWORK INTERFACE . . . . . . . . . . . . . . . . . .60

4.8 OSCILLOGRAPHIC DATA . . . . . . . . . . . . . . . . . .60
4.9 REL 350 SETTINGS . . . . . . . . . . . . . . . . . . . .60
4.10 MONITORING FUNCTIONS. . . . . . . . . . . . . . . . .60
4.11 TARGET (FAULT DATA) INFORMATION . . . . . . . . . . .61
4.12 COMMUNICATION CHANNEL TESTING . . . . . . . . . . .61
4.13 ROUTINE VISUAL INSPECTION . . . . . . . . . . . . . . .61
4.14 ACCEPTANCE TESTING . . . . . . . . . . . . . . . . . .61
4.15 NORMAL PRECAUTIONS . . . . . . . . . . . . . . . . . .61
4.16 DISASSEMBLY PROCEDURES . . . . . . . . . . . . . . .62
5 SETTING CALCULATIONS . . . . . . . . . . . . . . . . . . . .73
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . .73
5.2 RELAY SYSTEM SETUP . . . . . . . . . . . . . . . . . .73
5.3 OSCILLOGRAPHIC INFORMATION . . . . . . . . . . . . .74
5.4 PHASE COMPARISON-LOGIC SETTINGS . . . . . . . . . .75
5.5 PHASE COMPARISON ALGORITHM . . . . . . . . . . . .77
5.6 FAULT LOCATOR BLINDERS AND DISTANCE
PROTECTION COMMON SETTINGS . . . . . . . . . . . .84
5.7 BACK-UP SYSTEM SETTINGS . . . . . . . . . . . . . . .85
5.8 ZONE-2 AND ZONE-3 SETTINGS . . . . . . . . . . . . . .87
5.9 OUT-OF-STEP LOGIC SETTINGS . . . . . . . . . . . . . .89
5.10 TIME SETTINGS . . . . . . . . . . . . . . . . . . . . . .91
5.11 SETTING EXAMPLES . . . . . . . . . . . . . . . . . . .91

PART II: APPENDIXES

A BACKPLANE MODULE . . . . . . . . . . . . . . . . . . . . .107
B INTERCONNECT MODULE . . . . . . . . . . . . . . . . . . .111
C RELAY OUTPUT MODULE . . . . . . . . . . . . . . . . . . .115
D CONTACT INPUT MODULE . . . . . . . . . . . . . . . . . .121
E MICROPROCESSOR MODULE . . . . . . . . . . . . . . . . .125
F DISPLAY MODULE . . . . . . . . . . . . . . . . . . . . . .141
G POWER SUPPLY MODULE. . . . . . . . . . . . . . . . . . .145
H ANALOG INPUT MODULE . . . . . . . . . . . . . . . . . . .149
I MODEM MODULE . . . . . . . . . . . . . . . . . . . . . . .157
J CODEC MODULE . . . . . . . . . . . . . . . . . . . . . . .169
K DIGITAL COMMUNICATION INTERFACE . . . . . . . . . . . .175

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L ACCEPTANCE TESTS . . . . . . . . . . . . . . . . . . . . .183

M COMPUTER COMMUNICATION . . . . . . . . . . . . . . . . .205

PART III: DRAWINGS

SYSTEM DIAGRAMS. . . . . . . . . . . . . . . . . . . . . . . . .213

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List of Figures
Figure Number Page Number

1-1 Layout of REL 350 Modules Within Inner And Outer Chassis - - - - - - - - - - - - - - - - - - - 7
1-2 Block Diagram of REL 350 Relay - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8
1-3 Processor 1 Program Flow - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 9
1-4 Processor 2 Program Flow - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10

2-1 REL 350 Outline Drawing - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 14

3-1 REL 350 Segregated Phase Comparison, Fault Recognition- - - - - - - - - - - - - - - - - - - 30

3-2a REL 350 Phase Comparison Logic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 31
3-2b Offset Keying, Typical Internal Fault- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 32
3-2c Offset Keying, Typical External Fault - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 33
3-3 REL 350 Offset Keyer And Locals - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 34
3-4 REL 350 Two Count Mode Selection - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 35
3-5 REL 350 Trip Logic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 36
3-6 Single Phase-to-ground Fault Detection - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 37
3-7 Three-phase Fault Detection - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 38
3-8 Phase-to-phase Fault Detection- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 39
3-9 Communication Channel Interface - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 40
3-10 Unblock Logic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 41
3-11 Single Pole Trip - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 42
3-12 Reclosing Logic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 43
3-13 Loss of Potential Block Logic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 44
3-14 Zone 2 And Zone 3 Back-up System - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 45
3-15 Optional Directional Overcurrent Units - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 46
3-16 Blinders For The Out-of-step Logic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 47
3-17 OST And OSB Logic Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 48

4-1 REL 350 Backplate - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 70

4-2 REL 350 Systems External Connection (See inside back cover) - - - - - - - - - - - - - - - - - 71

5-1 Esk0253 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 101

5-2 Esk0254 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 102
5-3 Esk0347 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 103
5-4 Esk0348 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 104
5-5 Esk0349 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 105

A-1 REL 350 Backplane Module PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 108

A-2 REL 350 Backplane/transformer Module PC Board - - - - - - - - - - - - - - - - - - - - - - - 109
A-3 REL 350 Backplane/transformer Module Schematic - - - - - - - - - - - - - - - - - - - - - - - 110

B-1 REL 350 Interconnect Module PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - 112

B-2 REL 350 Interconnect Module Schematic - - - - - - - - - - - - - - - - - - - - - - - - - - - - 113

C-1 REL 350 Relay Output Module PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - 117

C-2a REL 350 Relay Output Module Schematic (Sheet 1 of 3) - - - - - - - - - - - - - - - - - - - 118
C-2b REL 350 Relay Output Module Schematic (Sheet 2 of 3) - - - - - - - - - - - - - - - - - - - 119
C-2c REL 350 Relay Output Module Schematic (Sheet 3 of 3) - - - - - - - - - - - - - - - - - - - 120

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Figure Number Page Number

D-1 REL 350 Contact Input Module PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - 122

D-2 REL 350 Contact Input Module Schematic - - - - - - - - - - - - - - - - - - - - - - - - - - - 123
E-1 REL 350 Microprocessor Module Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - 130
E-2 REL 350 Processor 1 Memory Map - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 131
E-3 REL 350 Processor 2 Memory Map - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 131
E-4 REL 350 Microprocessor PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 132
E-5a REL 350 Microprocessor Schematic (Sheet 1 of 7) - - - - - - - - - - - - - - - - - - - - - - 133
E-5b REL 350 Microprocessor Schematic (Sheet 2 of 7) - - - - - - - - - - - - - - - - - - - - - - 134
E-5c REL 350 Microprocessor Schematic (Sheet 3 of 7) - - - - - - - - - - - - - - - - - - - - - - 135
E-5d REL 350 Microprocessor Schematic (Sheet 4 of 7) - - - - - - - - - - - - - - - - - - - - - - 136
E-5e REL 350 Microprocessor Schematic (Sheet 5 of 7) - - - - - - - - - - - - - - - - - - - - - - 137
E-5f REL 350 Microprocessor Schematic (Sheet 6 of 7) - - - - - - - - - - - - - - - - - - - - - - 138
E-5g REL 350 Microprocessor Schematic (Sheet 7 of 7) - - - - - - - - - - - - - - - - - - - - - - 139
F-1 REL 350 Display Module PC Board (Sheet 7 of 7) - - - - - - - - - - - - - - - - - - - - - - 142
F-2 REL 350 Display Module Schematic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 143
G-1 REL 350 Power Supply PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 147
G-2 REL 350 Power Supply Schematic (See inside back cover) - - - - - - - - - - - - - - - - - - - 148
H-1 Analog Input Module Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150
H-2 Analog Input Module PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 151
H-3a Analog Input Module Schematic (Sheet 1 of 4) - - - - - - - - - - - - - - - - - - - - - - - - 152
H-3b Analog Input Module Schematic (Sheet 2 of 4) - - - - - - - - - - - - - - - - - - - - - - - - 153
H-3c Analog Input Module Schematic (Sheet 3 of 4) - - - - - - - - - - - - - - - - - - - - - - - - 154
H-3d Analog Input Module Schematic (Sheet 4 of 4) - - - - - - - - - - - - - - - - - - - - - - - - 155
I-1 REL 350 Modem Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 162
I-2 Modulation Diagram At 9600 Bps - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 163
I-3 REL 350 Modem PC Board - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 164
I-4a REL 350 Modem Schematic (Sheet 1 of 3) - - - - - - - - - - - - - - - - - - - - - - - - - - 165
I-4b REL 350 Modem Schematic (Sheet 2 of 3) - - - - - - - - - - - - - - - - - - - - - - - - - - 166
I-4c REL 350 Modem Schematic (Sheet 3 of 3) - - - - - - - - - - - - - - - - - - - - - - - - - - 167
J-1 Block Diagram - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 169
J-2 CODEC Module Schematic (See inside back cover) - - - - - - - - - - - - - - - - - - - - - - - 173
J-3 REL 350 CODEC Module- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 174
K-1 Digital Communication Internal Schematic (Direct Digital Fiber Optic Multi-mode) - - - - - - - - 176
K-2 Digital Communication Internal Schematic (Direct Digital Fiber Optic Single-mode)- - - - - - - - 177
K-3 Digital Communication Component Location - - - - - - - - - - - - - - - - - - - - - - - - - - 178
K-4 Component Location - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 179
K-5 Internal Schematic - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 180
K-6 Component Location - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 181
S-1 REL 350 System Block Diagram (Sheet 1 of 1) - - - - - - - - - - - - - - - - - - - - - - - 215
S-2a REL 350 System Logic Diagram (Sheet 1 ) - - - - - - - - - - - - - - - - - - - - - - - - - 217
S-2b REL 350 System Logic Diagram (Sheet 1)- - - - - - - - - - - - - - - - - - - - - - - - - - 219
S-3 REL 350 Application Diagram (Sheet 1 of 1) - - - - - - - - - - - - - - - - - - - - - - - 221

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List of Tables
Table Number Page Number

3-1 REL 350 Catalog Numbers - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 49

3-2 REL 350 Accessories- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 50
3-3 Faulted Phase Selection - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 50

4-1 Test Mode Functions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 55

4-2 Binary-to-Hexadecimal Conversion - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 56
4-3 Setting Functions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 63
4-4 Setting Information - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 65
4-5 Monitoring Functions - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 67
4-6 Target (Fault Data) Information - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 68

E-1 Coding for REL 350 Channel Data - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 128

E-2 Inputs from Modem to Microprocessor Board - - - - - - - - - - - - - - - - - - - - - - - - - - 129
E-3 Outputs from Microprocessor to Modem Board - - - - - - - - - - - - - - - - - - - - - - - - - 129

I-1 Second, Third and Fourth Data Bits Determine Phase Change - - - - - - - - - - - - - - - - - 161
I-2 First Data Bit Determines Amplitude - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 161
I-3 Serial Data Format - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 161

J-1 REL 350 Data Code Field - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 172

L-1 On Load Test Procedure - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 199

Trademarks
All terms mentioned in this book that are known to be trademarks or service marks are listed below. In addition,
terms suspected of being trademarks or service marks have been appropriately capitalized. ABB Power T&D
Company Inc. cannot attest to the accuracy of this information. Use of a term in this book should not be
regarded as affecting the validity of any trademark or service mark.
IBM and PC are registered trademarks of the International Business Machines Corporation.
WRELCOM is the registered trademark of the ABB Power T&D Company Inc.
INCOM is the registered trademark of the Westinghouse Electric Corporation

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