Digital_MASS_Question_October 2023

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1. Explain different types of adder circuits.

Solution:

Adders are one of the most widely used digital components in the digital integrated
circuit design and are the necessary part of Digital Signal Processing (DSP)
applications. With the advances in technology, researchers have tried and are trying to
design adders which offer either high speed, low power consumption, less area or the
combination of them.

The various adders are listed below

● Ripple Carry Adder (RCA)

● Carry Look Ahead Adder (CLaA)
● Carry Skip Adder (CSkA)
● Carry Save Adder (CSA)
● Carry Increment Adder (CIA)
● Carry Select Adder (CSIA)
● Carry Bypass Adder (CByA)

We have already discussed the Carry Ripple Carry Adder (RCA) , Carry Look Ahead
Adder (CLaA) and Carry Skip Adder (CSkA) in our course.

Let's look into other different adder circuits.

Carry Save adder:

The carry save adder seems to be the most useful adder for our application. It is
simply a parallel ensemble of k full-adders without any horizontal connection. Its
main function is to add three k-bit integers A, B, and C to produce two integers C 0
and S such that

C’ + S = A + B + C
As an example, let A = 40, B = 25, and C = 20, we compute S and C0 as shown
below:

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The i“' bit of the sum Si and the (i + l)“ bit of the carry C’»i is calculated using the equations
Si=Ai ⊕Bi⊕Ci

C'i i = ATR + ABC + BiCi

Thus the carry-save adder reduces the addition of 3 numbers to the addition of 2 numbers. The
propagation delay is 3 gates regardless of the number of bits. The carry-save unit consists of n
full adders, each of which computes a single sum and carries bit based solely on the
corresponding bits of the three input numbers. The entire sum can then be computed by shifting
the carry sequence left by one place and appending a 0 to the front (most significant bit) of the
partial sum sequence and adding this sequence with RCA produces the resulting n + 1-bit value.
This process can be continued indefinitely, adding an input for each stage of full adders,
without any intermediate carry propagation. These stages can be arranged in a binary tree
structure, with cumulative delay logarithmic in the number of inputs to be added, and invariant
of the number of bits per input. The main application of the carry save algorithm is, well known
for multiplier architecture, is used for efficient CMOS implementation of a much wider variety
of algorithms for high speed digital signal processing.

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Carry – Increment Adder

The design of Carry Increment Adder consists of RCA's and incremental circuitry. The
incremental circuit can be designed using Half adder and ripple carry chain with a
sequential order. The addition operation is done by dividing the total number of bits
into groups of 4 bits and addition operation is done using several 4-bit RCA's.
The block diagram of CIA is shown in Figure 2

Carry Select Adder

A carry select adder is a special way of implementing a binary adder. It's simple yet fast
adder. The block diagram of a carry select adder is shown in fig 3.

Carry Select Adder architecture consists of independent generation of sum and carry
i.e., Cin=l and Cin=0 are executed parallelly. Depending upon Cin, the external
multiplexers select the carry to be propagated to the next stage. Further, based on the
carry input, the sum will be selected. Hence, the delay is reduced. However, the
structure is increased due to the complexity of multiplexers.

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CarryBypassAdder

In Carry Bypass Adder (CBA), RCA is used to add 4-bits at a time and the carry
generated will be propagated to the next stage with the help of a multiplexer using select
input as Bypass logic. Bypass logic is formed from the product values as it is calculated
in the CLA. Depending on the carry value and by pass logic, the carry is propagated to
the next stage [2]. The architecture of Carry Bypass Adder (CBA) is given in Fig 5.

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With 2 i/ps, there are 4 combinations 00, 01, 10, 11.

So A, B & C are 2 bit i/ps and they can be assigned with any of the 4 possible values.

The table shows different possibilities of i/p combinations.

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