Comparison of different computational

platform by implementing planar phased array

controller

Project Report

Submitted by
A.RATHNA
(EDS19M010)

Under the supervision of

Prof. Vijayakumar Krishnasamy

Department of Electronics & Communication

Engineering
Indian Institute of Information Technology,
Design and Manufacturing, Chennai, Tamil Nadu,
600127, India
Contents

1 INTRODUCTION 1

2 Literature Review 2

3 Motivation 3
3.1 Role of computational platform . . . . . . . . . . . . . . . . . . 3
3.2 Different Computational Platform . . . . . . . . . . . . . . . . . 3
3.3 Need for comparison . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Objectives 5
4.1 Array Antenna . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 Implementation of Antenna
Array Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5 METHODOLOGY 9
5.1 Implementation of complex mathematical
functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.1 CORDIC ALGORITHM . . . . . . . . . . . . . . . . . . 9

6 Work Done 11
6.1 SERIAL INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2 CORDIC ALGORITHM . . . . . . . . . . . . . . . . . . . . . . 12

7 Conclusion 14

8 Future Work 15

Reference 16

i
List of Figures
1 planar array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 phased array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 BLock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Decimal to IEEE754 Floating point converter GUI . . . . . . . . 11
5 Sample Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Serial connection . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7 Cordic Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8 Cordic Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10 Device usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

ii
List of Abbreviations
FPGA Field Programmable Gate Array
GPU Graphics Processing Unit
CPU Central Processing Unit
Peripheral Component Interconnect Ex-
PCIe
press
USB Universal Serial Bus
JTAG Joint Test Action Group
Universal Asynchronous Receiver-
UART
Transmitter
DOA Direction of Arrival
AF Array Factor
PE Programming Elements
AP SoC All Programmable System on Chip
DMA Direct Memory Access

iii
1 INTRODUCTION

1 INTRODUCTION
Current trends in the evolution of computational platform seek
ways to provide high computational speed and low power consumption. The
project titled as “Comparison of different computational platform by imple-
menting planar phased array controller” focuses on analyzing the performance
of a different computational platform for a particular phased array controller.
Here performance means computational speed and power consumption. The
main problem is there is a trade-off between delay and power so that the im-
provisation of speed will leads to high power consumption.
To analyze the processor based computational platform we use the ARM
Cortex processor which is programmed by C and for a sequencer based com-
putational platform we use the FPGA board which is programmed by VHDL.

microprocessor-based systems have been used to perform this task for a

long time. But the problem is Software algorithms employed by the processors
don’t meet the highly demanding needs of all DSP tasks. So they use FPGAs
as co-processors to perform all the high-speed tasks that can’t be achieved by
microprocessors. But, they do not suit for hardware platforms because they
need complex circuits to perform the mathematical operations
This brief analysis permitted us to stress some trends about which plat-
forms should be used for specific applications.

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2 LITERATURE REVIEW

2 Literature Review
Closing the gap: CPU and FPGA Trends in
sustainable floating-point BLAS performance
This paper examines three of the basic linear algebra subroutine (BLAS)
functions: vector dot product, matrix-vector multiply, and matrix multiply. A
comparison of microprocessors, FPGAs, and Reconfigurable Computing plat-
forms is performed for each operation. The analysis highlights the amount of
memory bandwidth and internal storage needed to sustain peak performance
with FPGAs

Beam scanning of phased array antenna using

phase modification method for satellite applica-
tion
This paper provides brief analysis of the ability of array to control a
direction of main lobe systematic least mean square method and also validation
of design.For that we use s the design of a 1X4 micro strip array antenna
operating at 6.3GHz for C-band communication satellite application made it
an attractive choice for a wide variety of applications.

A design and implementation of control logic

of beam steering unit for phased array radar
This paper helps us to understand what is beam steering controller and
how it works.The work for the beam steering controller is given as
• The control logic will decode the data into suitable format
• Converts into serial format for loading the data into phase shifters.
•Controller and calculates the Phase gradients and phase commands based
on the different tables like standard table, collimation table, and Phase com-
mand table

Trends of CPU, GPU and FPGA for high-

performance computing
The comparison of various platforms like CPU,GPU and FPGA based
on Floating point operation and type of workload are given in this paper
It also gives the detail about Peak performance and power consumption
and also sustainable performance alos given here

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3 MOTIVATION

3 Motivation
3.1 Role of computational platform
We live in a world of ubiquitous and never stopping communication ser-
vices such as terrestrial and satellite broadcasting, surveillance, remote sens-
ing, or rescue operations, to say a couple of. Nowadays the usage of wireless
standards, services, and subscribers who want to enjoy it without disruption
of services, preferably at any location are increased.so,we have to offer more
robust techniques and technologies that will cope with this demand.
To ensure the services it is important to steer the beam of the antenna
to the desired direction (that is where max.radiation is required) without any
time delay. In that situation ,the beam of antenna is steered by changing a
phase shift to the excitation current .The change in phase shift is processed by
the phase shift controller.

3.2 Different Computational Platform

Considering the type of workload, we can establish a relation with the type
of processor. A sequential dominated workload is definitely for a CPU since
its higher frequencies improve the sequential execution. CPUs are also very
good for iterative workloads, leaving some space for FPGAs.
Parallel intensive applications require the many core processing of a GPU,
FPGA or many-core CPU. Even with multi-threaded implementations, CPU
is a poor computing platform for this Some parallel intensive applications
should be implemented in a specific platform while others could be equally
implemented in several platforms.
For example algebraic operations, spectral analysis, n-body simulations,
GPUs achieve better performance figures for a larger set of applications, fol-
lowed by the many-core CPU, the FPGA and finally the CPU.For the GPU
implementations, we highlighted the fact that memory is a limiting perfor-
mance factor.

3.3 Need for comparison

As we see before about phased Antenna array,the continuous change of ex-

citation will happens in a fraction of seconds and sometimes it will affect or
damage some elements which ended in degradation of performance. In that
condition we have to ensure that the controller used in this should be have
Fast Execution time and High performance.
Our aim is to comparing a different types of Computational platforms to
make a planar antenna array controller.By comparing processors parameters
we can ensure a controller that rectify any real time antenna problems.Because

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3 MOTIVATION

in real time applications the main things we have to consider is low latency
and high performance which is here determined by the computational platform
which we used to design a controller.

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4 OBJECTIVES

4 Objectives
4.1 Array Antenna
Implementation of antenna array controller in different computational plat-
forms mainly depends on the antenna design parameters.Here we use a planar
antenna array.Implementation of planar array have a various design parameter
to determine radiation pattern and direction of arrival(DOA).The below figure
represent the planar array structure

Figure 1: planar array

By selecting the below quantity for each element in the array we can obtain
required characteristics of antenna
1. Amplitude of the excitation current and
2. Phase of the excitation current
And these things are calculated by the array factor(AF) of planar array.if M
elements are placed along x-direction and N elements are placed along the
y-direction then array factor is given by

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4 OBJECTIVES

N
" N
#
X X
AF = I1n Im1 ej(m−1)(kdx sinθcosφ+βx ) ej(n−1)(kdy sinθsinφ+βy )
n=1 m=1

Im1 -Amplitude of excitation coefficients along x-direction;

I1n -Amplitude of excitation coefficients along y-direction;

dx &βx - The spacing and progressive phase shift between the elements in x-direction;

dy &βy - The spacing and progressive phase shift between the elements in y-direction;

The normalized form of array factor can be written as

" #" #
1 sin( M2 ψx ) 1 sin( N2 ψy )
AFn (θ, φ) =
M sin( ψ2x ) N sin( ψy )
2

where,

ψx = kdx sinθcosφ + βx

ψy = kdx sinθsinφ + βy

If it is desired to have only one main beam that is directed along θ = θ0 &
φ = φ0 , the progressive phase shift between the elements in x-direction and y-direction
must be equal to

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4 OBJECTIVES

ψx = −kdx sinθ0 cosφ0

ψy = −kdx sinθ0 sinφ0

and
nλ
" #
sinθ0 sinφ0 ± dy
ψ = tan− 1 mλ
sinθ0 coφ0 ± dx

nλ
" mλ
# " #
sinθ0 cosφ0 ± dx
sinθ0 sinφ0 ± dy
θ = sin− 1 = sin− 1
cosψ sinψ

Figure 2: phased array

From that we know that for implementation of planar antenna array we

need to calculate Array factor (AF) which will decide the excitation of ele-
ments according to their position to get an required radiation pattern and
DOA.normally planar array can provide more symmetrical pattern with lower
side lobes and they can scan main beam of antenna towards any point in space.

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4 OBJECTIVES

4.2 Implementation of Antenna

Array Controller
Our work mainly focus on implementing a antenna array controller in dif-
ferent processor.For that as we mentioned before we have to implement the
complex mathematical equation.As of now we use DSP processors to imple-
ment such function.But as per our project we want to make a adaptable and
self recoverable antenna also.In terms of this we want a re-configurable hard-
ware.Our aim is to choose the best computational platform for that i choose
three different processors
1.ARM processor
2. FPGA Platform

Implementation of complex mathematical equations into hard-

ware.for this we use following methods:

(a) Use some look-up tables for complex mathematical expressions. (FloRA)

(b) Use CORDIC algorithm- This is an extremely demanding task for high
speed, real-time operation such as required in many modern adaptive antenna,
radar, and sonar systems.

(c) Embed some soft core processor into an FPGA chip, which would then
use floating-point arithmetic and take advantage of some numeric library that
would help with implementation of floating-point operations in HW.

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5 METHODOLOGY

5 METHODOLOGY
5.1 Implementation of complex mathematical
functions
As we mentioned before we have to use any special methods to implement
the AF of the planar array into the processor.For that we can use any of the
following methods:

Figure 3: BLock diagram

5.1.1 CORDIC ALGORITHM

• Cordic algorithm can perform any complex mathematical calculations by
using simple shift and add operations. Even though it is a simplest method it
will take more time to perform the operations[13].
• It is primarily used because of it’s potential for efficient and low cost
implementation
• It is used for
1. The generation of trigonometric, logarithmic and transcendental
elementary functions
2. Complex number multiplication
3. Eigenvalue computation
4. Matrix inversion

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5 METHODOLOGY

5. Solution of linear systems and singular value decomposition (SVD)

for signal processing, image processing
6. General scientific computation

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6 WORK DONE

6 Work Done
6.1 SERIAL INPUT
As per the Antenna design we need Floating Point numbers to be entered
as a input.
First of all,We convert the decimal points to IEEE 754 floating point rep-
resentation by using MATLAB GUI.

Figure 4: Decimal to IEEE754 Floating point converter GUI

Figure 5: Sample Output

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6 WORK DONE

Figure 6: Serial connection

6.2 CORDIC ALGORITHM

Figure 7: Cordic Schematic

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6 WORK DONE

Figure 8: Cordic Output

Figure 9: Delay

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7 CONCLUSION

Figure 10: Device usage

7 Conclusion
• Our aim is to comparing a different types of Computational platforms to
make a planar antenna array controller.By comparing processors parameters
we can ensure a controller that rectify any real time antenna problems.
• Because in real time applications the main things we have to con-
sider is low latency and high performance which is here determined by the
computational platform which we used to design a controller.

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8 FUTURE WORK

8 Future Work
• The main work in this is implementing the mathematical equation which
determine the antenna characteristics.To achieve a perfect controller we have
to ensure that the equation is implemented in efficient way.
• By choosing efficient method for implementing Multiplication and Trigonom-
etry operations we can make it easier.
• After that,the main work is latching the data in processor.
• The most important thing here is selection of perfect comparison mech-
anism and also making the selected processor in Re-configurable way.
• These are the work we have to carried out in future.

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REFERENCES

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[8] M. Al Kadi, B. Janssen and M. Huebner, ”Floating-Point Arith-

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