Suggestion on Computer Organization & Architecture (CS401)

Stream: CSE 2nd year

Module 1 & Module 2

1. What do you mean by Von-Neumann architecture?

2. What do you mean by Harvard architecture?
3. What' is meant by the 'stored-program' concept'? Draw a diagram of von Neumann
architecture and explain it briefly.
4. Explain Harvard architecture with diagram.
5. What is von Neumann architecture? What is its bottleneck?
6. Explain the significant differences between the Von-Neumann and Harvard architecture
with diagram.
7. How floating-point addition is implemented. Explain briefly with a neat diagram.
8. Give Booth’s algorithm for multiplication of signed 2’s complement number in flowchart
and explain.
9. Briefly explain the IEEE 754 standard format for floating point representation in
single precision and double precision.
10. How NaN (Not a number) and infinity are represented in this standard.
11. Draw and explain the flowchart for division of two binary numbers using restoring
algorithm with an example.
12. Draw and explain the flowchart for division of two binary numbers using non-restoring
algorithm with an example.
13. Design a 3 bit ALU which will perform addition, subtraction, increment, decrement and
transfer operation.
14. Explain the difference between three-address, two-address, one-address instructions &
zero-address instruction with suitable examples.
15. Give an example and explain each type of addressing mode.
16. Evaluate the following expression using three, two, one and zero address instructions.
i. Z = (M+N)/ (P-Q)
17. Compare and contrast RISC and CISC architecture in brief.
18. Explain the reverse polish notation with an example using stack.
19. Describe the instruction cycle with diagram.
20. How many types of memories are found in digital computer?
21. A digital computer has a common bus system for 16 registers of 32 bits. The bus is
constructed with multiplexers.
How many selection inputs are there in each multiplexer?
What sizes of multiplexers are needed?
How many multiplexers are there in the bus?
22. Write the purpose of the following
a. Accumulator Program, Counter Address Register, Data Register, Program
Counter Instruction Register, Temporary Register, Input register, Output register
23. Draw and explain the bus system for four registers. Assume that there are four bits in
each register.
24. Draw and explain the organization for seven CPU registers in the control unit.
25. Show how computer bus is organized using tri-state buffer.
 26. Write notes on hard wired control unit and micro programmed control unit.
27. Define the following:
(a) Micro operation
(b) Micro instruction
(c) Micro program

28. Write down the difference between RISC and CISC architecture.
29. Differentiate between CISC and RISC architectures. What are their typical
characteristics? Give some examples(s) of processors of each category.
30. What is Amdahl’s law?

Module 5

1. What is instruction-level parallelism? How do processors exploit it to improve the

performance?
2. What do you mean by interconnection network in computer system? Describe the
different types of interconnection networks in computer system. What are multistage
switching networks?
3. Explain shared and centralized memory architecture with proper diagram.
4. What is Interconnection Network (ICN)? Explain static vs dynamic network.
5. What is loosely coupled system & tightly coupled system?
6. What is interconnection network?
7. Describe distributed shared memory architecture and centralized shared memory
architecture with suitable diagram and make a comparative study between them
8. What is cache coherence problem?
9. State the similarities and difference between multiprocessor and multi computer?
10. Explain the shared memory modes of MIMD.
11. Describe multiprocessor architecture.
12. Using a block diagram explain the operation of an SIMD array processor.
13. Short note on
a. Flynn’s classification
b. Omega,
c. Baseline
d. Butterfly
e. Crossbar
f. Cache coherence

Module 3
1. What is meant by pipeline architecture? How does it improve the speed of execution of
processor?
2. Explain data hazards with examples.
3. Explain control hazards with examples.
4. Explain structural hazards with examples.
5. Explain the techniques for Increasing ILP.
6. Explain arithmetic and instruction pipeline with proper diagram.
 7. What is instruction-level parallelism? How do processors exploit it to improve the
performance?
8. What do you mean by latency, simple cycles, greedy cycles and MAL.
9. What is dynamic pipeline? Distinguish static pipeline from dynamic pipeline.
10. Briefly describe the super-pipeline, super-scalar pipeline and VLIW processor
architecture. What are the limitations of the above architectures?
11. What do you mean by strip mining and vector stride?
12. What is ILP? Explain ILP with example.
13. Short note on
Vector processor (diagram must)
Array processor (diagram must)
VLIW (diagram must)
Super-pipelining (diagram must)
Super scalar (diagram must)
Speed up ratio

Module 4
1. How many 128 X 16 RAM chips are needed to construct a memory capacity of 4096
words (16 bits are one word)? How many lines of address must be used to access a
memory of 4096 words? For chip select, how many lines must be decoded?
2. Explain three types of cache memory mapping techniques.
3. What is locality of reference? What is memory mapping? Why is it needed?
4. What are ‘write through’ and ‘write back’ policies in cache?
5. Illustrate the characteristics of some common memory technologies.
6. Describe in detail about associative memory.
7. Discuss the different mapping techniques used in cache memories and their relative
merits and demerits.
8. Comparing paging and segmentation mechanisms for implementing the virtual memory.
9. Explain the organization of magnetic disk and magnetic tape in detail.
10. What is virtual memory? Why is it called virtual? Write the advantages of virtual
memory?
11. What is locality of reference? What is memory mapping? Why is it needed?
12. What is demand paging? What is segmentation?
13. What is cache memory? Define global miss and local miss with an example.
14. Describe different technique to reduce Miss Rate.
15. Describe different technique to reduce Miss Penalty.
16. Explain how a RAM of capacity 2K bytes can be mapped into the address space (1000) H
to (17FF) H of a CPU having a 16 bits address lines. Show how the address lines are
decoded to generate the chip select condition for the RAM.
17. Given the following, determine size of the sub-fields (in bits) in the address for direct
mapping, associative mapping and set associative mapping cache schemes: We have 256
MB main memory and 1MB cache memory. The address space of this processor is 256
MB. The block size is 128 bytes. There are 8 blocks in a cache set.
18. A hierarchical cache-main memory system has the following specifications:
Cache access time of 160 ns. Main memory access time of 960 ns. Hit ratio of cache
memory is 0.9.
 Calculate the following:
i. Average access time of the memory system
ii. Efficiency of the memory system.

19. A three-level memory system having cache access time of 15 ns and disk access time of
80 ns has a cache hit ratio of 0.96 and main memory hit ratio of 0.9. What should be the
main memory access time to achieve effective access time of 25 ns?
20. Explain how cache memory increases the performance of a computer system.
21. Why is the memory system of a computer organized as a hierarchy?
22. A certain program generates the following sequence of word addresses:
i. 5, 6, 10, 8, 14, 24, 4, 12
23. A page has four words; the number of page frames in main memory is 3. How many
page faults are generated if optimum page replacement policy is used?
24. Write short note on RAM and different types of ROM.