Chapter 1 Introduction

• Networking Architecture Overview

• Router Architecture Overview
 Networking Architecture Overview
A Generic Network:

: edge node : core node : end-host

• node: switch/router
• end-host: telephone/computer/server
• More intelligent at the edge nodes
• Higher speed at the core nodes
 Networking Architecture Overview
It is all about how to send information/packets
between end-hosts:
1. Routing Protocol
• Build the network topology/map
• Find one or multiple routes/paths from any node to any other nodes
• Build a routing/forwarding table
2. Two forwarding paradigms
• Connection-oriented: set up a virtual path and forward packets along
the path
• Connectionless: forward packets and let each node downstream figure
out how to forward the packets further downstream, known as hop-by-
hop forwarding
 Networking Architecture Overview
More on forwarding paradigms :
• Connection-oriented
• Build the network topology through a routing protocol: each node tells its
neighbors about its connectivity by flooding
• Based on the destination end-host’s global address, the routing protocol in the
first-hop node finds a route/path to the last-hop node, e.g., a shortest path
• The first-hop node uses a signaling protocol to install state information along
the path. The state information include incoming and out-going labels with
local significance (known as label swapping table) and resources reserved for
the path.
• The information is sent in the form of labeled packets. At each intermediate
node, the incoming label in the packet is matched against the label swapping
table to find the outgoing label and output interface to the downstream node.
• The incoming label is replaced by the outgoing label before the packet is sent to
the output interface downstream, known as label swapping.
 Networking Architecture Overview
More on forwarding paradigms :
• Connectionless
• Build the network topology through a routing protocol: each node tells
its neighbors about its connectivity by flooding; every node finds a path
to every other node and for each destination node, record only the next-
hop node along the path to the destination node, resulting in a
destination-node-to-next-hop-node mapping table, known as
routing/forwarding/longest prefix match (LPM) table. More on LPM
later
• The information is sent in the form of packets with destination host’s
global address attached
• At each intermediate node, the destination host’s global address is
matched against the LPM table to find the next-hop node and the packet
is sent to the next-hop node
 Networking Architecture Overview
IP internetworking basics:

• Shared medium: broadcast domain

– e.g., Ethernet and token ring
– Use MAC (multiple access control) address to forward frames,
known as layer 2 forwarding

• Point-to-Point
– e.g., packet over SONET (POS)
 Networking Architecture Overview
• IP Internetworking is connectionless
• To go from one IP network to another,
hop-by-hop forwarding based on the
destination IP address is performed,
known as layer 3 forwarding
 Networking Architecture Overview
Layering concept and addressing schemes:
• Internet protocols are designed in layers;
the lower layer provides service to its
immediate upper layer:

L5 Application

L4 Transport

L3 Internetworking

L2 Data link/MAC

L1 PHY
 Networking Architecture Overview
• Addressing schemes:
– Layer 2/MAC address:
• A global 48-bit flat address
• Cannot scale to large networks
– Layer 3/IP address:
• A global 32-bit two layer hierarchical address:
network part and host part

Network address host address

 Networking Architecture Overview
Two level routing hierarchies
• Intradomain: OSPF, IS-IS, and RIP
• Interdomain: BGP
• LPM: select the one with the largest number of matched
bits
interdomain
intradomain
2.2.3.*

2.2.2.* 2.2.2.2
 About the project at this point
Please go to
http://www.intel.com/design/network/products/
npfamily/sdk_download.htm
website and click on “IXA SDK 3.51 Tools
CD1 Part 1” to download IXP 2400 simulator
 Router Architecture Overview
• A historical Perspective
• NP-based Distributed Router Architecture
• Queuing Mechanisms: A quick review

References:
• H. Jonathan Chao, “Next Generation Routers”, Proceedings
of the IEEE, vol. 90, no. 9, September 2002.
• James Aweya, “IP Router Architectures: An Overview”,
Nortel Networks Ottawa, Canada, K1Y 4H7.
 A Historic Perspective
What’s inside a node? Conceptually there are
two components, known as control plane and
data plane components
• Control plane:
– Routing
– Signaling
– Building forwarding/label swapping table
• Data plane: packet processing
– Longest Prefix Matching/Label Swapping
– Demux and mux
 A Historic Perspective
• First Generation:

Memory CPU

NIC NIC NIC

 A Historic Perspective
• Second Generation:

Memory CPU

NIC NIC NIC

 A Historic Perspective
• Third Generation

Control Card

NIC NIC

NIC
Switch NIC
Fabric
NIC NIC
 NP-Based Distributed Router Architecture
• Third Generation Revisit:
Control Module

Routing
Engine MPLS Control Plane
Control
QoS/DiffServ

Forwarding Forwarding
Engine Cell / Packet Engine

QoS/DiffServ Enabled QoS/DiffServ Enabled

Switch Fabric
NIC NIC

Data Plane
 NP-Based Distributed Router Architecture
Network Interface Card (NIC):

Source: “Network Processors and Coprocessors for Broadband Network Applications,” T. A.

Chu, ACORN Networks
 NP-Based Distributed Router Architecture

Fast and Slow Paths:

Control Module

Routing MPLS
Engine Control
QoS/DiffServ

Forwarding Forwarding
Engine Cell / Packet Engine
QoS/DiffServ Enabled QoS/DiffServ Enabled
Switch Fabric
NIC NIC
NP-Based Distributed Router Architecture

• What is a Forwarding Engine?

– Embedded (multi)processor
• Cannot keep up with multigigabit rates
– ASIC
• Fastest, but
• High cost, long time-to-market, expensive, time-
consuming to change, little reuse across products,
requires expertise
– Network Processor
 NP-Based Distributed Router Architecture

Network Processor:
• Special purpose microprocessor optimized for packet
processing at high speed
– Higher speed than embedded processor with comparable prices
– Fully Programmable
• Not designed for a specific protocol but for general protocol
processing using RISC like instruction set
• Updating/adding protocol functions involves only software
changes
NP-Based Distributed Router Architecture

ASICs
Performance

Network Processors

General purpose/embedded
processors

Cost
 NP-Based Distributed Router Architecture
Challenges:
• A NPU has to perform pre-queuing packet processing
• Pre-queuing packet processing has zero-delay tolerance
• Traditional router design has been focused on the queuing management
and scheduling disciplines and pre-queuing packet processing has been
hard-wired
• Suddenly, one has to program the NPU to realize all the pre-queuing
functions originally done by ASIC
• One has to decide what should go to the fast path and what to the slow
path
• Function partitioning
– Between the control plane and data plane
– Among components in the data plane
– Among components in the NPU
become key issues for NPU programming
• Need a fast performance analysis methodology for quick decision
making
 NP-Based Distributed Router Architecture
NP Architecture:
• Micro-engines (MEs) can be configured to work in pipeline and/or parallel
• Each ME can be configured to support multiple number of threads
• Thread execution may be scheduled in various ways
• MEs share external resources
 Queuing Mechanisms – A Quick Review
• Input queuing 2 1

– FIFO in inputs
1
– Head of line blocking
(HOL) 58% utilization
[Karol 87]
– Not efficient use of
memory
– Scalable, simple
 Queuing Mechanisms – A Quick Review
• Output queuing
– Strictly non-blocking
– Not Scalable, complex
– Not efficient use of memory

Output Output Output

Queue Queue Queue
 Queuing Mechanisms – A Quick Review
• Virtual output queuing
– maintain virtual output queues at each input
– Eliminated HOL
– Not strictly non-blocking
– Much better than input queuing
 Queuing Mechanisms – A Quick Review
• Head of line blocking is eliminated

2 1

1
 Queuing Mechanisms – A Quick Review

• Still not strictly nonblocking as output queuing

2 1
 Queuing Mechanisms – A Quick Review
• Shared Memory
– Going across bus twice
– Both packet size and switch size determine
whether strictly non-blocking can be achieved.
– Efficient use of memory
1

2
3
 Queuing Mechanisms – A Quick Review

Queue management and Scheduling:

• Queue management: how the packets are queued and serviced

in a given queue, e.g., tail-drop, RED, WRED
• Queue scheduling: how the packets from different queues are
scheduled to be sent, e.g., strict priority, round-robin,
weighted fair queuing