Cairo University SPARC V2 (CUSPARC V2)

PROCESSOR
S. E. D. Habib*, Mohamed Wagih I Ismail, Ahmed Ibrahim S. Khalil, Ezz El-Din O. Hussein, Alhassan F. Khedr,
Safaa A. Abdelfattah, Ahmed Reda , and Mohamed Elgendy.
Electronics and Communications Engineering Department, Cairo University, Giza, Egypt
*Corresponding Author: seraged@ieee.org

Abstract- The Cairo University SPARC (CUSPARC) other blocks with a white background color are essentially
processor is an IP embedded processor based on SPARC V8 the same as in CUSPAEC V1 [1,2]. The following
ISA standard. It is fully developed at Cairo University and is paragraphs present the features of the main enhancements
the first Egyptian processor. CUSPARC was implemented on added to CUSPARC V2.
several FPGA and ASIC platforms. Its first ASIC version
(CUSPARC V1) was implemented on Si in 2010 using IBM
0.13ȝm CMOS 8RF-DM process.
This paper reports the design, fabrication and testing of an
enhanced version of CUSPARC, labelled CUSPARC V2.
CUSPARC V2 is augmented with an ADPLL, a hardware
multiplier, and four JTAG scan chains.

Keywords:
IP processors, Embedded processor, SPARC V8, CUSPARC,
ADPLL, JTAG.

I: INTRODUCTION
CUSPARC [1,2] is an intellectual property embedded
processor fully developed at Cairo University, Egypt. It
conforms to SPARC V8 ISA [3]. CUSPARC was
implemented on several FPGA platforms as well as on
IBM 0.13ȝm CMOS 8RF-DM process [2]. This early
ASIC implementation of CUSPARC processor is,
henceforth, labelled CUSPARC V1. A many-core
message-passing processor based on the CUSPARC V1
core was designed [4]. It consists of 16 cores arranged in
4x4 mesh architecture
This paper introduces the design, fabrication, and testing of
CUSPARC V2 processor. This V2 version integrates a 32
bit hardware multiplier, an All-Digital PLL, and four JTAG
scan chains with the CUSPARC V1 core. Section II
highlights the enhancements added to CUSPARC V2.
Section III outlines the design methodology adopted.
Section IV presents the performance measures of
CUSPARC V2, and compares them with other processors
manufactured at the same technology node. Section V
concludes this paper.
II: CUSPARC V2 ENHANCEMENTS
Fig.1 shows the overall CUSPARC V2 architecture. The
three blocks with a gray background color identify the
CUSPARC V2 enhancements over the V1 version. The
Fig. 1: CUSPARC V2 Architecture
A: HW Multiplier
An on-chip integer multiplier is added in
CUSPARC V2. Hardware multiplication enhances
Clocks Per Instruction (CPI), DMIPS/MHz, Power
efficiency metrics of the processor as well as its
performance for DSP applications.
The implemented multiplier is a single cycle 32-bit
multiplier that is optimized for the power-delay product. A
single cycle multiplier is selected rather than a pipelined
multiplier so as to keep the processor pipeline simple.
However, single cycle multiplier should be carefully
optimized to avoid significant decrease in the maximum
frequency of operation. Our final multiplier design uses a
simple partial product generator with (7;3) compressor for
the partial product accumulator. The final stage adder is a
ripple block-carry look-ahead adder [5,6].
B: All Digital PLL
On-chip frequency synthesizers are mandatory for

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processors working at frequencies exceeding ~ 300 MHz.
PLLs are typically used to implement these frequency
synthesizers. We opted for an All-Digital PLL design
approach for its ease of design and ease of portability
amongst different technology nodes. Fig. 2 shows a
simplified block diagram of the ADPLL architecture. Our
ADPLLs is built mainly of Digitally-controlled Oscillator
(DCO), Digital Loop Filter (DLF), and synchronization
blocks.
Our DCO is composed of many inverting delay sections
connected as a ring oscillator. Coarse control bits control
the number of sections in the ring. Additionally, fine and
very fine frequency control are affected via Digitally
Controlled Varactor (DCV) cells [7,8]. The DCO control
word is made of 44 control bits, of which 16 are for coarse
control, 12 for fine control, and 16 for very fine control. A
binary search algorithm is used to speed up the lock time.
A synchronizer is used to sample the reference clock by the
fast output clock of the DCO. This synchronizer represents
a compromise solution between the low performance bang-
bang phase detector and the high cost TDC. The digital
loop filter is a PI controller with an optimized digital
implementation to reduce the power consumption and
speed up the calculations.
Binary Search
Fref Ref Edge Shift R/L
Synchronization Algorithm
FSM
Div Edge
Phase Error Digital Loop Filter Shift R/L
(DLF)
Fraction
Fig. 2: Architecture of the implemented ADPLL
Several features were added to ADPLL to facilitate its
testing. Mainly, we augmented our ADPLL with an
internal custom scan path to control and initialize the
ADPLL operation. Using this scan chain, we can set the
ADPLL to work in open loop or closed loop mode. The
frequency multiplication ratio of the PLL can also be set
via this scan chain.
C: JTAG Scan chains
One boundary scan chain as well as three internal JTAG
scan chains are implemented in CUSPARC V2. The
boundary scan chain covers all I/Os of the chip. The
internal JTAG scan chains are organized as follows:
• Register file scan chain covering all registers of the
windowed register file of CUSPARC V2.
• Memory data and address (bus) scan chain, covering
the signals of the fast Wishbone bus of the
processor.
• Status and control registers scan chain.
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Fig. 3 depicts a bird’s view of how the three internal scan
chains of CUSPARC V2.
Fig. 3: Organization of the three internal JTAG scan chains
III: Design Flow
A classical digital design flow is adopted. Our RTL coding
style for CUSPARC is mainly structural. Standard cell
design flow is followed. ARM’s Artisan standard cell
library for IBM CMOS 130 nm 8RF technology is used in
this flow. Synopsys Design Compiler (DC) is used for the
synthesis process. Cadence SoC Encounter is used for
standard cell place and route. Mentor Graphics HDL
simulator ModelSim is heavily used at all design levels up
to full post-layout testing of full chip.
16
Coarse
SR
IV: Test Results and Performance Measures
Digital Controlled FDCO
Fine
16+12
Oscillator A: CUSPARC Test Board
(DCO)
SR
A test PCB is developed specifically to test the fabricated
CUSPARC chip. This board contains mainly the
єȴ CUSPARC chip, 256 Mbit flash memory, three 2Mx36 bit
SSRAM chips, Cyclone FPGA chip, 24 MHz crystal
Modulator
1st Order
oscillator, an RS232 interface, and 7 inch capacitive touch
LCD.
The configuration of this board allows several modes of
testing CUSPARC V2 chip. The processor bus is passed to
the FPGA to do glue logic operations. More importantly,
this passing of important processor signals to FPGA
enables us to monitor all the processor bus activities via the
SignalTap on-chip logic analyzer of Altera FPGAs. Also,
CUSPARC can run from small programs loaded inside the
FPGA built-in memory modules, independent of SRAM
and flash memories. Furthermore, the Digital Clock
management modules inside the FPGA allow very simple
way of testing the processor at different clock frequencies.
B: Core Testing
B.1 DMIPS/MHz
The Dhrystone metric {Dhrystone Mega Instructions Per
Sec (DMIPS)} is widely used to measure the performance
of embedded processors [9]. The DMIPS/MHz metric is
obtained from the following equation:
‫ܵܲܫܯܦ‬Ȁ‫ ݖܪܯ‬ൌ  ͳͲ଺ Ȁሺ‫ͳ כ ܯ‬͹ͷ͹ሻ
302
Where M is the number of clock cycles needed to execute simulations for the DCO output clock frequency variation
the Dhrystone program once. For CUSPARC V2, M was with the very fine control word showed that the very fine
determined to be 445 using SW simulations as well as HW control step in clock period is approximately constant at 2.6
testing. Therefore, the DMIPS/MHz rating for CUSPARC ps.
V2 is 1.279, compared with 1.025 for CUSPARC V1 [2].
The improvement of DMIPS/MHz for CUSPARC V2 is On the hardware test side, we tested the ADPLL under the
due to the implementation of the HW multiplier. same conditions, as shown in Fig. 7. The ADPLL was
configured via its scan chain to work in the open loop
B.2 Maximum Frequency of Operation mode. The coarse control word was scanned over its 16
Post-layout Modelsim simulation of CUSPARC V2 core settings, and the DCO output frequency was measured via
was carried out at the different process corners. At the the ADPLL divided output clock pin. These hardware tests
typical-typical corner maximum frequency is 188 MHz. revealed, as expected, some jitter in the output DCO
frequency. Therefore, for each control word, we have two
Hardware testing determined that the maximum frequency measured DCO output frequencies, the maximum
of the core clock is 188 MHz for the tested IC. measured frequency (max_measur) and the minimum
measured frequency (min_measur). The hardware DCO
B.3 Core Power Dissipation output frequency measurement is shown by the
Again, the power dissipation metrics for CUSPARC V2 are max_measur and min_measur traces of Fig. 8. The
evaluated using post-layout simulation in parallel with real measured DCO output frequency falls within the ss and ff
hardware testing. In both cases, the dynamic power technology corners
consumption is evaluated for the processor running the
Dhrystone V2.1 benchmark.
On the simulation side, the signal activity of the individual
nodes is extracted and passed to Synopsys PrimeTime tool
to evaluate the power consumption. On the hardware
testing side, a small resistor was inserted in series with the
1.2 V core supply. The processor ran the Dhrystone V2.1
in an infinite loop, and the DC voltage across this resistor
is measured. This test is repeated for several clock
frequencies, and the slope of the power- frequency curve is
calculated to yield the mW/MHz rating of the processor.
CUSPARC V2 scored 0.406 mW/MHz (including caches,
but excluding pads).

C: ADPLL Testing
C.1 ADPLL testing in open loop mode.
In the open loop mode, the DCO is working alone. The
phase (delay) detector, loop filter, and feedback divider are
bypassed, and the ADPLL reduces to the DCO alone. The
user inputs the DCO control word (44 bit, 16 coarse, 12
fine, and 16 very fine bits) via the ADPLL scan chain.
On the simulation side, we carried out detailed analog
simulations to characterize the DCO operation. Analog
simulations are necessary since the DCV cells cannot be
modeled in the digital domain [7]. Fig. 7 shows how the
clock frequency of the DCO varies with the coarse and fine
control words. Different curves in this figure correspond to
different coarse control values. For example curve labelled
C1 corresponds to coarse control value =1. For this case,
the DCO output clock varies with the fine control word (12
cases) as shown. The maximum clock frequency of the
DCO is ~ 340 MHz in tt corner. The clock period step is
almost constant, approximately 204ps for coarse tuning
step and 26.4 ps for the fine tuning step. Similar
Fig. 7: DCO Frequency Variation with Fine Cells
C.2: ADPLL testing in closed loop mode.
The ADPLL was simulated and hardware tested
successfully under closed loop conditions. The reference
clock was set to 24 MHz (crystal oscillator frequency on
the test PCB board), and the ADPLL multiplier was varied
to vary the processor’s core frequency.
D: CUSPARC Core and ADPLL test.
We carried out simulations and hardware testing for the
CUSPARC V2 core clocked by ADPLL in closed loop
configuration. The processor functioned correctly and ran
our set of benchmark programs successfully. Again, the
processor achieved a measured maximum frequency of
operation of 188 MHz.

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 This table shows that CUSPARC offers a good balance
between high total DMIPS, high maximum frequency of
operation, and high power efficiency DMIPS/mW. It
should be noted that the metric values for CUSPARC as
well as for the ARM and MIPS processors are for the cores
only excluding caches.

Fig. 8: Measured and simulated DCO output frequency with the
coarse control word.
E: Comparison of CUSPARC V2 with relevant
Processors.
Table 2 compares CUSPARC V2 and CUSAPRC V1 to
several famous ARM [7] and MIPS [8] cores. All these core
processors are implemented using 130 nm CMOS technology.
V: Conclusions
Version V2 of CUSPARC processor was designed,
implemented on Si using IBM 0.13ȝm CMOS 8RF-DM
process, and tested. This version features a HW multiplier,
an ADPLL and four JTAG scan chains. This processor
achieves a maximum frequency of operation of 188 MHz
together with a DMIPS/mW metric of 8.63.
Acknowledgements
The authors acknowledge a MOSIS MEP grant # 4960.
Also, the authors acknowledge the help of Mohamed
AbdElilah, Bassam Mohy Eldin, AbdElRahman
ElMashad, and Nagham Samir in the design of CUSPARC
test PCB and in testing of the processor itself.

Table 2: CUSPARC V2, V1, ARM and MIPS processors comparison

Feature CUSPARC CUSPARC ARM926EJ ARM968E ARM7TDMI MIPSM14K MIPSM14Kc
V2 V1
CPU ISA SPARC SPARC ARM/Thumb ARM/Thumb ARM/Thumb MIPS32 R2 MIPS32 R2
Arch. Width 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit 32-bit
Pipeline Depth 4 stage 4 stage 5 stage 5 stage 3 stage 5 stage 5 stage
Core Frequency(MHz) 188 260 238 297 184 100 100
Core Area(mm^2) 2.24 1.38 1.45 0.45 0.35 0.35 0.61
DMIPS/MHz 1.279 1.025 1.1 1.1 0.9 1.5 1.5
DMIPS at max. freq. 240.4 266.5 261.8 326.7 165.6 150 150
Power(mW/MHz) 0.148 0.11 0.36 0.14 0.18 0.12 0.14
Ef¿ciency(DMIPS/mW) 8.64 9.31 3.05 7.85 5.22 12.5 10.7

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