e-ISSN: 2582-5208

International Research Journal of Modernization in Engineering Technology and Science

( Peer-Reviewed, Open Access, Fully Refereed International Journal )
Volume:04/Issue:02/February-2022 Impact Factor- 6.752 www.irjmets.com

A LITERATURE REVIEW ON ASIC IMPLEMENTATION OF SUPERSCALAR

MICROPROCESSOR USING RISC V
Aman Shariff M A*1, Mohammed Maaz*2, Nidhith B R*3, Rohan C*4,
Prof. Mohamed Anees*5
*1,2,3,4Student, Electronics And Communication Engineering, Vidyavardhaka College Of Engineering,
Mysore, Karnataka, India.
*5Guide, Electronics And Communication Engineering, Vidyavardhaka College Of Engineering,
Mysore, Karnataka, India.
ABSTRACT
This project is on superscalar RISC-V architecture-based microprocessor RV32IMC. According to the literature
survey we noticed that the previously modified 32-bit RV32IMC which was implemented in FPGA has a
frequency of 50MHz, due to which the performance was not good enough for many higher applications as a
result we have decided to work on the performance aspect of the processor so that it would better support
other such higher applications.
Here in this project, we are trying to achieve the processor’s clock speed around 60-80MHz, by some research
and modifications in the physical design of the RV32IMC. Basically, we are implementing 3 to achieve a higher
performance we would need to compromise with the power and area aspects of the processor’s design.
In this project we will not be changing the RTL code of RV32IMC as we will be increasing the performance of
the processor by modifying physical design parameters like proper floor planning, placement etc. and we will
also do analysis for focusing more to overcome the problems that we will come across while increasing the
processor’s clock speed, problems like Noise etc.
I. INTRODUCTION
A Superscalar Processor is a CPU that implements a form of parallelism called instruction-level parallelism
within a single processor. In contrast to a scalar processor that can execute at most one single instruction per
clock cycle, a superscalar processor can execute more than one instruction during a clock cycle by
simultaneously dispatching multiple instructions to different execution units on the processor.
RISC-V is an open-source and royalty-free ISA (Instruction Set Architecture) standard. RISC-V ISA was a
university project that was developed by a group of professors taking in consideration with the high royalties
taken by Intel and ARM and hence was made open source, now many companies are investing in the
development of RISC-V ISA. It relies on the RISC architecture. This means that the hardware is less complicated,
and the instruction set contains fewer instructions, compared to a CISC architecture.
Physical design is the process of transforming a circuit description into the physical layout, which describes the
position of cells and routes for the interconnections between them. The main concern is the physical design of
VLSI-chips is to find a layout with minimal area. In short physical design means to convert netlist (. v) file into
GDSII file format (layout form) that is logical connectivity of cells converted into physical connectivity.

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 e-ISSN: 2582-5208
International Research Journal of Modernization in Engineering Technology and Science
( Peer-Reviewed, Open Access, Fully Refereed International Journal )
Volume:04/Issue:02/February-2022 Impact Factor- 6.752 www.irjmets.com
II. LITERATURE REVIEW
Roland Holler, Dominic Haselberger, Dominik Ballek, Peter Rossler,- Advances in semiconductor
miniaturization are an important driven for FPGA since their environment in 1980’s. This increasing number of
available on chip resources on one hand and on the other hand a decrease in part cost let the FPGA market
grow steadily in recent years, hence more and more microprocessor are integrated into programmable logic
devices. As this microprocessor represented as central unit in digital system. In parallel to this an Open-Source
RISC-V hardware community grow steadily hence more than 100 of open-source CPU Cores can be found and
due to this it was easy to select a specific core design for a particular project. The RISC-V CPU Core was tested
and was found that Freedom RISC-V CPU-IP Core, RISC Y RISC-V CPU-IP Core and Pico RV32 RISC-V CPU-IP
Core were suitable for FPGA.
Ben Keller, Martin Cochet, Brian Zimmer, Jaehwa Kwak, Alberto Puggelli, Yunsup Lee, implemented a RISC-V
Processor SoC With Integrated Power Management at Sub microsecond Timescales in 28 nm FD-SOI. A RISC-V
system-on-chip (SoC) with integrated voltage regulation, adaptive clocking, and power all these things are been
implementing in a 28 nano-meter fully depleted silicon on-insulator process. Dc to dc converter supply an
application core using clock, it uses a clock from a free running adaptive clock generator by which it is able to
achieve high system conversation energy (82 to 89%) and energy efficiency while delivering up to 231 mill
watts of power. While an adaptive voltage scaling algorithm reduces energy consumption by 39.8% with
negligible performance penalty.
Mrs. Rupali S. Balpande, Mrs. Rashmi S. Keote, worked on Design of FPGA based Instruction Fetch & Decode
Module of 32-bit RISC (MIPS) Processor. Instruction Fetch module include fetch instruction and latch module
addresses, an arithmetic module check and a validity of instruction module and synchronous control module.
The instruction decoder module is based on 32-bit CPU by pipeline theory, it includes register file, write back to
register file, signed bit extend relatively check and it is simulated on QuartusII successfully. Static time
sequence shows the instruction fetch & decode module completing required function. They adopted top-down
method and have used VHDL to describe the system. The result indicates IF stage completes prospective
function.
Ruiyang Zhu, Meitang Li, Tianrong Zhang, Yuan Shen, Kangjia Cai, implemented a Two-way Superscalar
Processor with Out-of-Order Execution and Early Branch Resolution. The main aim was to increase the speed of
the processor. They adopted RISC-V architecture and Implemented using R10K algorithm because of its
elegance compared with other algorithms. They included early branch resolution as it helps in achieving better
performance, they also implemented a two-way superscalar out-of-order execution and have tested this in
system Verilog HDL. Synthesize of the processor was done with a clock period of 10.6 nano-seconds. The results
were successful achieving 160 percent of speedup when compared to a traditional 5-stage in-order pipeline
processor.
Gokulan T, Akshay Muraleedharan & Kuruvilla Varghese, has implemented a 40 MHz, 32-bit, 5-stage dual-
pipeline superscalar processor based on RISC-V Instruction Set Architecture. It supports integer, multiply-
divide and atomic read modify-write operations. The proposed system implements in-order issuing of
instructions. The interrupt controller supports four levels of pre-emptive priority, which is programmable for
individual interrupts. Error control module provides single error correction and double error detection for the
main memory. Wishbone B.3 bus standard is adopted for on-chip communication. The processor is
implemented on Virtex-7 XC7VX485TFFG1761-2 FPGA based board. CoreMark and Dhrystone benchmark
values for the design are 3.84/MHz and 1.0603 DMIPS/MHz respectively. In this paper, a 32-bit superscalar
processor with two 5- stage pipelines are presented. It implements the RV32IMAFD extension of RISC-V ISA.
This work is focussed on improving the throughput by incorporating additional functionalities to the scalar
processor. The processor is designed in Verilog using Xilinx Vivado 2018.2 and is implemented on Virtex-7
XC7VX485TFFG1761-2 FPGA based board. The maximum achievable frequency with this FPGA is 40 MHz A 32-
bit, single core, dual-pipeline, superscalar architecture is discussed in this paper.
Shashi Kumar V, Gurusiddayya Hiremath, implemented a RISC processor with low power optimization
techniques. To minimize the power of the processor techniques as clock tree optimization and clock gating to
reduce dynamic power along with Multi-Vth, Power Shut Off (PSO) and Multi Supply Voltage (MSV) to reduce
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 e-ISSN: 2582-5208
International Research Journal of Modernization in Engineering Technology and Science
( Peer-Reviewed, Open Access, Fully Refereed International Journal )
Volume:04/Issue:02/February-2022 Impact Factor- 6.752 www.irjmets.com
leakage power are proposed. Synthesis is done using Encounter RTL Compiler to generate netlist at the gate
level and the back-end flow of VLSI design is carried out on Cadence Encounter Digital Implementation System
using the power intent captured by the Common Power Format (CPF) which aid in the low power
implementation the processor. low power techniques are accompanied by entanglement and issues of its own,
but it is possible to resolve these issues with the right methodology, awareness about low power, tools and
standards.
Michael Joseph Neri, Victor Emmanuel Baylosis, Phoebe Meira Chua, Allen Jason Tan and Redentor Immanuel
Ridao, has worked on A Five Pipelined Superscalar RISC - V RV32IMC processor implemented on a Digilent Arty
A7 Board with a Xilinx Artix-7 FPGA. The main objective was to check the processor’s speed along with its
computational capabilities for its usage in IoT applications, the serial communication protocols were checked,
it’s power consumption and Timing. The Model design obtained a frequency of 50 MHz when run in the
specified FPGA. The model also has a functional interrupt handling scheme and supports communication
through the I 2 C, SPI, and UART protocols.
Dominik Langen, & Jorg-Christian Niemann, et.al.[8] has implemented a RISC in both FPGA Prototype and ASIC
Implementation in a 0.6µm and an 0.13µm technology, respectively. The core was developed by using the
hardware description language VHDL. The effects on the features like area and power consumption as well as
computational power are analysed. A Motorola M-core processor was selected, A S-core processor was
developed using VHDL, such that it is binary compatible with the Motorola’s M-Core architecture. Thus,
enhancing the opportunity to add special hardware blocks and make use of the 11% unimplemented opcode
space. A comparison to a ASM 0.6µm technology realization has demonstrated the improvements in area and
power consumption as well as a remarkable increase of the maximum clock frequency. Addition of special
hardware blocks increases the computational power of the core. Proving that the S-core is a good fit for this SoC
design and a good choice for multiprocessor implementation.
III. OUTCOME OF THE LITERATURE REVIEW
 IP Core that are suitable for FPGA, and we also got to know about the importance of open-source RISC-V
architecture.
 The reduction in power consumption, causes in compromise with the processor’s performance
 The modules present in instruction fetch and decoder module and their working.
 The working of a Two-way Superscalar microprocessor, Out of Order execution and the different methods
used to improve the speed of the processor.
 Overview about 5-stage superscalar pipeline. The operating frequency and various other aspects such as
FPGA used were identified.
 We learnt power optimization techniques used to minimize the power of the processor.
 Outcome about processor’s behaviour performance, power consumption and timing aspects changes and
got to know the computational capabilities of a Five Pipelined Superscalar RISC - V RV32IMC processor for
the application of IOT and serial communication.
 The difference in FPGA and ASIC Implementation, and the improvements in the area and power
consumption.
IV. REFERENCES
[1] Roland Holler, Dominic Haselberger, Dominik Ballek, Peter Rossler “Open-Source RISC-V Processor IP
Cores for FPGAs”, Department of Electronic Engineering University of Applied Sciences Technikum
Wien Hochstadtplatz 6, 1200 Vienna, Austria, 2019.
[2] Ben Keller, Martin Cochet, Brian Zimmer, Jaehwa Kwak, Alberto Puggelli, Yunsup Lee “A RISC-V
Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm”, Members
and Student Members of IEEE, 2017.
[3] Mrs. Rupali S. Balpande, Mrs.Rashmi S. Keote “Design of FPGA based Instruction Fetch & Decode
Module of 32-bit RISC (MIPS) Processor”, Electronics Engineering Department. Yeshwantrao Chavan
College of Engineering. Nagpur, India.
[4] Ruiyang Zhu, Meitang Li, Tianrong Zhang, Yuan Shen, Kangjia Cai “A Two-way Superscalar Processor
with Out-of-Order Execution and Early Branch Resolution”, UNIVERSITY OF MICHIGAN – COMPUTER
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 e-ISSN: 2582-5208
International Research Journal of Modernization in Engineering Technology and Science
( Peer-Reviewed, Open Access, Fully Refereed International Journal )
Volume:04/Issue:02/February-2022 Impact Factor- 6.752 www.irjmets.com
ARCHITECTURE (EECS 470), 2020.
[5] Gokulan T, Akshay Muraleedharan, Kuruvilla Varghese “Design of a 32-bit, dual pipeline superscalar
RISC-V processor on FPGA”, IEEE - Electronic Systems Engineering, Indian Institute of Science,
Bangalore, INDIA - 2020 23rd Euromicro Conference on Digital System Design (DSD), 2020.
[6] Shashi Kumar V, Gurusiddayya Hiremath, “Low Power Implementation of RISC-V Processor”, IOSR
Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 3, Ver. II, May-Jun-2016.
[7] Michael Joseph Neri, Redentor Immanuel Ridao, Victor Emmanuel Baylosis, Phoebe Meira Chua, Allen
Jason Tan “Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for
Large-Scale Wireless Sensor Networks”, IEEE REGION 10 CONFERENCE (TENCON) Osaka, Japan,
November 16-19, 2020.
[8] Dominik Langen, Jorg-Christian Niemann, Mario Porrmann, Heiko Kalte, Ulrich Ruckert Heinz Nixdorf
Institute, “Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC
Implementation” IEEE Bielefeld University of Paderborn Paderborn, German, 2018.

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