[1] Sarika U. Kadam, S. D.

Mali, “Design of Risc Processor using VHDL”, 2016International Journal of

Research Granthaalaya, Vol.4 (Iss.6): June, 2016, DOI:10.5281/zenodo.56647.

A RISC processor using VHDL was designed in 2016 by Sarika U. Kadam, S.D. Mali. The 16-bit RISC
processor under consideration is created using VHDL, a parallel programming language. With Xilinx
ISE 13.1i, it is both synthesised and simulated. Pipelining is a technique for speeding up processors.
Pipelining breaks up an instruction cycle so that multiple instructions can be executed
simultaneously. Several instructions are made specifically for these CPUs. Moreover, multiplier was
created using ADD guidelines. Every instruction is successfully replicated. Simulation outcomes
demonstrate the proposed processor's proper operation. The suggested processor operates at
210.775 MHz and has a 4.744 ns delay. It is evident by comparing the proposed work to earlier
processors that the suggested processor has less. Comparing to this in our project the delay has been
reduced.

Swati Joshi1,Sandhya Shinde2, Amruta Nikam3, 32- Bit Pipeline RISC Processor in VHDL using Booth
Algorithm, e-ISSN: 2395 -0056, 2016

When factors like limited power are taken into account for cyclic controlling and encoding.The
problems in classic RISC architecture can be attributed to the quantity of stages (pipelines).Problems
with speed and performance are resolved. Considering that the architecture of general-purpose
processors now heavily emphasises power. Reduced power usage contributes to longer battery life,
less heat generation, and greater gadget dependability. By using numerous low power techniques,
such as the Booth Multiplier, the minimising of power dissipation is accomplished at multiple design
process levels. The advantage of this paper is they used finite state machine for instruction decoding
and generation of new control statement according to pipeline sequence, so synchronization
problem is resolved. The disadvantage of this paper is they do not eliminate control hazard.

M. N. Topiwala and N. Saraswathi, "Implementation of a 32-bit MIPS based RISC processor using
Cadence," 2014 IEEE International Conference on Advanced Communications, Control and
Computing Technologies, Ramanathapuram, India, 2014, pp. 979-983, doi:
10.1109/ICACCCT.2014.7019240.

This paper describes the development of a 32-bit, 5-stage pipelined, MIPS-based RISC core. A RISC
(Reduced Instruction Set Computer) architecture is the MIPS (Microprocessor without Interlocked
Pipeline Stages) architecture. A RISC is a type of microprocessor that was created to carry out a
condensed set of instructions in order to boost the processor's overall speed. Instruction Fetch (IF),
Instruction Decoding (ID), Execution (EX), Memory Access (MEM), and Write Back (WB) modules
make up the five phases of the MIPS pipeline. Instruction Memory, Data Memory, ALU, Registers, and
other modules are employed. The goal of this study is to implement the pipeline efficiently by
incorporating the Hazard detecting unit and Data forwarding unit. Verilog-HDL is used in the design's
development. The major objective is to use the Cadence tool to complete the ASIC flow (RTL to GDS
II). Using the usual libraries of tsmc 0.18 um technology, the module functionality and performance
issues of area, power consumption, and propagation delay are examined.
Mrs. Rupali S. Balpande,Mrs. Rashmi S. Keote, “Design of FPGA based instruction Fetch and Decode
Module of 32-bit (MIPS) processor,” International Conference on communication Systems and
Network Technologies,DOI:10.1109/CSNT.2011.91,2011

: The paper proposes 32-bit RISC processor with floating point arithmetic for high speed and low
power consumption .It is having five stage pipelining which is designed using VHDL. Number of
instruction are designed for this processors. We use 5-stage pipelining which involves instruction
fetch module, instruction decode, module, execution module, memory i/o and write block. This
paper focuses on the decoder unit which is having different instruction formats for different type of
instructions. The advantage of this paper is decoder module by the use of instruction formats (R-
type, I-type, J- type, I/o-type) and datapths ,the execution of any instruction becomes faster and
errorless. It is easy to edit &debug.

Vishwas V.Balpande ,Vijendra P.Meshram,Ishan A. Patilm,Sukeshini N.Tamgadem,Prashant Wanjari,

“Design and Implementation of RISC processor on FPGA”,

The proposed article uses VHDL programming to design a 16-bit RISC processor. To increase total CPI
(Clock Cycles per Instruction), pipelining is employed in four stages (instruction fetch stage,
instruction decode stage, execution stage, and memory/IO - write back stage). In contrast to
traditional CISC processors, which use microprogrammed control, the control unit is designed using a
hardwired control technique. Implementing a prefetch unit mitigates structural risks, forwarding
mitigates data risks, and flushing and delaying mitigate control risks. VHDL is used to model and
simulate the design before a successful FPGA implementation. The Spartan-II FPGA from Xilinx
operates at a maximum frequency of 26 MHz.