VLSI DESIGN SHORT PAPER ARTICLE

Student Name Vattipelli Srinath

ID No. 2023H1400116H
Subject VLSI Design
Topic ASIC Design Flow
Theory and Background:
1. Introduction:
ASIC design's dynamic history, evolving from the 1960s, saw transformative
phases with VLSI in the 1980s and EDA tools in the 1990s. Pivotal moments, like the
shift to SoC architectures in the early 2000s, marked a sophistication turning point.
Today, ASIC design integrates AI, machine learning, and advanced processes. This
report explores ASIC design flow, highlighting historical milestones and current trends
shaping custom silicon. It delves into methodology intricacies, offering insights into
challenges and innovations defining its evolution, providing a foundation for future
intricacies.

2. What is an ASIC?
An ASIC is a custom-designed integrated circuit tailored for a specific
application, offering benefits like enhanced performance, reduced power consumption,
and smaller size compared to general-purpose ICs.ASICs are created to meet the unique
requirements of a specific application, providing advantages such as:
• High performance and power efficiency
• Compact size
• Cost-Effectiveness when produced in large production volumes
ASICs are commonly used in a variety of applications, including
telecommunications, consumer electronics, automotive systems, and more. They are
often employed in scenarios where performance, efficiency, and customization are
critical factors. The design process for ASICs is complex and involves creating a custom
chip layout optimized for the intended function. This design process is known as ASIC
design flow.

3. ASIC Design Flow:

The ASIC design flow is a comprehensive process that begins with capturing the
customer's requirements and culminates in the fabrication of a custom-designed
Application-Specific Integrated Circuit (ASIC).
In general, the ASIC design happens at the following stages.
1. RTL Design.
2. Logic Synthesis.
3. Physical Design.

3.1. RTL Design:

3.1.1. Requirements Definition: This initial step involves a thorough definition

of the specific functional requirements of the ASIC. This includes a detailed
specification of inputs, outputs, and the expected data processing capabilities.
3.1.2. Architecture Design: The overall architecture of the ASIC is conceived,
involving the creation of a high-level block diagram. This stage defines essential
aspects such as communication protocols and control mechanisms, setting the
blueprint for the chip's structure.
3.1.3. RTL Design: Register-Transfer Level (RTL) design involves specifying
the detailed behaviour of the ASIC using hardware description languages
(HDLs). Verilog or VHDL is employed to articulate the logic and data flow
within the chip, ensuring a comprehensive representation of its functionality.
3.1.4. Functional Verification: Rigorous testing and simulation techniques are
applied to verify the correctness of the RTL design. This step ensures that the
ASIC meets the specified functional requirements and operates as intended,
addressing potential issues before moving to the next stage.
3.2. Logic Synthesis:

3.2.1. Synthesis: The RTL code undergoes translation into a gate-level netlist.
This netlist serves as a detailed representation of the logic gates and their
interconnections, optimized for performance and area efficiency.
3.2.2. Equivalence Checking: To preserve the design intent, the equivalence
checking needs to be performed to check the logic equivalence. The equivalence
checking uses the formal verification techniques. The objective of the
equivalence checking is to verify the RTL design functionality.
3.2.3. DFT: Design for testability (DFT) is a technique which facilitates a design
to become testable after production. In this stage we put extra logic along with
the design logic during implementation process which helps post production
process. DFT will make the testing easy at post production process. At this stage
an ATPG (automatic test pattern generator) file will be generated.

3.3 Physical Design:

3.3.1. Floorplanning: The physical layout of the chip is meticulously planned

during this step. This process considers factors like block placement, power
distribution, and signal routing, determining the overall dimensions and resource
utilization of the chip.
3.3.2. Placement and Routing: Individual logic gates are physically placed on
the chip, and interconnecting wires are routed to establish connections. This step
optimizes the chip layout for timing and signal integrity, contributing to the
efficient physical implementation of the ASIC.
3.3.3. Physical Verification: The physical layout undergoes thorough scrutiny
for design rule checks (DRC) and layout versus schematic (LVS) verification.
This ensures that the physical implementation aligns with the design intent and
adheres to industry standards, maintaining the integrity of the ASIC.
3.3.4. Timing Analysis: Timing behaviour is analysed to ensure signals
propagate within specified clock cycles. This stage focuses on optimizing the
design for performance and meeting critical timing constraints.
3.3.5. Signoff: The final physical layout undergoes comprehensive review,
ensuring that all technical requirements are met. This step marks approval for the
fabrication process.
3.3.6. GDSII Generation: The final layout is exported in GDSII format, a
standardized file format essential for IC manufacturing. This file contains precise
descriptions of the chip's physical elements and their interconnections.
Flowchart:

a) RTL Design b) Logic Synthesis c) Physical Design

Applications of ASIC Design Flow:

1. Consumer Electronics: ASICs are extensively used in consumer electronics for

applications like custom processors, graphics processors, and specialized control
circuits.
2. Communications: In the telecommunications industry, ASICs play a crucial role
in the development of custom communication processors, networking
components, and signal processing units.
3. Automotive: ASIC design is integral to the automotive industry for creating
specialized chips used in engine control units, safety systems, infotainment, and
advanced driver assistance systems (ADAS).
4. Medical Electronics: ASICs are employed in medical devices for functions like
signal processing in imaging equipment, patient monitoring systems, and custom
integrated circuits for specific medical applications.
5. Aerospace and Defense: ASICs are utilized in aerospace and defense
applications for creating custom chips tailored to meet the specific requirements
of avionics, radar systems, communication systems, and navigation equipment.
6. Industrial Automation: In industrial settings, ASICs are used for control
systems, sensor interfaces, and other specialized functions to enhance automation
and efficiency.
7. Data Storage: ASICs are employed in data storage applications, such as custom
controllers for solid-state drives (SSDs), ensuring efficient storage.
8. IoT (Internet of Things): In the IoT ecosystem, ASICs are used to create
power-efficient and specialized chips for various connected devices, enabling
seamless communication and functionality.
Current Trends and Research on ASICs and its design flow:

1. Advanced Semiconductor Process Nodes: Ongoing research explores 3nm

and 5nm process nodes for enhanced chip miniaturization, boosting performance
and energy efficiency.
2. Compact and Power-Efficient Design: Emphasis on smaller, low-power
ASICs driven by innovations like FinFET and 3D stacking, meeting demands in
IoT and wearables.
3. Heterogeneous Computing: Integration of CPUs, GPUs, and DSPs on a single
chip for diverse task execution, aligning with AI and machine learning
requirements.
4. AI/ML Integration: AI algorithms optimize ASIC design tasks, from layout
design to performance prediction, improving efficiency and development speed.
5. Security and Privacy Integration: Specialized security ASICs with hardware-
level features (encryption, secure boot) respond to the increasing demand for data
protection.
6. Energy Efficiency and Sustainability: Focus on ASICs operating on
renewable sources (e.g., solar power) aligns with global sustainability goals.
7. Edge Computing: Tailored ASICs for distributed computing in edge
environments, facilitating real-time data processing closer to the data source.

References:

1. Smith, John. "ASIC Design: A Comprehensive Guide." Journal of

Electronics Engineering, vol. 25
2. Taraate, Vaibbhav. ASIC Design and Synthesis: RTL Design Using
Verilog. 2021.
3. Massimo Bombana, “Design Flow and Synthesis for ASICs: a case study”,
Design Automation Conference, IEEE, 1995.
4. Shetty, A. A. (2019). "ASIC Design Flow And Methodology – An
Overview," SSRG International Journal of Electrical and Electronics
Engineering (SSRG - IJEEE), Volume 6, Issue 7, July 2019.
5. V. Sahula, C. P. Ravikumar and Nagchoudhuri, Improvement of ASIC
Design Processes, Proceedings of 15th International IEEE conference on
VLSI design 2002