DIGITAL INTEGRATED

CIRCUIT (IC) DESIGN

Physical Aware Digital System Design

ISaac
Intelligent Systems and Advanced Computing

W A T Mahesh Dananjaya
dananjayamahesh@gmail.com
ISAAC – Intelligent Systems and Advanced Computing

DIGITAL INTEGRATED
CIRCUIT (IC) DESIGN
ISAAC

Intelligent Systems and Advanced Computing

W A T Mahesh Dananjaya

Department of Electronic and Telecommunication Engineering

University of Moratuwa

Sri Lanka

(dananjayamahesh@gmail.com)
ISAAC – Intelligent Systems and Advanced Computing

Contents
1 Integrated Circuit Design ................................................................................................................ 3

2 Digital Integrated Circuits ............................................................................................................... 5

2.1 Electronic System Level........................................................................................................... 6

2.2 RTL Design ............................................................................................................................... 6

2.3 Physical Design ........................................................................................................................ 6

3 Physical Design ................................................................................................................................ 6

3.1 VLSI Physical Design ................................................................................................................ 6

3.2 Physical Design Step Nodes .................................................................................................... 8

3.3 Technology Library Support .................................................................................................... 8

3.4 Design Categories Based on the Physical Design Flow ........................................................... 9

3.4.1 Full Custom Design .......................................................................................................... 9

3.4.2 Semi-Custom Design ....................................................................................................... 9

3.4.3 Pre-Cast Designs.............................................................................................................. 9

3.5 Illustration of the Physical Design Steps ............................................................................... 10

3.5.1 Floor Planning ............................................................................................................... 10

3.5.2 Clustering or Partitioning .............................................................................................. 11

3.5.3 Placement ..................................................................................................................... 12

3.5.4 Clock Tree Synthesis (CTS) ............................................................................................ 13

3.5.5 Routing .......................................................................................................................... 15

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1 Integrated Circuit Design

Integrated circuit design is becoming much more complicated task as design extended across
very large scale integration and technology scaling makes the chip density higher. Therefore
nowadays chip design is concern the optimal tradeoff between various facts such as
performance, power, area etc.

USER DESIGNER

Modern integrated circuits consist of miniaturized electric components built into an

electric network on a monolithic semiconductor substrate by photolithography techniques.
Integrated circuit design has evolved through some eras and nowadays Very Large Scale
Integration (VLSI) is also feasible and available. However there are two major portions of the
IC design in their nature.
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Integrated Circuits

Analog IC Digital IC

And also modern IC design compromise to several common stages in both digital and analog
format. But processes carried out by different stages could be varying due to their nature.

General Integrated Circuit Design Steps are as follows whether it is a digital or an analog one.
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2 Digital Integrated Circuits

Digital Integrated Circuits deploys only few discrete states of transistors. Digital
Integrated Circuits nowadays consist of billions of transistors with Very Large Scale Integrity
(VLSI). Digital IC design refer to production of components such as Microprocessors,
Memories (RAM, ROM and FLASH), FPGA, ASIC, SOC, NOC and MPSOCs. Digital design
mostly focuses on

o Logical correctness
o Maximizing circuit density
o Placing circuits in a way so that clock and timing signals can be routed efficiently.

Digital Integrated circuit design flow can be categorized into three main sub domains,

o System Design
o RTL Design
o Physical Design

Then we have a fabrication process that is common for both digital and analog circuits design.

And also this design flow can be classified as three separated design perceptions

o Front-End Design- System Design and RTL design

o Back End Design-Physical Design

Digital Design

Front-End Design Back-End Design

System Design RTL Design Physical Design

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2.1 Electronic System Level

System level functionalities and specifications are completed at this stage. This is the
stage that define overall system functionalities and modular functionalities where designer
finalize what to design. It may be a pseudo model, but most of the time various programming
languages and tools are used to model the system such as C,C++ model, SystemC, System
Verilog transactional level, Simulink and MATLAB. System level modeling with basic
functional cores are the foundation of any digital design. With the support of the programming
languages we have to model the system with algorithms. If it fails we should never go ahead
upon design flow.

2.2 RTL Design

Stage where user specification are mapped into the Register Transfer Level (RTL) description.
This describes the behavior as well as the structure of the digital circuit designs on the chip as
well as interconnection and outputs. Verilog, System Verilog and VHDL are common
languages used for modelling at this stage.

2.3 Physical Design

Stage of the chip designs according to the predefined set of guide lines. This takes the RTL
design, technology libraries provided with relevant technology cells, course of constraints and
design the chip. This stage defines the chip which gates to use, how much area need, where to
place cells and how to wire them together in a limited area. Then the designers can analyses
performance, speed, cost and area. But physical design flow doesn’t affect the functionalities
at all.

3 Physical Design
3.1 VLSI Physical Design
VLSI physical designs process is lying between synthesis process and fabrication
process. The design come out from the physical design layer can be directly used to fabrication
process. Although physical design is organized as a single component, it consist of several
different and significant design steps. Physical design steps belong to back-end design stage
and it is totally depends on the results given by synthesis process. And also tech library support
is paramount important for the physical design stage to reserve area, power and lesser cross
talks. Clustering, floor planning, placing, routing, clock tree synthesis (CTS) are the major
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physical design steps. Following diagram illustrate the position of physical design in the
common ASIC design flow.

Design Specification

Architectural Design

RTL Modeling

Synthesis

Physical Design

Layout sign off

Fabrication

Package and Test

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3.2 Physical Design Step Nodes

Partitioning and Clustering

Floor Planning

Placement

Clock Tree Synthesis

Signal Routing

Timing Closure

3.3 Technology Library Support

There are two part of the technology libraries that are used by two different design stages, front-
end and back end, of the development cycle. LIB part of the technology library is used for the
synthesis process which basically the front end design. And the LEF (Layout Exchange
Format) is used for the physical design flow which is basically the back end design consist of
clustering,
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3.4 Design Categories Based on the Physical Design Flow

Although two main categories exist in the past nowadays designers identify three major
categories of the design.

o Full Custom
o Semi-Custom
o Precast

3.4.1 Full Custom Design

Designers have the complete flexibility for their layout (physical) design. There are no
predefined cells to be used for the design. As a example ASIC designs are vulnerable for
full custom designs. There any cells that obey to DFM can be used dynamically according
to designers specifications admitted with the tech libraries.

3.4.2 Semi-Custom Design

Pre-defined library cells are used which have been tested with DFM (Design for
Manufacturability). Designers have the flexibility in placement and routing. Size of the
cells depends on the design specifications and requirements of the designers. IP cores are
the emerging semi-custom designs. As an example ARM cores.

Semi-custom designs are becoming significant to electronic revolution in the recent

history as it fasten the manufacturing and design process as well as reducing time to market.
Semi-custom designs are popular because design companies are supported to face the
competition with other companies.

There are two types of semi-custom designs.

o Fabricated
o Fables

ARM cores are fabless cores and some cores are fabricated and sometimes they are used for
the SOC (System on Chip) design.

3.4.3 Pre-Cast Designs

Pre cast means designers cannot define any physical layer content and cells to be used.
They have been specified with the relevant technologies. Designers only have access to the
modelling level and synthesis level with limited specifications with general components. No
technology libraries that are specified by the designers, are going to be used for the physical
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layout. Most of the time reconfigurable technologies such as FPGAs are categorizing into this
specific group. This technologies are based on the trial and error approach and used for research
and academic purposes. But in the recent history they have been deployed for some commercial
level applications.

3.5 Illustration of the Physical Design Steps

3.5.1 Floor Planning
Floor plan is the physical plan of the chip. In other way it is the initial phase of the physical
synthesis process. In the floor plan phase,

o Physical plan of the chip

o Size of the die
o Boundaries and core area
o Wire tracks
o Pin locations
o Positioning of blocks/macros on the die

Is carrying out according to the input constraints given by the designers.

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Initial Process of the physical design is to convert synthesized logic cells into structures of
actual physical dimensions in the way that they suit to place to achieve best functionality. Floor
planning is the process of identifying physical structures and allocate area and other resources
to optimize the performance and chip size and also to decide the I/O structure and the aspect
ratio. Based on the area and the physical hierarchy floor plan will be designed and optimized.
This is the phase of identifying hard macros to the design used in design, memory and other IP
cores and placement requirements and routing possibilities. Therefore we need some input and
constraints to plan the floor.

o Size of the chip

o Aspect Ratio: Horizontal routing resources and vertical routing resources
o Core Utilization: Standard cell area and core area
o Technology: .lib or tech file
o Power
o I/O constraints

This phase of better floor planning need to avoid the unnecessary wastages in chip/die
area and also to avoid routing congestions. Actual main concern when doing floor plan is the
tradeoff between area and the speed. This because due to placement potential and routing
resources available for routing. Best floor planed design may lead to less connection lengths,
reduction in area, shorter interconnect distances, modules/structures of the design to be much
closer, faster end-to-end signal flow paths and less routing resources to be used. This well
planned floor will cause to consistent and compromised placing and routing time. Especially
in routing when data path designing it causes to less interventions and congestions.

3.5.2 Clustering or Partitioning

Partitioning is the process of dividing chip into sub-blocks. After synthesis process the
logic cells are matched into a millions and billions of semiconductor layer devices. Designing
the physical layer with placing and routing becomes a critical problem in complex ICs.
Therefore as a pragmatic remedy designers divide the complete design problem into different
sub problems by partitioning the physical layout according to few paramount important factors.
Divided the synthesized logic cells into separate partitions in such a way that each partition has
a separate set of logic cells and minimum connections from it to outside partitions. Number of
connections are the basic concern here because placing and routing is basically depends on the
number of cells and routes they have. With this partitioning strategy floor planning, placing
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and routing also becomes sub system problem and we only need to optimize those things within
the cluster/partitions. Therefore it is easier to placement and routing. Then we can integrate
them into build the complete physical layout or top level module.

3.5.3 Placement
Placement is the process of placing each and every physical cell inside the physical
layout according to the floor plan specifications. In this phase standard cells of each
frame/platform are placed using partitioned Design Exchange Format (DEF). In this step all
cells placed within rows of the chip area/die and also route channels between rows to
interconnect them.

o Standard Cell placement of each frame/platform using partitioned DEF

o Scan re-routing based on location of scan flops
o Parasitic extractions

Those are the few steps in this stage. And also there are some optimizations carrying out at
this stage.

o Static Time Analysis (STA) with ideal clock and estimated wire parasites based on
placement
o Fix timing issues

Placement process is based on the hierarchical view and dependencies between cells according
to their functions and layout. Placement process is optimized according to the physical
resources. Placement stage consist of four major phases.

o Pre-Placement Optimization
o In Placement Optimization
o Post- Placement Optimization (PPO) before clock tree synthesis (CTS)
o PPO after CTS

Pre-Placement Optimization: Optimize the netlist before placement. HFN are collapsed. It can
also downsize the cells.

In-Placement Optimization: Re-optimize the logic based on virtual route VR.in this stage
various functions are carrying out.

o Cell sizing
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o Cell moving
o Cell Bypassing
o Net Splitting
o Gate Duplication
o Buffer Insertion
o Area Recovery

Optimization performs iteration of set up fixing, increment timing and congestion driven
placement.

Post Placement Optimization: This is done before CTS performs netlist optimization with ideal
clock. It can fix setup, hold, max trans/cap violation. This process include optimization based
on global routing.

Post Placement Optimization: This is carrying out after CTS optimizations timing with
propagated clock. It tries to preserve clock skew.

3.5.4 Clock Tree Synthesis (CTS)

Clock is the caliber behind the sequential digital designs. Building a clock throughout
a complex design and synchronize the clock signal is paramount important to have a good
performance. Therefore building the clock tree is important. Buffer insertion in clock path so
that all sequential elements receive the clock at the same time. This is very crucial for faster
timing closure.

CLK
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Importance and goal of having CTS is to minimize skew and insertion delay.
After CTS hold slack should improve. Clock tree begins at defined clock source and
ends at stop pins of flops. There are 2 types of stop pins.

o Ignore pins
o Sync Pins

If clock is divided then separate skew analysis is required. Another important parameter is that
area overhead by clock shielding so that the noise is not coupled to other signals. Therefore we
can optimized the CTS by shielding the clock which is known as Clock Tree Optimization
(CTO). This also can be achieved by optimizing,

o Buffer sizing
o Gate sizing
o Buffer relocation
o Level adjustments
o HFN synthesis

We try to improve setup slack in pre-placement, in placement and post placement optimization
before CTS stages while neglecting hold slack. In post placement optimization after CTS hold
slack is improved

3.5.4.1 Clock Tree Constraints

o Clock insertion Delay: consideration of propagation of clocks from clock source
to flop.
o Clock Skew: Difference in propagation time due to various reasons such as
Bandwidth differences to the sequential flops in the same tree hierarchy.
o Maximum Transition Time: Clock is alternative signal that transition various
upon internal capacitance of pins and wires.
o Clock Tree Power

3.5.4.2 Clock Tree Power

There are typical reasons to have varying power on clock process upon cells.

o Clock Gating Cells

o Minimum number of clock components before clock gating elements
o Improving clock latency
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3.5.5 Routing
Routing is the process of establishing connection between placed components on the
physical layer via top metal layers. There are lots ways to do the routing in the design. Better
routing prevent the congestions and interventions from other signal. There are two major
routing scenarios.

o Global Routing
o Detailed Routing

Global routing allocates routing resources that are used for connections. Detailed routing assigns
routes to specific metal layers and routing tracks within the global routing resources.