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5. Can be customized to each user's application, or an organizations particular design rules. 6. New rules are easily added, and the component libraries can be easily maintained by the user.
ARCHITECTURE
STEED consists of an inference engine, three data bases, and a compiler utility. The inference engine acts as a control mechanism, and is part of the expert system shell software. The rules in the Rulebase are applied to the facts in the Fact Database. Using a pattern matching scheme, the control mechanism determines which rules are satisfied, prioritizes them, and controls the firing of rules. The Fact Compiler converts the schematic netlist into facts, adds component knowledge from the Library Database, and generates the Fact Database. The Library Database contains detailed user-supplied knowledge about specific components. All databases are maintained in ASCII format, and can be examined and/or modified by the user. The Library Database and Rulebase are created and updated using a standard text editor. The Fact Compiler is written in XLISP, while CLIPS is written in the C language.
DESIGN GOALS
STEED (Testability Enhancement Expert Design System) has been built to perform testability analysis and design rule checking on circuit board designs at an avionics f i i . Typically, all circuit designs are reviewed by the test engineering staff prior to releasing design drawings. The purpose of this design review is to insure that the circuit and/or assembly can be tested, both in manufacturing and in the field. A "testability checklist" is used to compare the design against; the rules in the checklist are specific to the type of product, test equipment used, manufacturing processes, and other factors. STEED can use these same testability rules; the advantage is that the review process can be automated. A circuit designer 64th no particular expertise in DFT can run STEED and insure that the circuit meets some basic testability requirements.
THE RULES
The rules currently built into STEED are:
* Are LS122, LS123, or U 2 2 1 one-shot devices used? They have peculiar reset behavior. * Are there open-collector gates without pull-up resistors on-board? * Look for wire-OR and wire-AND circuits. * Look for Data buss isolation between UPand peripherals. * Look for isolation between UPoutputs and peripherals. * Look for isolation between peripherals and UPinputs. * Check for incompatible logic families.
* Detect input pins which are left floating. * Detect outputs tied together (not OC or tri-state). * Can tester control the system clock ? * Can sequential logic can be initialized to
a known state under tester control?
FEATURES
1. General purpose; not limited to a technology, class of
circuits or components. Can be applied to both analog and digital circuits. 2. Interfaces to engineer's "native design enviroment". Uses netlist output of a popular schematic capture software package as input. Totally resident on a PC. All databases are stored in ASCII. User is not burdened with re-entering the design in another format. 3. Uses inexpensive, widely available PC platform. 4. Runs very fast. Circuit compiled in less than 1 minute, run time under 10 seconds for circuit with 100 nodes.
CONCLUSlON
STEED is able to correctly identify several common circuit features which make a circuit untestable (or are bad design practice). STEED provides a measure of "expert" advice at a low time and effort overhead to the design engineer. It automates the testability design review process, and helps to insure that a circuit meets the testability design rules.