LAB MINI PROJECT

COURSE CODE: EEE 330

COURSE TITLE: VLSI Circuits I Lab

PROJECT REPORT

Name of the project: "Implementation of a 64-bit Full Adder

through Simvision and the Design of an 8T 1-bit Full Adder
with Layout using Cadence Virtuoso"

Submitted to:
Rubayat Chowdhury, Lecturer,
Department of EEE, BUBT

Submission Date: 26th November, 2023

 Group – A
‘Team Error’

Team Members
NAME ID

Hasibur Rahman 19202108001

Md. Sahadat Hossain Sani 19202108004

Saiful Islam Tuhin 19202108015

Md. Arif Hasan Masum 19202108022
Md.Nure Alam Siddiki 19202108024
Wahidur Rahman Easin 19202108033
Shah Akramul Haque 19202108067

Department of Electrical and Electronic Engineering,

Bangladesh University of Business and Technology (BUBT)
 Title
"Implementation of a 64-bit Full Adder through Simvision and the Design of an 8T
1-bit Full Adder with Layout using Cadence Virtuoso"

Introduction
In the term of digital electronics, full adders play a crucial role as fundamental
building blocks of any complex design, the heart of modern computing systems.
Their ability to perform addition operations on binary numbers is essential for a wide
range of computational tasks. This project delves into the implementation and design
of full adders, utilizing both simulation and layout tools to comprehensively explore
their functionality.
Initially, a 64-bit full adder is implemented using Simvision, a popular simulation
software. This approach allows for in-depth analysis of the adder's behavior and
verification of its correctness. The simulation process involves defining the adder's
logic structure, assigning appropriate inputs and outputs, and observing the resulting
outputs for various input combinations.
Subsequently, an 8-transistor (8T) 1-bit full adder is designed and laid out using
Cadence Virtuoso, a powerful electronic design automation (EDA) tool. This stage
focuses on translating the functional design of the adder into a physical layout that
adheres to manufacturing constraints and ensures optimal performance. The layout
process encompasses transistor placement, routing interconnects, and verifying
design rule compliance.
By employing both simulation and layout techniques, this project provides a
comprehensive understanding of full adder implementation and design. The
combination of these approaches enables the verification of the adder's functional
correctness at the circuit level and the realization of a physical layout that meets
manufacturing requirements. This project's findings contribute to the advancement
of digital design methodologies and the development of efficient computational
circuits.
 Motivation
Full adders are fundamental building blocks in digital circuits, forming the backbone
of complex design and other computational components. Their efficient
implementation is crucial for achieving high performance and power efficiency in
modern digital systems. This project aims to explore and compare two distinct
approaches to designing and implementing full adders: simulation using Simvision
and layout design using Cadence Virtuoso.
Simvision Simulation:
Simvision offers a user-friendly graphical interface for simulating digital circuits,
making it an ideal tool for exploring the functionality and timing characteristics of
full adders. By simulating various full adder designs, we can gain insights into their
behavior, identify potential bottlenecks, and optimize their performance.
Cadence Virtuoso Layout Design:
Cadence Virtuoso provides a powerful suite of tools for creating and analyzing
circuit layouts. By designing and laying out an 8-transistor (8T) 1-bit full adder using
Cadence Virtuoso, we can delve into the physical aspects of full adder
implementation, considering factors such as transistor sizing, layout optimization,
and parasitics.
Comparative Analysis and Contribution:
By comparing the simulation results of various full adder designs with the layout
and performance of the 8T 1-bit full adder, we can gain a comprehensive
understanding of the trade-offs between different design approaches. This analysis
will provide valuable insights into the effectiveness of each method and contribute
to the development of more efficient full adder implementations.
In addition to the technical motivations, this project also aims to enhance our
understanding of digital circuit design methodologies, from functional simulation to
physical layout. By applying both Simvision and Cadence Virtuoso, we will gain
hands-on experience with two essential tools used in the digital design industry.
 Objectives
The primary objectives of this project are two part:
Implementation of a 64-bit Full Adder through Simvision:
• To design and simulate a 64-bit full adder using Simvision, ensuring its
functionality and correctness.
• To thoroughly analyze the simulation results and verify the adder's behavior
under various input conditions.
Design of an 8T 1-bit Full Adder with Layout using Cadence Virtuoso:
• To design an 8-transistor (8T) 1-bit full adder using Cadence Virtuoso,
adhering to design specifications and layout guidelines.
• To perform comprehensive circuit analyses, including transient response, DC
response, AC response, and noise analysis, to evaluate the adder's
performance.
• To calculate the power consumption (average power) of the circuit, providing
a measure of its energy efficiency.
• To ensure the layout's integrity by conducting design rule checks (DRC) and
layout versus schematic (LVS) checks.
By achieving these objectives, this project report aims to provide a valuable resource
for students, researchers, and professionals in the field of Full Adder
implementations, combining simulation-driven insights with layout design precision
in a state-of-the-art technology node.
 Literature Review
Full adders, fundamental components of arithmetic logic units (ALUs), play a
pivotal role in digital systems, enabling the execution of arithmetic operations. These
versatile circuits, capable of adding two binary numbers and a carry-in bit, form the
backbone of computational units in microprocessors, digital signal processors
(DSPs), and other digital devices.
The design and implementation of full adders have been extensively explored in the
realm of digital design. Numerous research efforts have focused on optimizing full
adder circuits for performance, power consumption, and area efficiency. Various
transistor-level implementations have emerged, each with its unique characteristics
and trade-offs.
From Simulation to Layout: A Comprehensive Approach
The implementation of full adders encompasses both simulation and layout
techniques. Simulation plays a crucial role in verifying the functional correctness of
the circuit design. Circuit simulation tools, such as Simvision, enable designers to
test the adder's behavior under various input conditions, ensuring that it produces the
expected output for all possible combinations.
Layout, on the other hand, focuses on the physical realization of the circuit on a chip.
Layout editing tools, such as Cadence Virtuoso, allow designers to meticulously
place and route transistors, wires, and other components within the physical
constraints of the layout. Adhering to design rules and ensuring optimal circuit
performance are essential aspects of layout design.
Performance Analysis: Delving into Circuit Behavior
Circuit analysis provides valuable insights into the behavior of full adders. Transient
response analysis reveals the circuit's behavior over time, while DC response
analysis characterizes its operating point. AC response analysis sheds light on the
circuit's frequency response, and noise analysis assesses its sensitivity to noise.
These analyses are crucial for understanding the circuit's performance under various
operating conditions.
Power consumption, a critical factor in digital design, is often a key consideration
for full adder implementation. Calculating the power consumption (average power)
of the circuit provides a quantitative measure of its energy efficiency. This
information is essential for optimizing the circuit for power-constrained
applications.
Design Rule Checks and Layout versus Schematic: Ensuring Integrity
Design rule checks (DRC) and layout versus schematic (LVS) checks are essential
verification steps in full adder design. DRC ensures that the layout adheres to the
design rules of the fabrication process, preventing potential manufacturing defects.
LVS compares the layout with the schematic representation, identifying and
resolving any discrepancies between the two. These checks ensure the integrity of
the layout and guarantee that the circuit will function as intended.

Required Equipment
1. Laptop or PC
2. Cadence Software

Verilog Code
Test Bench Code
Verification Waveform
Schematic Diagram and Symbol
 Test Bench

Transient, AC, DC and Noise Analysis

Layout
LVS and DRC Check
 Results and Discussions
This project successfully implemented a 64-bit full adder using Simvision and
designed an 8T 1-bit full adder with layout using Cadence Virtuoso. The 64-bit full
adder was verified for correctness through waveform analysis, and the 8T 1-bit full
adder was analyzed using transient response, DC response, AC response, and noise
response analyses.

64-bit Full Adder Implementation and Verification:

The implementation of the 64-bit full adder in Simvision involved modeling the
adder's behavior using Simvision's graphical user interface (GUI). The adder was
simulated under various input conditions, and the resulting waveforms were
analyzed to verify the adder's correctness. The simulation results confirmed that the
adder produced the expected output for all possible input combinations.

8T 1-bit Full Adder Design and Analysis:

The design of the 8T 1-bit full adder in Cadence Virtuoso involved creating a
schematic representation of the adder using Virtuoso's schematic editor. The
schematic was then translated into a layout using Virtuoso's layout editor. The layout
was carefully crafted to ensure that the transistors, wires, and other components were
placed and routed correctly within the physical constraints of the layout.
the design of an 8T 1-bit Full Adder with Layout using Cadence Virtuoso in a 45nm
GPDK proved to be a robust endeavor. Utilizing four pMOS1v and four nMOS1v
transistors, and integrating Metal1, Metal2, and Poly for gate connections, our layout
design exhibited commendable characteristics in various analyses.
The 8T 1-bit full adder was analyzed using four types of analyses: transient response,
DC response, AC response, and noise response. The transient response analysis
illustrated the circuit's dynamic behavior, showcasing efficient switching. DC
response analysis confirmed stable voltage levels, while AC response analysis
demonstrated a commendable bandwidth, essential for high-speed processing.
Moreover, the noise response analysis underscored the layout's resilience against
external and internal noise sources.
Crucially, the layout adhered to 45nm GPDK standards, as confirmed by clean
Design Rule Check (DRC) and Layout versus Schematic (LVS) processes, ensuring
manufacturability without errors.
The results of the analyses showed that the 8T 1-bit full adder met the design
specifications.
The implementation of the 64-bit full adder in Simvision and the design of the 8T 1-
bit full adder in Cadence Virtuoso demonstrate the effectiveness of using simulation
and layout tools to design and verify digital circuits. The results of the waveform
analysis and the circuit analyses show that the adders meet the design specifications.
These results can be used to inform the design of future digital circuits.

Conclusion
In this project, we successfully implemented a 64-bit Full Adder through Simvision,
confirming its correctness by analyzing waveforms based on 64-bit inputs and
outputs. The simulation results validated the precision of our design, ensuring
reliable addition operations across the entire 64-bit data path.

In conclusion, our project not only achieved its objectives but also contributes to the
advancement of digital circuit design. The 64-bit Full Adder and the 8T 1-bit Full
Adder layout showcase reliability and efficiency, holding implications for high-
performance computing and microprocessor architectures. The successful
integration of simulation tools like Simvision and layout design platforms like
Cadence Virtuoso in a 45nm GPDK reflects a holistic approach toward optimizing
digital circuitry for contemporary applications. This project serves as a valuable step
forward in the ongoing evolution of computational efficiency and performance.

References
[1] Harris, D., & Harris, S. (2007). Digital Design and Computer Architecture. Morgan Kaufmann.

[2] Weste, N. H. E., & Harris, D. (2010). CMOS VLSI Design: A Circuits and Systems Perspective. Addison-
Wesley.

[3] Baker, R. J. (2018). CMOS: Circuit Design, Layout, and Simulation. Wiley.

[4] Mead, C., & Conway, L. (1980). Introduction to VLSI Systems. Addison-Wesley.