Dissertacao

Development and Implementation of a Data Acquisition
System for Teaching Purposes
Francisco José Antunes Marques Esteves
Thesis to obtain the Master of Science Degree in
Electronics Engineering
Supervisor: Prof. Pedro Miguel Pinto Ramos
Examination Committee
Chairperson: Prof. João Costa Freire

Supervisor: Prof. Pedro Miguel Pinto Ramos
Member of the committee: Prof. António Joaquim dos Santos Romão Serralheiro
September 2015
ii
Acknowledgements
Without my family none of what is written here would be possible. Without the patience and support
from my father Manuel, my mother Sandra and my sister Marta, I would not be the man I am today. Even
when I was lazy, they kept motivating me and always made me strive to achieve more, to be more.
I would like to thank my supervisor, Professor Pedro Miguel Pinto Ramos, for all the support,
guidance, knowledge that he passed to me. Most of all, for the patience, experience, availability and
making me think outside the box, specially at the right moment and usually when I thought some tasks
were hopeless and the only solution was restart.
A special thank to Mr. Pina dos Santos for his helpful tips and, most of all, for saving me from my
rookie mistakes and sometimes shaky hands when soldering. To my colleagues that accompanied me
since the beginning of the bachelors, specially to Luı́s Magalhães and, afterwards, Gonçalo Carito. They
made me try harder, always with new solutions and feedback on how to improve.
Finally, I would like to thank three good friends of mine, Ricardo Faria, Pedro Moreira and Pedro
Silva, that gave me the friendship during all these years to let of the steam after classes and during our
lazy hours in each of our gatherings as the ”brovention”.
To all, a huge thank you.
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ii
Abstract
A data acquisition (DAQ) system acquires analog data into digital form for storage, processing and
analysis. These signals are sampled, converted to digital and stored by a computer or by a standalone
device. A DAQ system consists of an analog signal conversion hardware and DAQ measurement
hardware. These systems can be standalone or coupled to a computer and can acquire multiple
channels of data.
In the simplest form, a technician logging the temperature of an oven on a piece of paper is acquiring
data. As technology progressed, this type of process has been simplified and made more versatile
and reliable through electronic equipment. Compared to traditional measurement systems, personal
computer-based DAQ systems exploit the processing power, display and connectivity capabilities of the
computer, providing a more powerful, flexible and cost-effective measurement solution.
The aim of this work is to develop, implement and characterise a small-sized, production cost
reduced data acquisition system powered and controlled by an USB interface for educational purposes.
A computer controls the values of the sampling frequency, range of channels, number of points to acquire
and then retrieves the data acquired.
This system is based on a PIC24 microcontroller which is used to control all the board integrated
circuits, together with a USB Hi-Speed FT232H integrated circuit to connect to the PC. This data
acquisition board has four differential channels with simultaneous acquisition in the four channels, up
to 100 kSamples/s/ch, 4 input ranges of amplitude, resolution of 16-bit and can perform continuous
acquisition in the four channels. Also, part of the work also includes developing virtual instrumentation
(VI) similar to the National Instruments DAQ VI for identical use in LabVIEW.
Keywords: Data Acquisition, USB, ADC, PIC
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iv
Sumário
Um sistema de aquisição de dados (DAQ) adquire dados analógicos e passa para formato digital,
para armazenamento, processamento e análise. Estes sinais são amostrados, convertidos para digital
e armazenados por um computador ou por um outro dispositivo. Um sistema DAQ é composto por
hardware de conversão de sinal e hardware de medição aquisição de dados. Estes sistemas podem
ser independentes ou acoplados a um computador e podem adquirir dados de múltiplos canais.
De forma simplificada, medir a temperatura de um forno registando o valor numa folha de papel é
efectuar uma aquisição de dados. Com a evolução da tecnologia, este tipo de processo foi simplificado e
está versátil e fiável através de equipamentos eletrónicos. Em comparação com os sistemas tradicionais
de medição, os sistemas de aquisição de dados actuais permitem explorar o poder de processamento
e recursos de conectividade de um computador proporcionando uma solução de medição poderosa,
flexı́vel e de baixo custo.
O objectivo deste trabalho é desenvolver, implementar e caracterizar um placa de aquisição de
sinais pequena, de custo de produção reduzido e controlada por uma interface USB para fins educa-
cionais. O controlo através do PC controla os valores da frequência de amostragem, o alcance dos
canais, número de pontos a adquirir e guarda a informação adquirida.
Este sistema baseia-se num microcontrolador PIC24 que é usado para controlar todos os circuitos
integrados da placa, em conjunto com um circuito integrado FT232H de USB Hi-Speed para ligar ao PC.
Este sistema de aquisição de sinais tem quatro canais diferenciais analógicos com aquisição simultânea
nos quatro canais, até 100 kS/s/ch, quatro alcances de amplitude entrada com uma resolução de 16
bits e pode fazer aquisição contı́nua nos quatro canais. Também parte do trabalho também inclui o
desenvolvimento de instrumentação virtual (VI) semelhante aos VI da National Instruments para uso
em LabVIEW.
Palavras-chave: Sistema de Aquisição, USB, ADC, PIC
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Contents
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Sumário . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
List of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Purpose and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Goals and Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Document Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Key Components of a DAQ Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Processing Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Characterisation of Data Acquisition Systems . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1 Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2 Amplification Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Processing and Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.1 Resource Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.2 Parallel Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.3 Firmware Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6 LabVIEW Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
vii
4 System Characterisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 Analog Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Crosstalk Between Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.3 Continuous Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4 Delay Between Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.5 Average Power Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Apendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
A Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
B Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
C PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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List of Tables
Table 1.1 Features of some acquisition systems available on the market. . . . . . . . . . . . . 2

Table 2.1 ADC architectures comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2.2 Simple comparison between the PIC, FPGA and DSP. . . . . . . . . . . . . . . . . 9
Table 2.3 Communication protocols used on data acquisition systems. . . . . . . . . . . . . . 9
Table 3.1 Gain of the instrumentation amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3.2 FT232H read and write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3.3 Current consumptions of each component. . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4.1 Crosstalk values of the four channels of the DAQ system. . . . . . . . . . . . . . . . 33
Table 4.2 Time delays of the four channels of the DAQ system related to channel 1. . . . . . 35
Table A.1 Bill of materials - capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table A.2 Bill of materials - resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table A.3 Bill of materials - converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table A.4 Bill of materials - USB interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table A.5 Bill of materials - other components. . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table A.6 Bill of materials - total costs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
List of Figures
Figure 1.1 Picture of parts of a DAQ System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2.1 16-Bit resolution versus 3-Bit resolution chart of a 5 kHz sine wave. . . . . . . . . . 7
Figure 2.2 Block diagram of a non simultaneous acquisition system. . . . . . . . . . . . . . . . 9
Figure 2.3 Block diagram of a simultaneous acquisition system with sample and hold. . . . . . 10
Figure 2.4 Block diagram of a simultaneous acquisition system. . . . . . . . . . . . . . . . . . 10
Figure 2.5 Two channel measurement of two sine signals using a non-simultaneous acquisi-
tion system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2.6 DAQ Settling Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 2.7 Non-simultaneous acquisition system (left) and simultaneous acquisition system
(right). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2.8 Differential measurement (left) and measurement referenced to GND (right). . . . . 12
Figure 3.1 Block diagram of the proposed data acquisition system. . . . . . . . . . . . . . . . 15
Figure 3.2 Proposed signal conditioning circuit schematic. . . . . . . . . . . . . . . . . . . . . 16
Figure 3.3 Proposed input protection circuit schematic. . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3.4 Frequency response of the AI for the different possible gains. . . . . . . . . . . . . 17
ix
Figure 3.5 Level shift circuit for bipolar input for the ADC (ADS8361). . . . . . . . . . . . . . . 18
Figure 3.6 Block diagram of the ADS8361 analog to digital converter. . . . . . . . . . . . . . . 19
Figure 3.7 Mode III, Timing Diagram for M0 = 1 and M1 = 0. . . . . . . . . . . . . . . . . . . . 20
Figure 3.8 Block diagram of the PIC24EP512GU810 microcontroller. . . . . . . . . . . . . . . 21
Figure 3.9 FT245 asynchronous FIFO interface read signal waveforms. . . . . . . . . . . . . . 23
Figure 3.10FT245 asynchronous FIFO interface write signal waveforms. . . . . . . . . . . . . . 23
Figure 3.11Firmware flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3.12Virtual instrumentation layout for sequential acquisition. . . . . . . . . . . . . . . . . 25
Figure 3.13Virtual instrumentation layout for sequential acquisition. . . . . . . . . . . . . . . . . 26
Figure 3.14Virtual instrumentation layout for continuous acquisition. . . . . . . . . . . . . . . . 26
Figure 4.1 Average channel 1 analog bandwidth for the different input ranges. . . . . . . . . . 30
Figure 4.5 Average noise floor of channel 2 for the amplitude range of ±10 V. . . . . . . . . . 32
Figure 4.6 Average power spectrum of channel 1 for the amplitude range of ±10 V of a sine
signal with 48 kHz and 9,5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 4.7 Simultaneous Acquisition with the four channels of the DAQ system. . . . . . . . . 34
Figure 4.8 Average power spectrum of a sine signal with a frequency of 5 kHz. . . . . . . . . . 35
Figure 4.9 Average power spectrum of a square signal with a frequency of 5 kHz. . . . . . . . 36
Figure 4.10Average power spectrum of a triangular signal with a frequency of 5 kHz. . . . . . . 36
Figure 4.11Power spectrum of a single sampling set triangular signal with a frequency of 5 kHz. 37
Figure B.1 Schematic of the mini USB type B. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure B.2 Schematic of the LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure B.3 Schematic of the DC converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure B.4 Schematic of the FT232H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure B.5 Schematic of the FT232H decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure B.6 Schematic of the FT232H EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure B.7 Schematic of the PIC24EP512GU810. . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure B.8 Schematic of the ADC ADS8361. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure B.9 Schematic of the signal conditioning for channel 1. . . . . . . . . . . . . . . . . . . 51
Figure C.1 Top layer of the PCB board without components. . . . . . . . . . . . . . . . . . . . 53
Figure C.2 Bottom layer of the PCB board without components. . . . . . . . . . . . . . . . . . 53
Figure C.3 Top layer of the PCB board with components. . . . . . . . . . . . . . . . . . . . . . 54
Figure C.4 Bottom layer of the PCB board with components. . . . . . . . . . . . . . . . . . . . 54
x
List of Acronyms
ADC Analog to Digital Converter
CMRR Common Mode Rejection Ratio
CPU Central Processing Unit
DAC Digital to Analog Converter
DAQ Data Acquisition
DMA Direct Memory Access
DPSRAM Dual Port Static Random Access Memory
DSP Digital Signal Processor
ENOB Effective Number Of Bits
EEPROM Electrically Erasable Programmable Read-Only Memory
FIFO First In, First Out
FPGA Field Programmable Gate Array
FRC Internal Fast RC
FTDI Future Technology Devices International Ltd.
GND Ground
GPIB General Purpose Interface Bus
I2 C Inter-Integrated Circuit
IA Instrumentation Amplifier
ISR Interrupt Service Routine
LSB Least Significant Bit
PCB Printed Circuit Board
PC Personal Computer
PGA Programmable Gain Amplifier
PIC Peripheral Interface Controller
xi
PMP Parallel Master Port
PPS Peripheral Pin Select
PWM Pulse-Width Modulation
SDRAM Synchronous Dynamic Random-Access Memory
SINAD Signal-to-Noise and Distortion Ratio
SPI Serial Peripheral Interface
SRAM Static Random-Access Memory
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
VHDL VHSIC Hardware Description Language
VI Virtual Instrumentation
Wi-Fi Wireless-Fidelity
xii
CHAPTER 1
Introduction
1.1 Purpose and Motivation
Every data acquisition task has its own special challenges. Data acquisition test and measurement
can be mobile or fixed, can be used on a test cell or under extreme environmental conditions and
in laboratory research or for academic purposes. These systems can be used not only for electric
signals but also to measure temperature, acceleration, sound, force and pressure, light or position and
displacement, with a transducer is required at the input of the DAQs channels. Obtaining proper results
from a DAQ system depends on the signal conditioning, the DAQ hardware, the computer and the
software.
Signal conditioning assures that the signal about to be measured will not damage the system,
protecting against overcurrent and overvoltage and adjusting the input ranges to the ADC input range.
The main component composing the DAQ hardware is the analog to digital converter that digitises the
conditioned signal with a certain resolution and sampling frequency. It is also composed by a processing
unit to transmit the acquired data to the computer to be processed and analysed.
Figure 1.1: Picture of parts of a DAQ System [1].
The main criteria to take into account when selecting a data acquisition system are the maximum
sampling frequency, number of channels, input ranges, ADC resolution and the possibility of simultane-
ous acquisition. In Table 1.1, a comparison between some of the DAQs available in the market is shown.
The cost of the device is also important since the goal is to develop an acquisition system similar to
the available systems in the market with a lower production cost. The costs of the currently available
devices vary according to the criteria above and some other specific characteristics of each device.
In order to reduce costs, the aim of this work is to develop, implement and characterise a small-sized
data acquisition device powered and controlled by USB. The computer-DAQ communication bus can
drastically affect the maximum speeds at which one is able to continuously acquire data.
This DAQ should have four channels of analog acquisition with simultaneous acquisition in at least
two channels, up to 50 kS/s/ch, USB PC connection, capable of continuous acquisition, 4 or 5 ranges
1
of input amplitude resolution, 16-bit. Eventually, it might include a DAC and digital I/O with 8 or 16 bits.
Part of the work also includes developing VIs similar to the NI DAQ for use with identically in LabVIEW.
The USB connection should be made using a Cypress integrated circuit or similar.
The presented system is based on a PIC24EP512GU810 microcontroller which is used to control all
the board integrated circuits, together with a USB Hi-Speed FT232H integrated circuit to connect to the
PC. This data acquisition board has four differential channels with simultaneous acquisition in the four
channels, up to 100 kS/s/ch, 4 input ranges of amplitude resolution of 16-bit and continuous acquisition
in the four channels. Part of the work also includes developing virtual instrumentation (VI) similar to the
National Instruments DAQ VI for identical use in LabVIEW.
Table 1.1: Features of some acquisition systems available on the market.
Maximum Number
Manufacturer Model Acquisition Sampling Resolution of Range Price
Frequency channels
NI USB-6008 [2] Non Simultaneous 10 kS/s1 12 bit 12 ±1 V up to ±10 V 160 e

National Instruments
NI USB-6009 [2] Non Simultaneous 48 kS/s 14 bit 12 ±1 V up to ±10 V 220 e
NI USB-9215 [3] Simultaneous 100 kS/s/ch 16 bit 4 ±10 V 519 e
DT9816 [4] Simultaneous 50 kS/s/ch 16 bit 6 ±5 V or ±10 V 315 e

Data Translation
DT9816 A [4] Simultaneous 150 kS/s/ch 16 bit 6 ±5 V or ±10 V 385 e
DT9816 S [4] Simultaneous 750 kS/s/ch 16 bit 6 ±5 V or ±10 V 460 e
USB-1901 [5] Simultaneous 2502 kS/s 16 bit 16 ±0, 2 V up to ±10 V 455 e

ADLINK Technology
KUSB-3100 [6] Simultaneous 50 kS/s 12 bit 8 ±1, 25 V up to ±10 V 380 e

Keithley
U2300A [7] Simultaneous 3 MS/s3 16 bit 16 ±1, 25 V up to ±10 V 1235 e

Agilent
U2500A [8] Simultaneous 2 MS/s/ch 16 bit 16 ±1, 25 V up to ±10 V 1365 e
1.2 Goals and Challenges
The main objective of this dissertation is to develop, implement and characterise a small-sized data
acquisition board powered and controlled via USB to obtain a production cost reduced system with
similiar capabilities of the NI USB-9215. In order to achieve this, some key milestones were established:
• Defining the scope of acquiring signals (frequency and amplitude of the signal);
• Selection and test(s) of the Integrated circuit(s) responsible for signal acquisition (ADC);
1 Thousand samples per second (kiloSamples per second).
2 Multiplexing, channel-gain-queue.
2 For a single channel.
2
• Development of an analog conditioning circuitry of the input signals of the DAQ;
• Selection of a processing unit and communication (PIC or dsPIC);
• Definition and implementation of the control commands from the DAQ;
• Implementation of the complete system in the printed circuit board;
• Development of the PIC firmware and LabVIEW VIs;
• Experimental validation of the designed system;
• Presentation of the results.
1.3 Document Organisation
In Chapter 2, an overview and characterisation of the data acquisition key components, such as
signal conditioning, ADC and the processing unit, are described.
The proposed system architecture and methodology are presented together with a description of
the main blocks of the system to be developed in Chapter 3. Also a current consumption analysis is
presented.
Chapter 4 contains the system characterisation such as the crosstalk between channels, average
power spectrum of each channel, measurement of the time delay between channels, continuous acqui-
sition example and the analog bandwidth of each channel.
Finally, in Chapter 5, a project overview, result discussion and design limitations and improvements
are presented.
3
4
CHAPTER 2
State of the Art
2.1 Key Components of a DAQ Device
In this chapter some concepts about the project and characterisation of acquisition systems are
introduced. These include the basic building blocks of their constitution, types of existing architectures
and typical characteristics. The DAQ acts as the interface between a computer and signals from the
outside world. It primarily functions as a device that acquires incoming voltages and converts into digital
form so a computer can process, analyse and store them.
The three key components of a DAQ device used for measuring a signal are: the analog signal
conditioning circuitry, analog-to-digital converter (ADC) and the microcontroller [1]. The USB bus serves
as the communication interface between the DAQ device and computer for transmitting configurations
and measured data. DAQ devices are offered on the most common computer buses including USB, PCI
[9], PCI Express [10] and Ethernet [11].
2.2 Signal Conditioning
Signals from sensors or the outside world either can be noisy or, when the amplitude of a signal
can harm the human being, it can be too dangerous to measure them directly. One of the key elements
of signal conditioning is protecting the circuit from these adverse effects that might occur, such as an
unexpected increase in voltage and/or current.
Signal conditioning circuitry adjusts a signal into a form that is suitable for input into an ADC.
This circuitry can include amplification, attenuation, filtering and galvanic isolation. Signal conditioning
provides distinct enhancements to both the performance and accuracy of data acquisition systems [12].
Amplifiers can increase input voltage level to better match the ADC input range, thus increasing
the measurement resolution and sensitivity, allowing for a better use of the number of bits in the ADC.
However, in signal amplification, noise is also amplified along with the signal. One way to reduce the
influence of noise in the measurements is the amplification of the signal as near as possible to the signal
source. Data acquisition measurement systems are designed in order to permit the measurement of
signals with a wide range of amplitudes (from µvolts to tens of volts).
Attenuation is necessary when input voltages, are beyond the ADC input range or in order to
condition those voltages as an input of any integrated circuit if required. Similarly attenuation is typi-
cally necessary when measuring voltages in a DAQ system since the ADCs have a small range and
attenuation is required in order for the input signal match best the ADCs range.
To prevent surges, the use of diodes in the circuit enables the limitation of voltage to provide an
alternate path for the current.The use of a resistance in series with the input of the circuit enables its
5
limitation [14].
Diodes can limit the voltage through a wave-shaping circuit and is used to either remove or clip a
portion of the applied signal to control the shape of the output waveform. One of the most basic clipping
circuit is the half-wave rectifier. A half-wave rectifier clips either the negative half cycle or the positive
half cycle of an alternating waveform, which allows to pass only one half cycle. Such a circuit has great
applications in radars, digital computers and other electronic systems for removing unwanted portions
of the input signal voltages above or below a specified level [15].
Filters reject unwanted noise within a certain frequency range. Frequently, lowpass filters are used
to block out high-frequency noise in electrical measurements. Another common use for filtering is to pre-
vent aliasing from high-frequency signals. This can be done by using an anti-aliasing filter to attenuate
signals above the Nyquist frequency [12] in order to avoid spread spectrum. It is necessary to take into
account that the acquisition board may not be used in measurements using subsampling techniques
(spectral mirroring), when the signal under test has a frequency higher than half the maximum sampling
frequency used.
The signal can be isolated from its source to the measurement device without a physical connection
by using transformer, optical or capacitive coupling techniques. In addition to breaking ground loops,
isolation blocks high-voltage surges and rejects high common-mode voltage and thus protects both
the operators and expensive measurement equipment. With isolation, noise immunity is very high and
the rejection of common mode voltages (CMRR) are also higher comparing with systems that are not
isolated [12].
2.3 Analog-to-Digital Converter
An ADC is a device that provides a digital representation of an analog signal at an instant in time
[1]. In practice, analog signals continuously vary over time and an ADC takes periodic samples of the
signal at a predefined sampling rate. These samples are transferred to a computer over a bus where the
original signal is reconstructed from the samples in software. The key characteristics of an ADC are the
maximum conversion rate, the number of bits, the voltage input range, the output type (series/parallel)
and the type of input scale (unipolar/bipolar) [16].
The maximum conversion rate defines the digital bandwidth of the ADC which is the maximum
frequency the ADC can sample [17]. However, signals with frequencies above half of the maximum
sampling frequency can be sampled through subsampling techniques, if the analog bandwidth of the
ADC and signal conditioning circuitry allows [18].
The number of bits in a data acquisition system is the number of bits of the digitiser. Any ADC,
has inherent performance limitations so the effective number of bits provided by the system can be
useful in determining if the system is right for the application. Every converter has non-linearity, noise
from reference voltages and aperture jitter. The effective number of bits (ENOB) is a measure of the
dynamic performance of an ADC and its associated circuitry. It is determined by sampling a spectrally
pure sinusoidal wave and determining the RMS signal and noise levels recorded by the system. Often,
6
data acquisition system manufacturers specify a SINAD (performance parameter). SINAD is the ratio of
the fundamental sinusoidal signal power acquired to the total noise and distortion since this parameter
contains noise and distortion. It can be used to calculate effective number of bits (ENOB) [19].
The smallest detectable change in the signal determines the resolution that is required of the DAQ
device. Resolution refers to the number of binary levels an ADC can use to represent a signal [20] and
is dependent on the input range and on the number of bits of the ADC uses. Figure 2.1 compares how
a sine wave would be represented if it were acquired through an ADC with different resolutions, an ideal
3-bit ADC and an ideal 16-bit ADC. Since the latter has more bits, better resolution can be achieved.
Figure 2.1: 16-Bit resolution versus 3-Bit resolution chart of a 5 kHz sine wave [20].
The representation of the sine wave with a 3-bit resolution resembles more a step function than a
sine wave where the 16-bit ADC provides a cleaner sine wave. The ADC resolution is the value of the
bit with the lowest weight LSB (Least Significant Bit) and can be calculated by,
Maximum input range − Minimum input range

LSB = , (2.1)
2n − 1
where n is the number of bits.

Different output types of the converter allows different transmission rates (single or multiple serial
lines or parallel communication). Therefore, they might provide a higher conversion rate and, usually, a
parallel output converter has higher transmission rate. The scale can be unipolar, which is more suited,
if the signal to measure has only one polarity (only positive voltage values) or bipolar if the signal has
positive and negative voltage values or between reference voltages [18].
There are different architectures for data converters (voltage-frequency, voltage-time, successive
approximations and sigma-delta), each following a principle of operation and therefore, with different
conversion techniques that can be further classified into non integrator and integrator converters and
are displayed in Table 2.1. The cost associated with a certain type of ADC will depend on the existing
relationship between resolution and sampling frequency of the ADC. Better resolution or high sampling
frequencies result in a higher cost of ADC [21, 22].
7
Table 2.1: ADC architectures comparison [16, 23].
Sampling Energy Consumption

Architecture Resolution Conversion Method
Frequency
4000 a 20000 Low

Dual Slope < 1000 Samples/s Analog Integration
counts
Comparators
capacitors increase High
Flash 6 a 10 bits > 1.5 GSamples/s
by a factor of 2 for
each bit.
Successive Successive Low
8 a 16 bits < 5 MSamples/s
Approximations Approximations
Over-Sampling
Sigma-delta 14 a 24 bits < 2 MSamples/s Modulator, Digital Medium
Decimation Filter
Digital Correction Medium
Pipeline 10 a 16 bits < 100 MSamples/s
Logic
Good resolution, high sampling rates and low consumption are featured in pipeline, sigma-delta and
successive approximation ADC architectures. The integrator converters do not have a high conversion
rate although they have a great immunity to noise and high resolution. The flash converters are those
with the highest sampling frequencies and are also quite fast. However, they have a high energy
consumption and low number of bits when compared with other architectures. For a low energy and
resolution the best suited for this DAQ is the successive approximations architecture.
2.4 Processing Control Unit
In a data acquisition system, the processing control unit controls the analog signal conditioning
(amplification chain or attenuation with digitally programmable gains). It is also responsible for collecting
the data from the ADC and control the sampling frequency [18]. This controller can be a PIC (Peripheral
Interface Controller), a DSP (Digital Signal Processor) or a FPGA (Field Programmable Gate Array). A
comparison between the three controllers is shown in Table 2.2. The controllers can communicate with
other devices through several protocols. The most commonly used protocols are SPI, I2C, UART and
USB. Another protocol is parallel communication that is used to communicate between the processing
unit and the other components. All of these protocols can be implemented in software. However, the
existence of dedicated hardware modules in the control unit for the implementation of a DAQ system
allows more control flexibility of each module.
Since processing the data would require a high amount of computing power, the data must be
transferred to another peripheral such as a computer. The transfer of data between the acquisition
system and the PC can be done by the microcontroller itself or by an auxiliary component.
Depending on the transmission rates required, portability and communication type of the DAQ,
some protocols are more viable than others. For higher transmission rates, PCI and PCI-Express are
ideal. For greater portability, protocols like ethernet, USB or 802.11x are more suited. In Table 2.3, some
key characteristics to choose the communication protocol are shown.
1 For technology Wi-Fi 801.11a [25]
8
Table 2.2: Simple comparison between the PIC, FPGA and DSP.
Processing Units
PIC DSP FPGA

Onboard processing,
Use of communication Completely configurable,
Main advantages higher clock frequency
protocols, cheap, low great for hardware
and higher rates of
power consumption prototyping
acquisition
Must be developed in
Main Higher power VHDL or Verilog which
disadvantages Lower clock frequency
consumption requires time and
experience
Table 2.3: Communication protocols used on data acquisition systems [24].
Comunication
Ethernet PCI PCI Express USB Hi-Speed 802.11x
Speed 125 MB/s 132 MB/s 250 MB/s/ch 60 MB/s 6.75 MB/s/ch1
Communication type Series Parallel Parallel Series Wireless
Portability Yes No No Yes Yes
2.5 Characterisation of Data Acquisition Systems
There are three different architectures acquisition systems: two for simultaneous acquisition and
one for non-simultaneous (multiplexed) acquisition. Simultaneous acquisition systems have full sampling
rate for all channels, no phase delay between channels, smaller crosstalk between adjacent channels
due to individual input amplifiers. Conversely, in multiplexed acquisition systems there is a phase
delay between the acquisition channels, the maximum sampling rate depends on the number of active
channels and the cross talk between channels is increased as all signals are routed through the same
active component. Often, multiplexed architectures can use its full sampling rate as long as only one
channel is active.
In multiplexed acquisition systems, acquiring data is done using just one ADC and a channel
selector (multiplexer) that selects each channel sequentially [26]. The block diagram of the architecture
of a non-simultaneous acquisition system is shown in Figure 2.2.
Figure 2.2: Block diagram of a non simultaneous acquisition system.
The two most common simultaneous sampling architectures are simultaneous sample and hold
9
(SSH) and multi-analog-to-digital converter (multi-ADC). The SSH architecture is comprised by sample
and hold added to the output of the signal conditioning circuit for each channel. The sample and hold
samples the voltage of a continuously varying analog signal. It holds its value at a constant level for a
specified minimum period of time so that it can be sequentially converted by the ADC [18] as seen in
Figure 2.3. It is possible to minimise this time delay in order to allow faster sampling, but it is limited by
the performance of the ADC/amplifier combination. To achieve simultaneous sampling with a multiplexed
architecture, the data acquisition device must contain SSH circuitry for each input channel before the
ADC/amplifier [26].
Figure 2.3: Block diagram of a simultaneous acquisition system with sample and hold.
The third option of simultaneous acquisition is composed by one ADC and one PGA per channel as
seen in Figure 2.4.
Figure 2.4: Block diagram of a simultaneous acquisition system.
The delay between channels is due to the change the of channel of the channel selector in multi-
plexed acquisition systems. The multiplexer at the entrance of the ADC can only select one channel at
the time and depends on the sampling frequency. Higher sampling frequencies can cause higher delays
depending on the conversion rate of the ADC as seen in Figure 2.5. Therefore, the acquired signal
will be sampled at different instances causing a delay. This delay can be corrected through a software
application to correct the time stamps of each sample.
The time taken for the digital code to achieve the output and remain within some error band is
called the settling time and is shown in Figure 2.6. The settling time is made of four different periods:
the switching time or dead time (during which the digital switching, but not the output, is changing),
the slewing time (during which the rate of change of output is limited by the slew-rate), the recovery
10
Figure 2.5: Two channel measurement of two sine signals using a non-simultaneous acquisition system
[27].
time (recovering from its fast slew and may overshoot) and the linear settling time (when the output
approaches its final value in an exponential or near-exponential manner) [28].
Figure 2.6: DAQ Settling Time [28].
In Figure 2.7 the architectures for simultaneous acquisition and non-simultaneous acquisition, re-
spectively, are represented. Mainly for non-simultaneous acquisition, the settling time is important due to
the channel selector since it is required to wait long enough for the signal to stabilise for each channel at
the entrance of the ADC. This required time to wait is due to the discharge of the parasitic capacitor at the
entrance of the amplifier before selecting another channel. This problem does not exist in simultaneous
acquisition with a sample and hold since there is one ADC per channel.
Crosstalk is a function of how close the signals are to each other and the frequency content of the
signal. If the signals do not have rapid changes, crosstalk should not be an issue although it is correlated
with the effect of the settling time when the signals have rapid changes. Crosstalk is usually caused
by undesired capacitive, inductive or conductive coupling from one circuit, part of a circuit or channel
to another. This phenomenon is measured as the difference of the power of the signal applied to a
channel and the power detected in the channel under test at the same frequency. This phenomenon
also happens in simultaneous acquisition systems, and that despite the fact that channels possess
independent signal conditioning and being isolated.
There is always some interference between different channels, though with a much lower value
11
Figure 2.7: Non-simultaneouson-simultaneous acquisition system (left) and simultaneous acquisition
system (right).
when compared with non-simultaneous acquisition systems [24].

For the measurement of electrical signals, it is always necessary to use two different points of the
circuit, where one of them is always a potential of reference. In the most common measurements, the
potential corresponds to the reference ground (GND) which by convention has a potential of 0 V. If there
is any noise at the terminals, this will always be present when the measurement is carried out, since it
is independent from the measurement method.
In some cases, and in order to perform a measurement taking into account a different reference,
the differential measurement is used and the reference can take any voltage as long as it is within the
systems limits. As seen in Figure 2.8, both methods use an amplifier. The first method presents a
differential input and in the second, one of the terminals is connected to GND [24].
Figure 2.8: Differential measurement (left) and measurement referenced to GND (right).
Differential measurements have the advantage of good common noise immunity because any inter-
ference in the terminals always equally affects the other, cancelling each other in the measurement of
the signal. Indeed it makes the signal difference between the two terminals. In the National Instruments
DAQs, the disadvantage is the need to occupy two channels. The reference to GND measurement has
the advantage of occupying just one channel and the disadvantage of being more sensitive to noise in
longer links.
The range of a data acquisition system is the range of amplitudes it can measure. Some devices
allow the user to control the range through programmable gain amplifiers (PGA) that allow different
ranges for the same channel. Then, the best range for the signal at hand is chosen. Usually, the
12
range depends on the signal conditioning in the channels of the DAQ and, therefore, it will condition the
available ranges. Typical DAQ devices have voltage ranges of ±5 V or ±10 V. The voltage levels that can
be represented are distributed evenly across a selected range to take advantage of the full resolution.
For exemple the DAQ NI-6009 [2] has seven ranges from ±1 V to ±10 V. Assuming a ±10 V range
and 12 bits of resolution (4,096 evenly distributed levels), the DAQ can detect a 5 mV change, where a
device with 16 bits of resolution (65,536 evenly distributed levels) can detect a 300 µV change [20].
One of the most important specifications of a DAQ device is the maximum sampling rate, which
is the speed at which the DAQ device’s ADC takes samples of a signal. Typically, the sampling rate
can either be hardware or software timed and the sampling rate depends on the maximum frequency
component of the signal that it is trying to measure or generate [20]. If the sampling is software
timed then it is managed by a controller that runs the operation of the ADCs, the PGAs and the other
components used for signal conditioning. Also, it is dependent on an internal clock driver of high
frequency (in the order of MHz), which will be divided by an integer in the control circuit, generating
a lower frequency that will control the sampling rate of the DAQ device. This signal is generated by
the control unit to allow different rhythms and it is given by the internal clock frequency (fCLK ) of the
microprocessor and a integer number (nCLK ).
fCLK
fs = , (2.2)
nCLK
where nCLK is the number defined by a counter. Usually an interruption is used to control the sampling
frequency (fs ). When the desired sampling frequency is impossible to get without an integer, the closest
integer must be used depending on the rounding of the value desired.
Jitter is a digital phenomenon defined as the short-term variations of a digital signal’s instants from
their ideal positions in time. Jitter is an error in a digital circuit caused by timing variations of the discrete
samples that make up a digital signal. The accumulation of jitter will eventually lead to data errors.
Jitter can be caused by several things, including inaccuracies in the digital clock, which is supposed to
produce a timing pulse at specific intervals, by DC ripples in the power supply and by the data stream
itself. Jitter is a digital phenomenon that can produce noise and degrade the data of a DAQ system [29].
According to the Nyquist theorem it is possible to fully recover information from a signal if the
sampling is performed at a frequency at least twice the maximum frequency of the sampled signal
[17]. Bandwidth is defined as the measure of a circuit or transmission channel to go by a signal without
significant attenuation over a range of frequencies. Bandwidth is measured between the lower and upper
frequency points where the signal amplitude falls −3 dB below the pass-band frequency. The half-power
points are the −3 dB points.
There are two types of bandwidths in an acquisition system, the analog and the digital. The analog
bandwidth of an acquisition system is dependent on the ADC and the IAs used [24]. The digital
bandwidth of a acquisition system is related to the maximum sampling rate. For example, a system
that has an analog bandwidth of 1 MHz and a maximum sampling rate of 300 kSamples/s allows the
acquisition of signals up to a frequency of 150 kHz according to the Nyquist theorem. If subsampling
13
techniques are used, it is the analog bandwidth and not the digital bandwidth that becomes limiting factor
[18].
Usually, the analog bandwidth is bigger than the digital bandwidth in the acquisition systems. In
non-simultaneous acquisition systems, the digital bandwidth of the ADC will be distributed by all existing
channels, thus limiting the maximum sampling frequency of the input signals. In simultaneous acquisition
systems, each channel has at its disposal all the digital bandwidth of the ADC, as there is a dedicated
ADC for each channel.
14
CHAPTER 3
Proposed Architecture
In this chapter the several blocks of the proposed architecture for the data acquisition system are
presented (Figure 3.1).
Figure 3.1: Block diagram of the proposed data acquisition system.
The proposed architecture is composed by three main blocks. The signal conditioning, the analog to
digital converter and the digital control using the USB communication protocol. These proposed system
has simultaneous acquisition, where the analog to digital conversion happens with a single four-channel
ADC [30]. This solution is cheaper than using four ADCs (one per channel) and can still achieve high
acquisition ratios since the data transmission is done by serial interface with two data output lines. To set
the sampling frequency, the input range of each channel, the transmission of the acquired data and the
clock signal supplied to the ADC a microcontroller (PIC24EP512GU810) [31] is used. The acquired data
is sent to a PC through the integrated circuit FT232H [32] from FTDI, which receives the data through
8 bit parallel communication from the PIC microcontroller. This integrated circuit allows the system to
send data through the USB Hi-Speed communication protocol. The interface between the user and the
data acquisition system, allowing the visualisation and data processing, can be done by an application
developed in LabVIEW. This way the user can control the sampling frequency, the input range of each
channel and the sampling mode (sequential or continuous).
3.1 Signal Conditioning
The signal conditioning circuit can be separated into two parts, the input protection and the amplifi-
cation block. In the input, a protection circuit limits the voltage and current that reaches the input of the
amplifier block, which in turn amplifies the signal before reaching the ADC. Through various techniques
for signal conditioning, including attenuation and signal amplification, the acquisition system allows the
15
measurement of a range of high and low amplitude signals. In Figure B.9 the proposed schematic of the
signal conditioning is represented.
Figure 3.2: Proposed signal conditioning circuit schematic.
3.1.1 Input Protection
In the proposed data acquisition system, the maximum voltage is ±10 V. This system must be
protected against higher voltage and electric current values that could damage the circuit and its com-
ponents. In Figure 3.3, the schematic of the proposed circuit is represented.
This overload protection reduces the current entering the circuit by having resistor, R1 = 1 MΩ, in
series with the input of the circuit. The worst case scenario is at the maximum voltage rating, where
Vin =10 V, using Ohm’s law, the maximum current entering the circuit would be 10 µA.
A voltage divider is created using R1 and R2 in order to reduce the voltage to half. In that way, the
amplification block can receive the input signal without damaging the instrumentation amplifiers. Again,
assuming the worst case scenario that only half of the input voltage goes through the divider and, in
order to make sure it won’t damage the instrumentation amplifier (with R2 = 1 MΩ), a biased diode
clipping was inserted to make sure the voltage that goes to the input of the IA is at a maximum 5 V.
The diode clipping (BAS70-07 shotkey diodes [33]) works for the positive input voltage signal when
input voltage exceeds voltage (+V). The diode D1 conducts while diode D2 is reversed biased and so
voltage +V appears across the output. This output voltage +V stays as long as the input signal voltage
exceeds +Vcc. On the other hand, and for the negative input voltage signal, the diode D1 remains
reverse biased and diode D2 conducts only when input voltage exceeds voltage −Vcc in magnitude.
Thus, during the negative half cycle, the output stays at −V as long as the input signal voltage is greater
than −Vcc. These diodes have a direct voltage of 0,4 V, 70 mA of direct current and 70 V of reverse
voltage.
16
10 MHz, 20 V/μs, G = 1, 2, 5, 10 iCMOS
ProgrammableFigure
Gain3.3:Instrumentation Amplifier
Proposed input protection circuit schematic.
AD8250
3.1.2 Amplification Block FUNCTIONAL BLOCK DIAGRAM
10-lead MSOP DGND WR A1 A0
The amplification block aims to adjust, as much 2 as 6 possible,
5 4 the amplitude of the signal to exploit
gains: 1, 2, 5, 10
LOGIC
ogrammable gain setting
the dynamic range of the ADC. To–INmake 1 this possible, it must be known at the outset what the maximum
V to ±15 V
formance range of the signal to be measured is. In that way, the user can use the digitally programmable gain
8 dB (minimum), G = 10
of the amplifier to better suit his needs. The use of instrumentation amplifiers is chosen (AD8250 [34]
7 OUT
: 10 ppm/°C (maximum)
ft: 1.7 μV/°C (maximum),
fromG =Analog
10 Devices) for three reasons: because they have programmable gains (in this case, four
ormance
digitally
ime: 615 ns to 0.001% programmable gains (1,+IN
(maximum) 2, 105 and 10)); they also have a joint CMRR mode (of 80 dB1 ), which
AD8250
e: 20 V/μs (minimum)
amplifies only the difference between the signals at its inputs; and finally because they make differential
06288-001
n: −110 dB THD at 1 kHz 8 3 9

+VS –VS REF
ver frequency: 80 dB measurements.
to 50 kHz (minimum)
nV/√Hz, G = 10 (maximum) Figure 1.
1 mA 25
NS 20
G = 10
15 G=5
ysis
ement
GAIN (dB)
10
G=2
5
SCRIPTION
G=1
n instrumentation amplifier with digitally 0
ains that has GΩ input impedance, low output

–5
stortion making it suitable for interfacing with
ng high sample rate analog-to-digital converters –10
06288-023
1k 10k 100k 1M 10M 100M

high bandwidth of 10 MHz, low THD of −110
FREQUENCY (Hz)
g time of 615 ns (maximum) to 0.001%. Offset
Figure 2. Gain vs. Frequency
ft are guaranteed to 1.7 μV/°C and 10 ppm/°C,
= 10. In addition to its wide input common Figure 3.4: Frequency response of the AI for the different possible gains [34].
Table 1. Instrumentation Amplifiers by Category
boasts a high common-mode rejection of 80 dB
General Mil Low High Speed
to 50 kHz. The combination of precision dc Purpose Zero Drift Grade Power PGA
pled with high speed capabilities
This makes the has a maximum
IA also AD82201 bandwidth
AD82311 ofAD620
10 MHz AD627 (for 1a gain of 1 V/V [34]) and a slew rate of
AD8250
ent candidate for data acquisition. Furthermore, AD8221 AD85531 AD621 AD6231 AD8251
1 For the minimum gain of 1 V/V at 50 kHz.
olution simplifies design and manufacturing AD8222 AD85551 AD524 AD82231 AD8253
rmance of instrumentation by maintaining a AD82241 AD85561 AD526
ternal resistors and amplifiers. AD8228 AD85571 AD62417
1
Rail-to-rail output.
r interface consists of a parallel port that allows
in in one of two ways (see Figure 1). A 2-bit word The AD8250 is available in a 10-lead MSOP package and is
be latched using the WR input. An alternative is specified over the −40°C to +85°C temperature range, making
20 V/µs. The bandwidth of the instrumentation amplifier used is 10 MHz when it is configured for the
minimum gain and approximately 1 MHz for the maximum gain. This can be seen in Figure 3.4 which
shows the frequency response of the AI for the different possible gains. The slew rate is given by,
SR ≥ 2πf × A (3.1)
where f is the frequency and A is the amplitude of the sine signal. At lower frequency of approximately
636 kHz and at maximum amplitude of 5 V (due to the clipping circuit), it is possible to calculate the
signal that will need to have the maximum rate of change of output voltage (slew rate) of 20 V/µs.
Table 3.1 displays the gain of the amplifier block associated with each range.
Table 3.1: Gain of the instrumentation amplifier.
Gain
Maximum Range (V)
V/V dB
1 0 ±10
2 6 ±5
5 14 ±2
10 20 ±1
Since the output of the amplification block is a bipolar signal with a voltage reference of 0 V (GND),
it is yet required to be in the input range of the ADC, which is between 0 V and 5 V. To adjust the signal
to the input range of the ADC and make an offset correction, a level shift circuit for a bipolar input [30] is
placed. Using a operational amplifier circuit and four external resistors that assures that the measured
voltage is above 0 V and around the the internal reference voltage (2,5 V) of the ADC as displayed in
Figure 3.5. For a bipolar input of ± 5 V, R1 =2 kΩ and R2 =10 kΩ.
Figure 3.5: Level shift circuit for bipolar input for the ADC (ADS8361) [30].
18
3.2 Analog to Digital Converter
To choose an analog to digital converter, there are some parameters to take into account, such as
the conversion method, the resolution, the maximum sampling rate, the data interface, the number of
channels, the type of acquisition and the cost.
The chosen analog to digital converter is the ADS8361 [30] from Texas Instruments. It is a high-
speed, low-power, dual, 16-bit A/D converter that operates from +3 V/+5 V supply. It has a 4 µs
successive approximation A/D converter, two differential sample-and- hold amplifiers, 16-bit resolution,
an internal +2,5 V reference, up to 500 ksamples/s sampling ratio, four fully differential input channels
grouped into two pairs for high-speed and simultaneous signal acquisition. Inputs to the sample-and-
hold amplifiers are fully differential and are maintained differentially to the input of the A/D converter.
The high-speed dual serial interface and control inputs minimise software overhead. The output data for
each channel is available as a 16-bit word. To achieve the maximum throughput rate, the master clock
must be set at 10 MHz. A minimum of 20 clock cycles are required for each 16-bit conversion, as the
data output format are 20 bits with the first two bits having the channel information (0 or 1, A or B) and
the last two bits being zeros.
Figure 3.6: Block diagram of the ADS8361 analog to digital converter [30].
The ADC has four modes of operation, all depending on the channel selection and on the data
output. These modes are selected with M0 and M1. A0 is used to choose which channel to send (0
or 1). The channel selection allows to send information of a single channel of either channels (A and
B alternating) or to always send a specific channel that changes the data output as well (from a single
output (Serial Data A pin only) or both the data outputs pin).
The chosen mode is Mode III since it sends information of each channel sequentially. A0 pin
is ignored in this mode and with both data output pins active. Serial Data A pin sends information
from channel CHA0 and CHA1 and Serial Data B pin from CHB0 and CHB1 sequentially. The RD
19
Figure 3.7: Mode III, Timing Diagram for M0 = 1 and M1 = 0.
and CONVST signals are linked together independently of the mode. This way, whenever the ADC is
requested to convert data, it will be requested to send it as well (instead of storing it in the internal
comparator). BUSY goes high during a conversion and returns low after the third LSB has been
transmitted on either the Serial A or Serial B output pin. After all the configurations by the user, CS
goes low when the microcontroller is ready to receive data. The timing diagram for Mode III can be seen
in Figure 3.7.
The conversion method of this ADC from voltage to binary two’s complement is made by linear
interpolation and has a LSB of 76 µV. Where 0 V is the voltage for the negative full-scale code 8000H ,
the voltage of 2,5 V is the bipolar zero code of 0000H and the voltage of 5 V for the positive full-scale code
is 7F F FH . With two of these points, it is possible to determine in the LabVIEW program, the measured
ADC voltage.
3.3 USB Interface
The USB interface is a the FT232H, a single channel USB 2.0 Hi-Speed (480Mb/s) to UART/FIFO
integrated circuit and can be configured in a variety of serial or parallel interfaces. The proposed mode
of operation is the one that allows the use of the PMP module by the microcontroller. Therefore, the
asynchronous 245 FIFO mode that has a transfer data rate up to 8 Mbyte/s. When configured in this
mode, it has two input pins used to read and write strobes and two output flags (read and write flag) that
are active low. When one of them is high, the microcontroller is unable to perform that operation in the
FIFO (read or write or both). When low, when there is data available to read from the FIFO or write into
the FIFO, the strobes can be used. In this mode, data is written or read on the falling edge of the strobe
20
signals and does not provide a output clock signal (and does not expect one). To enter this mode, the
external EEPROM must be set to 245 asynchronous FIFO mode which only needs to be programmed
from the computer once.
The two output flags are connected to the microcontroller as two external interrupts and both
stop the normal behaviour of the firmware (waiting instructions or acquisition) to deal with one of two
situations: either the FIFO is full and the microcontroller is unable to write more data (this is not supposed
to ever happen but, if it ever happens, it stops the acquisition); or the user sends instructions from the
LabVIEW program, such as start acquisition, stop acquisition or any other generic configurations, before
starting to acquire.
3.4 Processing and Control Unit
The processing unit has an architecture with 16 bits (because of the chosen ADC) is needed. It is
also important to know the processing speed, the serial communication protocol speed and the existence
of a bidirectional parallel communication module. The PIC24EP512GU810 microcontroller has a 16 bit
architecture, a working frequency of 120 MHz, a flash memory of 512 kB, a Random Access Memory
(RAM) of 52 kB, 16/32 bit timers and 15 configurable channels DMA, as seen in Figure 3.8. The DMA
has priority arbitration and can access the UART, SPI, I2 C, timers, input compare and output compare.
The microcontroller has nine 16-bit timers and up to four 32-bit timers that can be remappabled from the
peripheral pin select (PPS). The PPS increases the pinout options available on this device, being able to
better tailor the microcontroller to the application, rather than trimming the application to fit the device.
Figure 3.8: Block diagram of the PIC24EP512GU810 microcontroller [35].
21
3.4.1 Resource Management
The Internal Fast RC (FRC) oscillator provides a nominal 7,37 MHz clock without requiring an ex-
ternal crystal or ceramic resonator and starts immediately. After a power-on reset, the FRC parameters
can be changed to work at a oscillator frequency of 140 MHz. Since one instruction cycle takes two
oscillator cycles, the instruction cycle frequency is 70 MHz.
Two control variables are used to register data provided by the user sent from the LabVIEW VI as
acquisition and samples. The variable acquisition is a 8-bit variable that stores the type of acquisition.
If 1, it means it is a sequential acquisition with a predetermined number samples. If 0, it means is a
continuous acquisition and it will only be stopped by the user. The samples is a 32-bit variable that
stores the amount of samples requested by the user. Therefore, in a sequential acquisition mode there
is a limit of samples that can be requested (maximum number of samples is 232 ).
There are several ways to configure the PWM that is sent as clock input to the ADC. The more
efficient way is to use a timer to count how many instruction cycles are required to create a 10 MHz
PWM and then call an interrupt to process the bits into a byte sized variable. To avoid the PIC from
stopping the counter of instruction cycles timer when an interrupt service routine (ISR) is issued (which
would be a problem since data would be lost), one channel of the DMA is used to count the cycles so
that the CPU is free to process the input bits as well as other tasks.
To store the bits received from the ADC 3 byte sized variables in a buffer were allocated in the
SRAM. Since writing to flash memory or the EEPROM would take time and resources of the CPU and
from the DMA. Therefore, a buffer with the channel (0 or 1) and the two bytes from the two serial data
outputs (A and B) of the ADC was chosen to perform the task. A circular buffer in the SRAM was not
implemented because, although most of the SRAM is accessed through a single port (either the DMA
or CPU can read or write at a time), there is 4 kB as a dual port SRAM (DPSRAM). That allows for both
the DMA and CPU to access at the same time without having to incur any arbitration delays since there
is a separate dedicated bus to this area only. Sending data from the PIC (master) to the USB interface
(slave) is made with another DMA channel and uses the parallel master port (PMP) module of the
microcontroller. If a serial communication protocol was being used between the microcontroller and the
computer it would not be able to perform a lossless transmission. To avoid decreasing the throughput
of the communication between the microcontroller and the computer a parallel-serial communication
interface (FTDI 232H) was used.
3.4.2 Parallel Communication
The PMP module is configured in 8-bit mode, Master Mode 2 (separate read and write strobe pins),
no chip-select lines active, no address lines active and strobe polarity active low. Since no addressing
is required to write the USB interface in the mode FT245, and since 8-bit mode is only about how to
read/write the register PMDIN1 which is on an 8-bit data bus, the 8-bit mode was chosen. This specific
DMA channel was configured in order that, when the byte sized buffer is full (two complete bytes of
two different channels were read), it automatically sends the data to the USB interface. Since the PMP
22
module is an independent module from the CPU, it allows to save instruction cycles from the CPU since
it is not required for it to intervene in this operation, only being notified by an interrupt flag when the
operation as been finished.
Figure 3.9: FT245 Asynchronous FIFO interface read signal waveforms [32].
To perform a read on the parallel port, the microcontroller reads the low byte of the PMDIN1 register.
Then, the read line (PMRD) is strobed and the read data is placed into the low byte of the PMDIN1
register. The read data obtained from the PMDIN1 register is actually the read value from the previous
read operation. Therefore, the first read will be a dummy read to initiate the first bus read and fill the
read register. Also, the requested read value will not be ready until the BUSY bit is observed low. In a
back-to-back read operation, the data read from the register will be the same for both reads and the next
read of the register will yield the new value.
Figure 3.10: FT245 Asynchronous FIFO interface write signal waveforms [32].
To perform a write onto the parallel bus, the microcontroller writes to the low byte of the PMDIN1
register. The lower byte of the data written into PMDIN1 register is placed onto the data bus. Then, the
write line (PMWR) is strobed. The timings of the Figures 3.9 and 3.10 are displayed in the Table 3.2.
Table 3.2: FT232H read and write timings [32].
Timings (ns) T1, T3, T6 T2, T7 T4, T10 T5, T11 T8, T9
Min 1 49 0 30 5
Max 14 - - - -
23
3.4.3 Firmware Flowchart
To better summarise the resources described before, in Figure 3.11 the flowchart comprises all the
information at a basic level of what happens from the moment that the DAQ system is powered on and
being used. After each cycle of verifying if the user wants to stop the information is sent through the
parallel interface.
Figure 3.11: Firmware flowchart.
24
3.5 Current Consumption
The DAQ system is projected to be powered only by the USB port and has a projected current
consumption between 232 mA and 447 mA as seen in Table 3.3. Even though the USB port supplies
500 mA, the maximum current limit is unachievable since only up to 300 mA are supplied from the DC-
DC converter. Therefore, the actual current consumption is between 232 mA and 300 mA and there is
a high dependency on the PIC power consumption. If too many PIC modules are powered up, the DAQ
system will shut down from lack of current.
Table 3.3: Current consumptions of each component.
Current
Supplied Drawn
Converters 300 mA 170µA
ADC 35 mA
Signal Conditioning 32 mA
USB Interface 61 mA
PIC 105 mA to 320 mA
Total 300 mA 232 mA to 447 mA
3.6 LabVIEW Software
The virtual instrumentation (VI) that the user can use is exactly as the one in the Figure 3.12. This
layout VI was developed with the resources and drivers supplied by the datasheet [32].
Figure 3.12: Virtual instrumentation layout for sequential acquisition.
25
With Device ID, the system designator can be chosen and it is possible to know which system the
user is controlling at that time. The user can pick which channels wants to receive information from by
selecting the respective boolean variable. Also it has a 32-bit variable with the Number of samples to be
required by the user for the DAQ system and the gains of each instrumentation amplifier.
Figure 3.13: Virtual instrumentation layout for sequential acquisition.
This VI returns an error if one happened during the acquisition and a cluster of arrays with the
acquired samples to the user. The user then can choose how to process or how display them as seen
in Figures 3.12 and 3.13.
Figure 3.14: Virtual instrumentation layout for continuous acquisition.
In the continuous acquisition VI (Figure 3.14) the data that is being constantly read by the VI in a
26
while cycle that will only stop if the user hit the stop button. The reading process starts with a request for
how many bytes can be read from the FIFO of the USB Interface, then it proceeds to transfer bytes to
the computer. The array of 8-bit values is converted into an array of 16-bit values only to be separated
by channel information (0 or 1) and by channel data (A or B). Using the interpolation method mentioned
before, it is possible to convert the 16-bit data into a voltage value. These values will be joined into a
cluster of arrays to be delivered to the user as it can be seen in Figure 3.12.
27
28
CHAPTER 4
System Characterisation
In this chapter the tests to develop a characterisation of the system are presented: the analog
bandwidth of the system, the crosstalk between channels, the delay between channels, the average
power spectrum of a sine signal in each channel and an example of continuous acquisition. A specific
VI was built to perform each of these tests to taylor the needs and calculations of each test. They are
described in detailed bellow.
4.1 Analog Bandwidth
The analog bandwidth test describes the influence the circuit that precedes the analog to digital
converter at the incoming signal.
In order to perform this test to each channel, a VI that uses the developed DAQ system and the
function generator TG1010A generates the input signals into the DAQ. The generator is controlled by the
VI and is connected to the computer through GPIB communication. This VI controls all the parameters
of the DAQ system as well as the amplitude and frequency of the generated input signal. The amplitude
is at each of the limit of each configurable gain input range. In each measured frequency, the difference
between the output signal and the input signal is calculated. This is done to each sample in the frequency
sweep, from 10 Hz to 1,5 MHz, and each sweep was made 20 times.
The average analog bandwidth of each channel are presented in the Figures 4.1 to 4.4.
From Figures 4.1 to 4.4, it is possible to check that the DAQ system analog bandwidth depends
on the smallest scale (±1 V) where the gain is higher. Above 1 MHz the analog bandwidth is distorted,
decreasing the gains to the amplitude input ranges of 1 V and 2 V and the slight increase in the amplitude
input ranges of 5 V and 10 V. The device mainly responsible for limiting the analog bandwidth is the
instrumentation amplifier of each channel with a slew rate of 20 V/µs and which starts distorting the
input signal at 650 kHz. To see changes (effect of the capacitor of the diode) in the figures above we
would need to change the IA or do a sweep with strong signals instead of weak signals.
The overall DAQ system analog bandwidth is independent from the gain until approximately 700 kHz.
After that, the gain distorts the analog bandwidth.
29
Figure 4.1: Channel 1 analog bandwidth for the different input ranges.
30
31
4.2 Crosstalk Between Channels
In order to test the crosstalk between channels, one input signal is placed on one channel with the
other three connected to the ground plane. The influence detected on those channels is measured.
Crosstalk, in dB, is measured as the difference between the power detected in the channel where the
input signal is and the channel being tested,
Crosstalk (dB) = Pinput signal (dB) − Pdetected (dB). (4.1)
Each test was performed 20 times to obtain the average power spectrum of each channel. After-
wards, the crosstalk was measured. In Figure 4.5, there is the average noise floor of channel 2 for
the amplitude range of ±10 V represented after the array samples had been acquired. The FFT was
performed to that array then the point by point averages were placed into another array.
The input signal to test the crosstalk requires a high frequency and amplitude in order so that slight
changes can be noticed on other channels. The testing signal was a sine signal with 48 kHz and 9,5 V
whose spectrum can be seen in Figure 4.6.
Figure 4.5: Average noise floor of channel 2 for the amplitude range of ±10 V.
32
Figure 4.6: Average power spectrum of channel 1 for the amplitude range of ±10 V of a sine signal with
48 kHz and 9,5 V.
From the results, displayed in the Table 4.1 it can be concluded that the crosstalk effect is spread
evenly among all the channels. It is also almost independent of the channel distance and higher than
the noise floor detected. This is due to a bad design decision in the PCB, since a power supply line in
the PCB crosses all channels, causing an even interference along the PCB board. Since the crosstalk
values obtained are higher than the noise floor detected (±90 dB), the floor to be considered is the
crosstalk floor as the minimum limit of the signals to measure.
Table 4.1: Crosstalk values of the four channels of the DAQ system.
Input signal Tested channel

Channel 1 Channel 2 Channel 3 Channel 4
Channel 1 - 86,11 dB 86,65 dB 86,95 dB
Channel 2 86,37 dB - 86,38 dB 86,53 dB
Channel 3 86,54 dB 86,09 dB - 86,23 dB
Channel 4 86,99 dB 86,44 dB 86,27 dB -
4.3 Continuous Acquisition
To test the DAQ system and check if continuous acquisition was possible, four different input signals
were measured as it can be seen in Figure 4.7. They have the same amplitude and different frequencies.
Also, they were sampled at a frequency of 100 kSamples/s/ch to assure that less periods of each signal
had to be acquired. In channel 1, there is a sine signal with a frequency of 1 kHz. In channel 2, there is
a sine signal with a frequency of 750 Hz. In channel 3, there is a square signal with a frequency of 600
Hz and finally channel 4 is a triangular signal with a frequency of 500 Hz.
33
Figure 4.7: Simultaneous Acquisition with the four channels of the DAQ system.
Even though each channel has an input signal with different frequencies, there is a measure delay
between each channel to measure that a different test was made. The delay between channels was
measured and is displayed in Table 4.2.
4.4 Delay Between Channels
In order to measure the delay between channels, the same input signal was placed in all four
channels with the same amplitude and frequency in a continuous and simultaneous acquisition. To
measure the delay, it has to be known the period between samples and after that the phase difference
between channels can be measured. The time delay is given by,
1
∆φx fsignal
∆t = , (4.2)
360o
where ∆t is the time delay, ∆φ is the phase delay in degrees and fsignal is the frequency of the signal.
To obtain this data, an internal VI was supplied by the software LabVIEW. As input, it has the measured
sine signal (as an array) and as outputs, the frequency, amplitude and phase of this array.
The time delay is given related to channel 1 and displayed in Table 4.2.
The time delay does not varies in average between all channels from −24,3 ns to 30,05 ns. The
value of the time delay can change depending on the frequency of the input signal tested. Compared to
known DAQ systems with no simultaneous acquisition, the time delay is inferior.
34
Table 4.2: Time delays of the four channels of the DAQ system related to channel 1.
Tested channel
Channel 1 Channel 2 Channel 3 Channel 4
Channel 1 - 12,28 ns -24,30 ns 29,49 ns
Channel 2 -12,31 ns - -19,87 ns 25,37 ns
Channel 3 21,23 ns -9,32 ns - 14,35 ns
Channel 4 30,05 ns -18,81 ns -13,79 ns -
4.5 Average Power Spectrum
A single sweep sample acquisition does not collect enough data to give accurate information about
the power spectrum of a signal in a channel. Therefore, using several sweeps over a period of time
assures a higher accuracy in the data measured. If it was required an even higher accuracy, it could
be achieved by sweeping over a longer period of time (more samples than before), which reduces the
variance of the resulting spectrum.
To verify the behaviour of a channel, 300 kSamples at a sampling rate (Fs ) of 100 kSamples/s are
acquired of several different input signals (sine signal, square signal and triangular signal) with the same
amplitude, the same frequency and with 50% duty cycle. The channel is measured 20 times and the
5 kHz frequency is chosen in order that, up to the Nyquist frequency ( F2s ), several harmonics of the
triangular signal and square signal could be seen.
Figure 4.8: Average power spectrum of a sine signal with a frequency of 5 kHz.
35
Figure 4.9: Average power spectrum of a square signal with a frequency of 5 kHz.
Figure 4.10: Average power spectrum of a triangular signal with a frequency of 5 kHz.
36
From the average power spectrums measured, it can be seen, as expected, that the square signal
has higher power in the fundamental frequency and its harmonics than in the triangular signal (as seen
in Figures 4.9 and 4.10). The average power spectrum in any of the cases tested provides a clearer
noise floor, fundamental frequency and harmonics than a single sweep would with the same number
of samples at the same sampling rate as seen is Figure 4.11. Changing the signal frequency would
allow us see the other harmonics (e.g. 11th and above) hidden in the first harmonics (1st to 9th) due to
spectral mirroring.
Figure 4.11: Power spectrum of a single sampling set triangular signal with a frequency of 5 kHz.
37
38
CHAPTER 5
Conclusions
Current data acquisition systems like the NI-6008 and NI-6009, commonly used in the courses at
IST, already allow, not only for a wide range of academic applications, but also domestic and industrial
applications. The usefulness of a data acquisition system is that it allows for the configuration of many
of its parameters through a virtual graphic software interface and this is an asset to be taken into
consideration. The main advantage of the produced prototype is that the development cost is far lower
compared to the others already existent in the market. This is mainly due to the fact that the this DAQ
does not have some extra specifications as the ones analysed (higher maximum frequency, number of
channels and input ranges). But, contrary to the all-purpose market solutions, this solution focuses on
the academic environment and, more specifically, on teaching purposes.
The developed prototype has four differential channels, all with simultaneous acquisition and a sam-
pling frequency of 100 kSamples/s/ch, and with input amplitude ranges between ±1 V and ±10 V. The
prototype is entirely powered by USB. The PIC24EP512GU810 shows the versatility of a microcontroller
with peripheral pin selection, specially when implementing communication protocols between the PIC
and the the other main devices (ADC and FT232H). USB interfacing was the industry standard USB 2.0
Hi-Speed since it allowed to achieve the desired data transmission rates.
This work was able to be cost-efficient by lowering the cost of the signal conditioning of the system.
Thanks to this, the cost of the major components of these data acquisition systems were lowered. One
of the main advantages is the possibility of being built within the university instead of buying one already
existing in the market. Also the development cost was absorbed by the work developed within the
thesis. Only considering the production cost of this DAQ system, it would be the lowest price for its
characteristics compared to the ones in Table 1.1.
As expected from the average power spectrums measured, it can be seen that the square signal
has higher power in the fundamental frequency and its harmonics than the triangular signal for a duty
cycle of 50%. The average power spectrum in any of the cases tested provides a clearer noise floor,
fundamental frequency and harmonics than a single sweep would with the same number of samples at
the same sampling rate.
The analog bandwidth of this data acquisition system is of 700 kHz, which is higher than the
sampling rate with a value of 100 kSamples/s, and can be used in applications that need under sampling
techniques. The analog bandwidth is higher (1 MHz) for some input amplitude ranges. This happens
due to the instrumentation amplifier slew rate distorting the signal. Therefore, the recommended working
bandwidth is 700 kHz.
From the crosstalk tests, an even distribution of the crosstalk between channels was measured. In
the planning of PCB design, the supply block was to be the furthest away from the signal conditioning
39
as possible in order to avoid a higher crosstalk between adjacent channels. The biggest mistake with
impact on the crosstalk between channels is the fact that the power supply is intertwined between all
channels and specially the data lines.
The main goal with the simultaneous acquisition test was, first, to know if the system would choke
at the total sampling frequency of 100 kSamples/s for all four channels and, second, if it also allowed to
verify the existing channel delay between them. It is truly a simultaneous acquisition since the system
worked properly with the desired maximum sampling frequency and also demonstrated that the channel
delay varies in average between all channels from −24, 3 ns to 29, 4 ns.
During the development phase of the prototype and during the acquisition tests, it was shown that
the prototype system requires only USB power supply and that the current consumption is between 232
mA and 300 mA.
The developed prototype system main goal is to be used for teaching purposes. Therefore, the
virtual communication interface with the computer was developed in LabVIEW 2014, although the drivers
supplied by the USB interface allowed for virtual communication interfaces with other softwares as well
as other operating systems.
Currently the system is fully operational and, even though this prototype is cheaper than the ones
currently used in the market, a better DC-DC converter is required since it would allow the PIC to use
as much current as it needs. The current solution works by disabling/not using some internal modules,
such as the input capture module that would be vital for a better DMA/CPU synergy and better firmware
programming.
For future work, changing the DC-DC converter to allow for full usage of the PIC capabilities would
be a significant change. Small redesign of the PCB design are desirable to avoid all the power supply
lines to cross with data lines at any point in the circuit. Also, the development of a box to protect the
prototype could be added.
40
References
[1] National Instruments. What is data acquisition. [Online]. http://www.ni.com/data-acquisition/what-is/
[2] National Instruments, User Guide and Specifications NI USB-6008/6009.
[3] National Instruments, User Guide and Specifications NI USB-6215.
[4] Data Translation, ECONseries Low Cost USB Data Acquisition Modules.
[5] ADLINK Technology Inc., USB-1900 series.
[6] KUSB 3100 Series - USB-Based Data Acquisition Modules, Keithley.
[7] Agilent U2300A Series USB Modular Multifunction Data Acquisition Devices, Agilent.
[8] Agilent U2500A Series USB Modular Simultaneous Sampling Multifunction DAQ Devices, Agilent.
[9] Doug Abbott, PCI Bus Demystified, 2004.
[10] Technology Ajay V. Bhatt and Research Labs, Creating a PCI ExpressTM Interconnect, Intel
Corporation.
[11] IEEE 802.3™: ETHERNET, IEEE.
[12] National Instruments, What is Signal Conditioning.
[13] “What is Voltage Rating.” [Online]. http://www.wisegeek.com/what-is-voltage-rating.htm
[14] National Instruments, Basic Linear Design.
[15] “Clipping Circuits.” [Online]. http://www.circuitstoday.com/clipping-circuits-2
[16] Pedro Ramos, “Conversores DA/AD,” Acetatos das aulas teóricas de Instrumentação e Medidas,
2011-2012.
[17] Franco Maloberti, Data Converters. Springer US, 2007, ch. 3, pp. 77–140.
[18] Pedro Miguel Fonseca Pinto, “Sistema de Aquisição de Dados baseado em DSP,” Master’s thesis,
Instituto Superior Técnico, Dezembro 2012.
[19] Tony Girard, Understanding Effective Bits, Signatec.
[20] National Instruments, How to Choose the Right DAQ Hardware for Your Measurement System.
[21] Walt Kester James Bryant, Analog-Digital Conversion Architectures.
[22] Texas Instruments, Understanding Data Converters.
[23] Jim LeClare, A Simple ADC Comparison Matrix, Maxim Integrated, June 2003.
41
[24] Ricardo Jorge Duarte da Silva, “Placa de aquisição alimentada por USB,” Master’s thesis, Instituto
Superior Técnico, Novembro 2011.
[25] Pi Huang, “Understanding IEEE 802.11ac VHT Wireless,” May 2013. [Online].
http://electronicdesign.com/communications/understanding-ieee-80211ac-vht-wireless
[26] National Instruments, Simultaneous Sampling Data Acquisition Architectures.
[27] National Instruments, “How Do I Eliminate Ghosting From My Measurements?” [Online].

http://digital.ni.com/public.nsf/allkb/73CB0FB296814E2286256FFD00028DDF
[28] Walt Kester and James Bryant, Basics of ADCs and DACs, 2007.
[29] An Introduction to Jitter in Communications Systems, Maxim Integrated.
[30] Texas Instruments, Dual, 500kSPS, 16-Bit, 2 + 2 Channel, Simultaneous Sampling Analog-To-
Digital Converter.
[31] Microchip, dsPIC33EPXXX(GP/MC/MU)806/810/814 and PIC24EPXXX(GP/GU)810/814.
[32] Future Technology Devices International Ltd FT232H Single Channel Hi- Speed USB to Multipur-
pose UART/FIFO IC.
[33] NXP Semiconductors, BAS70 series 1PS7xSB70 series General-purpose Schottky diodes.
[34] Analog Devices, AD8250: 10 MHz G = 1, 2, 5, 10 iCMOS® Programmable Gain Instrumentation

Amplifier.
[35] “PIC24 Block Diagram.” [Online]. http://www.microchip.com/pagehandler/en-us/family/16bit/

architecture/architecture.html
42
APPENDIX A
Bill of Materials
In this appendix are detailed all the costs, value and description of each component use in this data
acquisition system.
Table A.1: Bill of materials - capacitors.
Capacitors
Value Farnel Description Quantity Cost Unit (e) Line Cost (e)
27 pF KEMET C0603X270J5GACAUTO CAP, MLCC, C0G/NP0, 27PF, 2 0,193 0,386

50V, 0603
0,1 µF KEMET C0603C104Z3VACTU CAP, MLCC, Y5V, 0.1UF, 25V, 15 0,0075 0,113
0603
1 µF MULTICOMP MC0603X105M6R3CT CAP, MLCC, X5R, 1UF, 4 0,0115 0,046
6.3V, 0603
10 µF VISHAY TP8R106M016C CAP, TANT, 10UF, 16V, CASE R 3 0,475 1,425
10 µF MURATA GRM188R61C106MA73D CAP, MLCC, X5R, 10UF, 1 0,205 0,205
16V, 0603
4.7 µF KEMET T495A475K020ATE1K8 CAP, TANT, 4.7UF, 20V, CASE 3 1,490 4,470
A
Total table cost 6,645 e
Table A.2: Bill of materials - resistors.
Resistors
Value Farnel Description Quantity Cost Unit (e) Line Cost (e)
0Ω YAGEO RC0603FR-070RL RESISTOR, THICK FILM, 0 OHM, 7 0,005 0,035

100MW, 1%
20 kΩ SUSUMU RR0816P-202-B-T5 THIN FILM CHIP RESISTOR 12 0,124 1,488
300 Ω BOURNS CR0603-FX-3000ELF RESISTOR THICK FILM, 300 16 0,0236 0,378
OHM, 1%, 0603
10 kΩ TE CONNECTIVITY CRGH0603J10K RESISTOR, POWER, 10 0,0097 0,097
10K, 0.2W, 5%, 0603
20 kΩ BOURNS CR0603-FX-2002ELF RESISTOR THICK FILM, 4 0,025 0,100
20KOHM, 1%, 0603
1 MΩ BOURNS CR0603-FX-1004ELF RESISTOR THICK FILM, 16 0,0416 0,666
1MOHM, 1%, 0603
43
Table A.3: Bill of materials - converters.
Converters
Type Farnel Description Quantity Cost Unit (e) Line Cost (e)
DC-DC XP POWER IR0505S DC/DC CONVERTER, SEMI REG, DUAL 1 12,170 12,170
5V
LDO ANALOG DEVICES ADP122AUJZ-3.3-R7 IC, LDO, 3.3V, 0.3A, 1 1,210 1,210
5TSOT
Table A.4: Bill of materials - USB interface.
USB Interface
BNC Jack TE CONNECTIVITY / AMP 5227161-7 RF COAXIAL, BNC, 4 2,650 10,600

RIGHT ANGLE JACK, 50OHM
BNC Jam Nut TE CONNECTIVITY / AMP 1-329631-2 NUT, BNC CONNEC- 4 0,185 0,740
TOR LEAD, JAM NUT
12 MHz Crystal TXC 7B-12.000MEEQ-T XTAL, 12.000MHZ, 10PF, SMD, 5.0X3.2 1 1,240 1,240
EEPROM MICROCHIP 93LC56B-I/SN IC, EEPROM SERIAL 2K, 93LC56, 1 0,220 0,220
SOIC8
Mini USB B TE CONNECTIVITY / AMP 1734035-1. CONNECTOR, MINI 1 1,010 1,010
USB B, RECEPTACLE, SMT
FT232H FTDI FT232HL-REEL INTERFACE, USB - UART/FIFO, 48LQFP 1 4,600 4,600
ESD Supressor LITTELFUSE PGB1010603MR SUPPRESSOR, ESD, 0603, 2 0,236 0,472
15KV
LEDs OSRAM LGQ971 LED, GREEN, 10MCD, 570NM, SMD 3 0,129 0,387
Ferrite MURATA BLM15AX601SN1D FERRITE, BEAD, 0402, 0.34OHM, 2 0,018 0,035
0.5A
Table A.5: Bill of materials - other components.
Signal conditioning, ADC and PIC

PIC MICROCHIP PIC24EP512GU810-I/PF MCU, 16BIT, PIC24, 1 14,010 14,010

140MHZ, TQFP-100
IAs ANALOG DEVICES AD8250ARMZ IC, INSTR AMP, 10MHZ, 4 9,680 38,720
84DB, 10MSOP
OP Amps TEXAS INSTRUMENTS OPA2227UE4 OP AMP, DUAL LOW 4 8,620 34,480
NOISE, SMD, 2227
Diodes NXP BAS70-07 DIODE, SCHOTTKY, SOT-143 8 0,022 0,176
ADC TEXAS INSTRUMENTS ADS8361IDBQG4 16BIT ADC, DUAL, 1 18,930 18,930
SMD, 8361, SSOP24
PCB 10x10 From PCB POOL 1 53,95 53,95
44
Table A.6: Bill of materials - total costs.
Description Cost (e)
Capacitors 6,645
Resistors 2,764
Converters 13,380
USB Interface 19,304
Signal conditioning, ADC and PIC 160,266
Total estimated cost 202,359 e
45
46
APPENDIX B
Schematic
In this appendix the schematics of the data acquisition system are displayed. The schematics are
presented in Figure B.9 are components from a single channel since they are similar only changing the
labels in the components for each channel. The figures are displayed from the power supply up to the
input of the channel.
Figure B.1: Schematic of the mini USB type B.
Figure B.2: Schematic of the LEDs.
47
Figure B.3: Schematic of the DC converters.
Figure B.4: Schematic of the FT232H.
48
Figure B.5: Schematic of the FT232H decoupling.
Figure B.6: Schematic of the FT232H EEPROM.
49
Figure B.7: Schematic of the PIC24EP512GU810.
Figure B.8: Schematic of the ADC ADS8361.
50
Figure B.9: Schematic of the signal conditioning for channel 1.
51
52
APPENDIX C
PCB
In this appendix the PCB of the data acquisition system is displayed. In Figures C.1 and C.2, are
the PCB top and bottom layers. The marked areas are: the microcontroller PIC24EP512GU810 (A), the
ADC ADS8361 (B), the USB interface FT232H (C), the converters (D), the channel conditioning of each
channel (E) and finally the EEPROM (F). The complete system can be seen in Figures C.3 and C.4.
Figure C.1: Top layer of the PCB board without components.
Figure C.2: Bottom layer of the PCB board without components.
53
Figure C.3: Top layer of the PCB board with components.
Figure C.4: Bottom layer of the PCB board with components.
54

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Development and Implementation of a Data Acquisition

System for Teaching Purposes

Francisco José Antunes Marques Esteves

Thesis to obtain the Master of Science Degree in

Supervisor: Prof. Pedro Miguel Pinto Ramos

Chairperson: Prof. João Costa Freire

Keywords: Data Acquisition, USB, ADC, PIC

Palavras-chave: Sistema de Aquisição, USB, ADC, PIC

List of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii

2 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1.1 Features of some acquisition systems available on the market. . . . . . . . . . . . . 2

Figure 1.1 Picture of parts of a DAQ System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

ADC Analog to Digital Converter

CMRR Common Mode Rejection Ratio

CPU Central Processing Unit

DAC Digital to Analog Converter

DAQ Data Acquisition

DMA Direct Memory Access

DPSRAM Dual Port Static Random Access Memory

DSP Digital Signal Processor

ENOB Effective Number Of Bits

EEPROM Electrically Erasable Programmable Read-Only Memory

FIFO First In, First Out

FPGA Field Programmable Gate Array

FRC Internal Fast RC

FTDI Future Technology Devices International Ltd.

GPIB General Purpose Interface Bus

ISR Interrupt Service Routine

LSB Least Significant Bit

PCB Printed Circuit Board

PGA Programmable Gain Amplifier

PIC Peripheral Interface Controller

PPS Peripheral Pin Select

PWM Pulse-Width Modulation

SDRAM Synchronous Dynamic Random-Access Memory

SINAD Signal-to-Noise and Distortion Ratio

SPI Serial Peripheral Interface

SRAM Static Random-Access Memory

UART Universal Asynchronous Receiver/Transmitter

USB Universal Serial Bus

VHDL VHSIC Hardware Description Language

1.1 Purpose and Motivation

Figure 1.1: Picture of parts of a DAQ System [1].

Table 1.1: Features of some acquisition systems available on the market.

NI USB-6008 [2] Non Simultaneous 10 kS/s1 12 bit 12 ±1 V up to ±10 V 160 e

NI USB-9215 [3] Simultaneous 100 kS/s/ch 16 bit 4 ±10 V 519 e

DT9816 [4] Simultaneous 50 kS/s/ch 16 bit 6 ±5 V or ±10 V 315 e

DT9816 S [4] Simultaneous 750 kS/s/ch 16 bit 6 ±5 V or ±10 V 460 e

USB-1901 [5] Simultaneous 2502 kS/s 16 bit 16 ±0, 2 V up to ±10 V 455 e

USB-1903 [5] Simultaneous 2502 kS/s 16 bit 16 ±0, 2 V up to ±10 V 565 e

KUSB-3100 [6] Simultaneous 50 kS/s 12 bit 8 ±1, 25 V up to ±10 V 380 e

KUSB-3108 [6] Simultaneous 50 kS/s 16 bit 8 ±0, 02 V up to ±10 V 1110 e

U2300A [7] Simultaneous 3 MS/s3 16 bit 16 ±1, 25 V up to ±10 V 1235 e

1.2 Goals and Challenges

• Selection of a processing unit and communication (PIC or dsPIC);

• Definition and implementation of the control commands from the DAQ;

• Implementation of the complete system in the printed circuit board;

• Development of the PIC firmware and LabVIEW VIs;

• Experimental validation of the designed system;

• Presentation of the results.

1.3 Document Organisation

State of the Art

2.1 Key Components of a DAQ Device