EE 287

ASIC Design CMOS Latches

Latches
Store (Hold) a logic value through feedback Break feedback path to Set the latch Clock is used to control Sampling or Holding
Samples on the active LEVEL Holds on the inactive Level
EE 287 notes Morris Jones

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Latch

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Set and Reset

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Set and Reset

Almost always Inverted
Due to Latch internals

Asynchronous Not timed by clock Limits on how and when used in most ASIC design guides
System reset Timing tool problems with these
EE 287 notes Morris Jones

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Pass Latch Example

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Latch clocking
Active on a level Sample the entire time clock is active Output follows the input 2 inverter delays later When clock changes, latch Holds

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Flip Flops
Appear to sample on a clock edge
Rising or falling

Actually made by placing two latches next to each other

Master is the first one Slave the second one On opposite phases of the clock
EE 287 notes Morris Jones

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Master-Slave Flip Flop

Master

Slave

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While Clock is High

Master Samples input

Slave holds old value from previous clock edge

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When Clock Goes Low

Slave Holds the input. Master passes it to the output

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Master-Slave with NAND Gates

D C Q

Master

Slave

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Setup time
Logic in latch/FF takes more time than clock signal
D input must be earlier than clock for latch to latch in value.
Signal must be stable and not change Clock usually defines time

Multiple paths for signals inside latch

Can trace it out in low level latch design Normally just stated for FF or latch
EE 287 notes Morris Jones

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Input Setup Time

For the Latch to work, the D signal must get all the way around the inverter loop before the clock disables the D input
EE 287 notes Morris Jones

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Input Hold Time

After the clock changes, the input must remain stable for the latch to work Some input paths are faster than the clock inside the latch

EE 287 notes Morris Jones

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Input Hold Time

The amount of time the input must be stable after the clock edge before the mux in the latch changes, and the input will not influence the output
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EE 287 notes Morris Jones

Input Setup and Hold Time

Clock

Input Setup D Input Hold

D value doesnt matter

D Stable
EE 287 notes Morris Jones

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Output Hold Time

Delay from the time the clock changes until the output changes
Min and max times are really required

EE 287 notes Morris Jones

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Output Hold Time (C-Q)

Output doesnt change until the D and Clock can propagate to Q

EE 287 notes Morris Jones

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C to Q time

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Input Setup Time

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Meta-Stable States

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Meta-Stable State
VM is Vin=Vout Two inverters in series (Most Latches)
Stable inflection point

Noise will knock it off the VM sometime

Adds delay to a logic path

Issues crossing clock domains

EE 287 notes Morris Jones

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MUX Based Latch

C 0 0 1 0 1 0 1 1 D The S/D capacitance is too much load in pass latch
C
D

Q=CD*CQold Qold
/C

clk\ C

Din
CLK

/C

EE 287 notes Morris Jones

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Gated Clock
D D
SET

CLR

CK EN

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Gated Clock Example In Cell

C EN

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Clock Timing
Latch Hold time Logic Delay Time

Output Hold Time

Latch Setup Time

EE 287 notes Morris Jones

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