Lec10 Grafcet DAC

Automação Industrial
(AI)
Module 10.
• Grafcet / SFC – part 2

• A2D converter (page 21)
Cristiano Premebida
cpremebida@deec.uc.pt
Edition: 2023-24
Page 1 of 36
Outline
• GRAFCET
• Examples – practical problems
• A2D converter
Page 2
GRAFCET – a bit of history
• 1975 – Decision of the workgroup "Logical Systems" of AFCET (Association

Française de Cybernétique Economique et Technique) on the creation of a
committee to study a standard for the representation of logical systems and
automation.
• 1977 – GRAFCET definition, Graphe Fonctionnel de Commande Etape-Transition. https://www.maxicours.com/se/cours/savoir-lire-un-grafcet/
• 1979 – Dissemination in schools and adopted as research area for the implementation
of solutions of automation in the industry.
• 1988 - GRAFCET becomes an international standard denominated as Sequential

Function Chart (SFC), by I.E.C. 60848.
Paulo J.Oliveira, Jose Gaspar. Slides do curso: Industrial Automation (Automação de Processos Industriais) – GRAFCET. Page
Page 37
3 of
GRAFCET – basic elements Transitions
Steps Connections
Direction of undirected A logical receptivity function can

Actions can be
Arcs is in context. be associated with each Transition.
associated with Steps.
Page 47
4 of
GRAFCET – arcs / connections
Oriented connections (arcs)
In a GRAFCET:
• An Arc can connect Steps to Transitions
• An Arc can connect Transitions to Steps
• Arcs must be in-between: A Step can not have Transitions

directly as inputs (source); A Step can not have Transitions as
direct outputs (drain); Similarly for the Transitions.
Page 57
5 of
GRAFCET - state Initial State
The set of markings of a

GRAFCET constitutes its state.
Page 67
6 of
GRAFCET – state “evolution”
Rule 1: Initial State
• State evolution requires active Steps at the beginning of operation (at least one).
Rule 2: Transposition of a Transition (All active Transitions are transposed immediately.)

• A Transition is active or enabled only if all the Steps at its input are active (if not it is inactive).
• A Transition can only be transposed if it is active and is true the associated condition (receptivity function).
Rule 3: Evolution of active Steps

• The transposition of a Transition leads to the deactivation of all the Steps on its inputs and the activation of all Steps
on its outputs.
Rule 4: Simultaneous transposition of Transitions

• All active Transitions are transposed simultaneously.
Rule 5: Simultaneous activation and deactivation of a Step

• In this case the activation has priority.
Page 77
7 of
OR Convergences:
GRAFCET • If Step 1 active and a TRUE then deactivate Step 1
and activate Step 3 (state of Step 2 remains unchanged).
OR Divergences:
The same happens for Step 2 and b.
• If Step 1 active and a is TRUE
then deactivate Step 1 and activate Step 2. 1
(Schneider)
If both Steps 1 and 2 are active and a and b are TRUE
• If a and b are TRUE and Step 1 active a b
then Steps 1 and 2 are deactivated and Step 3 is activated.
(Schneider) then deactivate Step 1 and
activate Steps 2 & 3 2 3 1 2
a b
AND Divergences (fork):
• If Step 1 active and a TRUE AND Convergences (join):
then deactivate Step 1 and activate Steps 2 and 3. 3
• If Steps 1 and 2 active and a TRUE
then deactivate Steps 1 and 2 and activate Step 3.
1
1 2
a
a
2 3
3
Page 87
8 of
GRAFCET – a simple example
Page 97
9 of
SFC - GRAFCET Sequential Function Charts (SFCs) are a graphical technique for writing concurrent control programs. (They
are also known as Grafcet or IEC 848.) SFCs are a subset of the more complex Petri net techniques.
Example - SFC for control of a two door security system
One door requires a two digit entry code, the second door requires a three digit entry code.
The execution of the system starts at the top of the diagram at the Start block when the
power is turned on. There is an action associated with the Start block that locks the doors.
• Note: in practice the SFC uses ladder logic for inputs and outputs, but this is not shown
on the diagram.
• After the start block the diagram immediately splits the execution into two processes and
both steps 1 and 6 are active.
- Steps are quite similar to states in state diagrams.
- The transitions are similar to transitions in state diagrams, but they are drawn with thick
lines that cross the normal transition path.
- When the right logical conditions are satisfied the transition will stop one step and start the
next.
• While step 1 is active there are two possible transitions that could occur. If the first
combination digit is correct then step 1 will become inactive and step 2 will become
active.
• If the digit is incorrect then the transition will then go on to wait for the later transition for
the 5 second delay, and after that step 5 will be active.
Step 1 does not have an action associated, so nothing should be done while waiting for either
of the transitions.
The logic for both of the doors will repeat once the cycle of combination-unlock-delay-lock
has completed.
H. Jack. “Automating Manufacturing Systems with PLCs” Page

Page 1010
of 7
SFC – another example
SFC for controlling a stamping press.
In the diagram the press starts in an idle state.
When an automatic button is pushed the press will turn on the press
power and lights.
When a part is detected the press ram will advance down to the bottom
limit switch. The press will then retract the ram until the top limit switch
is contacted, and the ram will be stopped. A stop button can stop the
press only when it is advancing.
Note: normal designs require that stops work all the time.
When the press is stopped a reset button must be pushed before the
automatic button can be pushed again.
After step 6 the press will wait until the part is not present before
waiting for the next part.
Without this logic the press would cycle continuously.

Page 1111
of 7
SFC to Ladder
The SFC can be converted “directly” to ladder logic with methods very similar to
those used for state diagrams as shown in the next Figures (next 2 slides).
The method shown is patterned after the block logic method.
One significant difference is that the transitions must now be considered

separately.
The ladder logic begins with a section to initialize the states and transitions to a
single value.
The next section of the ladder logic considers the transitions and then checks for
transition conditions.
If satisfied the following step or transition can be turned on, and the transition
turned off. This is followed by ladder logic to turn on outputs as requires by the
steps. This section of ladder logic corresponds to the actions for each step. After
that the steps are considered, and the logic moves to the following transitions or
steps.
The sequence examine transitions, do actions then do steps is very important.

If other sequences are used outputs may not be actuated, or steps missed entirely.

Page 1212
of 7
SFC

Page 1313
of 7
SFC

Page 1414
of 7
SFC
Many PLCs also allow SFCs to entered be as graphic diagrams.
Small segments of ladder logic must then be entered for each transition
and action.
Each segment of ladder logic is kept in a separate program. If we

consider the previous example the SFC diagram would be numbered.
The numbers are sequential and are for both transitions and steps.

Page 1515
of 7
SFC Sample Ladder Logic for a Graphical SFC Program
Some of the ladder logic for the SFC is shown in Figure.
Each program corresponds to the number on the diagram.
The ladder logic includes a new instruction, EOT, that will tell the PLC
when a transition has completed.
When the rung of ladder logic with the EOT output becomes true the SFC
will move to the next step or transition.
When developing graphical SFCs the ladder logic becomes very simple,
and the PLC deals with turning states on and off properly.

Page 1616
of 7
SFCs can also be implemented using ladder logic that is not based on
Step logic
latches, or built in SFC capabilities. The previous SFC example is
implemented below.
The first segment of ladder logic in Figure (below) is for the transitions.
The logic for the steps is shown in right hand-side Figure.
Ladder logic for transitions

Page 1717
of 7
SFC – practice problem
Develop an SFC for a two person assembly
station.
The station has two presses that may be used

at the same time.
Each press has a cycle button that will start the
advance of the press.
A bottom limit switch will stop the advance,
and the cylinder must then be retracted until a
top limit switch is hit.

Page 1818
of 7
Create an SFC for traffic light control.
The lights should have cross walk buttons for both directions
of traffic lights.
A normal light sequence for both directions will be green 16
seconds and yellow 4 seconds.
If the cross walk button has been pushed, a walk light will be
on for 10 seconds, and the green light will be extended to 24
seconds.

Page 1919
of 7
Draw an SFC for a stamping press that can advance and retract
when a cycle button is pushed,
and then stop until the button is pushed again.

Page 2020
of 7
Part II
analog-2-digital signal conversion

Page 2121
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A-D converters
Steps in analog-to-digital conversion of continuous analog signals from process.
Analog-to-Digital Converters
The procedure for converting an analog signal
from the process into digital form typically
consists of the following steps and hardware
devices, as illustrated in the Figure:
1. Sensor and transducer. This is the measuring device that generates the analog signal.
2. Signal conditioning. The continuous analog signal from the transducer may require conditioning to render it into more suitable
form. Common signal conditioning steps include (1) filtering to remove random noise and (2) conversion from one signal form to
another, for example, converting a current into a voltage.
3. Multiplexer. The multiplexer is a switching device connected in series with each input channel from the process; it is used to time-
share the analog-to-digital converter (ADC) among the input channels. The alternative is to have a separate ADC for each input
channel, which would be costly for a large application with many input channels.
Because the process variables need to only be sampled periodically, using a multiplexer provides a cost-effective alternative to
dedicated ADCs for each channel.
Mikell P. Groover, "Automation, Production Systems, and Computer-integrated Manufacturing", Pearson, 5th ed. (2018). Page
Page 2222
of 7
ADC
4. Amplifier. Amplifiers are used to scale the incoming signal up or down to be compatible with the range of the analog-to-digital converter.
5. Analog-to-digital converter. As its name indicates, the function of the ADC is to convert the incoming analog signal into its digital counterpart.
Consider the operation of the ADC, which is the heart of the conversion process. Analog-to-digital conversion occurs in three steps: sampling,
quantization, and encoding. Sampling consists of converting the continuous signal into a series of discrete analog signals at periodic intervals, as
shown in the Fig. In quantization, each discrete analog signal is assigned to one of the finite numbers of previously defined amplitude levels. The
amplitude levels are discrete values of voltage ranging over the full scale of the ADC. In the encoding step, the discrete amplitude levels obtained
during quantization are converted into digital code, representing the amplitude level as a sequence of binary digits. In selecting an analog-to-
digital converter for a given application, the following factors are relevant: (1) sampling rate, (2) conversion time, (3) resolution, and (4)
conversion method.
Analog signal converted into series of

discrete sampled data by analog-to-
digital converter.
Page 2323
of 7
ADC
The sampling rate is the rate at which the continuous analog signals are sampled or polled. A higher sampling rate means that the continuous
waveform of the analog signal can be more closely approximated. When the incoming signals are multiplexed, the maximum possible sampling
rate for each signal is the maximum sampling rate of the ADC divided by the number of channels that are processed through the multiplexer.
For example, if the maximum sampling rate of the ADC is 1,000 samples/sec, and there are 10 input channels through the multiplexer, then the
maximum sampling rate for each input line is 1,000/10 = 100 sample/sec. (This ignores time losses due to multiplexer switching.)
The maximum possible sampling rate of an ADC is limited by the ADC conversion time. Conversion time of an ADC is the time interval between
the application of an incoming signal and the determination of the digital value by the quantization and encoding steps of the conversion
procedure.
Conversion time depends on the type of conversion procedure used by the ADC and the number of bits n used to define the converted digital
value. As n is increased, conversion time increases (bad news), but resolution of the ADC improves (good news).
The resolution of an ADC is the precision with which the analog signal is evaluated.
Because the signal is represented in binary form, precision is determined by the number of quantization levels, which in turn is determined by the
bit capacity of the ADC and the computer. The number of quantization levels is defined as
𝑁𝑞 = 2𝑛
where 𝑁𝑞 = number of quantization levels and n = number of bits.
Page 2424
of 7
ADC 𝑅𝐴𝐷𝐶 =
𝐿
= 𝑛
𝐿
Resolution can be defined in equation form as 𝑁𝑞 − 1 2 −1
where 𝑅𝐴𝐷𝐶 = resolution of the ADC, also called the quantization-level spacing, which is the length of each quantization level; 𝑳 = full-scale range
of the ADC, usually 0–10 V (the incoming signal must typically be amplified, either up or down, to this range); and 𝑁𝑞 = the number of
quantization levels.
Quantization generates an error because the quantized digital value is likely to be different from the true value of the analog signal.
The maximum possible error occurs when the true value of the analog signal is on the borderline between two adjacent quantization levels; in
this case, the error is one-half the quantization-level spacing.
By this reasoning, the quantization error is defined

1
𝑄𝑢antization error = ± 𝑅𝐴𝐷𝐶
2
Various conversion methods are available by which to encode an analog signal into its digital equivalent. The most commonly used technique, called the successive
approximation method: a series of known trial voltages are successively compared to the input signal whose value is unknown. The number of trial voltages
corresponds to the number of bits used to encode the signal.
The first trial voltage is half the full-scale range of the ADC, and each successive trial voltage is half the preceding value.
Comparing the remainder of the input voltage with each trial voltage yields a bit value of “1” if the input exceeds the trial value and “0” if the input is less than the
trial voltage. The successive bit values, multiplied by their corresponding trial voltage values, provide the encoded value of the input signal.
Page 2525
of 7
Example
Successive Approximation Method
Suppose the input signal is 6.8 V. Use the
successive approximation method to
encode the signal in a 6-bit register for
an ADC with a full-scale range of 10 V.
Page 2626
of 7
Analog to digital conversion: successive approximation
Various conversion methods are available by which to encode an analog signal into its digital equivalent. The most commonly used technique,
called the successive approximation method:
1. a series of known trial voltages are successively compared to the input signal.
2. The number of trial voltages corresponds to the number of bits used to encode the signal.
3. The first trial voltage is half the full-scale range of the ADC, and each successive trial voltage is half the preceding value.
4. Comparing the remainder (ie, the difference) of the input voltage with each trial voltage yields a bit value of “1” if the input exceeds the trial
value
5. Otherwise, the bit value will be “0” if the input is less than the trial voltage.
6. The successive bit values, multiplied by their corresponding trial voltage values, provide the encoded value of the input signal.
Example: Suppose the input signal is 6.8 V. Use the successive

approximation method to encode the signal in a 6-bit register trial voltage values:
for an ADC with a full-scale range of 10 V. 5.00
2.50
1.25
0.625
… And so on
Page 2727
of 7
Example
Difference between the input voltage and the
trial value:
1. (6.8 - 5.0) = 1.8 ie, >0 →1

2. (1.8 - 2.5) <= 0 →0
3. (1.8 - 1.25) = 0.55 ie, > 0 →1
4. (0.55 - 0.625) <= 0 →0
5. (0.55 - 0.3125) = 0.2375 ie, > 0 →1
6. (0.2375 - 0.15625) ie, > 0 →1
Page 2828
of 7
Analog I/O Modules
Discrete devices are inputs and outputs that have only two states: on and off.
In comparison, analog devices represent physical quantities that can have an infinite number of values. Typical analog inputs and
outputs vary from 0 to 20 mA, 4 to 20 mA, or 0 to 10 V.
The analog input interface module (installed on a PLC) contains the circuitry necessary to accept an analog voltage or current
signal from the level transmitter field device. This input is converted from an analog to a digital value for use by the processor.
Analog input modules normally have multiple input channels that allow 4, 8, or 16 devices to be interface to the PLC.
The two basic types of analog input modules are voltage sensing and current sensing.
Input modules have user-selectable dip switch settings to choose whether each input will be a current or voltage input. Analog
sensors measure a varying physical quantity over a specific range and generate a corresponding voltage or current signal.
Common physical quantities measured by a PLC analog module: temperature, speed, level, flow, weight, pressure, and position.
F. Petruzella . “Programmable Logic Controllers”, 5th Edition, 2017. Page

Page 2929
of 7
Analog I/O Modules
The transition of an analog signal to digital values is accomplished by an analog-to-digital (A/D) converter, the main element of
the analog input module. Analog voltage input modules are available in two types: unipolar and bipolar.
Unipolar modules can accept an input signal that varies in the positive direction only. For example, if the field device outputs 0 to
+10 V, then the unipolar modules would be used.
Bipolar signals swing between a maximum negative value and a maximum positive value. For example, if the field device outputs
−10 to +10 V a bipolar module would be used.
The resolution of an analog input channel refers to the

smallest change in input signal value that can be
sensed and is based on the number of bits used in the
digital representation. Analog input modules must
produce a range of digital values between a maximum
and minimum value to represent the analog signal
over its entire span. Typical specifications:
F. Petruzella . “Programmable Logic Controllers”, 5th Edition, 2017. Page

Page 3030
of 7
Analog I/O Modules
An analog signal is a signal with an amplitude that varies continuously with time (time‐continuous) and within a given amplitude
range. In other words: an analog signal is defined for every instant of time within a given interval.
“A signal can be continuous in time but not in amplitude and is therefore, strictly speaking, not an analog signal, but we usually
call it an analog signal anyway.”
A/D Conversion
Analog‐to‐digital converters are, as indicated, the unit that is used in order to digitize analog signals. In order to avoid using an
A/D converter for each individual analog input signal, normally there is a multiplexer that routes one signal at a time into the A/D
converter. Typically, there will also be an interface that contains a so‐called “sample and hold” circuit.
Principle for A/D conversion
Dag H. Hanssen. “Programmable Logic Controllers: A Practical Approach to IEC 61131-3 using CoDeSys”, 1st Ed., Wiley, 2015. Page
Page 3131
of 7
Analog I/O Modules
A/D conversion can also include several other steps such as:
1. Sampling at fixed time intervals (sampling period T).

2. Use of a “sample and hold” circuit for quantifying and coding.
3. Quantifying. Here, each sample value is rounded off to the “nearest level possible.”
4. Coding. Here, each quantified value is converted to a binary code. When the samples are quantified and coded, the signal is
usually referred to as a digital signal.
Illustration of sampling
Sampling
When an analog signal is sampled, this takes place at a certain speed
called the sampling frequency. The concept of sampling period is often
used or just plain sampling time. This is the time interval between each
sample, T. Other notations that are common are Δt or Ts. The relationship
between sampling frequency and sampling period is given by f = 1/T. If, for
instance, we have a sampling period of T = 0.1 seconds, the sampling
frequency 1/T = 10 Hz, in other words, 10 sampling points every second.
Sampling thus occurs at fixed intervals of time between samples as shown
in the Figure.
Page 3232
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Analog I/O Modules Original analog signal and the discrete signal y(k)
The discrete signal can be written as a sequence (arithmetic series) of all

values (the numbers).
Let us call this series y(k), where the argument k indicates the sample
number or, expressed another way, where in the sequence the value occurs.
Sample and Hold

This “functional circuit” is used to maintain the amplitude constant until the
next sample arrives.
This is done to permit the A/D converter to process the complete sample, that
is, to both quantify and code. An illustration of the operation of a “sample and
hold” function is shown in the Figure below:
Page 3333
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Analog I/O Modules
Quantification
All digital systems (PCs, microcontrollers, PLCs, etc.) use a certain number of bits to represent and store a value. This means that the discrete
sampled values are rounded off to the nearest possible level. How big this roundoff is depends on the number of bits used in the quantification.
More bits give better resolution.
Example
Consider a 3‐bit quantifier. This means that the digital system has
three bits available for a binary representation of each value.
With three bits, we have 2^3 = 8 possible levels. This gives 8 − 1 =
7 different intervals within which the individual sample can lie.
Let us assume that a signal that varies in the range 0–10 V is to

be digitized. The binary code:
• 000 will then represent 0 V

• 111 will represent 10 V
Page 3434
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Example: quantification
After sampling, we will have (approximately) the following series of values:
y(k) = 1.8, 3.9, 5.3, 6.6, 7.3, 9.1, 5.8, …
These values must now be coded so that each value receives the binary code that is closest to the
original value. Refer again to the figure and find that the series will have the following digital codes:
y(k) = 001, 011, 100, 100, 101, 110, 100, …
We see that even though the discrete samples can be quite different in value, they may have the same digital code. In this example, the value 5.3
and of the value 6.6 will both be represented by the binary number 100.
This is what we call quantification error. It is easy to calculate what the maximum distortion introduced by this error will be. This number will
then describe how good a resolution we have in our sampling process.
Since the analog signal range is 0–10 V, the difference (in volts) between each quantification level will be equal to 10 / 7 = 1.43V.
We get the maximum error when the sample lies between two levels, so the maximum error here is equal to 0.71 V.
10 − 0 10
𝐸𝑟𝑟𝑜𝑟 = = = 0.71428 𝑉
2(23 − 1) 14
Page 3535
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Example – quantification error
A general formula for quantification error can be written as
𝑦𝑚𝑎𝑥 − 𝑦𝑚𝑖𝑛
𝐸𝑟𝑟𝑜𝑟 =
2(2𝑛 − 1)
where 𝑦𝑚𝑎𝑥 and 𝑦𝑚𝑎𝑥 represent the limits for the analog (electrical) signal range and n is the number of bits used in the
quantification.
Example:
An analog signal has an electrical value range from 4 to 20 mA. The signal is
sampled and quantified with an 8‐bit A/D converter. As a result of around
half, the greatest error we can get will then be
𝑦𝑚𝑎𝑥 − 𝑦𝑚𝑖𝑛 20 − 4
𝐸𝑟𝑟𝑜𝑟 = = = 0.0314 𝑚𝐴
2(2𝑛 − 1) 2(256 − 1)
Page 3636
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Automação Industrial

• Grafcet / SFC – part 2

• Examples – practical problems

• 1975 – Decision of the workgroup "Logical Systems" of AFCET (Association

• 1977 – GRAFCET definition, Graphe Fonctionnel de Commande Etape-Transition. https://www.maxicours.com/se/cours/savoir-lire-un-grafcet/

• 1988 - GRAFCET becomes an international standard denominated as Sequential

Direction of undirected A logical receptivity function can

Oriented connections (arcs)

• An Arc can connect Steps to Transitions

• An Arc can connect Transitions to Steps

• Arcs must be in-between: A Step can not have Transitions

The set of markings of a

Rule 2: Transposition of a Transition (All active Transitions are transposed immediately.)

Rule 3: Evolution of active Steps

Rule 4: Simultaneous transposition of Transitions

Rule 5: Simultaneous activation and deactivation of a Step

H. Jack. “Automating Manufacturing Systems with PLCs” Page

In the diagram the press starts in an idle state.

Without this logic the press would cycle continuously.

H. Jack. “Automating Manufacturing Systems with PLCs” Page

The method shown is patterned after the block logic method.

One significant difference is that the transitions must now be considered

The sequence examine transitions, do actions then do steps is very important.

H. Jack. “Automating Manufacturing Systems with PLCs” Page

H. Jack. “Automating Manufacturing Systems with PLCs” Page

H. Jack. “Automating Manufacturing Systems with PLCs” Page

Each segment of ladder logic is kept in a separate program. If we

H. Jack. “Automating Manufacturing Systems with PLCs” Page

Some of the ladder logic for the SFC is shown in Figure.

Each program corresponds to the number on the diagram.

H. Jack. “Automating Manufacturing Systems with PLCs” Page

Ladder logic for transitions

H. Jack. “Automating Manufacturing Systems with PLCs” Page

The station has two presses that may be used

H. Jack. “Automating Manufacturing Systems with PLCs” Page

H. Jack. “Automating Manufacturing Systems with PLCs” Page

H. Jack. “Automating Manufacturing Systems with PLCs” Page

H. Jack. “Automating Manufacturing Systems with PLCs” Page

Analog signal converted into series of

By this reasoning, the quantization error is defined

Example: Suppose the input signal is 6.8 V. Use the successive

1. (6.8 - 5.0) = 1.8 ie, >0 →1

F. Petruzella . “Programmable Logic Controllers”, 5th Edition, 2017. Page

The resolution of an analog input channel refers to the

F. Petruzella . “Programmable Logic Controllers”, 5th Edition, 2017. Page

Principle for A/D conversion

1. Sampling at fixed time intervals (sampling period T).

The discrete signal can be written as a sequence (arithmetic series) of all

Sample and Hold

Let us assume that a signal that varies in the range 0–10 V is to

• 000 will then represent 0 V

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