Module1 - ARM Microcontroller MIT Portrait

ARM MICROCONTROLLER& EMBEDDED SYSTEMS | MODULE 1: ARM
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32-BIT MICROCONTROLLER
Module-1
ARM-32 bit Microcontroller
About ARM
➢ Based on Client requirements ARM (ADVANCED RISC MACHINE) will lend its
architecture of Core + debug systems; the bus interface interfaces and peripherals are
designed by ARM in collaboration with semiconductor chip manufacturers.
➢ The physical chip manufacturing and marketing is done by the Semiconductor manufacturers
who have licensed IP from ARM and can fbricate the Cortex-M3 processor in their silicon
designs, adding memory, peripherals, input/output (I/O), and other features.
➢ Cortex-M3 processor-based chips from different manufacturers will have different memory
sizes, types, peripherals, and features.
➢ Unlike many semiconductor companies, ARM does not manufacture processors or sell
the chips directly.
➢ Instead, ARM licenses the processor designs to business partners, including a majority
of the world’s leading semiconductor companies.
➢ Based on the ARM’s low-cost and power-efficient processor designs, these partners
create their processors, microcontrollers, and system-on-chip solutions. This business model
is commonly called Intellectual Property (IP) licensing.
➢ In addition to processor designs, ARM also licenses systems-level IP and various software
IPs.
➢ To support these products, ARM has developed a strong base of development tools,
hardware, and Software products to enable partners to develop their own products.
➢ The ARM Cortex™-M3 processor, the first of the Cortex generation of processors
released by ARM in 2006, was primarily designed to target the 32-bit microcontroller
market is the successor of earlier ARM7 variants.
➢ NXP (Philips), Texas Instruments, Atmel, OKI, and many other vendors delivering
MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 1

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robust 32-bit Microcontroller Units (MCUs) are the clients of ARM.

Important features of ARM architecture/ processors & controllers which use
ARM architecture
➢ Greater performance efficiency: Allowing more work to be done without increasing the
frequency or power requirements.
➢ Low power consumption: Enabling longer battery life, especially critical in portable
products including wireless networking applications.
➢ Enhanced determinism: Guaranteeing that critical tasks and interrupts are serviced as
quickly as possible and in a known number of cycles.
➢ Improved code density: Ensuring that code fits in even the smallest memory footprints.
➢ Ease of use: Providing easier programmability and debugging for the growing number of
8-bit and 16-bit users migrating to 32 bits.
➢ Lower cost solutions: Reducing 32-bit-based system costs close to those of legacy 8-bit
and 16-bit devices and enabling low-end, 32-bit microcontrollers to be priced at less than
US$1 for the first time.
➢ Wide choice of development tools: From low-cost or free compilers to full-featured
development suites from many development tool vendors.
History of ARM
➢ ARM was formed in 1990 as Advanced RISC Machines Ltd., a joint venture of Apple
Computer, Acorn Computer Group, and VLSI Technology.
➢ In 1991, ARM introduced the ARM6 processor family, and VLSI became the initial
licensee.
➢ Later on Texas Instruments, NEC, Sharp, and ST Microelectronics, licensed the
ARM processor designs, using ARM processors into mobile phones, computer hard
disks, personal digital assistants (PDAs), home entertainment systems, and many other
consumer products.
Architecture Versions
➢ Earlier different naming was done to different processor architectures. There were
different versions, family and numbering and suffixes. Ex: ARM_family_numbered
suffix_other suffix;
➢ But from 5th version onwards TDMI features (Thumb, JTAG, Fast Multipliers, ICE
module) were decided as basic requirements of ARM architecture and any additional
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features apart from these will mentioned through suffixes.

➢ From 7th version onwards a Cortex and profile have been designated.
Suffixes ARM processors Suffixes ARM processors Different processor names
with with
“26” or Cache and MMUs S Synthesizable ARM920T
“36,” (Memory (HDLcode- netlist)
Management Unit) J Jazelle technology ARM926EJ-S
“46” MPUs (Memory E Enhanced DSP Cortex-M0, Cortex-M1,Cortex-
Protection Unit) T Thumb instruction M2
support (cortex is used from version 6/7 as
std + profile.)
Profiles: A, R, M.
Understanding Profiles and its applications

➢ Cortex M3 belongs to Version 7 and a Microcontroller architecture.
The A profile (Application processors)

➢ Designed for high-performance open Application platforms supporting OS like Symbian,
Windows, Linux.
➢ Processors requiring highest processing power, virtual memory system, MMUs, and,
optionally, enhanced Java support and secure program execution environment.
➢ Example: High-end mobile phones, electronic wallets for financial transactions.
The R profile (Real-time Processors)

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➢ Real-time, high-performance low latency processors targeted primarily at the higher end real-
time market
➢ Examples: high-end breaking system, Hard drive controllers, in which high processing
power, where high reliability are essential.
The M profile( Microcontroller)
➢ Processors for low-cost applications looking for processing efficiency, low cost, low
power consumption, low interrupt latency, and ease of use.
➢ Example: Industrial control applications, Real-time control systems.
Evolution of ARM architecture summarized below
Instruction Set Development (About Thumb-2)

ARM Instruction SET
1. It consists of 32 bit instructions.
2. Consists of all instructions to accomplish many/various types of processor
operations efficiently.
3. Used for complex calculations, multiple conditional branching, Intr. Handlers.
4. Occupies more code memory as instructions are longer. So low code density.
Thumb Instruction SET
1. It consists of 16 bit instructions.
2. Consists of only a subset of ARM instructions.
3. So It can’t accomplish all types of operations. But to do so, several
instructions may have to be written.
4. Occupies lesser space in code memory and has higher code density.
Thumb-2 Instruction SET

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1. It is Superset of both 32 bit ARM & 16-bit Thumb instruction set used in M3
and higher versions.
2. The switching b/w ARM & Thumb state isn’t required compared to earlier versions. Hence
overhead delay can be avoided.
3. Delivers significant benefits in terms of ease of use, code size, and performance.
➢ Problem of Processor switching b/w ARM & Thumb mode in Lower versions like ARM7
produces over head delay is shown below.
In Thumb-2 this problem doesn’t exist at all as there is only one Superset Thumb-2 (IS).
Few power full instructions of Thumb-2 are:
➢ UFBX, BFI, and BFC: Bit field extract, insert, and clear instructions
➢ UDIV and SDIV: Unsigned and signed divide instructions
➢ WFE, WFI, and SEV: Wait-For-Event, Wait-For-Interrupts, and Send-Event; these allow the
processor to enter sleep mode and to handle task synchronization on multiprocessor systems.
➢ MSR and MRS: Move to special register from general-purpose register and move special
register to general-purpose register; for access to the special registers.
➢ Cortex-M3 processor is not backward compatible with traditional ARM7 because M3 uses
Thumb-2 (IS) and some instructions of ARM7 may not be supported by M3 which uses
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thumb-2 IS only.
Advantages of Cortex-3 using Thumb-2

1. No state switching overhead, saving both execution time and instruction space.
2. No need to separate ARM code and Thumb code source files, making software
development, maintenance easier, good for small memory system devices like
microcontrollers and reduces the size of the processor.
3. Its easier to get the best efficiency and performance, in turn making it easier to write
software, because there is no need to worry about switching code b/w ARM and Thumb
to try to get the best density/performance.
Applications of Cortex M3 (Applications)
1. Low-cost microcontrollers: The Cortex-M3 controller is lower power, high
performance, and has ease-of-use features helping embedded developers to migrate to 32-
bit systems rather than 8/16 bit microcontrollers in consumer products from toys to
electrical appliances.
2. Automotive Industry: The Cortex-M3 processor has 240 external vectored interrupts,
with a built-in interrupt controller with nested interrupt supports, very high-performance
efficiency and low interrupt latency. So it can be used as real-time systems, with highly
integrated and cost-sensitive automotive applications in the automotive industry.
3. Data communications: The processor’s low power and high efficiency, coupled with
instructions in Thumb-2 for bit-field manipulation, make the Cortex-M3 ideal for
Bluetooth and ZigBee.
4. Industrial control: In industrial control applications where simplicity, fast response,
and reliability are key factors, Cortex-M3 processor’s interrupt feature, low interrupt
latency, and enhanced fault-handling features make it a strong candidate in this area.
5. Consumer products: In many consumer products, a high-performance
microprocessor (or several of them) are replaced with the Cortex-M3 processor, as it is-
highly efficient and low power consuming small sized processor with MPU enabling
complex software to execute under memory protection.

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Modes and Levels of operation of ARM Cortex-M3

Modes Levels Privilege Thread
Thread or Program (default after Reset)
Thread Mode Privilege User/base Thread
Exception Handler Always in Privilege

Handler Mode User/base
(ISR/EH programs) mode
(Exception Handler)
User level/Base Level Privilege Level

1. Thread Thread and Exception Handler
2. User access level (thread mode) Software in a privileged access level can access
Can’t access the system control space the system control space (SCS)— part of the
(SCS)— part of the memory region for memory region for configuration registers and
configuration registers and debugging debugging components.
components.
3. Instructions that access special registers MSR is allowed.
(such as MSR, except when accessing APSR)
cannot be used.
4. Can’t change from user to Privilege level Switch the program into the user access level
directly. It has to create an exception or rise and change SP using changing CR[ ] (Only Pr.Th
interrupt and switch to Handler mode and can write into CR)
then Change to Pr. Thread Level as there is Default a thread will run in Pr level when
no access to CR. Turned On.
5. CR[0]= 1 CR[0]= 0.
User level/Base Level

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Privilege Level
➢ When we compare the two opertions, it can be see that after completion of handler the
processor returns to level if there is no change in CR
User level/Base Level
➢ The MPU blocks the user programs from corrupting memory reserved for Privileged threads
along with CR of NVIC during user program crashes.

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➢ Simple applications can be run in Privilaged level for quick execution.
➢ When the processor is running a main program (thread mode), it can be either in a privileged
state or a user state.
➢ But the exception handlers should be always in a privileged state.
➢ When the processor exits reset, it is in thread mode, with privileged access rights. In the
privileged state, a program has access to all memory ranges (except when prohibited by MPU
settings) and can use all supported instructions.
➢ Software in the privileged access level can switch the program into the user access level using
the control register.
➢ When an exception takes place, the processor will always switch back to the privileged state
and return to the previous state when exiting the exception handler.
➢ A user program cannot change back to the privileged state by writing to the control register.
➢ It has to go through an exception handler that programs the control register to switch the
processor back into the privileged access level when returning to thread mode.

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➢ The separation of privilege and user levels improves system reliability by preventing
system configuration registers from being accessed or changed by some untrusted
programs.
➢ If an MPU is available, it can be used in conjunction with privilege levels to protect
critical memory locations, such as programs and data for OSs.
➢ The privileged accesses, usually used by the OS kernel, all memory locations can be
accessed (unless prohibited by MPU setup).
➢ When the OS launches a user application, it is likely to be executed in the user access
level to protect the system from failing due to a crash of untrusted user programs.
ARM Cortex-M3 Architecture in detail (Architecture & Various units of

Architecture)
➢ ARM Cortex architecture consists of the following

(a) Register Banks
(b) Built -In Nested Vectored Interrupt Controller
(c) Memory Protection Unit (MPU)
(d) Bus interface Unit BIU
(e) Debugging Interface/Support

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➢ Register Banks: it can be classified into 1. General Purpose Registers 2. Special

Registers
General Purpose Registers: (R0-R12)

➢ R0-R07 (Lower registers)
➢ Accessible by 16-bit T inst. And 32-bit T-2 inst.
➢ R8-R12 (Higher registers)
➢ Accessible by 32-bit T-2 inst only.
➢ R0-R12 (General Purpose Registers)
➢ Accessible by 32-bit T-2 inst.
➢ R13 (2 register banks: MSP (Main Stack Pointer) PSP (Process Stack Pointer))
➢ if CR[1]= 0
➢ MSP will be used as SP by privileged threads, OS kernel and Handlers.
➢ if CR[1]= 1
➢ PSP will be used as SP for Base level/user Thread.
➢ PSP Can’t be used by Handlers.
➢ R14 LINK REGISTER
➢ Used to store the return program counter (PC) when a subroutine or function is
called.
➢ useful in instructions like -
➢ BL: branch and link.
➢ BX: Branch and return
➢ Example program model
main ; Main program
...
BL function1 ; PC = function1 ; LR = the next instruction in main after BL
...
...
...
...
...
function1
Program code for function 1
...
...
...
...

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BX LR ; Return. PC=LR
➢ R15 PROGRAM COUNTER
➢ Points next inst. to executed.
➢ Example if PC= 0x1000 ,
➢ MOV R0, PC ; PUSH R0;
➢ Special Purpose Registers: PSR, IMR, CR
1. xPSR (Program Status Register- APSR, IPSR and EPSR)
➢ It is a 32-BIT REGISTER
➢ The following instructions can be used to read PSR registers.
➢ MRS r0, APSR ; Read Flag state into R0
➢ MRS r0, IPSR ; Read Exception/Interrupt state
➢ MRS r0, EPSR ; Read Execution state
➢ APSR Application Program Status Register

➢ Can READ the PSRs using the MRS inst.
➢ Can WRITE ONLY APSR using the MSR inst.
➢ Example-
MSR APSR, r0 ; Write Flag state
MSR EPSR, r0; ERROR
➢ IPSR (Interrupt Program Status register ) Read-Only

➢ EPSR (Execution Program Status register) Read-Only
➢ Example-
MRS r0, PSR ; Read the combined program status word

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MSR PSR, r0 ; ERROR

2. IMR (Interrupt Mask Register) has 3 indicators- PRIMASK, FAULTMASK,
BASEPRAI
➢ PRIMASK (PRIORITY MASK)
➢ Default will be ‘0’ FOR No Masking.
➢ If set to ‘1’ Disables all interrupts and fault exception handlers. But not NMI and
Hard Fault.
➢ BASEPRI (BASE PRIORITY )
➢ Can vary up to 8-BITS. if set to ‘1’, interrupt of same level and lower get disabled.
➢ Example to demonstrate set/reset of these IMR indicators.
x = __ get_BASEPRI( ); MRS r0, BASEPRI ;
x = __ get_PRIMARK( ); MRS r0, PRIMASK;
x= __ get_FAULTMASK(); MRS r0, FAULTMASK;
__ set_BASEPRI(x); MSR BASEPRI, r0;

__ set_PRIMASK(x); MSR PRIMASK, r0;
__ set_FAULTMASK(x); MSR FAULTMASK, r0;
__ disable_irq(); // Clear PRIMASK, enable IRQ

__ enable_irq(); // Set PRIMASK, disable IRQ
➢ Lower the Priority val greater its Priority. Reset= -3, NMI= -2 Hard Fault= -1
3. CONTROL REGISTER
➢ It is 32-bit register out which only last 2-bits are programmable.
➢ CR[1] is used to decide which of the Stack Pointer out of PSP and MSP are to be
used.
➢ CR[0] is used to decide the level a thread has to run-Base/user Level or Privilege
level.
➢ The result of setting/resetting of the CR[1], CR[0] bits are shown below.
CR[1] CR[1]=0 CR[1]=1
Stack pointer selector MSP will be selected PSP will be selected
CR[0] CR[0]=0 CR[0]=1
Thread level selector Thread in Privilege Thread in User Level
Level

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➢ Role of stack pointer and the 2 Levels are shown below

MSP Works for Thread & Handler mode and access common stack region.
Chances of corruption due to mismatch.
PSP Works only thread mode. Thread uses PSP while Handler uses MSP
➢ A code/thread can be run on

1. User level or 2. Privilege level by resetting /setting CR[0].
➢ But when an exception occurs processor switches to Handler mode.
➢ Summary of Special Purpose Registers
Built -In Nested Vectored Interrupt Controller

➢ Cortex-M3 processor includes an interrupt controller called the Nested
Vectored Interrupt Controller (NVIC) closely coupled to the processor
core.
➢ The following features have been implemented in NVIC:

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1. Nested interrupt support

2. Vectored interrupt support
3. Dynamic priority changes support
4. Reduction of interrupt latency
5. Interrupt masking
➢ Nested interrupt support

➢ All the external interrupts and most of the system exceptions can be programmed to
different priority levels;
➢ NVIC compares the present Intr. With other Intr. Occurring and handler of highest
priority will be executed/serviced.
➢ Vectored interrupt support
➢ When an interrupt is accepted, the starting address of the interrupt service routine
(ISR) is located from a vector table in memory and fetches the ISR. reduces time to
process the interrupt requests.
➢ Dynamic priority changes support
➢ Priority levels of interrupts can be changed by software during run time by BASEPRI.
➢ Reduction of interrupt latency
➢ To lower the interrupt latency automatic saving and restoring some register contents,
reducing delay in switching from one ISR to another, and handling of late arrival
interrupts.
➢ Interrupt masking
➢ Interrupts and system exceptions can be masked based on their priority level or
masked completely using BASEPRI, PRIMASK, and FAULTMASK to finish time-
critical tasks without being too many interrupts.
Memory MAP of Cortex M3, Memory Protection Unit (MPU)
➢ For efficient utilization of memory 4GB is segmented to different blocks as shown and can be
used differently.
➢ Data memory can still be put into the CODE region.
➢ External RAM can be used as code/program memory.
➢ System level block has interrupt controller and debug elements.
➢ Peripheral devices have fixed addresses and help porting of applications among different ARM
Cortex-M3.
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➢ Internal bus infrastructure is optimized for this memory usage.

➢ The Cortex-M3 memory mapping is as shown.
Memory Protection Unit (MPU)

➢ MPU role is to define access rules for Privilege & User access levels.
➢ This can be done in 2 ways:
a) Preventing untrusted user threads from accessing data used by Kernel & privilege
Level process.
b) Making certain memory regions as Read-Only and preventing data loss during
multitasking operations.
➢ Whenever the access rules are violated, a fault exception occurs, calling for analysis and
correction of the fault.
Bus interface Unit BIU
➢ There are several bus interfaces on the Cortex-M3 processor.
➢ The main bus interfaces are as follows:
a) Code memory buses accesses code memory region, consists of (I-Code & D-
Code) for instruction Fetches and data accesses at the same time.
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b) System bus accesses memory and peripherals including Static Random Access
Memory (SRAM), external RAM, external devices, and part of the system level
memory regions.
➢ Private peripheral bus accesses a part of the system-level memory dedicated to private
peripherals, such as debugging components.
Debugging Support
➢ Cortex-M3 provides the following debugging features (a)Program execution controls
(halting and stepping) (b) Instruction breakpoints (c) Data watch points (d) Registers and
Memory accesses (e) Profiling (f) Traces.
➢ Various events like breakpoints, watchpoints, fault conditions, or external debugging
request input signals can make the Cortex-M3 enter halt mode or execute the debug
monitor exception handler.
➢ Data Watch point and Trace (DWT) unit provides data watchpoint function to stop the
processor and generate trace information that can be output via the TPIU.
➢ Flash Patch & Breakpoint (FPB) unit provides a simple breakpoint function or remaps
an instruction access from Flash to a different location in SRAM.
➢ conceptual diagram of Debug support is shown below.
➢ In ARM cortex M3 the Debug system is kept outside (decoupled) the core. Bus
interface called the Debug Access Port (DAP) is provided at the core level which is
controlled by Debug Port (DP) device.
➢ The Debug ports are:
1. Serial-Wire JTAG Debug Port (SWJ-DP) and which supports the traditional
JTAG protocol as well as the Serial-Wire protocol.
2. Serial-Wire Debug Port (SW-DP) which supports only the Serial-Wire
protocol.
➢ The Trace signal is received by Trace Port Interface Unit (TPIU) then transferred to
PC or display device.
Another approach is:
➢ An Instrumentation Trace Macrocell (ITM) provides a new way for developers to
output data to a debugger.
➢ By writing data to register memory in the ITM, a debugger can collect the data via a
trace interface and display or process them.

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➢ This method is easy to use and faster than JTAG output.

Exceptions, Interrupts and Vector Table of Cortex-M3
➢ Cortex-M3 has interrupt priority handling and nested interrupt support in the interrupt
architecture.
➢ Therefore, it is easy to set up a system that supports nested interrupts where a higher-
priority interrupt can override or preempt a lower-priority interrupt handler.
➢ Cortex-M3 supports external vectored interrupts, and a number of internal exception
sources, such as system fault handling.
➢ Low Power and High Energy Efficiency feature is implemented in CORTEX-M3.
➢ The Cortex-M3 processor is designed with various features to allow designers to develop
low power and high energy efficient products.
➢ First, it has sleep mode and deep sleep mode supports, which can work with various
system-design methodologies to reduce power consumption during idle period.
➢ Second, its low gate count and design techniques reduce circuit activities in the processor
to allowactive power to be reduced. In addition, since Cortex-M3 has high code density, it
has lowered the program size requirement.
➢ At the same time, it allows processing tasks to be completed in a short time, so that the
processor can return to sleep modes as soon as possible to cut down energy use. As a
result, the energy efficiency of Cortex-M3 is better than many 8-bit or 16-bit
microcontrollers.
➢ Third, Cortex-M3 revision 2 onwards, a new feature called Wakeup Interrupt Controller
(WIC) is available, which allows the whole processor core to be powered down, while
processor states are retained and the processor can be returned to active state almost
immediately when an interrupt takes place.
➢ This makes the Cortex-M3 even more suitable for many ultra-low power applications that
previously could only be implemented with 8-bit or 16-bit microcontrollers.
➢ The Cortex-M3 has a number of predefined exception types, as shown in next page.

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Exceptions, Interrupts and Vector tables

➢ The exceptions and interrupts of Cortex-M3 are tabulated below:
➢ Vector table address after reset is given below
➢ To determine the starting address of the exception handler, a vector table, an array of word
data inside the system memory, each representing the starting address of one exception
type.
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➢ The vector table is relocatable, and the relocation is controlled by a relocation register in
the NVIC.
➢ The address is (type number X 04) = result in Hex. One can check the vector of different
exceptions given above.
Reset sequence of Stack Pointer and Program Counter

➢ It can be observed that the following changes occur after the Cortex M-3 Controller is
Reset .
➢ Address 0x00000000: Starting value of R13 (the SP)
➢ Address 0x00000004: Reset vector (the starting address of program execution)
➢ Whenever Reset is pressed/occurs : SP reads contents at the address 0x00000000: has

number equal to (4 +top most stack address)
➢ This means if a PUSH occurs after reset, the data starts from 20007C00H. Because
PUSH decrements SP by 4 and then stores the data.
➢ The PC reads Reset handler address (00000101) at 00000004H address of Reset Vector.
From this (00000101) location execution of Reset Handler takes place.

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➢ LSB is shown as ‘1’ for vector handler location as it is written in thumb code.

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ARM MICROCONTROLLER& EMBEDDED SYSTEMS | MODULE 1: ARM

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 1

robust 32-bit Microcontroller Units (MCUs) are the clients of ARM.

2 DEPT. OF ELECTRONICS & COMMUNICATION ENGG. | MIT MYSORE

features apart from these will mentioned through suffixes.

Understanding Profiles and its applications

The A profile (Application processors)

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 3

Instruction Set Development (About Thumb-2)

4 DEPT. OF ELECTRONICS & COMMUNICATION ENGG. | MIT MYSORE

Advantages of Cortex-3 using Thumb-2

6 DEPT. OF ELECTRONICS & COMMUNICATION ENGG. | MIT MYSORE

Modes and Levels of operation of ARM Cortex-M3

Exception Handler Always in Privilege

User level/Base Level Privilege Level

User level/Base Level

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 7

User level/Base Level

8 DEPT. OF ELECTRONICS & COMMUNICATION ENGG. | MIT MYSORE

➢ Simple applications can be run in Privilaged level for quick execution.

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 9

ARM Cortex-M3 Architecture in detail (Architecture & Various units of

➢ ARM Cortex architecture consists of the following

10 DEPT. OF ELECTRONICS & COMMUNICATION ENGG. | MIT MYSORE

➢ Register Banks: it can be classified into 1. General Purpose Registers 2. Special

General Purpose Registers: (R0-R12)

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 11

➢ APSR Application Program Status Register

➢ IPSR (Interrupt Program Status register ) Read-Only

12 DEPT. OF ELECTRONICS & COMMUNICATION ENGG. | MIT MYSORE

MSR PSR, r0 ; ERROR

__ set_BASEPRI(x); MSR BASEPRI, r0;

__ disable_irq(); // Clear PRIMASK, enable IRQ

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 13

➢ Role of stack pointer and the 2 Levels are shown below

➢ A code/thread can be run on

➢ Summary of Special Purpose Registers

Built -In Nested Vectored Interrupt Controller

14 DEPT. OF ELECTRONICS & COMMUNICATION ENGG. | MIT MYSORE

1. Nested interrupt support

➢ Nested interrupt support

➢ Internal bus infrastructure is optimized for this memory usage.

Memory Protection Unit (MPU)

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 17

➢ This method is easy to use and faster than JTAG output.

18 DEPT. OF ELECTRONICS & COMMUNICATION ENGG. | MIT MYSORE

Exceptions, Interrupts and Vector tables

➢ Vector table address after reset is given below

Reset sequence of Stack Pointer and Program Counter

➢ Whenever Reset is pressed/occurs : SP reads contents at the address 0x00000000: has

20 DEPT. OF ELECTRONICS & COMMUNICATION ENGG. | MIT MYSORE

MIT MYSORE | DEPT. OF ELECTRONICS & COMMUNICATION ENGG. 21

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