04 Sav 460 692.9011.51 J

Converter Gating- and Thyristor Operating Instructions
Monitoring Systems
SAV1, SAV21, SAV22
Edition: AA Order No.: 6DD2921-0AJ76

Copying of this document and giving it to others and the use or
communication of the contents thereof is forbidden without
express authority. Offenders are liable to the payment of
damages. All rights are reserved in the event of the grant of a
patent or the registration of a utility model or design.
We have checked the contents of this Manual to ensure that they

coincide with the described hardware and software. However,
deviations cannot be completely ruled-out, so we cannot
guarantee complete conformance. However, the information in
SIMADYN
this document is regularly checked and the necessary corrections SIMOVIS
included in subsequent editions. We are thankful for any SIMATIC
recommendations or suggestions. SIMOVERT are registered trademarks of Siemens AG.
 Siemens AG 1995 All rights reserved

Edition 10.95 Contents
Contents
Page
Definitions, warning information........................................................................................................5
1 Description ...........................................................................................................................................7
1.1 Applications............................................................................................................................................7
1.2 Design ....................................................................................................................................................7
1.3 Mode of operation ..................................................................................................................................9

1.3.1 Tasks of the SAV1 in the SIMOVERT I converters..............................................................................10
1.3.2 SAV21 and SAV22 tasks......................................................................................................................13
1.4 Connecting the SAV to controlled and uncontrolled supply voltages...................................................18
1.5 Binary DC voltage signals ....................................................................................................................19

1.5.1 Signal ranges .......................................................................................................................................19
1.5.2 Binary output signals............................................................................................................................19
1.5.3 Binary input signals ..............................................................................................................................20
1.6 Power supply voltage power-up and power-down ...............................................................................21
1.7 Processing the transfer signals ............................................................................................................21
1.8 Electrical noise immunity, shielding......................................................................................................22
1.9 Fiber-optic cable interfaces ..................................................................................................................23
1.10 SERS interface board (option) .............................................................................................................24

1.10.1 Brief description ...................................................................................................................................24
1.10.2 Mode of operation ................................................................................................................................24
1.10.3 Connector assignment .........................................................................................................................25
1.10.4 LED display ..........................................................................................................................................25
1.10.5 SIMADYN D function blocks (FB) for the CS41 coupling.....................................................................26
1.10.6 Fault/error assignment to the actual values output at function block DAV2.........................................27
1.10.7 Setting the IDENT number ...................................................................................................................27
1.11 Technical data......................................................................................................................................28
2 Start-up ...............................................................................................................................................30
2.1 Installation ............................................................................................................................................30
2.2 Installing/removing components...........................................................................................................31
2.3 Fiber-optic cable interfaces ..................................................................................................................32

2.3.1 Fiber-optic cable lengths ......................................................................................................................32
2.3.2 Fiber-optic cable - final handling and mounting....................................................................................32
Siemens AG 6DD2921-0AJ76 3
Converter Gating- and Thyristor Monitoring Systems Operating Instructions
Contents Edition 10.95
2.4 Pulse assignment.................................................................................................................................34

2.4.1 Pulse assignment for the SAV1............................................................................................................35
2.4.2 Pulse assignment for the SAV21..........................................................................................................36
2.4.3 Pulse assignment for the SAV22..........................................................................................................36
2.5 Reset- and reconfiguring buttons .........................................................................................................37
2.6 Zero ohm resistors ...............................................................................................................................38
2.7 Connector assignment .........................................................................................................................39

2.7.1 Plug connector -X1, socket connector -X2...........................................................................................39
2.7.2 Plug connector -X5...............................................................................................................................39
2.7.3 Plug connector -X8...............................................................................................................................40
2.7.4 Socket connectors -X4 and -X7............................................................................................................40
2.7.5 Socket connectors -X6 and -X9............................................................................................................41
2.7.6 Plug-in screw terminal -X3 ...................................................................................................................42
2.7.7 Screw connections for fiber-optic cables -X11 ... -X22 and -X31 ... -X42 ............................................42
3 Operation ............................................................................................................................................43
3.1 Optical status displays..........................................................................................................................43

3.1.1 System LEDs........................................................................................................................................43
3.1.2 SAV1 fault display ................................................................................................................................44
3.1.3 SAV21 fault display ..............................................................................................................................44
3.1.4 SAV22 fault display ..............................................................................................................................45
3.2 Causes of thyristor gating faults...........................................................................................................46
3.3 Causes of GTO gating faults (SIMOVERT I)........................................................................................47
3.4 Clock monitoring...................................................................................................................................47
3.5 Voltage monitoring ...............................................................................................................................47
4 Service.................................................................................................................................................48
4.1 Checking and maintenance..................................................................................................................48
4.2 Troubleshooting....................................................................................................................................48
4.3 Replacing sub-assemblies (AUL, LES) ................................................................................................48
4.4 Spare parts...........................................................................................................................................49
5 Abbreviations / terminology..............................................................................................................50
NOTE
♦ The information in this Manual does not purport to cover all details or variations in equipment, nor to provide
for every possible contingency to be met in connection with installation, operation or maintenance.
♦ Should further information be desired or should particular problems arise which are not covered sufficiently
for the purchaser’s purposes, please contact your local Siemens office.
♦ Further, the contents of this Manual shall not become a part of nor modify any prior or existing agreement,
committment or relationship. The sales contract contains the entire obligation of Siemens. The warranty
contained in the contract between the parties is the sole warranty of Siemens. Any statements contained
herein do not create new warranties nor modify the existing warranty.
4 Siemens AG 6DD2921-0AJ76
Edition 10.95 Definitions, warning information
Definitions, warning information

• QUALIFIED PERSONNEL
For the purpose of this Instruction Manual and product labels, a „Qualified person“ is someone who is familiar
with the installation, mounting, start-up and operation of the equipment and the hazards involved. He or she
must have the following qualifications:
1. Trained and authorized to energize, de-energize, clear, ground and tag circuits and equipment in
accordance with established safety procedures.
2. Trained in the proper care and use of protective equipment in accordance with established safety
procedures.
3. Trained in rendering first aid.
• DANGER
For the purpose of this Instruction Manual and product labels, „Danger“ indicates death, severe personal
injury and/or substantial property damage will result if proper precautions are not taken.
• WARNING
For the purpose of this Instruction Manual and product labels, „Warning“ indicates death, severe personal
injury or property damage can result if proper precautions are not taken.
• CAUTION
For the purpose of this Instruction Manual and product labels, „Caution“ indicates that minor personal injury or
material damage can result if proper precautions are not taken.
• NOTE
For the purpose of this Instruction Manual, „Note“ indicates information about the product or the respective
part of the Instruction Manual which is essential to highlight.
WARNING
Electrical equipment has components which are at dangerous voltage levels.
If these instructions are not strictly adhered to, this can result in severe bodily injury and
material damage.
Only appropriately qualified personnel may work on this equipment or in its vicinity.
This personnel must be completely knowledgeable about all of the warnings and service
measures according to this Instruction Manual.
The successful and safe operation of this equipment is dependent on proper handling,
installation, operation and maintenance.
Definitions, warning information Edition 10.95
CAUTION
Components which can be destroyed by electrostatic discharge (ESD)
Drive converters contain component and devices which can be destroyed by electrostatic discharge. These
devices and components can be easily destroyed if incorrectly handled. If it is absolutely necessary to handle
electronic boards then the following instructions must be observed:
♦ Electronic boards should only be touched when absolutely necessary.
♦ The human body must be electrically discharged before touching an electronics board.
♦ Boards must not come into contact with highly-insulating materials - e.g. plastic foils, insulated desktops,
articles of clothing manufactured from man-made fibers.
♦ Boards may only be placed on conductive surfaces.
♦ When soldering, the soldering iron tip must be grounded.
♦ Boards, and components should only be stored and transported in conductive packaging (e.g. metalized
plastic boxes, metal containers)
♦ If the packing material is not conductive, the boards must be wrapped with a conductive packing material,
e.g. conductive foam rubber or household aluminum foil.
The necessary ESD protective measures are clearly shown in the following diagram:
a = Conductive floor surface d = ESD overall
b = ESD table e = ESD chain
c = ESD shoes f = Cabinet ground connection
d d d
b b e
e
f f f f f
c c
a a a
Seated Standing Standing / sitting
Edition 10.95 1 Description
1 Description
1.1 Applications
The SAV system (converter gating and thyristor monitoring) with the necessary thyristor electronics (TE) or GTO
thyristor gating circuits (Gate Drive Unit GDU), is used to optically transfer signal data via plastic fiber-optic
cables in converter system with output ranges up to several 100 MW.
The SAV system is a gating- and monitoring system, whose functions can be adapted to the requirements of the
particular power semiconductor type (thyristor or GTO thyristor) by programming the LCA. Thus, this system is
suitable for example, for the subsequent applications:
− SIMOVERT D
− SIMOVERT I
− SIMOVERT S
− DC drives
− Static compensators
1.2 Design
SAV systems consist of sub-assemblies SAV1 SAV21 SAV22
and boards. Versions SAV1, SAV21 and
SAV22 are obtained by appropriately
equipping the basic board of the gating- LES1 AUL1 LES1 AUL2 LES1 LES2 AUL2
and monitoring logic (AUL) and the fiber-
optic receiver board (LES).
Fig 1.1 SAV system versions
Designation Explanation
SAV1 for GTO converters
SAV21/SAV22 for thyristor converters
AUL1 Gating- and monitoring logic for GTO converters
AUL2 Gating- and monitoring logic for thyristor converters
LES1 Opto-receiver and -transmitter board for 12 semiconductor devices (thyristors or GTOs)
LES2 As for LES1, however, without DC-DC converter, buffering and voltage monitoring
These boards are generally located in the power section. Thus, the SAV board housing has, in addition to the
mechanical function of protecting the sub-assemblies and boards, also the task of shielding the boards from
electromagnetic fields. The housing must therefore be grounded at the grounding connection (active grounding).
1 Description Edition 10.95
Opto-receiver- and -transmitter board LES
X11
X31
The front panels of the opto-receiver- and transmitter boards LES1 and LES2 (Fig. 1.2) are the
X13 X12
X33 X32
same. X11 to X22 and X31 to X42 are screw connections to connect plastic fiber-optic cables.
X11 to X22 are the opto inputs and X31 to X42 the opto outputs.
X16 X15 X14
X34
Gating- and monitoring logic
X36 X35
The front panels of the AUL1 and AUL2 are the same (Fig. 1.3).
X17
X37
X21 X20 X19 X18
X38
LED Color Significance
X40 X39
AUL1 AUL2
UH Green Power supply OK Power supply OK
X41
PA 1) Green LED function, refer to Section 3.1.1 LED function refer to Section 3.1.1
DUG 1) Red LED function, refer to Section 3.1.1 LED function refer to Section 3.1.1
X22
X42
BV1 Yellow Command output BV (X31 ... X36) Command output BV (X31 ... X36)
BV7 Yellow Command output BV (X37 ... X42) Command output BV (X37 ... X42)
Fig. 1.2
I=0 Yellow Zero current signal Zero current signal LES front panel
VZ 2) Green Status of the GTO gating circuit Status of the thyristor gating circuits
(11...22) (D1)
UH/VZ 2) Green Auxiliary power supplies (DSV) Status of the thyristor gating circuits
(31...42) (D2)
VZ UH/VZ
Push- Function RECON UH 11 17 31 37
button PA 12 18 32 38
RESET 13 19 33 39
DUG
RECON LCA re-configuration BV1 14 20 34 40
BV7 15 21 35 41
RESET Basic SAV status I=0 16 22 36 42
Connect. Connector type Function

AUL1 AUL2
X4 X7
X1 25-pin plug Firing pulses Firing pulses
connector
X1
X2 25-pin socket Firing pulses Firing pulses
connector
X3 3-pin insertable Power supply voltages Power supply
X5 X8
screw terminals voltage
X4, X7 9-pin socket Serial interface Serial interface
connector (option) (option)
X5, X8 15-pin plug Monitoring signals of No function
X2
connector the distributed power
supplies
X6, X9 37-pin socket Status signals Status signals
connector
X3 X6 X9
Fig. 1.3 AUL front panel

1) only if the SERS interface board (option) is inserted
2) LED flashes under fault conditions
1.3 Mode of operation

The SAV boards represent the interface element between the open-loop/closed-loop control and the gate drive
unit and the thyristor electronics. They are connected to ground potential.
The SAV board connections to the gating units, which are at a high-voltage, are realized using plastic fiber-optic
cables and shielded control cables to the SIMADYN D control (closed-loop control).
The task of the SAV boards is to condition the firing pulses corresponding to the drive-specific requirements, and
to logically combine them with the checkback signals from the Gate Drive Unit and the thyristor electronics.
Important signals are thus derived for the closed-loop control.
The hardware surrounding the LCA is essentially used to adapt the interfaces. This includes:
− Optocoupler inputs for firing pulses
− Optocoupler inputs to monitor the distributed power supplies (for SAV1)
− Opto inputs and outputs to gate and monitor the GTO- and conventional thyristors
− Push-pull output driver to transfer status signals over long distances (up to 200 m)
A 40-pin diagnostics interface on the backplane bus for each LES board permits the following:
− Information to be provided regarding the switching behavior of the thyristors or GTO thyristors
− the internal voltages to be checked
− the voltage monitoring to be checked
This diagnostic interface also supports start-up.
The LEDs located on the front panel provide information regarding:

− Gating- and checkback signal circuit faults
− DSV distributed power supply faults (for SAV1)
− Command output to the opto-transmitter driver (summed signal BV[1..6] and BV[7..12])
− INULL signal
− Power supply OK
− Data transmission link faulted 1)
− Processor active 1)
The SAV can be optionally expanded using a plug-on supplementary board (SERS interface board). It transfers
the following internal status signals to a higher-level communications system:
− Power supply OK
− Clock OK
− Redundancy status of the individual arms
− Status of the gating- and monitoring circuits, i.e. fiber-optic cable connections, opto-transmitter and opto-
receiver on the SAV and the thyristor electronics or GDU
− Status of the distributed power supply (DSV)
DUST6(B) as short telegram is used as the data transmission protocol. These individual signals/messages can
be conditioned, logged and visualized (SIMOVIS D) using the digital SIMADYN D control system. If the minimum
number of thyristors per arm is fallen below, the open- and closed-loop control can fault-trip the drive via this
information channel.
1) LEDs are active, if the optionally available serial interface board is inserted
(refer to Section 3.1.1).
1.3.1 Tasks of the SAV1 in the SIMOVERT I converters
SAV1 gates and monitors GTO thyristors. One application is for example, to gate and monitor the motor side for
SIMOVERT I converters. It conditions all of the input/output commands coming from the GTO monitoring and
interlocking board (GÜV) so that the commands can be monitored, and if required corrected for minimum switch-
ing times (on and off).
Further, the new switching status must have been established within a specific time after a command has been
output. Otherwise, the „thyristor arm fault“ or „redundancy reduced“ signal is output, corresponding to the
converter type (N- or N+1 version).
These status messages are transferred to the GÜV, arm-related. A thyristor arm fault activates the protective
algorithm there, which initiates higher-level measures to protect the GTO converter.
The distributed power supplies (DSV) for the Gate Drive Unit are also monitored by the SAV1, logically combined
with the internal „power supply OK“ signal, and transferred, as group signal to the GÜV (UH signal). After 10 ms,
this responds to the fault situation (DSV+GDU and SAV1 are buffered for at least 20 ms) by crowbar firing the
appropriate GTO.
Fig. 1.5 shows a general block diagram of the SAV.
The functions realized in the LCA are illustrated in Fig. 1.4. The modules illustrated there must fulfill the following
functions:
Syn- Correction to the Command

BVZ1 to BVZ6 min. switch. times BVK1 to BVK12 BV1 to BV12
chroni- TBA, TBE multiplic-
zation ation
BVIMP1 to
BVIMP12
SV1 to SV12 Syn- Thyr. status monit. V1 to V12

chroni- TBESE, TBASA
zation
Thyr. status VZ1 to VZ6

monit.
CLK_125 Clock-
(8 MHz) conditioning
RVZ1 to RVZ6
Reduced redund-
UEUH ancy RS
monitoring
UHV1 to UHV12 UH- UH_SR1

UHIBE, status
UEUH determination
Fig. 1.4 LCA structure of the SAV1
♦ Synchronization
The status checkback signals SV1 to SV12 and firing pulses BVZ1 to BVZ12 are synchronized with a clock CLK
via an input flipflop and a two-stage D flipflop combination to prevent metastable statuses. Further, input signals
which are present for less than a clock period, are suppressed. Thus, the output signal only changes for input
signals which are available as stable signals for longer than one clock period.
Pulse inhibit
Gating pulses Status checkback signals Status checkback signals Monitorings- Aknowledge signal
(long pulses) LES1 LES2 signals (DSV) Transfer signals +24V DC
Fig. 1.5
12
Edition 10.95
X1 X2 X11 bis X22 X11 bis X22 X5 X8 X6 X9 X3

SAV
P24E
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N
F
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LW

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Q
R

P
FRUW
QUIT_EXT
SAV block diagram

(
P24P
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&
1
Siemens AG 6DD2921-0AJ76
UERS
VZ_EXT_N
INULL_EXT_N
UEUH_SR1
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5
WL
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N.B. 24V 24V
(only SAV1)
5V 12V
8MHz
P5L
50kHz
BVZ1 to BVZ12 SV1 to SV12 SV13 to SV24 P12
Converter Gating- and Thyristor Monitoring Systems

V
5
9
G

Clock monitoring GN
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LCA logic, refer to Sections 1.3.1 and 1.3.2 UHIB

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FRLS_N
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VZ1 to VZ24 RVZ1 to RVZ6

Enable Enable
Flash frequency opto transmitter output driver
Clock_OK
BV[1:12], SV[1:24] for
UHIB
signals/messages
P24E, P24P, P12, P5L
UHIBE, UHIBR, UHIB
=1 =1 Coding

9
switch
BV1 to BV12
NOR2
NOR2
NOR2
NOR2

9
YE YE
GN GN GN GN RT GN YE
BV1-6 BV7-12
UL
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D
6
VZ_N
UH_N
(M1) (M2)
INULL_N
RS_N
V1 V12 V13 V24 IU DUST6 Processor INULL

F
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faulted active
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6
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1 40 1 40
LED group LED group
L
WL
( LES1) ( LES2)
F
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LES1 LES2
L
F
WH
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Option
X31 to X42 X31 to X42 X4 X7 X6 X9
BV1 to BV12 BV1 to BV12

Serial Zero load current signal
signal transfer thyristor/GTO status
Gating commands Gating commands redundancy status
(long opto pulses) (long opto pulses) power supply
LES1 LES2
11
1 Description
♦ Correction for minimum switching times T BE and TBA

Every command change starts a counter, which monitors the on- or off command for a minimum time and if
required, corrects this value. This can, for example, occur for dynamic operations. In this case, the gating unit
shortens the pulses which are then sent to SAV1 via the GÜV where they are checked to ensure that they are
plausible, i.e. only one on command per bridge half. This corrects the on/off commands to minimum switching
times. The minimum on time TBE and the minimum off time TBA cannot be separately set. Thus, the following is
always valid
TBE = TBA = TB typical value: TB = 208 µs + < 1 µs
The minimum time can be set in 16 µs steps up to 240 µs. As commands are processed at 4 MHz and the
minimum time monitoring is realized with a 1 µs cycle, time differences of < 1 µs can occur referred to the gating
signals of a bridge half.
♦ Thyristor status monitoring TBESE and TBASA

Output command and checkback signal are compared using an XNOR stage. A 4-bit counter, which is clocked
with 4 µs is started if the signals differ. Thus, times can be set in a range from 0 to 60 µs. Time deviations from
the set value of < 4 µs are possible, as the checkback signals are read-in with a higher clock frequency.
Generally, the monitoring times are set differently, as the GTO thyristor turns-on faster than it turns-off.
1
TBESE = T = 20 µs (typical value)
2 BASA
On/off command
SAV1
Checkback signal
GDU
TBESE TBASA
Fig. 1.6 Shift time monitoring
If the checkback signal of the new switching status isn’t received within a specified time, then the associated
GTO gating- and monitoring circuit is signaled as being faulted. If after this, i.e. after a correct switching
sequence, the signal equivalence is violated after the monitoring time has expired, then an error signal is
immediately output.
As shown in Fig. 1.4, the individual position information V1 to V12 is transferred as LCA output signals. These
signals control, on one hand, LEDs VZ11 to VZ22 (thyristor status) on the front panel of the AUL board, and on
the other hand, they are fed to socket connectors for processing the optional SERS interface board. Within the
LCA, these signals are fed to the „thyristor arm status identification“ module.
♦ Thyristor arm status identification

The thyristor signals associated with an arm are logically combined corresponding to the version and the number
of thyristor connected in series. These signals control the output driver, which transfers this information to the
GÜV.
♦ Reduced redundancy monitoring

This involves converters with redundant GTO thyristors (N + 1 version). The signals, associated with an arm, are
monitored with the individual position information V1 to V12 and the associated monitoring signals of the
distributed power supplies UH1 to UH12. The „redundancy reduced“ signal is transferred when a fault condition
is present:
− as group signal to the GÜV and
− as arm-related signal to the serial interface
♦ UH status determination
A group signal UH_OK is transferred to the GÜV. The individual signals are logically AND’d in this module.
♦ SAV1/GÜV interface
The interface to the GÜV (open-/closed-loop control) is defined as:
Converter Binary signals SAV1 to GÜV Binary signals from GÜV to

SAV1
6-pulse GTO converter − 6 thyristor arm signals − 6 on/off commands
(e.g. SIMOVERT I, motor-side) − UH_OK − Acknowledge signal
− RED_OK
− 6 thyristor arm signals (SR1) − 6 on/off commands (SR1)
− 6 thyristor arm signals (SR2) − 6 on/off commands (SR2)
− UH_OK_SR1 − Acknowledge signal (SR1)
− UH_OK_SR2 − Acknowledge signal (SR2)
♦ Clock conditioning
The LCA is supplied with an 8 MHz clock. The required intermediate frequencies for signal processing are
derived from this clock frequency.
1.3.2 SAV21 and SAV22 tasks
SAV21 and SAV22 control and monitor the conventional thyristors in the B6C- or (B6C)A(B6C) circuit configu-
ration. Different converter configurations are also possible (e.g. M3 circuit configuration). A prerequisite for
applying this technology is that the TAS21A thyristor electronics power supply is provided from the displacement
current of the RC circuit (snubber circuit).
These boards condition the firing pulses output from the control (long pulses) and convert them into opto signals
which are then sent to the thyristor electronics (TAS21A) via plastic fiber-optic cables. The firing readiness is thus
initiated, and a monitoring- and interlocking logic function activated, which senses the thyristor switching status,
and transfers this to the SAV21/22 via the checkback signal fiber-optic cable.
Thyristor switching statuses are signaled using time-coded checkback signals „thyristor conducts“ and „thyristor
blocks“. The current flow times of the individual thyristors are generated from these signals on the SAV21/22
using time decoding, and are logically combined to form a zero load current signal. If checkback signals are
missing, this is identified as a fault at the end of the firing pulse (refer to Fig. 1.8).
Converter monitoring and open-loop control are based on these time-coded checkback signals. Thus, checkback
signals are monitored, i.e. if a maximum value is exceeded or a minimum pulse duration fallen below, which in
the first case causes a fault message immediately and in the second case via the turn-on monitoring This causes
the SIMADYN D closed-loop control to output an alarm signal or to shutdown the converter.
Fig. 1.7 shows an overview of the functions implemented in the LCA.
$69!
LCA-THY
1) for N+1 version
Fig. 1.7 Rough structure of the LCA logic for a thyristor converter in an N + 1 version
The functions are partially identical with those in the logic for SAV1 (refer to Section 1.3.1). Thus, only the section
which was not previously described is explained.
A block diagram of the SAV with the general LCA functions is illustrated in Fig. 1.5. Fig. 1.7 should be inserted in
this general LCA block diagram.
♦ Turn-on monitoring (function module ASV)
After a firing command has been output to the thyristor electronics, at least one checkback signal is expected
within a time range of
command duration + 80 ... < 160 µs
A fault signal is generated if this is not the case.
t on = t BV + 80 ... < 160 µs

On
command
Status t = 0 ... < 80 µs

chckbk. sig
t
Fig. 1.8 Turn-on monitoring, checkback signal at the end of the command (fictitious end of current signal)
♦ Pulse duration monitoring (function module ASV)

The time-coded thyristor electronic checkback signals are decoded on the SAV. The current flow durations of the
individual thyristors are generated from these signals. The extremely significant zero load point signal is
generated from these for the cycloconverter closed-loop control.
The checkback signals are defined as follows:
− "Thyristor conducts":Opto pulse 10 ... 14 µs
− "Thyristor blocks": Opto pulse 4 ... 6 µs
They are monitored for pulse duration violation (exceeded or fallen below). A condition where the pulse duration
is exceeded is checked shortly before a four-bit counter is reset. A fault signal is generated if the synchronized
checkback signal is still present, e.g. after 17µs (Fig. 1.9, t1).
If the pulse duration is fallen below, this is only indirectly identified in so much that checkback signals are sup-
pressed < 2 µs (range A), and checkback signals, which are < 4 µs can be suppressed (range B), as the status
checkback signals are received asynchronously to the LCA clock and these signals are synchronized via the
input flipflop and the „SYNGU“ function module.
17 µs
12 µs
Status checkback signal
"thyristor conducts"
5 µs
Status checkback signal
"thyristor blocks"
A B
t0 t1 t
Fig. 1.9 Pulse duration monitoring and influence of the SYNGU stage
♦ Enable control (function module ASV)

This control signal is exclusively conceived to monitor the motor-side converter for SIMOVERT S drives.
The motor-side converter for SIMOVERT S, places certain requirements on the monitoring dialog (SAV21/22 -
TAS21A). For example, when the synchronous motor runs down to a speed n < 10 % (operating status „single-
quadrant operation“, line-side converter inhibited, command outputs to the motor-side converter), it results in
status checkback signals not being transferred to the SAV as the power supply voltage at the TAS21A thyristor
electronics has collapsed. In this case, the turn-on monitoring would otherwise erronously generate fault signals.
In order to correctly identify operating cases such as these, a group signal is generated from the line-side com-
mands, which only controls the ASV modules associated with the motor side. However, this open-loop control
function is only active, if the FRUW external input is energized from the open-/closed-loop control with an H
signal. It is possible to intervene here, which, dependent on the drive and its operating mode, can enable the
thyristor monitoring in the lower speed range, either early on, or even generally (in this case, the monitoring is
active over the complete speed range).
FRUW Effects
H signal ASV module, motor-side converter = f (line-side commands)
L signal Status checkback signal monitoring by the ASV module is enabled
♦ INULL thyristor (function module ASV)

The associated 4-bit counter for the pulse duration monitoring generates a so-called status signal decoding
pulse, which allows an enable signal to accept the logical status of the status checkback signal after 8µs (refer to
Fig. 1.9). Thus, the thyristor current flow times are generated on the SAV.
♦ Zero current conditioning

Converter-related gating
For the converter-related gating of the anti-parallel thyristors, connected in series of a (B6C)A(B6C) converter
(other circuit configurations are conceivable), the status checkback signals are evaluated, as if it involved a
fictitious number of arms connected in series of a (B6C)A(B6C) converter with a number of thyristors connected
in series of R = 1 (SAV21) or with the number of thyristors connected in series of R = 2 (SAV22) (Fig. 1.10).
Supply
I1.1 V1 V2 V3 I1.4
I2.4 I2.1
I1.3 I1.6
I2.6 I2.3
I1.5 I1.2
I2.2 I2.5
Neutral
point
Output-
phase INULL_EXT
INULL_V1_N INULL_V3_N
INULL_V2_N
PULLUP
AND2 NOR2B1
NOR2B1 TBUF AND2
AND2
AND2 Wired-AND AND2
SAV22 SAV21
INULL_SAV21
Zero load curr.

signal
(I=0 = H)
Fig. 1.10 Block diagram of the status checkback signal evaluation of a (B6C)A(B6C) converter with a number of thyristors connected in
series, R = 3 for converter-related gating (N version).
The pulse information (e.g.: I1.5 = bridge 1, pulse 5) refer to a complete B6C bridge arm.
A zero thyristor current signal (e.g. INULL_V1_N) is signaled with an L active. For SAV22, these signals for two
thyristors in a arm, are logically AND’d. In this case, current must flow through the two thyristors of an arm, so
that the signal „zero load current = L“ is output. For SAV21, a conductive thyristor (current flowing) results in the
signal „zero load current = L“ being output.
The further processing (NOR/AND functions) is functionally the same for SAV21 and SAV22, and provides, as
result, the zero load current signal, and INULL_SAV21 or INULL_SAV22.
Referred to Fig. 1.10, this evaluation philosophy means that a zero load current is signaled, if a thyristor has
assumed a blocking voltage from each of the fictitious converter bridges in all 6 arms. This means, that in Fig.
1.10, all thyristors, with a grey background, have a blocking voltage condition, and for the thyristors with the light
background enclosed by dotted lines, 1 per arm now have a blocking voltage condition.
As a result of this, a general statement can be made regarding converter-related gating:
1) A current greater than 0 is signaled, if, for SAV21, one thyristor, or for SAV22, two thyristors in an arm, are
conducting.
2) A current equal to zero is signaled, if one thyristor in all six arms of a fictitious converter bridge, has a blocking
voltage.
The faults identified by the monitoring logic (ASV) are stored, and INULL_V_N = H is output, i.e., it is signaled
that the current is greater than zero. This technique is necessary for N+1 versions, so that INULL_V_N signal
processing is not blocked by the AND stages.
Arm-related gating
The arm-related gating is conceived for N+1 versions. Fig. 1.11 illustrates an example of an N+1 version.
The arm-related gating and evaluation requires, when a fault condition occurs, that the INULL signal associated
with the faulted thyristor circuit, is suppressed.
The redundancy monitoring signals the faulted thyristor circuit. For an N+1 version, one thyristor circuit fault is
permissible per arm. The thyristor status monitoring only outputs a fault signal which causes the converter to be
shutdown, when a second fault occurs.
Supply
I1.1 V1 V2 V3 I1.4
I2.4 V3A V2A V1A I2.1

I1.3 I1.6
I2.6 I2.3
I1.5 I1.2
I2.2 I2.5
V1 to V18
V1A to V18A
(antiparallel bridge) Neutral-
point
Output-
phase INULL_EXT
INULL_V1_N INULL_V1A_N
PULLUP PULLUP
"1" AND4 "1" AND4
NOR2B1 TBUF NOR2B1 TBUF
Wired-AND AND2 Wired-AND AND2
SAV22 SAV22
INULL_SAV22
Zero load curr.-

signal
(I=0 = H)
Fig. 1.11 Block diagram of the status checkback signal evaluation of a (B6C)A(B6C) converter with a number of thyristors connected in
series, R=3 for arm-related gating (N+1 version).
The pulse information (e.g.: I1.5 = bridge 1, pulse 5) refer to a complete arm of B6C bridge.
1.4 Connecting the SAV to controlled and uncontrolled supply voltages

SAV boards can be connected to controlled and uncontrolled supply voltages.
The 24 V DC (P24E) supply voltage is connected through the plug-in screw terminal (-X3). The P24 E supply
voltage is fed to the opto-receiver board via the AULG basic board and the backplane bus. Here, the voltage is
fed to five 1000 µF buffer capacitors via a diode and a resistor.
The supply has its own path impedance, so that the connected functional areas are not disturbed by the continu-
ous buffer capacitor charging. The ground connection for the connected function areas is realized in a star
configuration from the last buffer capacitor (refer to Fig. 1.12).
P24P for serial

interface
P5L for
logic
24 V DC
+25 %, − 20 %
P24P for o/p

driver
Fig. 1.12 Supply and voltage distribution for the SAV board
Diode V201 has 2 tasks to fulfill:

1) A buffering function, i.e. energy is not taken from the supply side
2) Protection against incorrect polarity connection
Using this power supply concept, the SAV system is buffered for at least 20 ms at a minimum input voltage of
19.2 V.
1.5 Binary DC voltage signals

1.5.1 Signal ranges
Signal range for inputs, permissible ranges:
Nominal signal L signal Lower limit 0V

H signal Upper limit 24 V
Input current drain for an H signal 3.3 mA
Interpretted as H by the input Input voltage range Lower limit +13 V
Upper limit +35 V
Interpretted as L by the input Input voltage range (or inputs open-circuit) Lower limit −3 V 1)
Upper limit +5 V 1)
Signal range for outputs, permissible ranges:
Nominal signal L signal Lower limit 0V

H signal Upper limit 24 V
Permissible output current for an H signal 500 mA
Output has an H signal Output voltage range Lower limit +16 V 1)
Upper limit +30 V 1)
Output has an L signal Output voltage range Lower limit 0V
Upper limit +2 V 1)
1.5.2 Binary output signals
The output driver for signals, provided on the AUL board, is supplied from the buffered 24 V supply. FET driver
stages are always used. The important features of these driver stages are:
− two driver stages in one housing
− 1.0 A totem pole output
− inverting- and non-inverting input
− 40 ns rise- and fall time for a 1000 pF load
− shutdown input
− 16-pin dual-in-line package
For the binary output signals, the driver saturation voltage should be subtracted from the buffered 24 V. This is
dependent on the output current, and is 2.0 V at 50 mA, and 2.5 V at 500 mA.
WARNING
The output signals are not short-circuit proof. Thus, control cables may only be inserted when the system is in a
no-voltage condition.
Further, only pre-assembled, tested control cables should be used.
1) Corresponds to IEC 946 (1988)
1.5.3 Binary input signals
The binary input/output signals have a 24 V signal level (nominal value). The external binary input signals are de-
coupled through opto-couplers.
There are the following binary input signal groups

− DSV signals (only for SAV1)
− Control signals (firing pulses)
− External acknowledge signal
− Enable signal
For the control commands, the signals can be coupled in two ways according to the gating stage on the sender
side (e.g. GÜV or SE20.2).
GÜV SAV
Firing
pulse
Firing pulse
=H
LCA
M
Data transfer
link
Open-/closed- ≤ 200 m
loop control Power section
Fig. 1.13 Control command output via a totem pole output stage
Maximum cable length: 200 m, recommended control cable: LiYCY kx2x0,18 (k=pair number)
SAV
Firing
SE20.2
pulse
P24
Firing pulse
LCA
=L
Data transfer
link
Open-/closed- ≤ 100 m
loop control Power section
Fig. 1.14 Control command output via an open-collector output stage

Maximum cable length: 100 m, recommended control cable: LiYCY kx2x0,18 (k=pair number)
1.6 Power supply voltage power-up and power-down

It is not permissible that the opto-transmitters output opto signals when the power supply is powered-up and
down. Thus, a reset function is implemented on the SAV. When the power supply voltage is powered-up, the
LCA are configured, and the opto-transmitter drivers inhibited, until the power supply for the logic has been
established and the configuration data have been read from the LCA.
The I/O of the LCA are terminated through high-ohmic loads during the configuration, so that the display LEDs,
on the diagnostics module indicating the commands, have an H signal for this time. No opto signals are output,
as the opto-transmitter drivers are not enabled due to FRLS_N = L (shutdown signal active).
The same sequence (command output to the opto-transmitter drivers, shutdown signal active), can be monitored
at the diagnostics module by depressing the RECON button (LCA is re-configured).
At power-down, when a minimum voltage is fallen below, the LCA is brought into the reset status as a result of
UHIBL and/or UHIBR, and the enable signals for the opto-transmitter drivers are withdrawn.
1.7 Processing the transfer signals

Depending on the converter circuit configuration, several SAV boards can be used. For this case, the group
signals, generated on each SAV board, starting from one SAV, are read-in to the next SAV as transfer signal
(Fig. 1.15). Output signals, which are not logically combined in the subsequent SAV boards, must be connected
1:1 to the subsequent SAV boards (refer to the connector assignment, Section 2.6.5 and in Fig. 1.16 e.g. X6,
X9:25).
Thus, the signals to the open- and closed-loop control are limited to a minimum.
SAV1 SAV1 GÜV
UH_INT UH_INT
UH_EXT UH_OK
UH_EXT
24V DC
LCA LCA LCA
Power section Open-/closed-loop control
Fig. 1.15 Block diagram for processing the transfer signals. The corresponding is valid for SAV21 and SAV22
SAV SAV
M M M M
P24P P24P P24P P24P
X9 X6 X9 X6
1 N.C. 1 1 N.C. 1
2 2 2 2
3 UEUH 3 3 UEUH 3
4 N.C. 4 4 N.C. 4
5 FRUWP 5 5 FRUWP 5
6 FRUWM 6 6 FRUWM 6 ⇐ FRUW
7 QUIT_EXTP 7 7 QUIT_EXTP 7
8 QUIT_EXTM 8 8 QUIT_EXTM 8 ⇐ QUIT
9 INULL_EXT 9 9 INULL_EXT 9
10 VZ_EXT 10 10 VZ_EXT 10
1 INULL 1 1 INULL 1 To
1 1 1 1 INULL
12 12 12 12 the open-/closed-loop control
13 VZ 13 13 VZ 13
14 14 14 14 SIMADYN D
VZ
15 15 15 15
16 RS 16 16 RS 16
17 17 17 17
18 18 18 18
19 UH 19 19 UH 19
20 20 20 20
UH
21 21 21 21
22 N.C. 22 22 N.C. 22
23 23 23 23
24 24 24 24
25 N.C. 25 25 N.C. 25
26 26 26 26
27 27 27 27
28 N.C. 28 28 N.C. 28
29 N.C. 29 29 N.C. 29
30 N.C. 30 30 N.C. 30
31 N.C. 31 31 N.C. 31
32 N.C. 32 32 N.C. 32
33 N.C. 33 33 N.C. 33
34 N.C. 34 34 N.C. 34
35 35 35 35
36 UERS 36 36 UERS 36
37 37 37 37
Fig. 1.16 Example for wiring thyristor gating signals
The actual signal wiring should be taken from the appropriate circuit manual.
1.8 Electrical noise immunity, shielding

As SAV systems are installed in power sections used in industrial applications, they are subject to
electromaganetic noise fields.
The signals are transferred to the gating systems, which are at a high-voltage potential, through plastic fiber-optic
cables, which are immune to electrical noise and disturbances, and therefore cannot be influenced by electrical
burst. No measures against cable-borne noise are required for these interfaces.
For all other interfaces, signals are transferred hard-wired. In this case, cable-borne noise is possible. In order to
essentially suppress external noise and disturbances, it is possible to use non-symmetrical, floating signal
transmission. For this type of data transmission, the receiver (optocoupler) receives the signal together with the
transmitter-side reference potential. The signal information is therefore transferred to an optocoupler through a
closed-loop. The coupling capacitance of the optocoupler used in the SAV is 0.6 pF, so that higher-frequency
noise signals are essentially not coupled-in. An example of a non-symmetrical, floating signal coupling is
illustrated in Fig. 1.13.
The symmetrical noise components are kept low using twisted cables, so that the radiating- as well as impinging
electromagnetic fields compensate each other due to the alternating surface vectors.
Shielding, with the exception of the serial interface (refer to Section 1.10.3), should be realized so that the shield
is connected to the connector housing at both ends and at the shield retaining bar.
Refer to Section 1.11„Technical Data“ for information regarding the noise characteristics.
1.9 Fiber-optic cable interfaces

The opto-transmitter driver circuitry of the SAV systems is always the same. It is ensured, that there is no
significant signal delay over the complete operating temperature range, between the control signal and receive
signal on the GDU or the TAS21A thyristor electronics. This is of course also valid in the opposite direction. The
basic control circuit is illustrated in Fig. 1.17.
Fig. 1.17 Opto-transmitter driver control and associated signal diagram with a fictitious pulse pattern
In order to shorten the switch-on time of the opto-receiver in the thyristor electronics TAS21A and on the GDU,
the opto-transmitter diode current is increased using a „speed-up“ capacitor. In the first instant, the current spike
is only limited by a resistor.
The rise- and fall times of the opto-transmitter driver UC3707 are both 40 ns, therefore guaranteeing a high
switching speed. Thus, the positive current spike is almost instantaneous. The subsequent re-charging sequence
(time constant, approx. 13 µs) is defined by the resistor and the capacitor.
The current level at the falling edge reaches 24 mA after approx. 50 µs. In this stabilized status, the series circuit
of both resistors limits the current to the this value.
The continuous current and current increase can be selected by appropriately selecting the resistors. The
duration of the increased current phase is defined by the capacitance.
1.10 SERS interface board (option)

1.10.1 Brief description
The SERS interface board is an optional part of the SAV system. Its task is to serially transfer the status signals
of the gating circuits, generated on the gating- and monitoring logic (board AUL) of the SAV system (opto-
transmitter-fiber-optic cable- thyristor electronics and GDU - fiber-optic cable - opto-receiver) as well as board-
specific internal signals, to a higher-level communication system using the DUST6 protocol (refer to Fig. 1.18).
The interface board operates exclusively as slave and under the following boundary conditions:
− Only one actual value processing is implemented
− Baud rate = 117.6 kbaud
− Net data length = 8 bytes (short telegram)
DUST6 is a serial bus, where a master (e.g.CS41) and up to 15 SAV (slaves) can be connected. The bus
operates according to the master-slave principle.
The master sends a telegram to a slave, and the Master
addressed slave responds in the next telegram cycle; CS41
slaves which haven’t been addressed, do not respond.
If only one slave is connected, then it involves a point-
to-point connection, whereby the single slave has
address 0.
SAV SAV SAV Slaves SAV
Data transfer is realized via an RS485 interface. The 0 1 2 14
serial data is transferred, without ground reference, as
voltage difference between two corresponding cables. Fig. 1.18 Coupling several SAV boards to a higher-level
There is one core pair for the two signals to be communications board.
transferred (RxD and TxD), which consists of an
inverting and a non-inverting signal cable. The receiver evaluates the voltage differing between both cables, so
that common mode noise on the data transmission cable does not have a significant influence on the serial data.
1.10.2 Mode of operation
Before the microprocessor (V25+), can assume its actual task, interrupt-controlled, the hardware of the SERS
interface board must be initialized. In this SERS initialization phase, for example, the IDENT switch position is
checked, and when the DIP switch is correctly set, the slave address is stored (board identification).
If this has been realized error-free, the interrupts are enabled, and a jump is made into an endless loop to
cyclically scan the diagnostic signals received from the AUL board (refer to Fig. 1.5).
If SERS identifies a fault/error in the starting phase, then the start is aborted. Communications with the master
board are no longer possible. This status is signaled on the AUL board by switching-out the green LED PA (LED
goes dark), and the flashing red LED DUG.
In the receive interrupt, when a complete telegram has been received, the error register is evaluated to check for
overrun-, framing- or parity errors, and the DUST6-specific protocol frame is checked for its validity. If valid
receive data is available, the received telegram address is evaluated. If the telegram is for the SERS interface
board, a send job exists, and the diagnostic signals, entered in the TX alternating telegram buffer, are provided
with the protocol frames and prepared for transmission.
1.10.3 Connector assignment
The SERS interface board wiring is illustrated in Fig. 1.19. The cable connection should thus be established
according to the information in [1], Section, Bus cable:
[1]:CS41 communications module, connecting DUST6 and ET100U
Technical description 1992
X5, X6, X7, X8
X4
TM 1 14
TP 9 15
RM 5 7
RP 6 8
M5EXT 3,4 7,8 6

Insulated shield terminating
P5EXT 2
CS41
X7
TM 1
TP 9
RM 5
RP 6
M5EXT 3,4 7,8
P5EXT 2
SAV-SERS
X4
TM 1
TP 9
RM 5
RP 6
Insulated shield terminating

M5EXT 3,4 7,8
P5EXT 2
X7
TM 1 Connector housing
TP 9
120 Ohm
RM 5
RP 6
M5EXT 3,4 7,8
P5EXT 2
SAV-SERS
Fig. 1.19 Connector assignment, shield handling and bus terminating resistor
Generally, the shields of DUST 6 connecting cables are connected at the shield connecting bar where the cable
enters the cabinet. However, not in the SAV connector housing (refer to Fig. 1.19).
The last slave on the bus receive line must be terminated with 120 Ω. In this case, for example, the SM5 bus
terminating connector can be used. The bus terminating resistor must be soldered into the connector housing
(refer to Fig. 1.19). On the master side (CS41), its receive line already has an internal bus terminating resistor.
1.10.4 LED display
Refer to Section 3.1.
1.10.5 SIMADYN D function blocks (FB) for the CS41 coupling
The following configurations are possible at the 4 serial CS41 plug connections:
Possibility X5 X6 X7 X8
1 DUST6 / 6B DUST6 / 6B DUST6 / 6B DUST6 / 6B
2 DUST6 / 6B DUST6 / 6B -- ET100
3 -- ET100 -- ET100
One of these configurations is selected, and the number of bus nodes is defined in the master program by the
information entered in the CS41 board mask.
Example: Serial coupling of the CS41 with 5 SAV boards, short telegram.
Board mask:
D04CS4 : CS41 „Drive converter coupling SIMADYN D CS41“
T0 TG = 16[ms] „Cycle time, synchronization“
TSH 2C = DS „Telegram specification for X5 and X6“
TSL 2C = 0 „Telegram specification for X7 and X8“
ND5 2C = 5 „Number of units at connector X5“
ND6 2C = 0 „Number of units/ET100 at connector X6“
ND7 2C = 0 „Number of units at connector X7“
ND8 2C = 0 „Number of units/ET100 at connector X8“
X5A 1K < *SAV „Connector X5“
X6A 1K < „Connector X6“
As the SAV-SERS slave board only transfers actual XAS Actual value
values, on the SIMADYN D side, both FB DAV and DAV2
can be used to evaluate the actual values. For both FBs, 0 Main act. value Short
that (those) actual value(s) can be defined, which is (are) 1 Status word telegram
to be transferred from FB DAV or DAV2, using a select 2 Actual value 1
connector XAS. The assignment is as follows: 3 Actual value 2 Long
4 Actual value 3 telegram
XAS must be set to 0 at FB DAV2 for a short telegram, as 5 Actual value 4
the status signals, transferred from the SERS, are 6 Actual value 5
incorporated in the main actual value and in the status
7 Actual value 6
word.
FB mask: DAV2
H100 : DAV2 „Unit actual value, 2 actual values“
AD NK = *SAV „Hardware address“
DAD O2 = 4 „Unit number = IDENT-No. on the SERS board“
XAS O2 = 0 „Act. val. selection = 0 -> main act. val. and status word “
Y1 N2 > „Actual value 1“
Y2 N2 > „Actual value 2“
QF B1 > „Error“
The device address DAD (0 to 14) should be entered in an increasing, consecutive sequence (without gaps),
starting from 0.
The FB DTC is suitable for telegram error checking; if the configured number of consecutive missing telegrams is
exceeded, a bit is set in error word QF.
1.10.6 Fault/error assignment to the actual values output at function block DAV2
Actual value 1:
Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LED VZ34 VZ33 VZ32 VZ31 VZ22 VZ21 VZ20 VZ19 VZ18 VZ17 VZ16 VZ15 VZ14 VZ13 VZ12 VZ11
on AUL LES2 LES1
Actual value 2:
Bit 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
LED UHE TOK RVZ6 RVZ5 RVZ4 RVZ3 RVZ2 RVZ1 VZ42 VZ41 VZ40 VZ39 VZ38 VZ37 VZ36 VZ35
on AUL AUL FPGA XC3090 LES2
The OK signal status is H active. The fault/assignment is shown here for SAV22. LES2 is not used for SAV1. In
this case, the UH monitoring signals (UHV1 to UHV12) of the DSV are transferred.
When the serial interface fails, e.g. the DUST6 connecting cable is interrupted, nothing changes as far as the
transferred status words are concerned. The process image is retained. An evaluation of the status words in the
SIMADYN D open- and closed-loop control does not result in an erronous response.
1.10.7 Setting the IDENT number
There are two DIP switches S101 or S102 on the interface board, which should be set as following:
S102 S101 IDENT No.:

(decimal)
Bit 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 1 0 2
0 0 0 0 0 0 1 1 3
0 0 0 0 0 1 0 0 4
0 0 0 0 0 1 0 1 5
0 0 0 0 0 1 1 0 6
DIP switch 0 0 0 0 0 1 1 1 7
setting 0 0 0 0 1 0 0 0 8
0 0 0 0 1 0 0 1 9
0 0 0 0 1 0 1 0 10
0 0 0 0 1 0 1 1 11
0 0 0 0 1 1 0 0 12
0 0 0 0 1 1 0 1 13
0 0 0 0 1 1 1 0 14
This table shows that DIP switch S102 generally has the switch setting, logical „0“.
logical status
1 0 0 0 0 0 0 1 0 Fig. 1.20 Switch settings of DIP switches S101 and S102

The slave address of the SERS interface board
should be set at the DIP switches, binary-coded.
0 7 6 5 4 3 2 1 0 The setting shown corresponds to IDENT No = 2.
S102 S101
1.11 Technical data

♦ Ordering data Item No. MLFB
− SAV1 468 920.9001.00 6DD2920-0BA0
− SAV21 460 692.9010.00 6DD2920-0AH0
− SAV22 460 692.9011.00 6DD2920-0AJ0
− AUL1 468 920.9003.00 6DD2920-0BC0
− AUL2 460 692.9012.00 6DD2920-0AL0
− LES1 468 920.9002.00 6DD2920-0BB0
− LES2 460 692.9013.00 6DD2920-0AM0
− SERS 460 692.9014.00 6DD2920-0AP0
♦ Mechanical and climatic data

Operation
− ambient temperature 0 °C to 65 °C
− vibration stressing Class 13 acc. to SN29010
− frequency range 10 ... 58 Hz: 0.15 mm deflection
− frequency range 58 ... 500 Hz: 19.6 m/s2 acceleration
− scan rate: 1 octave/min
− pollutants Permissible mixed gas environments acc. to IEC 68
0.2 ppm SO2 + 0.2 ppm NO2 + 0.01 ppm H2S + 0.01 ppm Cl2
corresponds to environmental class 3C3 acc. to DIN EN
60721-3-3 / 06.94
− humidity Environmental class 3K5 acc. to DIN EN 60721-3-3 / 06.94
Moisture condensation not permissible
− cooling Self-convection
− max. installation altitude 1000 m above sea level
Storage and transport
− storage and transport temperature −40 °C to 85 °C
− vibration stressing Class 22 acc. to SN29010
− max. transport altitude 3000 m above sea level
Subracks
− SAV1, SAV21 Dimensions (W x H x D) 178 mm x 287 mm x 204 mm (refer to Section 2.1)
Weight 3.0 kg
− SAV22 Dimensions (W x H x D) 218 mm x 287 mm x 204 mm (refer to Section 2.1)
Weight 3.6 kg
♦ Electrical data
Supply voltage 24 V DC (+25 % / −20 %) acc. to VDE 0160 / E04.91
Buffer time
for VE = VEmin = 19.2 V and IE = 760 mA > 26 ms
Current drain (DC) without serial interface SAV22 : at 30 V: 360 mA
at 19.2 V: 460 mA
SAV21 : at 30 V: 250 mA
at 19.2 V: 310 mA
SAV1 : at 30 V: 365 mA
at 19.2 V: 400 mA
Current drain (DC) with serial interface SAV22 : at 30 V: 410 mA

at 19.2 V: 570 mA
SAV21 : at 30 V: 310 mA
at 19.2 V: 400 mA
SAV1 : at 30 V: 420 mA
at 19.2 V: 490 mA
Turn-on current
for VE = VEmax = 30 V 24 A, decay time constant tA = 7 ms
Degree of pollution 2 acc. to DIN VDE 0110, Part 1 / 1.89
moisture condensation not permissible
Overvoltage class ΙΙ acc. to DIN VDE 0110, Part 2 / 1.89
Degree of protection IP20 acc. to DIN VDE 0470, Part 1 =
^ EN 60529
Class of protection Ι acc. to DIN VDE 0106, Part 1 / 05.82
♦ EMC - electromagnetic compatibility ♦

Burst acc. to IEC 801-4
− control- and signal cables: Noise characteristics 4 acc. to DIN VDE 0160 / 04.91
2 kV test voltage
− power supply cables: Noise characteristics 4 acc. to DIN VDE 0160 / 04.91
2 kV test voltage
Surge acc. to IEC 801-5
− power supply cables: Noise characteristics 4 acc. to DIN VDE 0160 / 04.91
Surge voltage pulse: 1.2 / 50 µs
Peak value: 2 kV
Overvoltage strength 2 acc. to DIN VDE 0160 / 04.91
♦ Optional SERS interface board ♦

Data transfer protocol DUST6/6B via the RS485 interface
Baud rate 117.6 kbaud
Telegram length Short telegram
Data transmission length up to 1000 m
Data transmission protocol EIA 485
Maximum number of nodes 15
♦ Fiber-optic cables
Plastic fiber-optic cables CUPOFLEX fiber-optic cable core CA-1V2Y1P 980/1000 200A
tested acc. to DIN VDE 0432, Part 2
and DIN VDE 0472, Parts 513 and 503
2 Start-up Edition 10.95
2 Start-up
2.1 Installation
The dimensions of the SAV subrack can be taken from Fig. 2.1. The subrack carrier is retained using 2 mounting
brackets.
SAV1 / SAV21 SAV22
50
A A
Labeling
strips
VZ UH/VZ VZ UH/VZ
RECON UH 11 17 31 37 RECON UH 11 17 31 37
X11
X11
X11
X31
X31
X31
PA 12 18 32 38 PA 12 18 32 38
RESET DUG 13 19 33 39 RESET DUG 13 19 33 39
BV1 14 20 34 40 BV1 14 20 34 40 Shield
X13 X12
X13 X12
X13 X12
X33 X32
X33 X32
X33 X32
BV7 15 21 35 41 BV7 15 21 35 41
I=0 16 22 36 42 I=0 16 22 36 42 connection M5
X17 X16 X15 X14
X17 X16 X15 X14

X17 X16 X15 X14
X37 X36 X35 X34

X37 X36 X35 X34
X37 X36 X35 X34

266
266
X4 X7 X4 X7
X1 X1
190,5
190,5
X21 X20 X19 X18
X21 X20 X19 X18

X19 X18
X41 X40 X39 X38
X41 X40 X39 X38
X41 X40 X39 X38

X5 X8 X5 X8
188
188
X21 X20
X2 X2
Min. clearance
X22
X22
X22
X42
X42
X42
X3 X6 X9 X3 X6 X9
for air circulation
38
38
B B
50
9 159 9 199,6
177 217,6
232
232
136 176,6
Section A-B
shown without boards
287
204
Fig. 2.1 Dimension drawings
Edition 10.95 2 Start-up
2.2 Installing/removing components
CAUTION
Boards contain components which can be destroyed by electrostatic discharge.
If boards are touched which are not operational (unpacking, installing, etc.), static discharge
from the personnel handling the equipment can destroy the SAV.
The appropriate ESD instructions must be observed.
The SAV system is integrated into a conductive subrack, so that the components on the PC boards are protected
against static discharge. However, the ESD instructions must be observed as soon as the boards are removed
from the subrack!
The withdrawal elements of the sub-assemblies are electrically connected to the front panels. The AUL and LES
boards are screwed to the subrack to protect them against external EMC effects. Thus, it is ensured that the SAV
system represents a equipotential surface and that the basis connectors are correctly connected with the
backplane bus system. Further, active grounding should be provided so that any noise is discharged to ground
potential.
In order to prevent the SAV system being damaged, the power supply voltage must be powered-down when
installing/removing components!
2.3 Fiber-optic cable interfaces

2.3.1 Fiber-optic cable lengths
The required opto-power for the opto-receiver of the corresponding communications partner is defined by:
− limiting data of the opto-transmitter and its temperature-dependent wavelength shift
− opto-sensitivity of the opto-receiver
NOTE
A system reserve of 6 dB is recommended to ensure reliable and long-term converter operation. For a length
attenuation of 0.2 dB/m, fiber-optic cables up to 20 m can be used.
2.3.2 Fiber-optic cable - final handling and mounting
Siemens plastic opto cables, type CA-1V2Y1P980/1000 200A are used in the large drives to gate and monitor
the semiconductors. This fiber-optic cable can be cut during assembly and marked using a white ring. The cut
surface quality is sufficient (a clean smooth cut), so that the launching and extraction losses are low. The
maximum fiber-optic cable length is 20m for long pulse gating, as already explained in Section 2.3.1.
The following cutting equipment should be used:
Company, Spinner
Order No.: BN 549415
In order to guarantee consistent cut quality, the cutting knife should be replaced after a maximum of 100 cable
cuts.
The fiber-optic cable should be inserted into the housing of the transmitter- and receiver elements of the TAS21A
thyristor electronics up to the endstop at the lens and then tightened-up by hand.
The fiber-optic cables cut during assembly are marked using a white ring, which is just visible after the fiber-optic
cable has been correctly screwed into place.
Shield Opto-transmitter or opto-receiver
Fiber-optic cable
Lens
PC board
17.5 White ring

X
Fig. 2.2 Fiber-optic cable connection. Correct connection of the fiber-optic cable (X = 0) to the thyristor electronics
The white ring should be located 17.5 mm from where the fiber-optic cable was cut. X > 0 if the fiber-optic cable is
incorrectly adjusted. The opto-launching power changes (refer to Fig. 2.3).
An incorrect setting is visible as the white ring is shifted to the right exactly by this amount X.
If the white ring is shifted by X = 4 to 5 mm with respect to that shown in Fig. 2.2, this means that the fiber-optic
cable is not located inside the receive- or transmitter element.
The effect of incorrect adjustment on the opto launching power is illustrated in Fig. 2.3. It can be seen that for an
incorrect adjustment in the order of magnitude specified above, that the opto launching power is reduced by
almost 80%. Thus, the available system reserve is reduced by approx. 7 dB. This means that for fiber-optic cable
lengths above approx. 15 m there is no longer any system reserve.
1.0
φ in
φin(x=0) 0.8
0.6
0.4
Lens
0.2 Fiber
x
0
0 0.5 1.0 1.5 mm 2.0
x
Fig. 2.3 Change in the opto-launching power as a function of the fiber shift x
NOTE
It is absolutely necessary that the fiber-optic cables are carefully inserted and screwed into place in order to
guarantee long-term, disturbance-free converter operation. The fiber-optic cables should be marked using a
white ring in order to achieve minimum launching and extraction losses for the fiber-optic cable connections.
When connecting-up the fiber-optic cable it should be ensured that this ring is flush with the gland at the opto-
transmitter- and opto-receiver module (refer to Fig. 2.2).
2.4 Pulse assignment

There are a total of 12 possible pulse inputs for the SAV (BVZ1 to BVZ12), which are, corresponding to the
number of thyristors connected in series, read-in, conditioned, and distributed to the opto-transmitters (refer to
Sections 2.4.1 to 2.4.3).
The front elements of the SAV22 are illustrated in Fig. 2.4. An assignment between the BVZ command which is
read-in and the BV command which is output can be seen. When processing 12 commands, the assignment is
corresponding to the number, i.e. BVZ1 → BV1.
If only six commands are processed, then the assignment is: BVZ1 → BV1 and BV2.
For the SAV22, there is a fixed command assignment between the two LES boards, which is specified in Fig. 2.4
by the shading on the LES boards.
SAV22
LES1 LES2 AUL2
D1 D2 11
VZ
17 31
VZ
37
Optical status display
of the control circuits
X22 X21 X20 X19 X18 X17 X16 X15 X14 X13 X12 X11
X22 X21 X20 X19 X18 X17 X16 X15 X14 X13 X12 X11
X42 X41 X40 X39 X38 X37 X36 X35 X34 X33 X32 X31
X42 X41 X40 X39 X38 X37 X36 X35 X34 X33 X32 X31
BV1, SV1 VZ11 to VZ22: -> LES1
Thy.1 TAS21A 42 VZ31 to VZ42: -> LES2
16 22 36
BV1, SV13
Thy.2 TAS21A
Input, command interface
X4 X7 (12 pulses: BVZ1 to BVZ12)
X1: 25-pin plug connector

X1 X2: 25-pin socket connector
X5 X8
X2
BV12, SV12
TAS21A X3 X6 X9
Opto receiver
Opto transmitter 24 V DC
+25 % / − 20 %
Fig. 2.4 Front panel elements of SAV22-, assignment between the pulses and the optical LED displays
Example of a gating system with 12 firing pulses, number of thyristors connected in series, R=2
Two LED groups are located on the front panel of the AUL board, which are assigned to an LES board. The
assignment is linear corresponding to the numbering. Thus, for a gating circuit fault, (gating/checkback signal
channel BV4 / SV16), LED VZ34 flashes (second LED group → LES2).
2.4.1 Pulse assignment for the SAV1
If distributed power supplies are used for the Gate Drive Units, then for a number of thyristors connected in
series R>2, an arm-related gating should be implemented. Arm-related means that an SAV1 only gates a
complete arm.
Opto-transmitter and Command assignment for arm-related gating

associated opto-receiver
LES1 board R=1 R=2 R = 3,4 R = 5,6 R = 7 ... 12
-D1-X31/-D1-X11 BV1 BV1 BV1/ BV1/ BV1 to
-D1-X32/-D1-X12 BV2 BV4 BV3/ BV6
-D1-X33/-D1-X13 BV3 BV2 BV5
-D1-X34/-D1-X14 BV4
-D1-X35/-D1-X15 BV5 BV3 BV2/
-D1-X36/-D1-X16 BV6 BV5
-D1-X37/-D1-X17 BV7 BV4 BV2/
-D1-X38/-D1-X18 BV8 BV4/
-D1-X39/-D1-X19 BV9 BV5 BV3/ BV6
-D1-X40/-D1-X20 BV10 BV6
-D1-X41/-D1-X21 BV11 BV6
-D1-X42/-D1-X22 BV12
No. of SAV1 boards 1 1 2 3 6
The number of BV signals in a box indicates the number of SAV1 boards. For the number of thyristors connected
in series, R=5, 6, three SAV1 boards are required to gate the motor-side SIMOVERT I converter. Each board
processes two firing pulses, e.g. BV1 and BV2.
Opto-transmitter and Command

associated opto-receiver assignment
LES1 board R=1 R=2
-D1-X31/-D1-X11 BV1 BV1
-D1-X32/-D1-X12 BV2
-D1-X33/-D1-X13 BV3 BV2
-D1-X34/-D1-X14 BV4
-D1-X35/-D1-X15 BV5 BV3
-D1-X36/-D1-X16 BV6
-D1-X37/-D1-X17 BV7 BV4
-D1-X38/-D1-X18 BV8
-D1-X39/-D1-X19 BV9 BV5
-D1-X40/-D1-X20 BV10
-D1-X41/-D1-X21 BV11 BV6
-D1-X42/-D1-X22 BV12
No. of SAV21 boards 1 1
Opto-transmitter and associated opto-receiver Command assignment

LES1 board LES2 board R=2 R = 3,4 R = 5,6 R = 7,8 R=9 R = 13
1) ... 12 ... 24
-D1-X31/-D1-X11 -D2-X31/-D1-X11 BV1 BV1 BV1 BV1/ BV1/ BV1/

-D1-X32/-D1-X12 -D2-X32/-D1-X12 BV2 BV4 BV3/ to
-D1-X33/-D1-X13 -D2-X33/-D1-X13 BV3 BV2 BV5 BV6
-D1-X34/-D1-X14 -D2-X34/-D1-X14 BV4 BV2
-D1-X35/-D1-X15 -D2-X35/-D1-X15 BV5 BV3 BV2/
-D1-X36/-D1-X16 -D2-X36/-D1-X16 BV6 BV5
-D1-X37/-D1-X17 -D2-X37/-D1-X17 BV7 BV4 BV3 BV2/
-D1-X38/-D1-X18 -D2-X38/-D1-X18 BV8 BV4/
-D1-X39/-D1-X19 -D2-X39/-D1-X19 BV9 BV5 BV3/ BV6
-D1-X40/-D1-X20 -D2-X40/-D1-X20 BV10 BV4 BV6
-D1-X41/-D1-X21 -D2-X41/-D1-X21 BV11 BV6
-D1-X42/-D1-X22 -D2-X42/-D1-X22 BV12
No. of SAV22 boards 1 1 1 1) 2 3 6
1) BV5 and BV6 are assigned to SAV21.
2.5 Reset- and reconfiguring buttons

The RESET and RECON buttons are provided on the front panel of the AUL board. These buttons are arranged,
so that they can only be actuated, for example, using a ball-point pen.
The LCA is reconfigured by depressing the RECON button. This means that the data stored in the serial PROM
must again be read-into the LCA.
A reset is initiated as follows:
− depressing the RECON button
− depressing the RESET button
− by the external „external acknowledge" signal (H active)
− by powering the supply voltage up and down
The RESET signal is a low-active signal and must fulfill five functions.
1. Before the actual configuration, an L signal at the reset input causes a delay in the configuration process
2. If reset is active during configuration, then the system is re-initialized and re-configured.
3. If the reset is active after the configuration, a global, asynchronous reset is initiated, which resets all memory
elements in the IOB and in the CLB of the LCA.
4. Resets the external clock conditioning
5. The reset is wired to the optional SERS serial interface board, where it resets the microprocessor into the
initial state.
WARNING
It is not permissible to depress the RECON and RESET buttons during converter operation.
If these buttons are depressed during converter operation, the driver stages for the opto-
transmitters are inhibited. Thus, no input/output commands or firing pulses are output (pulse
inhibit!). This can, depending on the particular converter type, result in significant material
damage.
2.6 Zero ohm resistors

The zero ohm resistors provided on the board control certain board functions or ensure simpler board testing.
This data provides information regarding the factory status, i.e. the status when the equipment is supplied.
Part Function Function

code
SAV1 SAV21/SAV22
R310 Clock monitoring N.M.: The last output pulse pattern is Mounted: Causes a pulse inhibit
kept
R415 External acknowledge N.M.: Function is not evaluated in the N.M.: Function is not evaluated in
signal LCA the LCA
(QUIT_EXTL_N)
R416 External acknowledge Mounted: Enables the reset function, all output drivers
signal are inhibited
(QUIT_EXT_N)
R601 Active grounding Mounted: Connects the reference potential of the supply (0 V) with the
housing ground
R602 Board test Mounted: DC-DC converter G601 output connected with P5L of the logic
(AUL-BGR)
R353 Board test Mounted: DC-DC converter G1 output connected with P12 of the opto-
(LE-BGR) transmitter driver
N.M. = not mounted
2.7 Connector assignment

It is not possible to interchange connectors as different connector sizes are used.
2.7.1 Plug connector -X1, socket connector -X2
-X1 : 25-pin plug connector, D-subminiature according to DIN 41652

-X2 : 25-pin socket connector, D-subminiature according to DIN 41652
Pin Signal name Signal type Explanation

1 BVZP1 BEP Firing pulse 1+
2 BVZM1 1−
4 BVZM2 2−
6 BVZM3 3−
8 BVZM4 4−
10 BVZM5 5−
12 BVZM6 6−
14 BVZM7 7−
16 BVZM8 8−
18 BVZM9 9−
20 BVZM10 10−
22 BVZM11 11−
24 BVZM12 12−
25 N.C. Not connected
2.7.2 Plug connector -X5

1 UHVP1 BEP Voltage monitoring DSV 1+
2 UHVM1 DSV 1−
4 UHVM2 DSV 2−
6 UHVM3 DSV 3−
8 UHVM4 DSV 4−
10 UHVM5 DSV 5−
12 UHVM6 DSV 6−
2.7.3 Plug connector -X8

2 UHVM7 DSV 7−
4 UHVM8 DSV 8−
6 UHVM9 DSV 9−
8 UHVM10 DSV 10−
10 UHVM11 DSV 11−
12 UHVM12 DSV 12−
13,14,15 N.C. Not connected
2.7.4 Socket connectors -X4 and -X7
-X4, -X7 : 9-pin socket connector, D-subminiature according to DIN 41652
Pin DUST 6 Explanation

Signal name
1 RS485T− Send signal −
2 P5EXT 5V external
3 M5EXT Ground, external
5 RS485R− Receive signal −
6 RS485R+ Receive signal +
9 RS485T+ Send signal +
Connectors X4 and X7 are connected in parallel, thus making it simpler to handle the serial interface cable.
2.7.5 Socket connectors -X6 and -X9
-X6, -X9 : 37-pin socket connector, D-subminiature according to DIN 41652
Pin Signal Assignment for the thyristor converter Assignment for

type SIMOVERT I converters
Signal name Explanation Signal name Explanation
1 BA N.C. Not connected UHSR1 Aux. volt. status SR1,
OK = H
2 — M Ground M Ground
3 BE UEUH Transfer signal UEUH1 Transfer signal
UH UH from SR1
4 BA N.C. Not connected UHSR2 Aux. volt. status SR2,
OK = H
5 BEP IMPSP_EXTP Pulse inhibit, IMPSP_EXTP Pulse inhibit,
6 IMPSP_EXTM external IMPSP_EXTM external
7 BEP QUIT_EXTP Acknowledge signal, QUIT_EXTP Acknowledge signal,
8 QUIT_EXTM external QUIT_EXTM external
9 BE INULL_EXT Transfer signal, INULL_EXT Not connected
zero current signal
10 BE VZ_EXT Transfer signal, VZ_EXT Transfer signal
thyristor status thyristor status
11 BA INULL Zero load current VZ1 VZ status, arm 1
signal = H
13 BA VZ Thyristor status VZ2 VZ status arm 2
OK = H
14 — — Pin-to-pin connection — Pin-to-pin connection
16 BA RS Redundancy status VZ3 VZ status, arm 3
OK = H
19 BA UH Auxiliary power supply, VZ4 VZ status, arm 4
OK = H
22 BA N.C. Not connected VZ5 VZ status, arm 5
34 BA N.C. Not connected RS Redundancy status
OK = H
36 BE UERS Transfer signal, UERS Transfer signal,
redundancy status redundancy status
37 — P24P Buffered 24 V P24P Buffered 24 V
The assignment of the -X6 and -X9 connectors, connected in parallel, indicates the following input/output signals
− 4 transfer signals without electrical isolation (non-floating): (binary inputs)
− 2 binary signals with electrical isolation (floating)
− 15 output drivers without electrical isolation (non-floating)
These signals are wired to the LCA, and can therefore process any binary signal information.
2.7.6 Plug-in screw terminal -X3
-X3 : Plug-in three-pole screw terminal (Phoenix, MVST BR 2.5/3ST-5.08)
Pin Significance Connection cross-section

+ L+ (+24 V) Finely stranded (with connector sleeves)
− L− (ground) or solid: 0.2 ... 2.5 mm2
S Shield
The plug-in screw terminal may only be handled when it is not live.
2.7.7 Screw connections for fiber-optic cables -X11 ... -X22 and -X31 ... -X42
-X11 ... -X22, -X31 ... -X42 : Screw connections for fiber-optic cables with 2.2 mm external- and
1 mm core fiber diameter.
Inside diameter of the transmitter- and receiver elements: (2.2 to 2.35) mm
Edition 10.95 3 Operation
3 Operation
3.1 Optical status displays

The LEDs on the front panel of the AUL board signal the system status. The assignment of the gating circuits
(opto-transmitter - fiber-optic cable - thyristor electronics and GDU - fiber-optic cable - opto-receiver) and the
DSV (only for SAV1) to the LED displays can be taken from Sections 3.1.2 to 3.1.4.
The LEDs flash when there is a fault condition.
3.1.1 System LEDs
The system LEDs UH, PA, DUG, BV1, BV7 and I=0 indicate the following satuses:
LED designation LED status information
Bright Dark
UH (green) SAV power supply OK SAV power supply not OK
Function controlled via No data Data receive Data receive, Fault/error SERS not
th SERS interface received inserted
board data
transmitted
PA (green) Flashes, Flashes, Bright Dark Dark
approx. 2 Hz approx. 2 Hz
DUG (red) Dark Bright Bright Flashes, Dark
approx. 2 Hz
BV1 (green) On for command output = group signal (OR logic gate) from BV1 to BV6
BV7 (green) On for command output = group signal (OR logic gate) from BV7 to BV12
I=0 (yellow) Zero load current signal, LED bright for zero current
3 Operation Edition 10.95
3.1.2 SAV1 fault display
LED display LES1 LED display Monitoring signals of the

on AUL1 (control circuit) AUL1 distributed power supply
VZ11 -D1-X11, -D1-X31 UH31 -D2-X5:1,2 (DSV1)
VZ12 -D1-X12, -D1-X32 UH32 -D2-X5:3,4 (DSV2)
VZ13 -D1-X13, -D1-X33 UH33 -D2-X5:5,6 (DSV3)
VZ14 -D1-X14, -D1-X34 UH34 -D2-X5:7,8 (DSV4)
VZ15 -D1-X15, -D1-X35 UH35 -D2-X5:9,10 (DSV5)
VZ16 -D1-X16, -D1-X36 UH36 -D2-X5:11,12 (DSV6)
VZ17 -D1-X17, -D1-X37 UH37 -D2-X6:1,2 (DSV7)
VZ18 -D1-X18, -D1-X38 UH38 -D2-X6:3,4 (DSV8)
VZ19 -D1-X19, -D1-X39 UH39 -D2-X6:5,6 (DSV9)
VZ20 -D1-X20, -D1-X40 UH40 -D2-X6:7,8 (DSV10)
VZ21 -D1-X21, -D1-X41 UH41 -D2-X6:9,10 (DSV11)
VZ22 -D1-X22, -D1-X42 UH42 -D2-X6:11,12 (DSV12)
VZ = Thyristor status (a GTO)

UH = Auxiliary voltage
-D1-X11 to -D1-X22 = Opto receiver
-D1-X31 to -D1-X42 = Opto transmitter
LED display LES1 LED display LES2 is not inserted

on AUL2 on AUL2
VZ11 -D1-X11, -D1-X31 VZ31
VZ12 -D1-X12, -D1-X32 VZ32
VZ13 -D1-X13, -D1-X33 VZ33
VZ14 -D1-X14, -D1-X34 VZ34
VZ15 -D1-X15, -D1-X35 VZ35
VZ16 -D1-X16, -D1-X36 VZ36 No function
VZ17 -D1-X17, -D1-X37 VZ37 (LED group bright)
VZ18 -D1-X18, -D1-X38 VZ38
VZ19 -D1-X19, -D1-X39 VZ39
VZ20 -D1-X20, -D1-X40 VZ40
VZ21 -D1-X21, -D1-X41 VZ41
VZ22 -D1-X22, -D1-X42 VZ42
LED display LES1 LED display LES2

on AUL2 on AUL2
VZ11 -D1-X11, -D1-X31 VZ31 -D2-X11, -D2-X31
VZ12 -D1-X12, -D1-X32 VZ32 -D2-X12, -D2-X32
VZ13 -D1-X13, -D1-X33 VZ33 -D2-X13, -D2-X33
VZ14 -D1-X14, -D1-X34 VZ34 -D2-X14, -D2-X34
VZ15 -D1-X15, -D1-X35 VZ35 -D2-X15, -D2-X35
VZ16 -D1-X16, -D1-X36 VZ36 -D2-X16, -D2-X36
VZ17 -D1-X17, -D1-X37 VZ37 -D2-X17, -D2-X37
VZ18 -D1-X18, -D1-X38 VZ38 -D2-X18, -D2-X38
VZ19 -D1-X19, -D1-X39 VZ39 -D2-X19, -D2-X39
VZ20 -D1-X20, -D1-X40 VZ40 -D2-X20, -D2-X40
VZ21 -D1-X21, -D1-X41 VZ41 -D2-X21, -D2-X41
VZ22 -D1-X22, -D1-X42 VZ42 -D2-X22, -D2-X42
VZ = Thyristor status
3 Operation Edition 10.95
3.2 Causes of thyristor gating faults

The SAV21/SAV22 boards operate together with the thyristor electronics (TE)TAS21A, which signal the thyristor
status to the SAV using time-coded checkback signals. The monitoring philosophy is that the checkback signals
are not received when a fault situation occurs. Using this concept and the appropriate logic operations on the
thyristor electronics, the following faults and errors can be identified:
♦ Open gate ⇒ The gate current monitoring resets the memory to generate a fictitious end of
current signal. The logic remains de-activated due to the missing firing pulses.
No status checkback signals are output.
⇒ The SAV generates a fault signal at the end of the long pulse.
♦ Thyristor shorted after ⇒ The „thyristor blocks“ signal is no longer generated from the TE. The memory
current flow to generate a fictitious end of current signal remains reset as a result of the
„thyristor conducts“ signal.
⇒ The SAV generates a fault signal at the start of the next long pulse (function
module „Shorted thyristor identified“. If this module is not available, then the
turn-on monitoring signals this fault.
♦ Starting with shorted ⇒ TE voltage supply is not sufficient. The TE does not generate any checkback
thyristor signals.
⇒ The SAV generates a fault signal at the end of the long pulse.
♦ Fault, „fiber-optic cable ⇒ When a fiber-optic cable connection fails, there is a defective opto-receiver or
circuit" opto-transmitter, then checkback signals are not received, both on the TE as
well as on the SAV.
⇒ The SAV generates a fault signal.
♦ Pulse duration ⇒ The checkback signals of the TAS21A thyristor electronics are monitored on
monitoring (checkback the SAV to ensure that they are received in the specified time frames. A
signals) defective transmitter-time stage on the thyristor electronics will therefore be
immediately identified.
♦ SAV power supply ⇒ The "UH_OK" signal is set to low. The opto-transmitter driver is inhibited after
failed a buffer time expires (>20 ms).
♦ Clock monitoring (SAV) ⇒ Signal output of the quartz oscillator is monitored using a monostable circuit.
Response: Pulse inhibit for SAV21/22
Signals are inhibited
♦ Redundancy reduced ⇒ Concepts with N+k redundancies are possible. If redundancy is reduced, this is
signaled to the open-/closed-loop control. When redundancy has been
decreased, a fault signal is output.
3.3 Causes of GTO gating faults (SIMOVERT I)

Control commands (on/off commands) and the GDU checkback signals, must correspond to one another, with
the exception of the defined monitoring times in the switching transitions (TBESE, TBASA). A deviation causes
an immediate protective shutdown by the open- and closed-loop control. Possible fault causes are:
♦ „Gating circuit" fault ⇒ Failure of a gating circuit caused by:

- defective opto-transmitter or -receiver on the SAV1 or GDU
- defective fiber-optic cable
- fiber-optic cable not inserted or faulty
- defective opto-transmitter or -receiver on the SAV1 or GDU
Signals signaled by the GDU:
- faulted GDU
- defective GTO thyristor
- failed GDU power supply
These faults are identified by the SAV1 as the checkback signal and the
command no longer correspond.
♦ Power supply on the ⇒ The "UH_OK" signal is set to L.

SAV or DSV failed
⇒ The open- and closed-loop control responds to this signal within the buffer
time, and initiates a protective trip after 10 ms.
♦ Clock monitoring (SAV) ⇒ Signal output of the quartz oscillator is monitored using a monostable stage.
Response: The last pulse output is retained (SAV1)
Signals are inhibited
3.4 Clock monitoring

The 8 MHz and 50 kHz frequencies, derived from the quartz oscillator, are monitored by two monostable stages.
An AND gate generates the „TOK“ signal, which, when a fault condition occurs, withdraws the enable condition
for the driver stages „signals and possible opto-transmitter“ (opto-transmitter is controlled via R310 (refer to
Section 2.6). This signal is also transferred to the serial interface.
3.5 Voltage monitoring

The voltage monitoring function identifies power supply voltage faults. The board functions are controlled, using
the derived monitoring signals, so that no undesirable conditions occur (e.g. pulse output).
All of the voltages are monitored.

P24E : Supply voltage
P24P : Buffered supply voltage
P12 : Supply voltage for the opto-transmitter drivers
P5L : Supply voltage for the logic
The UH_OK signal is set to a low, if the supply voltage falls below 19 V.
4 Service Edition 10.95
4 Service
The SAV systems require no special care. However, they should be protected from dirt accumulation and
moisture.
Service/maintenance is not required. However, when servicing the thyristor modules, it should be checked that
the fiber-optic cables are tightly connected.
4.1 Checking and maintenance

Only a few tests can be carried-out at a reasonable cost and use of resources without using a special test unit.
Thus, the SAV system or the appropriate sub-assemblies must be returned to the manufacturer for a complete
check-out.
The ESD instructions should always be observed when working on the boards.
4.2 Troubleshooting
CAUTION
Defective SAV systems and sub-assemblies must be returned to the manufacturer for
repair.
Any information regarding the damage is helpful for troubleshooting and repair. This data is
also evaluated for a reliability analysis.
Thus, when the board is returned, information should be provided regarding the last
operating characteristics of the converter and other relevant points.
The ESD instructions must be observed if repairs are carried-out on-site.
4.3 Replacing sub-assemblies (AUL, LES)
WARNING
Work must only be carried-out with the power section adequately grounded.
Please follow all of the instructions in the General Instruction Manual (5 safety rules!)
The SAV system power supply must be switched-out and disconnected.
Further, the external interfaces to the particular sub-assembly must be withdrawn. The interface connections
must be clearly marked!
The locking screws must then be released and the board withdrawn from the subrack.
When packing the board, take care that none of the components are bent. Before shipping, use suitable
containers manufactured out of cardboard, wood or plastic (refer to the ESD instructions) with suitable filling
materials. A dessicating agent must be used if air-tight packing materials are used.
Edition 10.95 4 Service
The replacement board is inserted into the SAV subrack without any force until the first resistance is felt. The
retaining screws should then be gently tightened. Only then is the board correctly guided by the 96-pin basis
connector onto the backplane bus. By applying gentle pressure, the board snaps into the connector system. The
locking screws should now be tightened.
The external interfaces must now be re-connected as marked. For fiber-optic cable connections, please observe
the instructions and information in Section 2.3.2.
4.4 Spare parts
CAUTION
Spare boards must be ordered from the manufacturer by specifying the appropriate Order
No. (refer to Section 1.11).
5 Abbreviations / terminology Edition 10.95
5 Abbreviations / terminology
ADR Address byte
ASV LCA function module, status thyristor signal evaluation
AUL SAV-system board, gating- and monitoring logic
BA Binary output
BE Binary input
BEP Binary input with electrical isolation (floating)
BV(1..12) Thyristor gating signals (gating commands)
BVK On/off command monitored for the minimum time and if required corrected
BVS Synchronized thyristor arm command
BVZ(1..6) Thyristor arm command, torque direction 1
BVZ(7..12) Thyristor arm command, torque direction 2
CS41 SIMADYN D board communications system
DSV Distributed power supply
DUST6 Serial data transfer protocol for SIMADYN D units
FB Function block (SIMADYN D)
FPGA Field Programmable Gate Array
GDU Gate Drive Unit (gating board for GTO thyristors)
GÜV GTO thyristor monitoring- and interlocking board
HIW Main actual value
INULL_V_N Thyristor zero current signal (L active)
LCA Logic Cell Array (assigned name for XILINX for FPGA)
LES SAV- system board, opto-receiver- and -transmitter board for 12 thyristors
MR1 Torque direction 1
MR2 Torque direction 2
MSR Motor-side converter
N+k Redundant converter with k-x redundancy, k=1, 2, ...
NSR Line-side converter
PZD Process data
SAV Converter gating- and thyristor monitoring system
SAV1: For SIMOVERT I, motor converter side, 12 opto inputs/outputs, DSV monitoring
SAV21: Generally used for thyristor gating, 12 opto inputs/outputs
SAV22: Generally used for thyristor gating, 24 opto inputs/outputs
SERS Optional interface board for the SAV system
SST1 Serial interface 1
SVS Synchronized status checkback signal
TBA Turn-off duration
TBASA Time difference between the „off“ command and the „definetely off“ checkback signal
TBE Turn-on duration
TBESE Time difference between the „on“ command and the „definetely on“ checkback signal
Edition 10.95 5 Abbreviations / terminology
TE Thyristor electronics
UH Auxiliary power supply
V(1..24) Thyristor status signals (H = OK)
V25+ NEC µPD70325 microprocessor (internal 10 MHz clock)
Up until now the following editions have appeared: Edition Internal item No.
AA 460 692.9011.51 J AA-76
Edition AA consists of the following Sections:
Section Changes Edition date

1 Description First edition 10.95
2 Start-up First edition 10.95
3 Operation First edition 10.95
4 Abbreviations / terminology First edition 10.95
Drives and Standard Products Group ASI 1

Drive Systems Division System-Based
Postfach 3269, D-91050 Erlangen Drive Technology
Subject to change without prior notice Order No.: 6DD2921-0AJ76
Siemens Aktiengesellschaft Printed in the Federal Republic of Germany
1095

04 Sav 460 692.9011.51 J

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Converter Gating- and Thyristor Operating Instructions

Edition: AA Order No.: 6DD2921-0AJ76

We have checked the contents of this Manual to ensure that they

 Siemens AG 1995 All rights reserved

1.2 Design ....................................................................................................................................................7

1.3 Mode of operation ..................................................................................................................................9

1.4 Connecting the SAV to controlled and uncontrolled supply voltages...................................................18

1.5 Binary DC voltage signals ....................................................................................................................19

1.6 Power supply voltage power-up and power-down ...............................................................................21

1.7 Processing the transfer signals ............................................................................................................21

1.8 Electrical noise immunity, shielding......................................................................................................22

1.9 Fiber-optic cable interfaces ..................................................................................................................23

1.10 SERS interface board (option) .............................................................................................................24

1.11 Technical data......................................................................................................................................28

2.1 Installation ............................................................................................................................................30

2.2 Installing/removing components...........................................................................................................31

2.3 Fiber-optic cable interfaces ..................................................................................................................32

2.4 Pulse assignment.................................................................................................................................34

2.5 Reset- and reconfiguring buttons .........................................................................................................37

2.6 Zero ohm resistors ...............................................................................................................................38

2.7 Connector assignment .........................................................................................................................39

3.1 Optical status displays..........................................................................................................................43

3.2 Causes of thyristor gating faults...........................................................................................................46

3.3 Causes of GTO gating faults (SIMOVERT I)........................................................................................47

3.4 Clock monitoring...................................................................................................................................47

3.5 Voltage monitoring ...............................................................................................................................47

4.1 Checking and maintenance..................................................................................................................48

4.3 Replacing sub-assemblies (AUL, LES) ................................................................................................48

4.4 Spare parts...........................................................................................................................................49

Definitions, warning information

3. Trained in rendering first aid.

Components which can be destroyed by electrostatic discharge (ESD)

Seated Standing Standing / sitting

Fig 1.1 SAV system versions

Opto-receiver- and -transmitter board LES

X16 X15 X14

Connect. Connector type Function

Fig. 1.3 AUL front panel

1.3 Mode of operation

This diagnostic interface also supports start-up.

The LEDs located on the front panel provide information regarding:

1.3.1 Tasks of the SAV1 in the SIMOVERT I converters

Fig. 1.5 shows a general block diagram of the SAV.

Syn- Correction to the Command

SV1 to SV12 Syn- Thyr. status monit. V1 to V12

Thyr. status VZ1 to VZ6

UHV1 to UHV12 UH- UH_SR1

Fig. 1.4 LCA structure of the SAV1

X1 X2 X11 bis X22 X11 bis X22 X5 X8 X6 X9 X3

SAV block diagram

Converter Gating- and Thyristor Monitoring Systems

LCA logic, refer to Sections 1.3.1 and 1.3.2 UHIB

VZ1 to VZ24 RVZ1 to RVZ6

V1 V12 V13 V24 IU DUST6 Processor INULL

X31 to X42 X31 to X42 X4 X7 X6 X9

BV1 to BV12 BV1 to BV12

♦ Correction for minimum switching times T BE and TBA

♦ Thyristor status monitoring TBESE and TBASA

Fig. 1.6 Shift time monitoring

♦ Thyristor arm status identification

♦ Reduced redundancy monitoring

Converter Binary signals SAV1 to GÜV Binary signals from GÜV to

1.3.2 SAV21 and SAV22 tasks