Floor Planning.

BY : Abhishek Mandole
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Check_netlist (Sanity Check)
▪ This command instructs the tool to perform various checks on the netlist to identify potential
errors or inconsistencies (Floating input pins and nets, Direct path from outputs to ground,
Blackbox Module, Multi driven nets, Combinational Loops and pins mismatch)

Check_timing (Sanity Check)

▪ This command instructs the tool to perform a series of timing checks.(Clock not reaching the Flip
Flop, Multiple clocks driving same register, Unconstrained paths, Port IO delay missing, Port
slew/load missing, clock definitions missing)

report_design_mismatch –verbose (Sanity Check)

▪ Command that helps identify discrepancies between your design and a reference source. By
providing a detailed report.

initialize_floorplan –core_utilization 0.3 –core_offset{2}

▪ initialize_floorplan :This command used for creating or initializing a floorplan for a design.
▪ -core_utilization 0.3 : This option defines the target core utilization for the floorplan (0.3
indicates a utilization target is 30%).
▪ Core_offset{2} : This option defines the offset of core placement

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set_block_pin_constraints -self -allowed_layers {M3 M4} -sides 2
▪ Deals with defining constraints on the pin locations for a specific block within an Integrated
Circuit (IC) design.
▪ Set_block_pin_constraints : Used to specify restrictions on how pins of a particular block
can be placed during the design flow.
▪ -self : This option indicates that the constraints being defined apply to the block itself.
▪ -allowed_layers{M3 M4} : This option specifies the metal layers tha pins are allowed to
reside on (M3 and M4 by specifying these layers your restricting pin placement to only occur
on these two metal layers)
▪ -sides 2 : This option defines the number of sides of the block on which pins can be placed

place_pins -ports [get_ports -filter direction==out]

▪ Related to automated pin placement within a PD tool
▪ get_ports –filter direction==out : Retrieves a list of all ports in the design that are classified
as output ports
▪ get_ports : Is likely a function within the tool that fetches information about ports in the
design
▪ -filter direction==out : Acts as a filter specially selecting ports where direction attribute is
equal to “out”. This ensures only output ports are included in the list.

BY : Abhishek Mandole
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Set_block_pin constraints –slef –allowed_layers {M3 M4} –sides 4
▪ -sides 4 : This option defines the number of sides of the block on which pins can be placed
place_pins -ports [get_ports -filter direction==in]
▪ -filter direction==in : Acts as a filter specially selecting ports where direction attribute is equal to
“in”. This ensures only input ports are included in the list.

Set_attribute [get_ports*] physical status fixed

▪ Set_attribute : This suggests a function or command used to assign a specific property or
characteristic to objects within the design.
▪ get_ports : It likely a function that fetches details about ports.
▪ “*” : Acts as wildcard indicating that all the ports should be selected.
▪ physical_status : Likely refers to a property that controls the intended placement flexibility of the
port during the design flow.
▪ fixed : Indicates that the port location should be considered fixed

get_attribute [get_ports *] is_fixed

▪ This part retrives info about a attribute associated with all ports in the design.
▪ get_attribute : Is likely a function within the tool used to access attribute values of design objects.
▪ [get_ports *] : Retrives info about all ports using the get_ports function
▪ is_fixed : Likely refers to an attribute that indicates whether a port's location is fixed or movable
during the design flow
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set_attribute [get_cells -physical_context -filter design_type==macro] physical_status fixed
▪ Deals with fixing the placement of all macro cells in the design
▪ [get_cells –physical_context –filter design_type==macro] : This part retrieves information about
all macro cells in the design
▪ get_cells : Likely fetches info about cells in the design.
▪ -physical_context : Might be a filter that ensure the retrieved cells are part of physical design
layout, excluding any logical views
▪ -filter design_type==macro : filters the retrieved cells to include only those classified as macros
▪ physical_status : likely refers to a property that controls the intended placement flexibility of the
macro cell during the design flow
▪ fixed : indicates that the macro cell location should be considered fixed

get_attributes [get_cells -physical_ context -filter design_type==macro] is_fixed

▪ Status of all macro cells in the design
▪ get_attribute : Is likely a function within the tool used to access multiple attribute values of the
design object
▪ is_fixed : Likely refers to an attribute that indicates whether a macro cells location is fixed or
movable.

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create_keepout_margin -type hard -outer {1 1.2 1 1.2} [get_cells -physical_context –filter
design_type==macro]
▪ Creating keepout margin around all macro cells
▪ create_keepout_margin : This suggests a function or command used to define and create
keepout regions around objects in the design.
▪ -type hard :This option specifies the type of keepout margin to be created. “ hard” likely
indicates a stricker keepout region where no other objects are allowed to be placed.
▪ -outer { 1 1.2 1 1.2 } : This option defines the outer dimension of keepout margin as a list of four
values (left, top, right and bottom).
▪ [get_cells –physical_context –filter design_type==macro] : This part retrieves info about all
macro cells in the design and passes them as input to the “create_keepout_margin” function

set_boundary_cell rules -right_boundary_cell (cell name) -left_boundary_cell (cell name) -prefix

endcap
▪ Appears to be related to defining boundary cells for a design within a design.
▪ Set_boundary_cell rules : This command used to define rules for boundary cell.
▪ -right_boundary_cell and –left_boundary_cell : These options specify the names (types) of
cells that should be placed at right and left boundaries of the design.
▪ -prefix endcap : This option defines a prefix that will be prepended to the names of placed
boundary cells ( Example: If Cell23 is specified as the right boundary cell the actual placed cell
might have name like “endcap_cell23”)
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Compile_target_boundary_cell –target_objects [get_voltage_areas]
▪ Compile_target_boundary_cell : This part suggests a function or command used to compile
information and potentially generate objects (likely boundary cells) based on specified targets.
▪ -target_objects [get_voltage_areas] : This option defines the targets for which boundary cells
should be compiled.
▪ get_voltage_areas : likely retrieves information about voltage and ground areas within the design.

create_tap_cell –lib_cell (cell name) –distance 30 –skip_fixed_cell

▪ Deals with inserting tap cells
▪ create_tap_cell : This command used to create and insert tap cells.
▪ -lib_cell : This option specifies that the tap cell should be inserted from a pre-defined library
▪ -distance 30 : The option define the spacing between the tap cells.
▪ -skip_fixed_cell : This option instructs the tool to skip inserting tap cells at locations occupied by
fixed cells.

check_legality –cell [get_cells bound*]

▪ [get_cells bound*] : might retrieves these estimated placement areas for a group of cells.
▪ check_legality : Appears to be a verification step to ensure the legality of a specific cell's
placement within the design layout.

BY : Abhishek Mandole
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Check_legality –cells [get_cells tap*]
▪ Check_legality : Appears to be a verification step to ensure the legality of a specific cell's
placement within the design layout.
▪ -cells [get_cell tap*] : “-cell” this indicates the tool to focus on multiple cells.

Save_block –as floorplan_done

▪ Save_block : This suggests a function or command used to save a specific block or design
element within the tool
▪ -as floorplan_done : This option defines the name of the block. Here “floorplan_done” is the
name of the block.

BY : Abhishek Mandole
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Thank You

BY : Abhishek Mandole
LinkedIn : Abhishek Mandole