Inputs in physical design:

Netlist format is .v
Logical libraries format is .lib
Physical libraries format is .lef
upf format is .upf
Sdc format is. sdc
.I/O (.def) format is .def
LOADING THE INPUTS:
By using the below command inputs are being loaded.
open_block
/Projects/synopsys/inh68/ICC2_BLI_2019.12-SP4/lab2_floorpla
n/ORCA_TOP.dlib: ORCA_TOP/floorplan.design
link_block
PERFORMING SANITY CHECKS:
Sanity checks mainly checks the quality of netlist,issues related
to libraries and constraints.

1.NETLIST CHECKS:
Here will check if there are any floating pins or unconnected
pins
There shouldn’t be any black boxes
There shouldn’t be any multidriven ports.If so,with tri-state
buffer there will be possibilities to work.
Check for combinational loops.

2.LIBRARY CHECKS:
It checks the qualities of both libraries.
There should not be any linking issue or unresolved refrences
Missing cell information
Missing pin information

3.SDC CHECKS:
Check for unconstrained pins.
All flops are clocked or not
Setting input and output delay
COMMANDS USED FOR SANITY CHECKS IN ICC2:
Netlist: check_design
Libraries: check_library
Sdc: check_timing
FLOOR PLANNING:
Floor Planning involves determining the location, shape, and size of
modules in a way that one can avoid congestion.Here,WE SPACIFY
POSITIONS, INSERTING WELL TAP CELLS,DECAP CELLS,ENDCAP CELLS.

IN FLOOR PLAN MAIN IMPORTANT THING IS MACRO PLACEMENT

AND IN FLOORPLAN WE ALSO CREATE THE BLOCKAGES
IN THE FLOOR PLAN MAIN OBJECTS ARE MACRO PLACEMENT.,
DEFINE ASPECT RATIO(HEIGHT/WIDTH).
I/O PLACEMENTS.
CORE AREA INITIALIZATION.

CORE AREA : CORE AREA IS DEFINED FOR THE PLACEMENT OF STD CELLS,AND MACROS.

CORE AREA DEPENDS ON (i)ASPECT RATIO

ii)UTILIZATION.

UTILIZATION= (STD CELL AREA+MACRO AREA+BLOCKAGE AREA)/TOTAL AREA.

STD CELL UTILIZATION= (STD CELL AREA)/

(TOTAL CORE AREA - (MACRO AREA+BLOCKAGE AREA)).

INPUTS OF FLOOR PLANNING:

Netlist
Logical and physical libraries
Upf
SDC (optional)
COMMANDS FOR INITIATING FLOORPLAN:
initialize_floorplan -shape R -core_offset {10} -side_ratio
{2 2} -core_utilization 0.6

ASPECT RATIO = HEIGHT OF THR CORE/WIDTH OF THE CORE

ASPECT RATIO DECIDES THE CHIP OF THE BLOCK.

set_block_pin_constraints -sides {3 4} -allowed_layers {M3 M4} -

pin_spacing 5 -corner_keepout_distance 50 -self
place_pins -ports [get_ports *]
MACRO PLACEMENT GUIDELINES:
Macros should be placed based on the following guidelines
FLY LINES

PORTS COMMUNICATIONS.

MACRO'S SHOULD BE PLACED AT BOUNDARIES

MACRO GROUPING [LOGICAL HIERARCHY]

SPACING BETWEEN MACRO'S

NOTCHES AVOIDING

ORIENTATION

BLOCKAGES

AVOID CRIS CROSS PLACEMENT OF MACROS

MACROS SHOULD BE PLACED AROUND EDGES OF BLOCKS,KEEPING ARE LARGE MAIN AREA FOR STD CELLS

LEAVE A HALO SPACE BETWEEN MACROS ON ALL SIDES

KEEPOUT MARGIN OR HALO FOR MACROS:

We give Keepout margin / halo around the macros so that it dont allow
others cells to sit near The macros , and in this way Macros Pins are free to
route,If you dont give then it may be possible that Std cells may come and
sit near the Macros and this will lead to congestion.

HOW TO CREATE KEEPOUT MARGIN?

Create_keepout_margin –outer {1.2 1.2 1.2 1.2} [get_selection ]

COMMANDS:
change_selection [get_cells -hierarchical -filter "design_type ==
macro" ] # to select all macros
write_floorplan -objects [get_selection ] -output filename
#to save in tcl format
change_selection [get_ports ] # to select I/O ports
write_def -objects [get_selection ] macro_io.def
#to save in def format
get_selection # to get /to fetch info
change_selection #To select that particular object
Read_def deffile name # To source the def file into the design.
CREATING PHYSICAL ONLY CELLS:
We need to create physical only cells after floorplan by using the below
commands.
create_tap_cells -lib_cell DCAP_HVT -distance 30 -pattern stagger

set pre_place_cell "saed32_hvt|saed32_hvt_std/DCAP_HVT"

set_boundary_cell_rules -left_boundary_cell $pre_place_cell -

right_boundary_cell $pre_place_cell
POWER PLANNING:
Power planning means to provide power to the every
macros, standard cells, and all other cells are present
in the design.
Steps for creating power planing
Commands:-
To remove all patterns strategies:
remove_pg_strategies -all
remove_pg_patterns -all
remove_pg_regions -all
remove_pg_via_master_rules -all
remove_pg_strategy_via_rules -all
remove_routes -net_types {power ground} -ring -stripe -macro_pin_connect -
lib_cell_pin_connect > /dev/null

To connect VDD and VSS:

connect_pg_net
Reset_upf
Load_upf #path of file/

After loading the upf,we will remove all the level shifters in the design by using
below command, as we are not using multivoltage domain by using
To remove all level shifters :-
change_selection [get_cells -hierarchical -filter "is_level_shifter ==true"]
remove_objects [get_selection ]

Commit_upf

TO SET THE VIAS:

set_pg_via_master_rule pgvia_8x10 -via_array_dimension {8 10}

CREATE M1 RAILS:
create_pg_std_cell_conn_pattern rail_pattern -layers M1
set_pg_strategy M1_rails -core -pattern {{name: rail_pattern} nets: VDD VSS }
compile_pg -strategies M1_rails

TO CREATE HORIZONTAL MESH:

create_pg_mesh_pattern P_top_two -layers {{horizontal_layer: M2} {width:1.104}
{spacing: interleaving} {pitch:13.376} {offset:0} {trim:true}}

set_pg_strategy S_default_vddvss -core -pattern { {name: P_top_two} {nets:{VSS

VDD}} {offset_start: {20.343 11.2208}} }

compile_pg -strategies {S_default_vddvss}

TO CREATE VERTICAL MESH:

create_pg_mesh_pattern P_top_two1 -layers { {vertical_layer: M7} {width: 3.64 }
{spacing: interleaving} {pitch: 19.456} {offset: 0} {trim : true} }
set_pg_strategy S_default_vddvss -core -pattern { {name: P_top_two1} {nets:
{VSS VDD}} {offset_start: {13.938 13.648}} }

compile_pg -strategies {S_default_vddvss}

TO CREATE THE STACKED VIAS:

set_pg_strategy_via_rule S_via_m2_m7\
-via_rule { \
{ {{strategies: {S_m1_vddvss }} {layers: { M2 }} {nets: {VSS VDD}} } \
{{strategies: {S_default_vddvss }} {layers: { M7 }} {nets: {VSS VDD}}} \
{via_master: {default}} }}

compile_pg -strategies {S_default_vddvss S_m1_vddvss} -via_rule {S_via_m2_m7}