Ignatius Timothy Bonario
2022390013
Computer Architecture and Organization
Please answer following questions:
1. Please do Explicit and Implicit normalization in Binary Floating Point (1 Point)
1. 27
2. 3
3. -5.625
4. -4.125
2. Please do following arithmetic in Binary Floating Point and convert back again to
decimal (1 point):
1. 27 x - 3
2. 5.625 + (-4.125)
3. 5.65 - (-4.125)
3. I/O Modules
1. Please describe and explain solution for design issue in Interrupt
Driven I/O (0.5 Point)
2. Please describe and explain the difference between memory mapped
I/O and isolated I/O (0.5 point)
4. Instruction Set
1. Please describe and explain Type of Operation of Instruction Set (0.5
point)
2. Please describe and explain Type of Branch Instruction Set (0.5 point)
5. Processor Structure and Function
1. Please describe and explain type of Pipeline Hazard (0.5 point)
2. Please describe and explan type of Register Organization (0.5 point)
Answer:
1. Explicit and Implicit normalization in Binary Floating Point:
● Explicit normalization: In explicit normalization, the leading bit of the significand is
always assumed to be 1, so it is not stored. The exponent represents the position of the
binary point. For example, for the number 27 in binary floating-point format, it would
be represented as: 1.1011×241.1011×24.
● Implicit normalization: In implicit normalization, the leading bit of the significand is
assumed to be 1 and not stored explicitly. The exponent also represents the position of
the binary point. For example, for the number 27 in binary floating-point format with
implicit normalization, it would be represented as: 1.1011×241.1011×24.
2. Arithmetic in Binary Floating Point and Conversion:
● 27×(−3)27×(−3):
● 2727 in binary: 1101111011, exponent: 100100 (4 in binary)
● −3−3 in binary: 11001100, exponent: 1111 (3 in binary)
● Multiply the significands: 11011×1100=10100010011011×1100=101000100
● Add the exponents: 100+11=111100+11=111 (7 in binary)
● Result: 1.01000100×271.01000100×27 in binary
● 5.625+(−4.125)5.625+(−4.125):
● 5.6255.625 in binary: 101.101101.101, exponent: 101101 (5 in binary)
● −4.125−4.125 in binary: 100.001100.001, exponent: 100100 (4 in binary)
● Add the significands: 101.101+100.001=1001.110101.101+100.001=1001.110
● Result: 1.001110×221.001110×22 in binary
● 5.65−(−4.125)5.65−(−4.125):
● Perform the subtraction similarly.
3. I/O Modules:
● Design Issue in Interrupt Driven I/O: One significant issue in interrupt-driven I/O
is the potential for high interrupt rates, leading to interrupt overheads and decreased
system performance. Solutions to mitigate this issue include implementing interrupt
coalescing or using techniques like DMA (Direct Memory Access) to transfer data
without continuous CPU intervention.
● Difference between Memory-Mapped I/O and Isolated I/O:
● Memory-Mapped I/O: In memory-mapped I/O, hardware devices are treated
as if they were memory locations. The CPU can read from and write to these
memory addresses to communicate with the devices. It simplifies
programming as it uses the same instructions as memory access.
● Isolated I/O: Isolated I/O involves separate instructions and address spaces
for I/O operations. It doesn't share the same address space as memory, so
special I/O instructions are needed to communicate with devices. This
approach offers more control but requires additional instructions and address
space management.
4. Instruction Set:
● Type of Operation of Instruction Set: Instruction sets typically include various
types of operations such as arithmetic (addition, subtraction, multiplication, division),
logic (AND, OR, NOT), data movement (load, store), and control transfer (branching,
jump).
● Type of Branch Instruction Set: Branch instructions allow altering the flow of
execution in a program. Types of branch instructions include conditional branches
(based on certain conditions), unconditional branches (always taken), and relative
branches (with respect to the current instruction pointer).
5. Processor Structure and Function:
● Type of Pipeline Hazard: Pipeline hazards are situations in pipelined processors
where the next instruction cannot execute in the next stage due to data dependencies,
structural hazards (resource conflicts), or control hazards (branch instructions). Types
of pipeline hazards include data hazards (when an instruction depends on the result of
a prior instruction), structural hazards (resource conflicts), and control hazards (due to
branch instructions).
● Type of Register Organization: Registers are high-speed storage locations within the
CPU used to store data temporarily during processing. Types of register organization
include single-cycle, multi-cycle, and pipelined register organizations, each optimized
for different aspects of performance such as speed or complexity.
